Pixel driving circuit and driving method thereof, and display panel

Abstract

A pixel driving circuit and a driving method thereof, and a display panel. The pixel driving circuit comprises a driving transistor (DT), a data writing circuit (1), a compensation circuit (2), a light emitting control circuit (3), a storage circuit (4), a first transistor (T1), and a second transistor (T2). The first electrode of the driving transistor (DT) is connected to a first node (N1), the second electrode is connected to a second node (N2), and the gate is connected to a third node (N3); the data writing circuit (1) is connected to the first node (N1) and a data signal terminal (Da); the compensation circuit (2) is connected to the second node (N2) and the third node (N3); the light emitting control circuit (3) is connected to the driving transistor (DT), a first power supply terminal (VDD), a light emitting unit (OLED), and an enable signal terminal (EM); the storage circuit (4) is connected between the first power supply terminal (VDD) and the third node (N3). The first transistor (T1) and the second transistor (T2) are connected in series between the third node (N3) and the initial signal terminal (Vinit); the first transistor (T1) is an N-type oxide transistor, and the driving transistor (DT) is a P-type low temperature polysilicon transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, and a display panel. Background Art

[0002] The pixel driving circuit is used to drive the light-emitting unit in the pixel unit to emit light. In the related art, the pixel driving circuit includes a driving transistor and a capacitor. The driving transistor is used to output a driving current to the light-emitting unit according to its gate voltage output; the capacitor is connected to the gate of the driving transistor and is used to store charge to continuously provide voltage to the driving transistor during the light-emitting stage of the pixel driving circuit.

[0003] However, the gate of the driving transistor is prone to leakage through the transistor connected thereto, thereby affecting the light emission stability of the pixel driving circuit during the light emission phase.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field.

[0005] Public Content

[0006] According to one aspect of the present disclosure, a pixel driving circuit is provided, which includes: a driving transistor, a data writing circuit, a compensation circuit, a light emitting control circuit, a storage circuit, and a reset circuit. The first electrode of the driving transistor is connected to the first node, the second electrode is connected to the second node, and the gate is connected to the third node; the data writing circuit is connected to the first node and the data signal terminal, and is used to transmit the signal of the data signal terminal to the first node in response to a control signal; the compensation circuit is connected to the second node and the third node, and is used to connect the second node and the third node in response to a control signal; the light emitting control circuit is connected to the first electrode and the second electrode of the driving transistor, the first power supply terminal, the first electrode of the light emitting unit, and the enable signal terminal, and is used to connect the first power supply terminal and one electrode of the driving transistor in response to the signal of the enable signal terminal, and connect the first electrode of the light emitting unit and the other electrode of the driving transistor; the storage circuit is connected between the third node; the reset circuit includes: a first transistor and a second transistor. The first electrode of the first transistor is connected to the third node, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the reset signal terminal; the first electrode of the second transistor is connected to the second electrode of the first transistor, the second electrode is connected to the initial signal terminal, and the gate is connected to the reset signal terminal; wherein the first transistor and the second transistor are N-type oxide transistors, and the driving transistor is a P-type low-temperature polysilicon transistor.

[0007] In an exemplary embodiment of the present disclosure, the light emitting control circuit is used to connect the first power supply terminal and the second electrode of the driving transistor, and connect the first electrode of the light emitting unit and the first electrode of the driving transistor in response to the signal of the enable signal terminal.

[0008] In an exemplary embodiment of the present disclosure, the data writing circuit includes a third transistor, a first electrode of the third transistor is connected to the data signal terminal, a second terminal is connected to the first node, and a gate is connected to the first gate driving signal terminal.

[0009] In an exemplary embodiment of the present disclosure, the compensation circuit includes a fourth transistor, the first electrode of the fourth transistor is connected to the second node, the second electrode is connected to the third node, and the gate is connected to the second gate drive signal terminal; wherein the third transistor is a P-type low-temperature polysilicon transistor, and the fourth transistor is an N-type oxide transistor.

[0010] In an exemplary embodiment of the present disclosure, the compensation circuit includes a fourth transistor, a first electrode of the fourth transistor is connected to the second node, a second electrode is connected to the third node, and a gate is connected to the first gate drive signal terminal; wherein the third transistor and the fourth transistor are both P-type low-temperature polysilicon transistors.

[0011] In an exemplary embodiment of the present disclosure, the compensation circuit includes a fourth transistor, a first electrode of the fourth transistor is connected to the second node, a second electrode is connected to the third node, and a gate is connected to the first gate drive signal terminal; wherein the third transistor and the fourth transistor are both N-type oxide transistors.

[0012] In an exemplary embodiment of the present disclosure, the light-emitting control circuit includes a fifth transistor and a sixth transistor, wherein the first electrode of the fifth transistor is connected to the first power supply terminal, the second electrode is connected to the second node, and the gate is connected to the enable signal terminal; the first electrode of the sixth transistor is connected to the first node, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the enable signal terminal.

[0013] In an exemplary embodiment of the present disclosure, the fifth transistor and the sixth transistor are P-type low temperature polysilicon transistors.

[0014] In an exemplary embodiment of the present disclosure, the storage circuit includes a capacitor connected between the first power supply terminal and the third node.

[0015] According to one aspect of the present disclosure, a display panel is provided, comprising the above-mentioned pixel driving circuit, wherein the display panel comprises: a substrate, a first active layer, a first conductive layer, a second active layer, a second conductive layer, and a third conductive layer. The first active layer is located on one side of the substrate, the first active layer comprises a first active portion, and the first active portion is used to form a channel region of the driving transistor; the first conductive layer is located on the side of the first active layer away from the substrate, the first conductive layer comprises a first conductive portion, the orthographic projection of the first conductive portion on the substrate covers the orthographic projection of the first active portion on the substrate, and the first conductive portion is used to form a gate of the driving transistor. The second active layer is located on the side of the first conductive layer away from the substrate, the second active layer comprises: a second active portion, a third active portion, a fourth active portion, a fifth active portion, and a sixth active portion. The second active portion is located on the side of the first conductive portion on the substrate substrate in the first direction of the orthogonal projection of the substrate substrate; in the first direction, the orthogonal projection of the third active portion on the substrate substrate is located between the orthogonal projection of the first conductive portion on the substrate substrate and the orthogonal projection of the second active portion on the substrate substrate, and the orthogonal projection of the third active portion on the substrate substrate is located on the side of the orthogonal projection of the second active portion on the substrate substrate in the second direction, and the first direction intersects with the second direction; the fourth active portion is connected between the second active portion and the third active portion, and the orthogonal projection of the fourth active portion on the substrate substrate is located between the third active portion On the side of the orthogonal projection of the substrate in the third direction, the second direction is opposite to the third direction, and in the first direction, the orthogonal projection of the fourth active part on the substrate is located between the orthogonal projection of the first conductive part on the substrate and the orthogonal projection of the second active part on the substrate; the fifth active part is connected to the second active part, and the orthogonal projection of the fifth active part on the substrate is located on the side of the orthogonal projection of the second active part on the substrate in the first direction; the sixth active part is connected to the third active part, and the orthogonal projection of the sixth active part on the substrate is located on the side of the orthogonal projection of the third active part on the substrate in the second direction. The second conductive layer is arranged on the side of the second active layer away from the substrate, and the second conductive layer includes: a first gate line and a first protrusion.The first gate line extends along the second direction in the orthogonal projection of the substrate, the first gate line includes a second conductive portion, the orthogonal projection of the second conductive portion on the substrate coincides with the orthogonal projection of the second active portion on the substrate, and the second conductive portion is used to form the first gate of the second transistor; the first protrusion connects the first gate line, in the first direction, the orthogonal projection of the first protrusion on the substrate is located between the orthogonal projection of the first gate line on the substrate and the orthogonal projection of the first conductive portion on the substrate, the first protrusion includes a third conductive portion, the orthogonal projection of the third conductive portion on the substrate coincides with the orthogonal projection of the third active portion on the substrate, and is used to form the first gate of the first transistor. The third conductive layer is arranged on the side of the second conductive layer away from the substrate, and the third conductive layer includes: a first connecting portion and an initial signal line. The first connecting portion connects the sixth active portion and the first conductive portion through a via hole; the orthogonal projection of the initial signal line on the substrate extends along the second direction, the orthogonal projection of the initial signal line on the substrate is located on the side of the orthogonal projection of the first gate line on the substrate in the first direction, and the initial signal line is connected to the fifth active portion through a via hole.

[0016] In an exemplary embodiment of the present disclosure, the display panel further includes a fourth conductive layer, which is disposed between the first conductive layer and the second active layer. The fourth conductive layer includes: a second gate line and a second protruding portion, the second gate line extends along the second direction in the orthographic projection of the substrate, the second gate line includes a fourth conductive portion, the orthographic projection of the second active portion on the substrate is located on the orthographic projection of the fourth conductive portion on the substrate, and the fourth conductive portion is used to form a second gate of the second transistor; the second protruding portion connects the second gate line, in the first direction, the orthographic projection of the second protruding portion on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the first conductive portion on the substrate, the second protruding portion includes a fifth conductive portion, the orthographic projection of the third active portion on the substrate is located on the orthographic projection of the fifth conductive portion on the substrate, and the fifth conductive portion is used to form the second gate of the first transistor.

[0017] In an exemplary embodiment of the present disclosure, the light-emitting control circuit includes: a fifth transistor and a sixth transistor. The first electrode of the fifth transistor is connected to the first power supply terminal, the second electrode is connected to the second node, and the gate is connected to the enable signal terminal; the first electrode of the sixth transistor is connected to the first node, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the enable signal terminal. The first active layer also includes: a seventh active portion and an eighth active portion. The seventh active portion is used to form a channel region of the fifth transistor, and in the first direction, the orthographic projection of the seventh active portion on the substrate substrate is located between the orthographic projection of the first conductive portion on the substrate substrate and the orthographic projection of the fourth active portion on the substrate substrate; the eighth active portion is used to form a channel region of the sixth transistor, and in the first direction, the orthographic projection of the eighth active portion on the substrate substrate is located between the orthographic projection of the first conductive portion on the substrate substrate and the orthographic projection of the fourth active portion on the substrate substrate. The first conductive layer also includes a third gate line, the orthographic projection of the third gate line on the substrate extends along the second direction, the orthographic projection of the third gate line on the substrate covers the orthographic projections of the seventh active portion and the eighth active portion on the substrate, part of the third gate line is used to form the gate of the fifth transistor, and part of the third gate line is used to form the gate of the sixth transistor.

[0018] In an exemplary embodiment of the present disclosure, the data writing circuit includes a third transistor, the first electrode of the third transistor is connected to the data signal terminal, the second terminal is connected to the first node, and the gate is connected to the first gate drive signal terminal. The compensation circuit includes a fourth transistor, the first electrode of the fourth transistor is connected to the second node, the second electrode is connected to the third node, and the gate is connected to the second gate drive signal terminal. Wherein, the third transistor and the fourth transistor are both P-type low temperature polysilicon transistors. The first active layer also includes: a ninth active portion and a tenth active portion, the ninth active portion is used to form a channel region of the third transistor, the orthogonal projection of the ninth active portion on the substrate is located on the side of the orthogonal projection of the first conductive portion on the substrate in the fourth direction, and the fourth direction is opposite to the first direction; the tenth active portion is used to form a channel region of the fourth transistor, and the orthogonal projection of the tenth active portion on the substrate is located on the side of the orthogonal projection of the first conductive portion on the substrate in the fourth direction. The first conductive layer also includes a fourth gate line, which extends along the second direction under the orthographic projection of the substrate. The orthographic projection of the fourth gate line on the substrate covers the orthographic projections of the ninth active portion and the tenth active portion on the substrate. Part of the fourth gate line is used to form the gate of the third transistor, and part of the fourth gate line is used to form the gate of the fourth transistor.

[0019] In an exemplary embodiment of the present disclosure, the display panel further includes a fifth conductive layer, which is arranged on a side of the third conductive layer away from the substrate. The fifth conductive layer includes: a first power line, a first shielding portion, a first data line, and a second shielding portion. The first power line extends along the first direction in the orthogonal projection of the substrate substrate and includes a first edge; the first shielding portion is connected to the power line, the first shielding portion includes a second edge connected to the first edge of the first power line, the angle between the orthogonal projection of the first edge on the substrate substrate and the orthogonal projection of the second edge on the substrate substrate is less than 180°, and the orthogonal projection of the first shielding portion on the substrate substrate covers the orthogonal projection of the third active portion on the substrate substrate; the orthogonal projection of the first data line on the substrate substrate extends along the first direction and includes a third edge; the second shielding portion is connected to the data line, the second shielding portion includes a fourth edge connected to the third edge of the first data line, the angle between the orthogonal projection of the third edge on the substrate substrate and the orthogonal projection of the fourth edge on the substrate substrate is less than 108°, and the orthogonal projection of the second shielding portion on the substrate substrate covers the orthogonal projection of the second active portion on the substrate substrate.

[0020] In an exemplary embodiment of the present disclosure, the data writing circuit includes a third transistor, the first electrode of the third transistor is connected to the data signal terminal, the second terminal is connected to the first node, and the gate is connected to the first gate drive signal terminal. The compensation circuit includes a fourth transistor, the first electrode of the fourth transistor is connected to the second node, the second electrode is connected to the third node, and the gate is connected to the second gate drive signal terminal. Wherein, the third transistor is a P-type low temperature polysilicon transistor, and the fourth transistor is an N-type oxide transistor. The first active layer also includes an eleventh active portion, the eleventh active portion is used to form a channel region of the third transistor, and the orthogonal projection of the eleventh active portion on the substrate substrate is located on the side of the orthogonal projection of the first conductive portion on the substrate substrate in the fourth direction, and the fourth direction is opposite to the first direction; the first conductive layer also includes a fifth gate line, and the fifth gate line extends along the second direction in the orthogonal projection of the substrate substrate. The fifth gate line covers the eleventh active portion in the orthogonal projection of the substrate substrate, and part of the fifth gate line is used to form the gate of the third transistor. The fourth conductive layer further includes a sixth gate line, the sixth gate line extends along the second direction in the orthogonal projection of the substrate, and the orthogonal projection of the sixth gate line on the substrate is located on the side of the orthogonal projection of the fifth gate line on the substrate in the fourth direction. The second active layer further includes: a twelfth active portion, a thirteenth active portion, and a fourteenth active portion, the twelfth active portion is used to form the first channel region of the fourth transistor, the orthogonal projection of the twelfth active portion on the substrate is located on the orthogonal projection of the sixth gate line on the substrate; the thirteenth active portion is used to form the second channel region of the fourth transistor, the orthogonal projection of the thirteenth active portion on the substrate is located on the orthogonal projection of the sixth gate line on the substrate; the fourteenth active portion is connected between the twelfth active portion and the thirteenth active portion, and the orthogonal projection of the fourteenth active portion on the substrate is located on the side of the orthogonal projection of the sixth gate line on the substrate in the fourth direction. The second conductive layer further includes: a seventh gate line, the orthogonal projection of the seventh gate line on the substrate extends along the second direction, and the orthogonal projection of the seventh gate line on the substrate covers the orthogonal projections of the twelfth active portion and the thirteenth active portion on the substrate.

[0021] In an exemplary embodiment of the present disclosure, the fifth conductive layer further includes a second power line, the second power line extends along the first direction in an orthographic projection on the base substrate, and the orthographic projection of the second power line on the base substrate covers the orthographic projection of the fourteenth active portion on the base substrate.

[0022] In an exemplary embodiment of the present disclosure, the second power line includes a fifth edge, the fifth conductive layer also includes a third shielding portion, the third shielding portion is connected to the second power line, the third shielding portion includes a sixth edge connected to the fifth edge of the second power line, the angle between the sixth edge and the fifth edge in the orthographic projection on the substrate is less than 180°, and the third shielding portion covers the second active portion and the third active portion in the orthographic projection on the substrate.

[0023] According to one aspect of the present disclosure, a display panel is provided, which includes the above-mentioned pixel driving circuit.

[0024] According to one aspect of the present disclosure, a pixel driving circuit driving method is provided, for driving the above-mentioned pixel driving circuit, the driving method comprising:

[0025] In a reset phase, turning on the first transistor and the second transistor to input an initial signal to the third node and the first electrode of the light emitting unit through the initial signal terminal;

[0026] In the compensation phase, the compensation circuit is used to conduct the first node and the third node, and the data writing circuit is used to write a data signal to the first node;

[0027] In the light emitting stage, the light emitting control circuit is used to connect the first power supply terminal and one electrode of the driving transistor, and to connect the first electrode of the light emitting unit and the other electrode of the driving transistor.

[0028] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0030] Figure 1 A schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed in the present invention;

[0031] Figure 2 is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit disclosed in the present invention;

[0032] Figure 3 for Figure 2 A timing diagram of each node in a driving method of a pixel driving circuit;

[0033] Figure 4 is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit disclosed in the present invention;

[0034] Figure 5 is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit disclosed in the present invention;

[0035] Figure 6 A structural layout diagram of a first active layer in an exemplary embodiment of a display panel disclosed herein;

[0036] Figure 7 A structural layout diagram of a first conductive layer in an exemplary embodiment of a display panel disclosed herein;

[0037] Figure 8 A structural layout diagram of a fourth conductive layer in an exemplary embodiment of the display panel disclosed herein;

[0038] Fig. 9 A structural layout of a second active layer in an exemplary embodiment of a display panel disclosed herein;

[0039] Fig.10 A structural layout of a second conductive layer in an exemplary embodiment of a display panel disclosed herein;

[0040] Fig.11 A stacked structure layout of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, and a second conductive layer in an exemplary embodiment of a display panel disclosed herein;

[0041] Fig.12 A structural layout diagram of a third conductive layer in an exemplary embodiment of a display panel disclosed herein;

[0042] Fig.13 A stacked structure layout of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, a second conductive layer, and a third conductive layer in an exemplary embodiment of a display panel disclosed herein;

[0043] Fig.14 A structural layout diagram of a fifth conductive layer in an exemplary embodiment of the display panel disclosed herein;

[0044] Fig.15 A stacked structure layout of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, a second conductive layer, a third conductive layer, and a fifth conductive layer in an exemplary embodiment of a display panel disclosed herein;

[0045] Fig.16 For along Fig.15 A partial cross-sectional view of the dashed line AA;

[0046] Fig.17A structural layout diagram of a first active layer in another exemplary embodiment of a display panel disclosed herein;

[0047] Fig.18 A structural layout diagram of a first conductive layer in another exemplary embodiment of a display panel disclosed herein;

[0048] Fig.19 A structural layout diagram of a fourth conductive layer in another exemplary embodiment of the display panel disclosed herein;

[0049] Fig. 20 A structural layout diagram of a second active layer in another exemplary embodiment of a display panel disclosed herein;

[0050] Fig.21 A structural layout diagram of a second conductive layer in another exemplary embodiment of a display panel disclosed herein;

[0051] Fig. 22 A layout diagram of a stacked structure of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, and a second conductive layer in another exemplary embodiment of a display panel disclosed herein;

[0052] Fig.23 A structural layout diagram of a third conductive layer in another exemplary embodiment of the display panel disclosed herein;

[0053] Fig.24 A layout diagram of a stacked structure of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, a second conductive layer, and a third conductive layer in another exemplary embodiment of a display panel disclosed herein;

[0054] Fig.25 A structural layout diagram of a fifth conductive layer in another exemplary embodiment of the display panel disclosed herein;

[0055] Fig.26 A layout of a stacked structure of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, a second conductive layer, a third conductive layer, and a fifth conductive layer in another exemplary embodiment of a display panel disclosed herein;

[0056] Fig. 27 For along Fig.26 Partial cross-sectional view along the dashed line AA. DETAILED DESCRIPTION

[0057] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0058] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". Other relative terms, such as "high", "low", "top", "bottom", "left", "right", etc., also have similar meanings. When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0059] The terms "a", "an", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to indicate an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0060] This exemplary embodiment provides a pixel driving circuit such as Figure 1As shown, it is a structural schematic diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure. The pixel driving circuit may include: a driving transistor DT, a data writing circuit 1, a compensation circuit 2, a light emitting control circuit 3, a storage circuit 4, and a reset circuit 5. The first electrode of the driving transistor DT is connected to the first node N1, the second electrode is connected to the second node N2, and the gate is connected to the third node N3; the data writing circuit 1 is connected to the first node N1 and the data signal terminal Da, and is used to respond to a control signal to transmit the signal of the data signal terminal Da to the first node N1; the compensation circuit 2 is connected to the second node N2 and the third node N3, and is used to respond to a control signal to connect the second node N2 and the third node N3; the light emitting control circuit is connected to the first electrode and the second electrode of the driving transistor DT, the first power supply terminal VDD, the first electrode of the light emitting unit OLED, and the enable signal terminal EM, and the light emitting control circuit 3 is used to connect the first power supply terminal VDD and the first electrode of the driving transistor DT (i.e., the first node N1), and connect the first electrode of the light emitting unit OLED and the second electrode of the driving transistor DT (i.e., the second node N2) in response to the signal of the enable signal terminal EM; the reset circuit includes: a first transistor T1 and a second transistor T2. The first electrode of the first transistor T1 is connected to the third node N3, the second electrode is connected to the first electrode of the light-emitting unit OLED, and the gate is connected to the reset signal terminal Re; the first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, the second electrode is connected to the initial signal terminal Vinit, and the gate is connected to the reset signal terminal Re; wherein the first transistor T1 and the second transistor T2 are N-type oxide transistors, and the driving transistor DT is a P-type low-temperature polysilicon transistor. wherein the first electrode of the light-emitting unit OLED can be the anode of the light-emitting unit, and the cathode of the light-emitting unit OLED can be connected to the second power supply terminal VSS.

[0061] In the reset stage, the pixel driving circuit can turn on the first transistor T1 and the second transistor T2 to input the initial signal to the third node N3 and the first electrode of the light-emitting unit OLED through the initial signal terminal Vinit; in the compensation stage, the compensation circuit 2 can be used to turn on the first node N1 and the third node N3, and at the same time, the data writing circuit 1 is used to write the data signal to the first node N1, so as to write the voltage Vdata+Vth to the third node and store it in the storage circuit, wherein Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor; in the light-emitting stage, the light-emitting control circuit 3 is used to connect the first power supply terminal VDD and the first electrode of the driving transistor DT (i.e., the second node N1), and to connect the first electrode of the light-emitting unit OLED and the second electrode of the driving transistor DT (i.e., the second node N2), and the driving transistor DT outputs a driving current to the light-emitting unit OLED under the action of the charge of the third node N3.

[0062] In this exemplary embodiment, on the one hand, the driving transistor DT in the pixel driving circuit can be a P-type low-temperature polysilicon transistor, which has a higher carrier mobility, so that the pixel driving circuit is conducive to realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio; on the other hand, the first transistor T1 and the second transistor T2 are N-type oxide transistors, and the oxide transistor has a smaller leakage current, so that the leakage current of the third node N3 through the first transistor T1 and the second transistor T2 can be reduced in the light-emitting stage of the pixel driving circuit. On the other hand, the first transistor T1 and the second transistor T2 are connected in series between the third node N3 and the initial signal terminal Vinit, so that the leakage current from the third node N3 to the initial signal terminal Vinit can be reduced; on the other hand, in the reset stage, the voltage written to the third node N3 by the initial signal terminal Vinit needs to be able to turn on the driving transistor DT, so as to write the voltage Vdata+Vth to the third node N3 in the compensation stage. Therefore, the voltage of the initial signal terminal Vinit is small, generally a negative value. In the light-emitting stage, the voltage of the second node N2 is less than the voltage of the third node N3 and greater than the voltage of the initial signal terminal Vinit, that is, the voltage of the first electrode of the light-emitting unit OLED is less than the voltage of the third node N3 and greater than the voltage of the initial signal terminal Vinit. At the same time, since the second electrode of the first transistor T1 is connected to the first electrode of the light-emitting unit OLED, the voltage of the first electrode of the light-emitting unit OLED can effectively isolate the larger cross-voltage between the third node N3 and the initial signal terminal Vinit, thereby reducing the leakage current from the third node to the initial signal terminal Vinit.

[0063] exist Figure 1 In the pixel driving circuit shown, the voltage of the second node N2 changes with the voltage of the third node N3. For example, in the high grayscale state, the voltage of the third node N3 is low and the voltage of the second node is high. In the low grayscale state, the voltage of the third node N3 is high and the voltage of the second node is low. Therefore, under different display grayscales, there are different voltage differences between the third node N3 and the second node N2, so that under different display grayscales, the third node N3 has different leakage currents to the second node N. In particular, under the low grayscale state, the leakage current from the third node N3 to the second node N2 is large. At the same time, because the human eye is highly sensitive to brightness changes under low brightness, the leakage current from the third node N3 to the second node N2 will seriously affect the display effect of the display panel.

[0064] like Figure 2, which is a schematic diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. The light emitting control circuit 3 can be used to connect the first power supply terminal VDD and the second electrode of the driving transistor DT (i.e., the second node N2) in response to the signal of the enable signal terminal EM, and to connect the first electrode of the light emitting unit OLED and the first electrode of the driving transistor DT (i.e., the first node N1). Other structures of the pixel driving circuit can be the same as Figure 1 The pixel driving circuits shown are the same.

[0065] In this exemplary embodiment, the first power supply terminal VDD is connected to the second node N2, and the first electrode of the light-emitting unit OLED is connected to the first node. In the light-emitting stage, the voltage of the second node N2 is stabilized to the voltage of the first power supply terminal VDD, and the voltage of the second node N2 does not change with the change of the driving grayscale. Therefore, the pixel driving circuit has a relatively stable driving effect. In particular, in the low grayscale driving state, the voltage of the third node N3 is relatively high, and the voltage of the second node N2 is also relatively high, and the third node N3 has a small leakage current to the second node N2.

[0066] In this exemplary embodiment, Figure 1 , 2 As shown, the data writing circuit 1 may include a third transistor T3, a first electrode of the third transistor T3 is connected to the data signal terminal Da, a second terminal is connected to the first node N1, and a gate is connected to the first gate driving signal terminal Gate1.

[0067] In this exemplary embodiment, Figure 1 , 2 As shown, the compensation circuit 2 may include a fourth transistor T4, a first electrode of the fourth transistor T4 is connected to the second node N2, a second electrode is connected to the third node N3, and a gate is connected to the first gate drive signal terminal Gate1; wherein the third transistor T3 and the fourth transistor T4 may both be P-type low-temperature polysilicon transistors.

[0068] In this exemplary embodiment, Figure 1 As shown, the light emitting control circuit 3 may include a fifth transistor T5 and a sixth transistor T6, wherein the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first node N1, and the gate is connected to the enable signal terminal EM; the first electrode of the sixth transistor T6 is connected to the second node N2, the second electrode is connected to the first electrode of the light emitting unit OLED, and the gate is connected to the enable signal terminal EM. The fifth transistor T5 and the sixth transistor T6 may be P-type low temperature polysilicon transistors.

[0069] In this exemplary embodiment, Figure 2As shown, the light emitting control circuit 3 may include a fifth transistor T5 and a sixth transistor T6, wherein the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the second node N2, and the gate is connected to the enable signal terminal EM; the first electrode of the sixth transistor T6 is connected to the first node N1, the second electrode is connected to the first electrode of the light emitting unit OLED, and the gate is connected to the enable signal terminal EM. The fifth transistor T5 and the sixth transistor T6 may be P-type low temperature polysilicon transistors.

[0070] In this exemplary embodiment, Figure 1 , 2 As shown, the storage circuit 4 may include a capacitor C, and the capacitor C may be connected between the first power supply terminal VDD and the third node N3. It should be understood that the capacitor C may also be connected between the third node N3 and other stable signal terminals.

[0071] like Figure 3 As shown, Figure 2 A timing diagram of each node in a driving method of a pixel driving circuit. Among them, EM represents the signal timing of the enable signal terminal, Re represents the signal timing of the reset signal terminal, and Gate1 represents the signal timing of the first gate driving signal terminal. The driving method of the pixel driving circuit includes three stages: a reset stage T1, a compensation stage T2, and a light-emitting stage T3. In the reset stage T1, the reset signal terminal outputs a high-level signal to turn on the first transistor T1 and the second transistor T2, and the signal of the initial signal terminal Vinit is transmitted to the third node and the first electrode of the light-emitting unit OLED, wherein the driving transistor DT is turned on under the action of the signal of the initial signal terminal; in the compensation stage T2, the first gate driving signal terminal Gate1 outputs a low-level signal, the third transistor T3 and the fourth transistor T4 are turned on, and the data signal terminal writes a voltage Vdata+Vth to the third node, wherein Vdata is the voltage of the data signal terminal, and Vth is the threshold voltage of the driving transistor; in the light-emitting stage T3, the enable signal terminal outputs a low-level signal to turn on the sixth transistor T6 and the fifth transistor T5, and the driving transistor DT emits light under the action of the voltage Vdata+Vth stored in the capacitor C. The output current formula of the driving transistor I=(μWCox / 2L)(Vgs-Vth) 2 , where μ is carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current of the driving transistor in the pixel driving circuit of the present disclosure is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0072] In this exemplary embodiment, Figure 4 FIG. 1 is a schematic diagram of another exemplary embodiment of a pixel driving circuit disclosed in the present invention. Figure 2 Compared with the pixel driving circuit shown in FIG. 1 , the difference is that the third transistor T3 can be a P-type low-temperature polysilicon transistor, and the fourth transistor T4 can be an N-type oxide transistor. Accordingly, the fourth transistor T4 can be connected to the second gate driving signal terminal Gate2 to turn on the fourth transistor T4 through the second gate driving signal terminal Gate2 during the compensation stage. Among them, the oxide transistor has a smaller leakage current, so that the third node N3 can be reduced to leak to the second node through the fourth transistor during the light-emitting stage of the pixel driving circuit.

[0073] In this exemplary embodiment, Figure 5 FIG. 1 is a schematic diagram of another exemplary embodiment of a pixel driving circuit disclosed in the present invention. Figure 2 Compared with the pixel driving circuit shown in the figure, the difference is that the third transistor T3 and the fourth transistor T4 can both be N-type oxide transistors. The third transistor T3 and the fourth transistor T4 can both be turned on under the high level of the first gate driving signal terminal Gate1 in the compensation stage to write the compensation voltage to the third node. This setting can realize the driving of the third transistor T3 and the fourth transistor T4 only through the first gate driving signal terminal Gate1 while reducing the leakage of the third node N3 to the second node through the fourth transistor, that is, the display panel using the pixel driving circuit can drive the third transistor T3 and the fourth transistor T4 simultaneously through one gate driving circuit.

[0074] In this exemplary embodiment, Figure 1 , 2 The third transistor T3 and the fourth transistor T4 in , 4 and 5 may both be dual-gate structures, that is, the third transistor T3 and the fourth transistor T4 may include two active regions. This arrangement may reduce the leakage current of the third transistor T3 and the fourth transistor T4.

[0075] The present exemplary embodiment also provides a display panel, which may include Figure 2 The pixel driving circuit shown in FIG. Figure 6-15 As shown, Figure 6 A structural layout diagram of a first active layer in an exemplary embodiment of a display panel disclosed herein; Figure 7 A structural layout diagram of a first conductive layer in an exemplary embodiment of a display panel disclosed herein; Figure 8 A structural layout diagram of a fourth conductive layer in an exemplary embodiment of the display panel disclosed herein; Fig. 9 A structural layout of a second active layer in an exemplary embodiment of a display panel disclosed herein; Fig.10 A structural layout of a second conductive layer in an exemplary embodiment of a display panel disclosed herein; Fig.11 A stacked structure layout of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, and a second conductive layer in an exemplary embodiment of a display panel disclosed herein; Fig.12 A structural layout diagram of a third conductive layer in an exemplary embodiment of a display panel disclosed herein; Fig.13 A stacked structure layout of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, a second conductive layer, and a third conductive layer in an exemplary embodiment of a display panel disclosed herein; Fig.14 A structural layout diagram of a fifth conductive layer in an exemplary embodiment of the display panel disclosed herein; Fig.15 This is a layout of the stacked structure of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, a second conductive layer, a third conductive layer, and a fifth conductive layer in an exemplary embodiment of the display panel disclosed herein.

[0076] like Figure 6-13As shown, the display panel may include: a substrate 1, a first active layer, a first conductive layer, a second active layer, a second conductive layer, and a third conductive layer. The first active layer is located on one side of the substrate 1, and the first active layer includes a first active portion 21, and the first active portion 21 is used to form a channel region of the driving transistor DT; the first conductive layer may be located on the side of the first active layer away from the substrate 1, and the first conductive layer may include a first conductive portion 31, and the orthographic projection of the first conductive portion 31 on the substrate covers the orthographic projection of the first active portion 21 on the substrate, and the first conductive portion 31 is used to form a gate of the driving transistor DT. The second active layer may be located on the side of the first conductive layer away from the substrate 1, and the second active layer may include: a second active portion 42, a third active portion 43, a fourth active portion 44, a fifth active portion 45, and a sixth active portion 46. The second active portion 42 is located on the side of the first conductive portion 31 on the substrate substrate in the first direction Y1. The third active portion 43 is located on the side of the first conductive portion 31 on the substrate substrate in the first direction Y1. The third active portion 43 is located on the side of the first conductive portion 31 on the substrate substrate in the first direction Y1. The third active portion 43 is located on the side of the second active portion 42 on the substrate substrate in the second direction X1. The first direction Y1 intersects with the second direction X1. For example, the first direction Y1 is perpendicular to the second direction X1. The fourth active portion 44 is connected between the second active portion 42 and the third active portion 43. The fourth active portion 44 is located on the side of the third active portion 43 on the substrate substrate in the third direction X2. The second direction X1 is opposite to the third direction X2. In the first direction Y1, the fourth active portion 44 is located between the first conductive portion 31 on the substrate substrate and the second active portion 42 on the substrate substrate. The fifth active portion 45 may be connected to the second active portion 42, and the fifth active portion 45 may be located on the side of the second active portion 42 projected on the substrate substrate in the first direction Y1. The sixth active portion 46 may be connected to the third active portion 43, and the sixth active portion 46 may be located on the side of the third active portion 43 projected on the substrate substrate in the second direction X1. The second conductive layer may be disposed on the side of the second active layer away from the substrate substrate, and the second conductive layer may include: a first gate line 51, a first protrusion 52, wherein the first gate line 51 may be used to provide Figure 2The reset signal terminal in the substrate. The first gate line 51 extends along the second direction X1 in the orthographic projection of the substrate, and the first gate line 51 may include a second conductive portion 512, the orthographic projection of the second conductive portion 512 in the substrate may coincide with the orthographic projection of the second active portion 42 in the substrate, and the second conductive portion 512 may be used to form the first gate of the second transistor T2; the first protrusion 52 may be connected to the first gate line 51, and in the first direction, the orthographic projection of the first protrusion 52 in the substrate may be located between the orthographic projection of the first gate line 51 in the substrate and the orthographic projection of the first conductive portion 31 in the substrate, and the first protrusion 52 may include a third conductive portion 523, the orthographic projection of the third conductive portion 523 in the substrate may coincide with the orthographic projection of the third active portion 43 in the substrate, and the third conductive portion 523 may be used to form the first gate of the first transistor T1. The first active layer may be formed of a low-temperature polysilicon material, and the second active layer may be formed of an indium gallium zinc oxide material.

[0077] like Figure 8 , 11 As shown, the display panel may further include a fourth conductive layer, which is disposed between the first conductive layer and the second active layer. The fourth conductive layer may include: a second gate line 81 and a second protrusion 82, wherein the second gate line 81 may provide Figure 2 The reset signal end in the display panel, the second gate line 81 can be connected to the first gate line 51 through a via in the peripheral wiring area of ​​the display panel. The second gate line 81 extends along the second direction X1 in the orthographic projection of the substrate substrate, and the second gate line 81 can include a fourth conductive portion 814, the orthographic projection of the second active portion 42 on the substrate substrate can be located on the orthographic projection of the fourth conductive portion 814 on the substrate substrate, and the fourth conductive portion 814 can be used to form the second gate of the second transistor T2; the second protruding portion 82 can be connected to the second gate line 81, in the first direction Y1, the orthographic projection of the second protruding portion 82 on the substrate substrate can be located between the orthographic projection of the second gate line 81 on the substrate substrate and the orthographic projection of the first conductive portion 31 on the substrate substrate, the second protruding portion 82 can include a fifth conductive portion 825, the orthographic projection of the third active portion 43 on the substrate substrate can be located on the orthographic projection of the fifth conductive portion 825 on the substrate substrate, and the fifth conductive portion 825 can be used to form the second gate of the first transistor T1.

[0078] like Figure 8 , 11As shown, the fourth conductive layer may further include a sixth conductive portion 86 , the orthographic projection of the sixth conductive portion 86 on the base substrate covers the orthographic projection of the first conductive portion on the base substrate, and the sixth conductive portion 86 may be used to form an electrode of the capacitor C. An opening 861 may be provided on the sixth conductive portion 86 .

[0079] like Figure 7 , 12 As shown in FIG. 13 , the third conductive layer may be disposed on a side of the second conductive layer away from the substrate, and the third conductive layer may include: a first connecting portion 61 and an initial signal line 62. The initial signal line 62 may be used to provide Figure 2 The first connection portion 61 can be connected to the sixth active portion 46 through the via 71, and the first connection portion 61 can also be connected to the first conductive portion 31 through the via 78, so that the gate of the driving transistor DT and the first electrode of the first transistor T1 can be connected. The opening 861 of the via 78 located on the sixth conductive portion 86 in the orthographic projection of the substrate substrate is within the orthographic projection of the substrate substrate, that is, the edge of the orthographic projection of the via 78 on the substrate substrate and the edge of the orthographic projection of the opening 861 on the substrate substrate have a certain distance, so that the conductive material filled in the via 78 can be insulated from the sixth conductive portion 86.

[0080] like Figure 7 , 12 As shown in FIG. 13 , the orthographic projection of the initial signal line 62 on the substrate can extend along the second direction X1, and the orthographic projection of the initial signal line 62 on the substrate can be located on one side of the orthographic projection of the first gate line 51 on the substrate in the first direction Y1, wherein the initial signal line 62 can provide Figure 2 The initial signal end in the first transistor T2 can be connected to the first active portion 45 through the via 72, thereby realizing the connection between the second electrode of the second transistor T2 and the initial signal end.

[0081] In this exemplary embodiment, Fig. 9 , 11As shown, in the first direction Y1, the fourth active portion 44 and the sixth active portion 46 may be located between the first conductive portion 31 and the first gate line 51 on the substrate in the orthographic projection of the substrate, the fourth active portion 44 may be connected to the driving transistor through the conductive structure between the first conductive portion 31 and the first gate line 51, and the sixth active portion 46 may be electrically connected to the first conductive portion 31 through the conductive structure between the first gate line 51 and the first conductive portion 31, so that the pixel driving circuit of the display panel has a high degree of integration. In addition, the first transistor T1 and the second transistor T2 both adopt a dual-gate structure, the first gate line 51 and the second gate line 81 may simultaneously provide gate voltages to the first transistor T1 and the second transistor T2, and this arrangement may increase the response speed of the first transistor T1 and the second transistor T2, and at the same time, the gates of the first transistor T1 and the second transistor T2 located in the fourth conductive layer may shield their channel regions, thereby avoiding the influence of light on the characteristics of the channel regions of the first transistor T1 and the second transistor T2, so as to improve the electrical stability of the first transistor T1 and the second transistor T2. It should be understood that in other exemplary embodiments, the display panel may not be provided with the second gate line 81 .

[0082] In this exemplary embodiment, Figure 6 , 7 As shown in , 11, the first active layer may further include: a seventh active portion 27 and an eighth active portion 28. The seventh active portion 27 may be used to form a channel region of the fifth transistor T5, and in the first direction Y1, the orthographic projection of the seventh active portion 27 on the substrate may be located between the orthographic projection of the first conductive portion 31 on the substrate and the orthographic projection of the fourth active portion 44 on the substrate. The eighth active portion 28 may be used to form a channel region of the sixth transistor T6, and in the first direction Y1, the orthographic projection of the eighth active portion 28 on the substrate may be located between the orthographic projection of the first conductive portion 31 on the substrate and the orthographic projection of the fourth active portion 44 on the substrate. The first conductive layer may further include a third gate line 33, and the orthographic projection of the third gate line 33 on the substrate may extend along the second direction X1, and the third gate line 33 may be used to provide Figure 2 The third gate line 33 may include a first gate portion 331 and a second gate portion 332. The orthographic projection of the first gate portion 331 on the substrate may cover the seventh active portion 27, and the orthographic projection of the second gate portion 332 on the substrate may cover the orthographic projection of the eighth active portion 28 on the substrate. The first gate portion 331 may be used to form the gate of the fifth transistor T5, and the second gate portion 332 may be used to form the gate of the sixth transistor.

[0083] In this exemplary embodiment, Figure 6 , 7 As shown in Figure 11, the first active layer may also include: a ninth active portion 29 and a tenth active portion 210, the ninth active portion 29 is used to form the channel region of the third transistor T3, and the orthographic projection of the ninth active portion 29 on the substrate is located on the side of the orthographic projection of the first conductive portion 31 on the substrate in the fourth direction Y2, and the fourth direction X2 is opposite to the first direction Y1; the tenth active portion 210 is used to form the channel region of the fourth transistor T4, and the orthographic projection of the tenth active portion 210 on the substrate is located on the side of the orthographic projection of the first conductive portion 31 on the substrate in the fourth direction Y2. The first conductive layer may further include a fourth gate line 34, the fourth gate line 34 may extend along the second direction X1 when projected on the substrate, and the fourth gate line 34 may include a third gate portion 343 and a fourth gate portion 344, the third gate portion 343 may cover the ninth active portion 29 when projected on the substrate, and the fourth gate portion 344 may cover the tenth active portion 210 when projected on the substrate. The third gate portion 343 may be used to form a gate of the third transistor T3, and the fourth gate portion 344 may be used to form a gate of the fourth transistor T4.

[0084] In this exemplary embodiment, Fig.12 , 13 As shown, the third conductive layer also includes: a third connection part 63, a fourth connection part 64, and a fifth connection part 65. The third connection part 63 is connected to the fourth active part 44 through a via 73, and is connected to the active part 219 on one side of the eighth active part through the via 74 to connect the second pole of the first transistor T1 and the second pole of the sixth transistor T6. The third connection part 63 can also be connected to the fourth active part 44 through multiple vias, for example, the third connection part 63 can be connected to the fourth active part 44 through two vias. The fourth connection part 64 can be connected to one side of the seventh active part 27 through a via 75, and the fourth connection part 64 is also connected to the sixth conductive part 86 through a via 77, thereby connecting the first pole of the fifth transistor T5 and an electrode of the capacitor C. The fifth connection part 65 is connected to one side of the ninth active part through a via 76 to connect the first pole of the third transistor T3. It should be understood that the first connection part 61, the third connection part 63, the fourth connection part 64, and the fifth connection part 65 as a transfer layer can also be located in other conductive layers. For example, the first connection part 61 can also be located in any layer of the second conductive layer and the fifth conductive layer; the third connection part 63 can also be located in any layer of the first conductive layer, the second conductive layer, the fourth conductive layer and the fifth conductive layer; the fourth connection part 64 can also be located in the second conductive layer; the fifth connection part 65 can also be located in any layer of the second conductive layer and the fourth conductive layer.

[0085] like Fig.14 , 15 As shown, the display panel may further include a fifth conductive layer, and the fifth conductive layer may be arranged on the side of the third conductive layer away from the base substrate. The fifth conductive layer may include: a first power line 91, a first shielding portion 92, a first data line 93, and a second shielding portion 94. The first power line 91 may extend along the first direction Y1 in the orthographic projection of the base substrate, and include a first edge 911; the first shielding portion 92 is connected to the power line 91, and the first shielding portion 92 includes a second edge 922 connected to the first edge 911 of the first power line 91, and the angle between the orthographic projection of the first edge 911 on the base substrate and the orthographic projection of the second edge 922 on the base substrate is less than 180°. That is, the first shielding portion 92 is located on the side of the orthographic projection of the first power line 91 on the base substrate, as shown in FIG. Fig.14 , 15 The first shielding portion 92 may be located on the side of the orthogonal projection of the first power line 91 on the substrate substrate in the third direction X2. In this exemplary embodiment, the orthogonal projection of the first shielding portion 92 on the substrate substrate may cover the orthogonal projection of the third active portion 43 on the substrate substrate. The first shielding portion 92 may prevent the influence of light on the characteristics of the channel region of the first transistor T1, so as to improve the electrical stability of the first transistor T1. The orthogonal projection of the first data line 93 on the substrate substrate may extend along the first direction Y1, and include a third edge 933; the second shielding portion 94 may be connected to the data line 93, and the second shielding portion 94 may include a fourth edge 944 connected to the third edge 933 of the first data line, and the angle between the orthogonal projection of the third edge 933 on the substrate substrate and the orthogonal projection of the fourth edge 944 on the substrate substrate is less than 108°. That is, the orthogonal projection of the second shielding portion 94 on the substrate substrate is located on the side of the orthogonal projection of the data line 93 on the substrate substrate, such as Fig.14 , 15 As shown, the second shielding portion 94 may be located on one side of the data line 93 on the substrate in the second direction X1. The second shielding portion 944 may cover the second active portion 42 on the substrate in the substrate. The second shielding portion 944 may prevent the influence of light on the channel region characteristics of the second transistor T2, so as to improve the electrical stability of the second transistor T2. The first power line 91 may provide Figure 2 The first power supply terminal in the data line 93 can provide Figure 2 The first power line 91 can be connected to the fourth connection part 64 through the via 79 to connect to the first electrode of the fifth transistor T5. The data line 93 can be connected to the fifth connection part 65 through the via 710 to connect to the first electrode of the third transistor. Fig.14 , 15 As shown, the fifth conductive layer may further include a connecting portion 99, which may be connected to the third connecting portion 63 through a via 716, and the connecting portion 99 may also be connected to the anode of the light emitting unit through the via, so that the second electrode of the sixth transistor T6 is connected to the anode of the light emitting unit.

[0086] It should be understood that in other exemplary embodiments, the fifth conductive layer may further include a shielding layer connected to the first power line 91, the orthographic projection of the shielding layer on the substrate may cover the orthographic projection of the first conductive portion 31 on the substrate, and the shielding layer may shield the influence of other signals on the gate voltage of the driving transistor.

[0087] like Fig.16 As shown, along Fig.15 Partial cross-sectional view of the dashed line AA. The display panel also includes: a blocking layer 101, a first gate insulating layer 102, a second gate insulating layer 103, a third gate insulating layer 104, a buffer layer 105, a fourth gate insulating layer 106, a first dielectric layer 107, a second dielectric layer 108, a passivation layer 109, and a first flat layer 110. Among them, the base substrate 1, the blocking layer 101, the first active layer, the first gate insulating layer 102, the first conductive layer, the second gate insulating layer 103, the fourth conductive layer, the third gate insulating layer 104, the buffer layer 105, the second active layer, the fourth gate insulating layer 106, the second conductive layer, the first dielectric layer 107, the second dielectric layer 108, the third conductive layer, the passivation layer 109, the first flat layer 110, and the fifth conductive layer are stacked in sequence. Among them, the third connecting portion 63 can be connected to the fourth active portion 44 through the via 73, and connected to the active portion 219 through the via 74. The connection portion 99 in the fifth conductive layer can be connected to the third connection portion 63 through the via 716, and the connection portion 99 can also be connected to the anode layer located on the side of the fifth conductive layer away from the substrate through the via to connect the anode of the light emitting unit. A second flat layer can also be provided between the fifth conductive layer and the anode layer.

[0088] Among them, the materials of the dielectric layer and the passivation layer can be inorganic materials, such as at least one of silicon nitride, silicon oxide, silicon oxynitride or a combination thereof; or organic materials, such as: transparent polyimide (CPI), polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) and other materials.

[0089] The material of the conductive layer can also be at least one of copper, molybdenum, titanium, aluminum, nickel, silver, indium tin oxide (ITO), etc. or a combination thereof, or an alloy material of the above materials, or a stack, such as a titanium / aluminum / titanium triple stack.

[0090] The barrier layer and the buffer layer may be made of inorganic materials, for example, at least one of silicon nitride, silicon oxide, and silicon oxynitride, or a combination thereof.

[0091] The material of the planar layer may be an organic material, for example, transparent polyimide (CPI), polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) and the like.

[0092] The material of the gate insulating layer may be an inorganic material, for example, at least one of silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.

[0093] It should be understood that Fig.16 It only reflects the relative positions of the various layers of the display panel, and does not represent the specific structure of the display panel. In the actual structure of the display panel, the inorganic layer (including other insulating layers other than the flat layer) formed on the protruding structure will conformally cover the protruding structure. For example, the first gate insulating layer 102 will conformally cover the first active portion 21, and the third gate insulating layer 104 will conformally cover the fourth conductive portion 814.

[0094] In this exemplary embodiment, Fig.16 , vias 71, 72, 73 may penetrate the fourth gate insulating layer 106, the first dielectric layer 107, and the second dielectric layer 108; vias 74, 75, 76 may penetrate the first gate insulating layer 102, the second gate insulating layer 103, the third gate insulating layer 104, the buffer layer 105, the fourth gate insulating layer 106, the first dielectric layer 107, and the second dielectric layer 108; via 77 may penetrate the third gate insulating layer 104, the buffer layer 105, the fourth gate insulating layer 106, the first dielectric layer 107, and the second dielectric layer 108; vias 79, 710, 716 may penetrate the passivation layer 109 and the first flat layer 110. It should be noted that in the embodiment of the present disclosure, the passivation layer 109 may be omitted according to actual design requirements, that is, the passivation layer 109 may not be disposed on the third conductive layer (including the first connecting portion 61 pattern, etc.), and the first flat layer 110 may be directly disposed.

[0095] This exemplary embodiment also provides another display panel, which may include Figure 4 The pixel driving circuit shown in FIG. Figure 17-26 As shown, Fig.17 A structural layout diagram of a first active layer in another exemplary embodiment of a display panel disclosed herein; Fig.18 A structural layout diagram of a first conductive layer in another exemplary embodiment of a display panel disclosed herein; Fig.19 A structural layout diagram of a fourth conductive layer in another exemplary embodiment of the display panel disclosed herein; Fig. 20A structural layout diagram of a second active layer in another exemplary embodiment of a display panel disclosed herein; Fig.21 A structural layout diagram of a second conductive layer in another exemplary embodiment of a display panel disclosed herein; Fig. 22 A layout diagram of a stacked structure of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, and a second conductive layer in another exemplary embodiment of a display panel disclosed herein; Fig.23 A structural layout diagram of a third conductive layer in another exemplary embodiment of the display panel disclosed herein; Fig.24 A layout diagram of a stacked structure of a first active layer, a first conductive layer, a fourth conductive layer, a second active layer, a second conductive layer, and a third conductive layer in another exemplary embodiment of a display panel disclosed herein; Fig.25 A structural layout diagram of a fifth conductive layer in another exemplary embodiment of the display panel disclosed herein; Fig.26 This is a layout of the stacked structure of the first active layer, the first conductive layer, the fourth conductive layer, the second active layer, the second conductive layer, the third conductive layer, and the fifth conductive layer in another exemplary embodiment of the display panel disclosed herein.

[0096] like Figure 17-24As shown, the display panel may include: a substrate 1, a first active layer, a first conductive layer, a second active layer, a second conductive layer, and a third conductive layer. The first active layer is located on one side of the substrate 1, and the first active layer may include a first active portion 21, and the first active portion 21 is used to form a channel region of the driving transistor DT; the first conductive layer may be located on the side of the first active layer away from the substrate 1, and the first conductive layer may include a first conductive portion 31, and the orthographic projection of the first conductive portion 31 on the substrate covers the orthographic projection of the first active portion 21 on the substrate, and the first conductive portion 31 is used to form a gate of the driving transistor DT. The second active layer may be located on the side of the first conductive layer away from the substrate 1, and the second active layer may include: a second active portion 42, a third active portion 43, a fourth active portion 44, a fifth active portion 45, and a sixth active portion 46. The second active portion 42 is located on the side of the orthographic projection of the first conductive portion 31 on the substrate substrate in the first direction Y1; in the first direction Y1, the orthographic projection of the third active portion 43 on the substrate substrate is located between the orthographic projection of the first conductive portion 31 on the substrate substrate and the orthographic projection of the second active portion 42 on the substrate substrate, and the orthographic projection of the third active portion 43 on the substrate substrate is located on the side of the orthographic projection of the second active portion 42 on the substrate substrate in the second direction X1, and the first direction Y1 intersects with the second direction X1, for example, the first direction Y1 is perpendicular to the second direction X1. The fourth active portion 44 is connected between the second active portion 42 and the third active portion 43, and the orthographic projection of the fourth active portion 44 on the substrate substrate is located on the side of the orthographic projection of the third active portion 43 on the substrate substrate in the third direction X2. The second direction X1 is opposite to the third direction X2, and in the first direction Y1, the orthographic projection of the fourth active portion 44 on the substrate substrate is located between the orthographic projection of the first conductive portion 31 on the substrate substrate and the orthographic projection of the second active portion 42 on the substrate substrate. The fifth active portion 45 can be connected to the second active portion 42, and the orthographic projection of the fifth active portion 45 on the substrate substrate can be located on the side of the orthographic projection of the second active portion 42 on the substrate substrate in the first direction Y1. The sixth active portion 46 is connected to the third active portion 43, and the orthographic projection of the sixth active portion 46 on the substrate substrate is located on the side of the orthographic projection of the third active portion 43 on the substrate substrate in the second direction X1. The second conductive layer may be disposed on a side of the second active layer away from the substrate, and the second conductive layer may include: a first gate line 51 and a first protrusion 52, wherein the first gate line 51 may be used to provide Figure 4The first gate line 51 extends along the second direction X1 in the orthographic projection of the substrate, and the first gate line 51 may include a second conductive portion 512, the orthographic projection of the second conductive portion 512 in the substrate may coincide with the orthographic projection of the second active portion 42 in the substrate, and the second conductive portion 512 may be used to form the first gate of the second transistor T2; the first protrusion 52 may be connected to the first gate line 51, and in the first direction Y1, the orthographic projection of the first protrusion 52 in the substrate may be located between the orthographic projection of the first gate line 51 in the substrate and the orthographic projection of the first conductive portion 31 in the substrate, and the first protrusion 52 may include a third conductive portion 523, the orthographic projection of the third conductive portion 523 in the substrate may coincide with the orthographic projection of the third active portion 43 in the substrate, and the third conductive portion 523 may be used to form the first gate of the first transistor T1. The first active layer may be formed of a low-temperature polysilicon material, and the second active layer may be formed of an indium gallium zinc oxide material.

[0097] like Fig.19 , 22 As shown, the display panel may further include a fourth conductive layer, which is disposed between the first conductive layer and the second active layer. The fourth conductive layer may include: a second gate line 81 and a second protrusion 82, wherein the second gate line 81 may provide Figure 2 The reset signal end of the display panel, the second gate line 81 can be connected to the first gate line 51 through a via in the peripheral wiring area of ​​the display panel. The second gate line 81 can extend along the second direction X1 in the orthographic projection of the substrate substrate, and the second gate line 81 can include a fourth conductive portion 814, the orthographic projection of the second active portion 42 on the substrate substrate can be located on the orthographic projection of the fourth conductive portion 814 on the substrate substrate, and the fourth conductive portion 814 can be used to form the second gate of the second transistor T2; the second protruding portion 82 can be connected to the second gate line 81, in the first direction Y1, the orthographic projection of the second protruding portion 82 on the substrate substrate is located between the orthographic projection of the second gate line 81 on the substrate substrate and the orthographic projection of the first conductive portion 31 on the substrate substrate, the second protruding portion 82 can include a fifth conductive portion 825, the orthographic projection of the third active portion 43 on the substrate substrate can be located on the orthographic projection of the fifth conductive portion 825 on the substrate substrate, and the fifth conductive portion 825 can be used to form the second gate of the first transistor T1.

[0098] like Fig.19 , 22As shown, the fourth conductive layer may further include a sixth conductive portion 86, the orthographic projection of the sixth conductive portion 86 on the base substrate may cover the orthographic projection of the first conductive portion 31 on the base substrate, and the sixth conductive portion 86 may be used to form an electrode of the capacitor C. An opening 861 may be provided on the sixth conductive portion 86.

[0099] like Fig.23 , 24 As shown, the third conductive layer can be arranged on the side of the second conductive layer away from the substrate, and the third conductive layer can include: a first connecting portion 61 and an initial signal line 62. The initial signal line 62 can be used to provide Figure 4 The first connection portion 61 can be connected to the sixth active portion 46 through the via 71, and the first connection portion 61 can be connected to the first conductive portion 31 through the via 78, so that the gate of the driving transistor DT and the first electrode of the first transistor T1 can be connected. The opening 861 of the via 78 located on the sixth conductive portion 86 in the orthographic projection of the substrate is within the orthographic projection of the substrate, that is, the edge of the orthographic projection of the via 78 on the substrate is at a certain distance from the edge of the orthographic projection of the opening 861 on the substrate, so that the conductive material filled in the via 78 can be insulated from the sixth conductive portion 86.

[0100] The orthographic projection of the initial signal line 62 on the substrate can extend along the second direction X1, and the orthographic projection of the initial signal line 62 on the substrate can be located on one side of the orthographic projection of the first gate line 51 on the substrate in the first direction Y1, wherein the initial signal line 62 can provide Figure 4 The initial signal end in the first transistor T2 can be connected to the first electrode of the second transistor T2 by connecting the first electrode of the first transistor T2 to the initial signal end.

[0101] In this exemplary embodiment, in the first direction Y1, the fourth active portion 44 and the sixth active portion 46 are located between the orthographic projection of the first conductive portion 31 on the substrate and the orthographic projection of the first gate line 51 on the substrate, and the fourth active portion 44 can be connected to the driving transistor through the conductive structure between the first conductive portion 31 and the first gate line 51, and the sixth active portion 46 can be electrically connected to the first conductive portion 31 through the conductive structure between the first gate line 51 and the first conductive portion 31, so that the pixel driving circuit of the display panel has a high degree of integration. In addition, the first transistor T1 and the second transistor T2 both adopt a dual-gate structure, and the two gates of the first transistor T1 and the second transistor T2 can provide gate voltages at the same time, thereby increasing the response speed of the first transistor T1 and the second transistor T2, and at the same time, the gates of the first transistor T1 and the second transistor T2 located in the fourth conductive layer can shield their channel regions, thereby avoiding the influence of light on the characteristics of the channel regions of the first transistor T1 and the second transistor T2, so as to improve the electrical stability of the first transistor T1 and the second transistor T2. It should be understood that in other exemplary embodiments, the display panel may not be provided with the second gate line 81 .

[0102] In this exemplary embodiment, Fig.17 , 18 As shown in , 22, the first active layer may further include: a seventh active portion 27 and an eighth active portion 28. The seventh active portion 27 may be used to form the channel region of the fifth transistor T5, and in the first direction Y1, the orthographic projection of the seventh active portion 27 on the substrate may be located between the orthographic projection of the first conductive portion 31 on the substrate and the orthographic projection of the fourth active portion 44 on the substrate; the eighth active portion 28 may be used to form the channel region of the sixth transistor T6, and in the first direction Y1, the orthographic projection of the eighth active portion 28 on the substrate is located between the orthographic projection of the first conductive portion 31 on the substrate and the orthographic projection of the fourth active portion 44 on the substrate. The first conductive layer may further include a third gate line 33, and the orthographic projection of the third gate line 33 on the substrate may extend along the second direction X1, and the third gate line 33 may be used to provide Figure 4 The third gate line 33 may include a gate portion 331 and a gate portion 332, wherein the orthographic projection of the gate portion 331 on the substrate may cover the seventh active portion 27, and the orthographic projection of the gate portion 332 on the substrate may cover the orthographic projection of the eighth active portion 28 on the substrate. The gate portion 331 may be used to form the gate of the fifth transistor T5, and the gate portion 332 may be used to form the gate of the sixth transistor.

[0103] The first active layer further includes an eleventh active portion 211, the eleventh active portion 211 is used to form the channel region of the third transistor T3, the orthographic projection of the eleventh active portion 211 on the substrate is located on the side of the orthographic projection of the first conductive portion 31 on the substrate in the fourth direction Y2, the fourth direction Y2 is opposite to the first direction Y1; the first conductive layer may also include a fifth gate line 35, the fifth gate line 35 extends along the second direction X1 on the orthographic projection of the substrate. The fifth gate line 35 may include a gate portion 351, the orthographic projection of the substrate covers the eleventh active portion 211, and the gate portion 351 may be used to form the gate of the third transistor T3.

[0104] like Fig.19 , 20 As shown in , 21 and 22, the fourth conductive layer may further include a sixth gate line 87, the sixth gate line 87 may extend along the second direction X1 when projected on the substrate, and the sixth gate line 87 may be located on one side of the fifth gate line 35 when projected on the substrate in the fourth direction Y2. The second active layer may further include: a twelfth active portion 412, a thirteenth active portion 413, and a fourteenth active portion 414, wherein the twelfth active portion 412 may be used to form a first channel region of the fourth transistor T4, and the twelfth active portion 412 may be located on the sixth gate line 87 in the orthographic projection of the substrate; the thirteenth active portion 413 is used to form a second channel region of the fourth transistor T4, and the thirteenth active portion 413 may be located on the orthographic projection of the substrate; the fourteenth active portion 414 may be connected between the twelfth active portion 412 and the thirteenth active portion 413, and the fourteenth active portion 414 may be located on a side of the orthographic projection of the substrate substrate on the fourth direction Y2 of the sixth gate line 87. The second conductive layer may further include a seventh gate line 57, the seventh gate line 57 extending along the second direction X1 in the orthographic projection of the substrate, and the seventh gate line 57 covering the orthographic projection of the twelfth active portion 412 and the thirteenth active portion 414 in the orthographic projection of the substrate. The fourth transistor T4 has two channel regions, so that the leakage current of the third node through the fourth transistor can be further reduced. The seventh gate line 57 and the sixth gate line 87 can be connected through a via in the peripheral routing area of ​​the display panel end, and the seventh gate line 57 and the sixth gate line 87 can simultaneously provide a gate drive signal to the fourth transistor, thereby increasing the response speed of the fourth transistor T4. The seventh gate line 57 and the sixth gate line 87 can be used to provide Figure 4 The second gate drive signal terminal in.

[0105] In this exemplary embodiment, Fig.23 ,24 As shown, the first connection portion 61 is also connected to the side of the thirteenth active portion 413 away from the fourteenth active portion 414 through the via 75 to connect the second electrode of the fourth transistor T4 and the gate of the driving transistor DT. The third conductive layer also includes: a connection portion 63, a connection portion 64, a connection portion 65, a connection portion 66, and a connection portion 67. The connection portion 63 can be connected to the side of the twelfth active portion 412 away from the fourteenth active portion 414 through the via 73, and at the same time connected to the side of the seventh active portion 27 through the via 74 to connect the first electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5. The connection portion 64 can be connected to the sixth conductive portion 86 through the via 76. The connection portion 65 can be connected to the side of the seventh active portion 27 away from the connection portion 62 through the via 77 to connect the first electrode of the fifth transistor. The connection portion 66 may be connected to the active portion 219 on one side of the eighth active portion 28 through the via 715, and connected to the fourth active portion through the via 79 to connect the second electrode of the sixth transistor and the second electrode of the first transistor. The connection portion 67 may be connected to one side of the eleventh active portion 211 through the via 714 to connect the first electrode of the third transistor T3.

[0106] In this exemplary embodiment, the fourteenth active portion 414 is a conductor, and a parasitic capacitor is formed between the fourteenth active portion 414 and the seventh gate line 57 and the sixth gate line 87. When the voltage on the seventh gate line 57 and the sixth gate line 87 changes, the voltage of the fourteenth active portion 414 will also change accordingly based on the bootstrap effect of the capacitor, thereby causing the fourteenth active portion 414 to leak to the source and drain of the fourth transistor T4, and ultimately causing the pixel driving circuit to drive abnormally. Fig.25 , 26 As shown, the display panel may further include a fifth conductive layer, which may be disposed on a side of the third conductive layer away from the substrate. The fifth conductive layer may also include a second power line 95, which may be used to provide Figure 4 The first power supply terminal in the substrate. The orthogonal projection of the second power line 95 on the substrate substrate may extend along the first direction Y1, and the orthogonal projection of the second power line 95 on the substrate substrate may cover the orthogonal projection of the fourteenth active portion 414 on the substrate substrate. The second power line 95 has a stable voltage, and the second power line 95 may suppress the potential change of the fourteenth active portion 414, thereby reducing the leakage current of the fourteenth active portion 414 to the source and drain of the fourth transistor T4.

[0107] In this exemplary embodiment, Fig.25 , 26As shown, the second power line 95 may include a fifth edge 955, and the fifth conductive layer may also include a third shielding portion 98, the third shielding portion 98 is connected to the second power line 95, and the third shielding portion 98 includes a sixth edge 986 connected to the fifth edge 955 of the second power line 95, and the angle between the sixth edge 986 and the fifth edge 955 in the orthographic projection on the substrate substrate is less than 180°. That is, the orthographic projection of the third shielding portion 98 on the substrate substrate is located on the side of the orthographic projection of the second power line 95 on the substrate substrate. The orthographic projection of the third shielding portion 98 on the substrate substrate covers the second active portion and the third active portion. The third shielding portion 98 can avoid the influence of light on the channel region characteristics of the first transistor T1 and the second transistor T2, so as to improve the electrical stability of the first transistor T1 and the second transistor T2. The second power line 95 can also be connected to the connecting portion 64 through the via 710. As shown Fig.26 As shown, in this exemplary embodiment, the orthographic projection of the second power line 95 on the substrate substrate covers the orthographic projection of the first connection portion 61 on the substrate substrate. It should be understood that in other exemplary embodiments, the orthographic projection of the second power line 95 on the substrate substrate may not intersect or only partially intersect with the orthographic projection of the first connection portion 61 on the substrate substrate.

[0108] The fifth conductive layer may further include a data line 96 and a connection portion 97. The data line 96 is connected to the connection portion 67 through a via hole 713 to connect the first electrode of the third transistor T3. The connection portion 97 is connected to the connection portion 66 through a via hole 712 to connect the second electrode of the sixth transistor T6. The connection portion 97 may be connected to the anode of the light emitting unit through the via hole.

[0109] like Fig. 27 As shown, along Fig.26Partial cross-sectional view of the dashed line AA. The display panel also includes: a blocking layer 101, a first gate insulating layer 102, a second gate insulating layer 103, a third gate insulating layer 104, a buffer layer 105, a fourth gate insulating layer 106, a first dielectric layer 107, a second dielectric layer 108, a passivation layer 109, and a first flat layer 110. Among them, the base substrate 1, the blocking layer 101, the first active layer, the first gate insulating layer 102, the first conductive layer, the second gate insulating layer 103, the fourth conductive layer, the third gate insulating layer 104, the buffer layer 105, the second active layer, the fourth gate insulating layer 106, the second conductive layer, the first dielectric layer 107, the second dielectric layer 108, the third conductive layer, the passivation layer 109, the first flat layer 110, and the fifth conductive layer are stacked in sequence. The connecting portion 66 can be connected to the active portion 219 through the via 715, and connected to the fourth active portion 44 through the via 79, so as to connect the second electrode of the sixth transistor and the first electrode of the second transistor. The connecting portion 97 in the fifth conductive layer can be connected to the connecting portion 66 through the via 712, and the connecting portion 97 can also be connected to the anode layer located on the side of the fifth conductive layer away from the substrate through the via to connect the anode of the light-emitting unit. A second flat layer can also be provided between the fifth conductive layer and the anode layer.

[0110] The dielectric layer and the passivation layer may be made of silicon nitride or transparent organic resin, and the planar layer may be made of polyimide (PI), transparent polyimide (CPI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), etc. The conductive layer may be made of metal materials such as copper and molybdenum. The barrier layer may be made of inorganic materials.

[0111] It should be understood that Fig. 27 It only reflects the relative positions of the various layers of the display panel, and does not represent the specific structure of the display panel. In the actual structure of the display panel, the inorganic layer (including other insulating layers other than the flat layer) formed on the protruding structure will conformally cover the protruding structure. For example, the first gate insulating layer 102 will conformally cover the first active portion 21, and the third gate insulating layer 104 will conformally cover the fourth conductive portion 814.

[0112] This exemplary embodiment also provides a pixel driving circuit driving method, which is used to drive the above-mentioned pixel driving circuit. The driving method includes:

[0113] In a reset phase, turning on the first transistor and the second transistor to input an initial signal to the third node and the first electrode of the light emitting unit through the initial signal terminal;

[0114] In the compensation phase, the compensation circuit is used to conduct the first node and the third node, and the data writing circuit is used to write a data signal to the first node;

[0115] In the light emitting stage, the light emitting control circuit is used to connect the first power supply terminal and one electrode of the driving transistor, and to connect the first electrode of the light emitting unit and the other electrode of the driving transistor.

[0116] The driving method has been analyzed in detail in the above content and will not be repeated here.

[0117] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered merely as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0118] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A pixel driving circuit, in, include: A driving transistor, wherein a first electrode is connected to the first node, a second electrode is connected to the second node, and a gate is connected to the third node; A data writing circuit, connected to the first node and the data signal terminal, and configured to transmit a signal from the data signal terminal to the first node in response to a control signal; a compensation circuit, connected to the second node and the third node, and configured to connect the second node and the third node in response to a control signal; a light emitting control circuit, connected to the first and second electrodes of the driving transistor, a first power supply terminal, a first electrode of the light emitting unit, and an enable signal terminal, and used for connecting the first power supply terminal and an electrode of the driving transistor, and connecting the first electrode of the light emitting unit and another electrode of the driving transistor in response to a signal of the enable signal terminal; A storage circuit connected between the third nodes; Reset circuit, including: a first transistor, a first electrode connected to the third node, a second electrode connected to the first electrode of the light emitting unit, and a gate connected to a reset signal terminal; a second transistor, wherein the first electrode is connected to the second electrode of the first transistor, the second electrode is connected to the initial signal terminal, and the gate is connected to the reset signal terminal; Wherein, the first transistor and the second transistor are N-type oxide transistors, and the driving transistor is a P-type low-temperature polysilicon transistor; The light emitting control circuit is used for connecting the first power supply terminal and the second electrode of the driving transistor, and connecting the first electrode of the light emitting unit and the first electrode of the driving transistor in response to the signal of the enable signal terminal.

2. The pixel driving circuit according to claim 1, in, The data writing circuit includes: The third transistor has a first electrode connected to the data signal terminal, a second terminal connected to the first node, and a gate connected to the first gate driving signal terminal.

3. The pixel driving circuit according to claim 2, in, The compensation circuit comprises: a fourth transistor, wherein a first electrode is connected to the second node, a second electrode is connected to the third node, and a gate is connected to the second gate driving signal terminal; Wherein, the third transistor is a P-type low-temperature polysilicon transistor, and the fourth transistor is an N-type oxide transistor.

4. The pixel driving circuit according to claim 2, in, The compensation circuit comprises: a fourth transistor, wherein a first electrode is connected to the second node, a second electrode is connected to the third node, and a gate is connected to the first gate driving signal terminal; Wherein, the third transistor and the fourth transistor are both P-type low-temperature polysilicon transistors.

5. The pixel driving circuit according to claim 2, in, The compensation circuit comprises: a fourth transistor, wherein a first electrode is connected to the second node, a second electrode is connected to the third node, and a gate is connected to the first gate driving signal terminal; Wherein, the third transistor and the fourth transistor are both N-type oxide transistors.

6. The pixel driving circuit according to claim 1, in, The light emitting control circuit comprises: a fifth transistor, a first electrode connected to the first power supply terminal, a second electrode connected to the second node, and a gate connected to the enable signal terminal; A sixth transistor has a first electrode connected to the first node, a second electrode connected to the first electrode of the light emitting unit, and a gate connected to the enable signal terminal.

7. The pixel driving circuit according to claim 6, in, The fifth transistor and the sixth transistor are P-type low temperature polysilicon transistors.

8. The pixel driving circuit according to claim 1, in, The storage circuit includes: A capacitor is connected between the first power supply terminal and the third node.

9. A display panel, in, The display panel includes a pixel driving circuit, and the pixel driving circuit includes: A driving transistor, wherein a first electrode is connected to the first node, a second electrode is connected to the second node, and a gate is connected to the third node; A data writing circuit, connected to the first node and the data signal terminal, and configured to transmit a signal from the data signal terminal to the first node in response to a control signal; a compensation circuit, connected to the second node and the third node, and configured to connect the second node and the third node in response to a control signal; a light emitting control circuit, connected to the first and second electrodes of the driving transistor, a first power supply terminal, a first electrode of the light emitting unit, and an enable signal terminal, and used for connecting the first power supply terminal and an electrode of the driving transistor, and connecting the first electrode of the light emitting unit and another electrode of the driving transistor in response to a signal of the enable signal terminal; A storage circuit connected between the third nodes; Reset circuit, including: a first transistor, a first electrode connected to the third node, a second electrode connected to the first electrode of the light emitting unit, and a gate connected to a reset signal terminal; a second transistor, wherein the first electrode is connected to the second electrode of the first transistor, the second electrode is connected to the initial signal terminal, and the gate is connected to the reset signal terminal; Wherein, the first transistor and the second transistor are N-type oxide transistors, and the driving transistor is a P-type low-temperature polysilicon transistor; The display panel comprises: substrate substrate; A first active layer, located on one side of the base substrate, the first active layer comprising a first active portion, and the first active portion is used to form a channel region of the driving transistor; A first conductive layer is located on a side of the first active layer away from the substrate, and the first conductive layer includes: a first conductive portion, wherein an orthographic projection of the first conductive portion on the base substrate covers an orthographic projection of the first active portion on the base substrate, and the first conductive portion is used to form a gate of the driving transistor; The second active layer is located on a side of the first conductive layer away from the substrate, and the second active layer includes: A second active portion, whose orthographic projection on the base substrate is located on one side of the orthographic projection of the first conductive portion on the base substrate in the first direction; a third active portion, wherein in the first direction, an orthographic projection of the third active portion on the substrate is located between an orthographic projection of the first conductive portion on the substrate and an orthographic projection of the second active portion on the substrate, and the orthographic projection of the third active portion on the substrate is located on one side of an orthographic projection of the second active portion on the substrate in the second direction, and the first direction intersects the second direction; a fourth active portion connected between the second active portion and the third active portion, wherein an orthographic projection of the fourth active portion on the substrate substrate is located on one side of an orthographic projection of the third active portion on the substrate substrate in a third direction, the second direction is opposite to the third direction, and in the first direction, an orthographic projection of the fourth active portion on the substrate substrate is located between an orthographic projection of the first conductive portion on the substrate substrate and an orthographic projection of the second active portion on the substrate substrate; a fifth active portion connected to an end of the second active portion away from the fourth active portion, wherein an orthographic projection of the fifth active portion on the base substrate is located on one side of an orthographic projection of the second active portion on the base substrate in the first direction; a sixth active portion connected to an end of the third active portion away from the fourth active portion, wherein an orthographic projection of the sixth active portion on the base substrate is located on one side of an orthographic projection of the third active portion on the base substrate in the second direction; A second conductive layer is disposed on a side of the second active layer away from the base substrate, and the second conductive layer includes: a first gate line, whose orthographic projection on the base substrate extends along the second direction, the first gate line comprises a second conductive portion, the orthographic projection of the second conductive portion on the base substrate coincides with the orthographic projection of the second active portion on the base substrate, and the second conductive portion is used to form a first gate of a second transistor; a first protruding portion connected to the first gate line, wherein in the first direction, an orthographic projection of the first protruding portion on the substrate is located between an orthographic projection of the first gate line on the substrate and an orthographic projection of the first conductive portion on the substrate, the first protruding portion includes a third conductive portion, an orthographic projection of the third conductive portion on the substrate coincides with an orthographic projection of the third active portion on the substrate, and the third conductive portion is used to form a first gate of the first transistor; A third conductive layer is disposed on a side of the second conductive layer away from the substrate, and the third conductive layer includes: a first connecting portion, connecting the sixth active portion and the first conductive portion through a via hole; An initial signal line, whose orthographic projection on the base substrate extends along the second direction, is located on one side of the orthographic projection of the first gate line on the base substrate in the first direction, and is connected to the fifth active portion through a via.

10. The display panel according to claim 9, in, The display panel further includes: A fourth conductive layer is disposed between the first conductive layer and the second active layer, and the fourth conductive layer includes: a second gate line, the orthographic projection of which on the base substrate extends along the second direction, the second gate line comprising a fourth conductive portion, the orthographic projection of the second active portion on the base substrate being located on the orthographic projection of the fourth conductive portion on the base substrate, and the fourth conductive portion being used to form a second gate of the second transistor; a second protruding portion connected to the second gate line; in the first direction, an orthographic projection of the second protruding portion on the substrate is located between an orthographic projection of the second gate line on the substrate and an orthographic projection of the first conductive portion on the substrate; the second protruding portion includes a fifth conductive portion; an orthographic projection of the third active portion on the substrate is located on an orthographic projection of the fifth conductive portion on the substrate; and the fifth conductive portion is used to form a second gate of the first transistor.

11. The display panel according to claim 9, in, The light emitting control circuit comprises: a fifth transistor, a first electrode connected to the first power supply terminal, a second electrode connected to the second node, and a gate connected to the enable signal terminal; a sixth transistor, a first electrode connected to the first node, a second electrode connected to the first electrode of the light emitting unit, and a gate connected to the enable signal terminal; The first active layer further comprises: a seventh active portion, used to form a channel region of the fifth transistor, wherein in a first direction, an orthographic projection of the seventh active portion on the base substrate is located between an orthographic projection of the first conductive portion on the base substrate and an orthographic projection of the fourth active portion on the base substrate; an eighth active portion, used to form a channel region of the sixth transistor, wherein in a first direction, an orthographic projection of the eighth active portion on the base substrate is located between an orthographic projection of the first conductive portion on the base substrate and an orthographic projection of the fourth active portion on the base substrate; The first conductive layer further comprises: A third gate line is used to provide the enable signal terminal, the orthographic projection of the third gate line on the substrate extends along the second direction, the orthographic projection of the third gate line on the substrate covers the orthographic projections of the seventh active portion and the eighth active portion on the substrate, part of the third gate line is used to form the gate of the fifth transistor, and part of the third gate line is used to form the gate of the sixth transistor.

12. The display panel according to claim 9, in, The data writing circuit comprises: a third transistor, a first electrode connected to the data signal terminal, a second terminal connected to the first node, and a gate connected to a first gate driving signal terminal; The compensation circuit comprises: a fourth transistor, wherein a first electrode is connected to the second node, a second electrode is connected to the third node, and a gate is connected to the first gate driving signal terminal; Wherein, the third transistor and the fourth transistor are both P-type low-temperature polysilicon transistors; The first active layer further comprises: a ninth active portion, used to form a channel region of the third transistor, wherein an orthographic projection of the ninth active portion on the substrate is located on one side of an orthographic projection of the first conductive portion on the substrate in a fourth direction, the fourth direction being opposite to the first direction; a tenth active portion, used to form a channel region of the fourth transistor, wherein an orthographic projection of the tenth active portion on the base substrate is located on one side of an orthographic projection of the first conductive portion on the base substrate in a fourth direction; The first conductive layer further comprises: A fourth gate line is used to provide the first gate drive signal terminal, and its orthographic projection on the substrate extends along the second direction. The orthographic projection of the fourth gate line on the substrate covers the orthographic projections of the ninth active portion and the tenth active portion on the substrate. Part of the fourth gate line is used to form the gate of the third transistor, and part of the fourth gate line is used to form the gate of the fourth transistor.

13. The display panel according to claim 12, in, Also includes: A fifth conductive layer is disposed on a side of the third conductive layer away from the base substrate, and the fifth conductive layer includes: A first power line, used for providing the first power end, the orthographic projection of the first power line on the substrate extends along the first direction, and the first power line includes a first edge; a first shielding portion connected to the power line, the first shielding portion comprising a second edge connected to a first edge of the first power line, an angle between an orthographic projection of the first edge on the substrate and an orthographic projection of the second edge on the substrate being less than 180°, and an orthographic projection of the first shielding portion on the substrate covering an orthographic projection of the third active portion on the substrate; A first data line, used for providing the data signal end, the orthographic projection of the first data line on the substrate extends along the first direction, and the first data line includes a third edge; A second shielding portion is connected to the data line, the second shielding portion includes a fourth edge connected to the third edge of the first data line, the angle between the orthographic projection of the third edge on the base substrate and the orthographic projection of the fourth edge on the base substrate is less than 180°, and the orthographic projection of the second shielding portion on the base substrate covers the orthographic projection of the second active portion on the base substrate.

14. The display panel according to claim 10, in, The data writing circuit comprises: a third transistor, a first electrode connected to the data signal terminal, a second terminal connected to the first node, and a gate connected to a first gate driving signal terminal; The compensation circuit comprises: a fourth transistor, wherein a first electrode is connected to the second node, a second electrode is connected to the third node, and a gate is connected to the second gate driving signal terminal; Wherein, the third transistor is a P-type low temperature polysilicon transistor, and the fourth transistor is an N-type oxide transistor; The first active layer further comprises: an eleventh active portion, used to form a channel region of the third transistor, wherein an orthographic projection of the eleventh active portion on the base substrate is located on one side of an orthographic projection of the first conductive portion on the base substrate in a fourth direction, the fourth direction being opposite to the first direction; The first conductive layer also includes: a fifth gate line, used for providing the first gate driving signal terminal, wherein the orthographic projection of the fifth gate line on the substrate extends along the second direction, the orthographic projection of the fifth gate line on the substrate covers the orthographic projection of the eleventh active portion on the substrate, and a portion of the fifth gate line is used for forming the gate of the third transistor; The fourth conductive layer further comprises: a sixth gate line, used for providing the second gate driving signal terminal, the orthographic projection of the sixth gate line on the substrate extending along the second direction, and the orthographic projection of the sixth gate line on the substrate being located on one side of the orthographic projection of the fifth gate line on the substrate in the fourth direction; The second active layer further comprises: a twelfth active portion, used to form a first channel region of the fourth transistor, the orthographic projection of the twelfth active portion on the base substrate being located on the orthographic projection of the sixth gate line on the base substrate; a thirteenth active portion, used to form a second channel region of the fourth transistor, the orthographic projection of the thirteenth active portion on the base substrate being located on the orthographic projection of the sixth gate line on the base substrate; a fourteenth active portion connected between the twelfth active portion and the thirteenth active portion, wherein an orthographic projection of the fourteenth active portion on the base substrate is located on one side of an orthographic projection of the sixth gate line on the base substrate in a fourth direction; The second conductive layer further comprises: A seventh gate line is used to provide the second gate driving signal terminal, and its orthographic projection on the base substrate extends along the second direction. The orthographic projection of the seventh gate line on the base substrate covers the orthographic projections of the twelfth active portion and the thirteenth active portion on the base substrate.

15. The display panel according to claim 14, in, The fifth conductive layer further comprises: A second power line is used to provide the first power end, and its orthographic projection on the base substrate extends along the first direction. The orthographic projection of the second power line on the base substrate covers the orthographic projection of the fourteenth active portion on the base substrate.

16. The display panel according to claim 15, in, The second power line includes a fifth edge, and the fifth conductive layer further includes: A third shielding portion is connected to the second power line, the third shielding portion includes a sixth edge connected to the fifth edge of the second power line, the angle between the orthographic projection of the sixth edge on the substrate and the orthographic projection of the fifth edge on the substrate is less than 180°, and the orthographic projection of the third shielding portion on the substrate covers the second active portion and the third active portion.

17. A display panel, in, The invention comprises the pixel driving circuit as described in any one of claims 1 to 8.

18. A pixel driving circuit driving method, used to drive the pixel driving circuit according to any one of claims 1 to 8, in, include: In a reset phase, turning on the first transistor and the second transistor to input an initial signal to the third node and the first electrode of the light emitting unit through the initial signal terminal; In the compensation phase, the compensation circuit is used to conduct the first node and the third node, and the data writing circuit is used to write a data signal to the first node; In the light emitting stage, the light emitting control circuit is used to connect the first power supply terminal and one electrode of the driving transistor, and to connect the first electrode of the light emitting unit and the other electrode of the driving transistor.

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