A memory controller, a control method of accessing memory, and a storage device

Abstract

Provided are a memory controller, a control method for accessing a memory, and a storage device. The memory controller is used for accessing a dynamic random access memory, the dynamic random access memory includes a plurality of ranks, and the memory controller includes: a first cache used for storing a data read instruction for the dynamic random access memory; a second cache used for storing a data write instruction for the dynamic random access memory; and an arbitration module used for arbitrating the data read instruction and / or the data write instruction based on an arbitration rule. The arbitration rule includes an arbitration rule based on a timing requirement of a plurality of rank instruction jumps. Embodiments of the application help to improve the efficiency of the memory controller in accessing the dynamic random access memory by adding the arbitration rule based on the timing requirement of the plurality of rank instruction jumps in the arbitration rule of the memory access instruction.

Description

Technical Field

[0001] This application relates to the field of memory access control technology, and more specifically, to a memory controller, a method for controlling access to memory, and a storage device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used in electronic devices such as mobile phones, watches, and computers. The memory controller manages the data reading and writing operations of DRAM. When multiple DRAM access instructions are received, the memory controller typically arbitrates these instructions based on arbitration rules to determine the execution order. For example, the memory controller can arbitrate access instructions based on the sequentiality of read and write operations. However, under existing arbitration rules, the efficiency of the memory controller accessing DRAM needs improvement. Summary of the Invention

[0003] This application provides a memory controller, a method for controlling access to memory, and a storage device. The various aspects related to the embodiments of this application are described below.

[0004] Firstly, a memory controller is provided. The memory controller is used to access dynamic random access memory (DRAM), which includes multiple ranks. The memory controller includes: a first cache for storing data read instructions for DRAM; a second cache for storing data write instructions for DRAM; and an arbitration module for arbitrating data read instructions and / or data write instructions based on arbitration rules; wherein the arbitration rules include arbitration rules based on the timing requirements of instruction jumps across multiple ranks.

[0005] Secondly, a method for controlling memory access is provided. This method controls access to dynamic random access memory (DRAM), which includes multiple ranks. The method includes arbitrating data read and / or write instructions to DRAM based on arbitration rules; wherein the arbitration rules include arbitration rules based on the timing requirements of instruction jumps across multiple ranks.

[0006] Thirdly, a storage device is provided. The storage device includes dynamic random access memory and a memory controller as described in the first aspect.

[0007] The embodiments of this application help improve the efficiency of the memory controller accessing dynamic random access memory by adding arbitration rules based on the timing requirements of multiple rank instruction jumps to the arbitration rules of memory access instructions. Attached Figure Description

[0008] Figure 1 The diagram shown is a structural schematic of a memory controller.

[0009] Figure 2 The diagram shows the internal structure of a DDR memory controller.

[0010] Figure 3 The diagram illustrates a process for address arbitration when switching from read mode to write mode.

[0011] Figure 4 The diagram shows a flowchart of address arbitration for switching from write mode to read mode.

[0012] Figure 5 The diagram shows a process flow chart for memory cell arbitration when switching from read mode to write mode.

[0013] Figure 6 The diagram shows a flowchart of a memory cell arbitration process when switching from write mode to read mode.

[0014] Figure 7 The diagram shown is a structural schematic of a storage device.

[0015] Figure 8 The diagram shows a flowchart of a method for controlling memory access. Detailed Implementation

[0016] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0017] Dynamic random access memory (DRAM) is a type of semiconductor memory that primarily uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. Due to its advantages such as low cost, high transfer speed, and the ability to be read and written at any time, DRAM is widely used in electronic devices such as mobile phones, watches, and computers. For example, DRAM can serve as internal memory that directly exchanges data with the processor. It can also be used as a temporary data storage medium for the operating system or running programs.

[0018] The memory controller acts as a bridge for data exchange between the processor and dynamic random access memory (DRAM). For example, it controls DRAM read and write operations. Simultaneously, the memory controller also determines system memory performance. For instance, it determines important parameters such as the maximum memory capacity the processor can use and access speed.

[0019] When multiple access instructions to dynamic random access memory (DRAM) are received, the memory controller typically arbitrates these instructions based on arbitration rules to determine their execution order. In some implementations, the multiple access instructions can first be stored in a cache; then, the memory controller can arbitrate the instructions stored in the cache based on arbitration rules. For example, the memory controller can arbitrate access instructions based on the continuation of read and write operations. That is, the arbitration rules concatenate read instructions or write instructions as closely as possible. If the previous transfer corresponds to a read instruction, the read instruction will have a higher priority in the next arbitration. Conversely, if the previous transfer corresponds to a write instruction, the write instruction will have a higher priority in the next arbitration.

[0020] Double data rate synchronous dynamic random access memory (DDR SDRAM), as a type of dynamic random access memory, is widely used in high-performance computing and mobile applications where power consumption and area are critical. Taking a four-channel single-wafer DDR SDRAM as an example, this paper describes the process of the memory controller arbitrating access instructions.

[0021] Quad-channel single-die DDR consists of four memory cell sets (ranks), and each memory cell set includes multiple memory cells (banks). The number of banks in each rank is determined by the processor's bus width and the bank width. For example, the processor's interface width is 64 bits. This means that the processor sends or reads 64 bits of data from the DDR in one clock cycle. If the bank width is 8 bits, the rank interconnects with the processor by connecting eight banks in parallel. As an example, the previous transfer corresponds to a DDR read instruction, and the next arbitration result is to execute that DDR read instruction. If the DDR read instruction includes multiple instructions, one of the multiple DDR read instructions is executed randomly. However, the multiple DDR read instructions may include instructions for different ranks. Due to the different rank attributes, the overhead of jumping to the instructions for different ranks among the multiple read instructions is different. For example, the overhead could be timing requirements. Current arbitration rules do not consider rank attributes.

[0022] To address the aforementioned issues, embodiments of this application provide a memory controller. By adding arbitration rules based on the timing requirements of multiple rank instruction jumps to the arbitration rules of memory access instructions, embodiments of this application help improve the efficiency of the memory controller in accessing dynamic random access memory.

[0023] Figure 1 This is a schematic diagram of a memory controller provided in an embodiment of this application. The memory controller 100 can be used to access dynamic random access memory (DRAM). During DRAM access, the functions of the memory controller 100 may include one or more of the following: storing, arbitrating, decomposing, and converting access instructions. In some implementations, the DRAM includes multiple rank sequences.

[0024] See Figure 1 The memory controller 100 includes a first cache 110, a second cache 120, and an arbitration module 130, which will be discussed in conjunction with the following text. Figure 1 The device embodiments of this application will be described in detail.

[0025] The first cache 110 can be used to store data read instructions for dynamic random access memory (DRAM). The sender of the data read instruction can be various. For example, the data read instruction can be sent by the processor, the operating system, or a running application. The target data corresponding to the data read instruction can be located at any location in DRAM. For example, the target data can be located in a bank of DRAM. Or, the target data can be located in a rank of DRAM. As an example, for a dual-die DDR, the target data can be located in a rank in die 1 or in a rank in die 0.

[0026] The first cache 110 may include one buffer or multiple buffers. As one implementation, the first cache 110 can be divided into multiple buffers according to the sender of the data read instruction, with each buffer corresponding to one sender. As another implementation, the first cache 110 can be divided into multiple buffers according to the location of the target data. For example, for a dual-die DDR, the first cache 110 can be divided into two buffers. One buffer is used to store data read instructions with target data located in die0, and the other buffer is used to store data read instructions with target data located in die1.

[0027] Data read instructions can be stored in the first cache 110 in several ways. As an example, data read instructions can be stored in the first cache 110 by the address range of the target data.

[0028] The second cache 120 can be used to store data write instructions for dynamic random access memory (DRAM). The sender of the data write instruction can be various. For example, the data write instruction can be sent by the processor, the operating system, or a running application. The target data corresponding to the data write instruction can be located at any location in DRAM. For example, the target data can be located in a bank of DRAM. Or, the target data can be located in a rank of DRAM. As an example, for a dual-die DDR, the target data can be located in a rank in die 1 or in a rank in die 0.

[0029] The second cache 120 may include one buffer or multiple buffers. As one implementation, the second cache 120 may include multiple buffers according to the sender of the data write instruction, with each buffer corresponding to one sender. As another implementation, the second cache 120 may include multiple buffers according to the location of the target data. For example, for a dual-die DDR, the second cache 120 may include two buffers. One buffer is used to store data write instructions with target data located in die0, and the other buffer is used to store data write instructions with target data located in die1.

[0030] In some implementations, the data write instruction may include a data write location and the target data to be written. For example, if the data write instruction includes a valid chip select signal (CS) 0, then the location of the data to be written is die0. The second cache 120 can store the target data to be written. The write address of the target data can be randomly allocated in die0 by the memory controller. Alternatively, the data write instruction may include a data write address and the data to be written. The second cache 120 may include a data address cache and a write data cache. In other implementations, the data write instruction may include the target data to be written. The write address of the target data is randomly allocated by the memory controller.

[0031] The execution order of data read instructions in the first cache 110 and data write instructions in the second cache 120 can be determined by the arbitration module 130. As one implementation, the arbitration module 130 can arbitrate the data read instructions and data write instructions based on arbitration rules to determine the priority of these instructions.

[0032] The arbitration rules in arbitration module 130 can include various types. For example, arbitration rules can include arbitration rules based on the timing requirements of instruction jumps across multiple ranks. In some embodiments, the dynamic random access memory includes rank 1 and rank 2, and the timing requirement for switching from the current instruction to an instruction targeting rank 1 is less than the timing requirement for switching to an instruction targeting rank 2. That is, the time required to switch from the current instruction to an instruction targeting rank 1 is less than the time required to switch to an instruction targeting rank 2. As an example, switching from the current instruction to an instruction targeting rank 1 requires 1 clock cycle, while switching from the current instruction to an instruction targeting rank 2 requires 16 clock cycles. The arbitration result of arbitration module 130 can be that the instruction targeting rank 1 has a higher priority than the instruction targeting rank 2.

[0033] An arbitration rule based on the timing requirements of multiple rank instruction jumps can save latency overhead during instruction switching and improve instruction switching efficiency. Furthermore, this arbitration rule can bring benefits to dynamic random access memory utilization.

[0034] In some implementations, the arbitration module 130 can arbitrate the instruction to be executed when switching between a data read instruction and a data write instruction. The switching between data read instructions and data write instructions includes various scenarios. For example, the switching can include switching from a data read instruction to a data write instruction. That is, the previously executed instruction was a data read instruction, and the next instruction to be executed is a data write instruction. In other words, the arbitration module 130 arbitrates the data write instruction to be executed to determine its priority. Alternatively, the switching can include switching from a data write instruction to a data read instruction. That is, the previously executed instruction was a data write instruction, and the next instruction to be executed is a data read instruction. Furthermore, the switching can include switching from a data read instruction to a data read instruction, or it can include switching from a data write instruction to a data write instruction.

[0035] The arbitration rules in Arbitration Module 130 based on the timing requirements of multiple rank instruction jumps can be used alone or in combination with other arbitration rules.

[0036] In some implementations, other arbitration rules can be based on read-write continuity. That is, if the previously executed instruction was a data read instruction, then when arbitrating the next instruction, the data read instruction has higher priority, and vice versa.

[0037] In other implementations, arbitration rules can be based on timer timeouts. As an example, suppose the system is currently in data read mode with a data write timer running. When the data write timer expires, if the system is still in data read mode, it can switch back to data write mode. In other words, when the data write timer expires, the data write instruction has higher priority in the next arbitration process, and vice versa. This rule-based arbitration can prevent the system from remaining in one mode for an extended period, preventing instructions in the other mode from being executed.

[0038] In some embodiments, other arbitration rules can be based on the cache queue's fullness or emptiness. As an example, data read instructions can be stored in a read cache queue, and data write instructions can be stored in a write cache queue. If the system is currently in read mode, and the number of write instructions in the write cache queue exceeds a preset threshold, the system switches from read mode to write mode, and vice versa. The preset threshold for the cache queue can be set according to usage. For example, the preset threshold can be 90% of the cache queue's storage space. The cache queue may have one or more preset thresholds. This arbitration rule can prevent instruction loss caused by access instructions exceeding the cache queue's storage capacity when access volume is excessive.

[0039] Taking the timing requirements based on multiple rank instruction jumps and the arbitration rules based on timer timeouts as an example, this section introduces the use of arbitration rules based on multiple rank instruction jumps in combination with other arbitration rules. For instance, if the current mode is data read and the data write timer times out, the data write instruction will have higher priority in the next arbitration process. Among the pending data write instructions, switching to the data write instruction for rank 3 has the lowest timing requirement, so switching to the data write instruction for rank 3 has the highest priority.

[0040] The following text uses processor access to DDR as an example, combined with... Figures 2 to 6 The working process of the memory controller is introduced. Figure 2 This is a schematic diagram of the internal structure of a DDR memory controller. Figure 3 This is a flowchart illustrating the address arbitration process for switching from read mode to write mode. Figure 4 This is a flowchart illustrating the address arbitration process for switching from write mode to read mode. Figure 5 A schematic diagram illustrating the process of arbitrating a storage unit when switching from read mode to write mode. Figure 6 A schematic diagram illustrating the arbitration process for switching a storage unit from write mode to read mode.

[0041] See Figure 2The storage controller 200 includes a read address cache 210, a write address cache 220, a read / write mode arbitration module 230, a write data cache 240, and a storage cell queue and control module 250. The read address cache 210, write address cache 220, and write data cache 240 are connected to the processor 250. The storage cell queue and control module 250 and write data cache 240 are connected to the DDR (260). The read address cache 210 can be the first cache 110 described above, the write address cache 220 can be the second cache 120 described above, and the read / write arbitration module can be the arbitration module 130 described above.

[0042] The storage controller 200 can store the addresses corresponding to the data read instructions and data write instructions sent by the processor 250 into the read address cache 210 and the write address cache 220, respectively. The storage controller 200 can also store the data to be written corresponding to the data write instructions sent by the processor 250 into the write data cache 240.

[0043] The read / write mode arbitration 230 can arbitrate instructions for address pairs in the read address cache 210 and the write address cache 220 based on arbitration rules. The read / write mode arbitration 230 can also perform secondary arbitration on the above arbitration results based on the current status of the memory cell queue. In some implementations, the memory cell queue and control 250 can decompose and process the secondary arbitration results into DDR (260) executable instructions and send them to the DDR (260).

[0044] Based on the arbitration result of the read / write mode arbitration 230, the write data cache 240 can send data to the DDR (260). For example, if the arbitration result is to execute a write instruction, the write data cache 240 can send the data corresponding to that write instruction to the DDR (260).

[0045] In some implementations, the arbitration rules for read / write mode arbitration 230 include arbitration rules based on read / write continuity, arbitration rules based on timer timeout, arbitration rules based on cache queue full / empty conditions, and arbitration rules based on the timing requirements of multiple rank instruction jumps. Among them, the arbitration rule based on the timing requirements of multiple rank instruction jumps is applied during the switching process between data read instructions and data write instructions.

[0046] See Figure 3 The flowchart 300 for address arbitration when switching from read mode to write mode includes S301 to S316.

[0047] In step S301, the system is in data reading mode N, that is, the system is executing a data reading instruction for rank N.

[0048] In step S302, it is determined whether the write timer has timed out. If the write timer has timed out, the process jumps to step S303; if the write timer has not timed out, the process jumps to step S304.

[0049] In step S303, based on the arbitration rule for timer timeout, the system switches from read mode to write mode. Simultaneously, based on the arbitration rule for the timing requirements of multiple rank instruction jumps, the system switches from read mode N to write mode N+1. That is, the system switches from a data read instruction for rank N to a data write instruction for rank N+1.

[0050] In step S304, the data reading instruction continues to be executed.

[0051] In step S305, it is determined whether the water level of the read address cache 210 is greater than the second preset threshold (level 2) and whether the bank queen (BQ) is in write mode. If the water level of the read address cache 210 is greater than level 2 and the BQ is in write mode, then proceed to step S308. If the water level of the read address cache 210 is not greater than level 2 and the BQ is not in write mode, or if the water level of the read address cache 210 is greater than level 2 or the BQ is in write mode, then proceed to step S306.

[0052] In step S306, it is determined whether the water level of write address cache 220 is greater than level 2 and whether BQ is in write mode. If the water level of write address cache 220 is greater than level 2 and BQ is in read mode, then proceed to step S307. If the water level of write address cache 220 is not greater than level 2 and BQ is not in read mode, or if the water level of write address cache 220 is greater than level 2 or BQ is in read mode, then proceed to step S308.

[0053] In step S307, the system jumps to write mode N+1.

[0054] In step S308, the data reading instruction continues to be executed.

[0055] In step S309, it is determined whether the water level of the read address cache 210 is greater than the first preset threshold (level 1). If the water level of the read address cache 210 is greater than level 1, the process proceeds to step S312. If the water level of the read address cache 210 is not greater than level 1, the process proceeds to step S310.

[0056] In step S310, it is determined whether the water level of write address cache 220 is greater than level 1. If the water level of write address cache 220 is greater than level 1, the process proceeds to step S311. If the water level of write address cache 220 is not greater than the first preset threshold level 1, the process proceeds to step S312.

[0057] In step S311, the system jumps to write mode N+1.

[0058] In step S312, the data reading instruction continues to be executed.

[0059] In step S313, it is determined whether there are any pending instructions in the read address cache 210. If there are pending instructions in the read address cache 210, the process jumps to step S315. If there are no pending instructions in the read address cache 210, the process jumps to step S314.

[0060] In step S314, it is determined whether there are any pending instructions in the write address cache 220. If there are any pending instructions in the write address cache 220, the process proceeds to step S316.

[0061] In step S315, the data reading instruction continues to be executed.

[0062] In step S316, the system jumps to write mode N+1.

[0063] See Figure 4 The flowchart 400, which illustrates the address arbitration process for switching from write mode to read mode, includes S401 to S412.

[0064] In step S401, the system is in data write mode N, that is, the system is executing a data write instruction for rank N.

[0065] In step S402, it is determined whether the read timer has timed out. If the read timer has timed out, the process jumps to step S403; if the read timer has not timed out, the process jumps to step S404.

[0066] In step S403, based on the arbitration rule for timer timeout, the system switches from write mode to read mode. Simultaneously, based on the arbitration rule for the timing requirements of multiple rank instruction jumps, the system switches from write mode N to read mode N+1. That is, the system switches from a data write instruction for rank N to a data read instruction for rank N+1.

[0067] In step S404, the data writing instruction continues to be executed.

[0068] In step S405, it is determined whether the water level of write address cache 220 is greater than level 2 and whether BQ is in read mode. If the water level of write address cache 220 is greater than level 2 and BQ is in read mode, then proceed to step S408. If the water level of write address cache 220 is not greater than level 2 and BQ is not in read mode, or if the water level of write address cache 220 is greater than level 2 or BQ is in read mode, then proceed to step S406.

[0069] In step S406, it is determined whether the water level of read address cache 210 is greater than level 2 and whether BQ is in write mode. If the water level of read address cache 210 is greater than level 2 and BQ is in write mode, then proceed to step S407. If the water level of read address cache 210 is not greater than level 2 and BQ is not in write mode, or if the water level of read address cache 210 is greater than level 2 or BQ is in write mode, then proceed to step S408.

[0070] In step S407, the system switches to read mode N+1.

[0071] In step S408, the data writing instruction continues to be executed.

[0072] In step S409, it is determined whether there are any pending instructions in the write address cache 220. If there are any pending instructions in the write address cache 220, the process jumps to step S412. If there are no pending instructions in the write address cache 220, the process jumps to step S410.

[0073] In step S410, it is determined whether there are any pending instructions in the read address cache 210. If there are any pending instructions in the read address cache 210, the process proceeds to step S411.

[0074] In step S411, the system switches to read mode N+1.

[0075] In step S412, the data writing instruction continues to be executed.

[0076] It should be noted that, Figure 3 and Figure 4 The flowchart in the diagram can be seen as a flowchart of instruction switching in the cache queue of a die in LPDDR5. As one implementation, once the instruction in the current die's cache queue has finished executing, the process can switch to the cache queue of another die.

[0077] See Figure 5 The flowchart 500 for the arbitration of the storage queue when switching from read mode to write mode includes S501 to S512.

[0078] In step S501, the system is in data reading mode N.

[0079] In step S502, it is determined whether the write timer has timed out. If the write timer has timed out, the process jumps to step S503; if the write timer has not timed out, the process jumps to step S504.

[0080] In step S503, the system jumps from the data read instruction for rank N to the data write instruction for rank N+1.

[0081] In step S504, the data reading instruction continues to be executed.

[0082] In step S505, it is determined whether the read address level in the storage cell queue and control 250 is greater than the minimum threshold. If the read address level in the storage cell queue and control 250 is greater than the minimum threshold, the process proceeds to step S507. If the read address level in the storage cell queue and control 250 is not greater than the minimum threshold, the process proceeds to step S506.

[0083] In step S506, it is determined whether the write address level in the storage cell queue and control 250 is greater than the maximum threshold. If the write address level in the storage cell queue and control 250 is greater than the maximum threshold, the process jumps to step S510. If the write address level in the storage cell queue and control 250 is not greater than the maximum threshold, the process jumps to step S507.

[0084] In step S507, the data reading instruction continues to be executed.

[0085] In step S508, it is determined whether there are any pending data read instructions in the storage unit queue and control 250. If there are any pending data read instructions in the storage unit queue and control 250, the process proceeds to step S509. If there are no pending data read instructions in the storage unit queue and control 250, the process proceeds to step S511.

[0086] In step S509, the data reading instruction continues to be executed.

[0087] In step S510, the system jumps to write mode N+1.

[0088] In step S511, it is determined whether there are any pending data write instructions in the storage unit queue and control 250. If there are any pending data write instructions in the storage unit queue and control 250, the process jumps to step S512.

[0089] In step S512, the system jumps to write mode N+1.

[0090] See Figure 6 The flowchart 600 for the arbitration of the storage queue when switching from write mode to read mode includes S601 to S612.

[0091] In step S601, the system is in data write mode N.

[0092] In step S602, it is determined whether the read timer has timed out. If the read timer has timed out, the process jumps to step S603; if the read timer has not timed out, the process jumps to step S604.

[0093] In step S603, the system jumps from the data write instruction for rank N to the data read instruction for rank N+1.

[0094] In step S604, the data writing instruction continues to be executed.

[0095] In step S605, it is determined whether the write address level in the storage cell queue and control 260 is greater than the minimum threshold. If the write address level in the storage cell queue and control 260 is greater than the minimum threshold, the process proceeds to step S607. If the write address level in the storage cell queue and control 260 is not greater than the minimum threshold, the process proceeds to step S606.

[0096] In step S606, it is determined whether the read address level in the storage cell queue and control 260 is greater than the maximum threshold. If the read address level in the storage cell queue and control 260 is greater than the maximum threshold, the process jumps to step S610. If the read address level in the storage cell queue and control 260 is not greater than the maximum threshold, the process jumps to step S607.

[0097] In step S607, the data writing instruction continues to be executed.

[0098] In step S608, it is determined whether there are any pending data write instructions in the storage unit queue and control 260. If there are any pending data write instructions in the storage unit queue and control 260, the process jumps to step S609. If there are no pending data write instructions in the storage unit queue and control 260, the process jumps to step S611.

[0099] In step S609, the data writing instruction continues to be executed.

[0100] In step S610, the system switches to read mode N+1.

[0101] In step S611, it is determined whether there are any pending data read instructions in the storage unit queue and control 260. If there are any pending data read instructions in the storage unit queue and control 260, the process proceeds to step S612.

[0102] In step S612, the system switches to read mode N+1.

[0103] In this embodiment of the application, when switching between data reading and data writing, instructions with lower timing requirements have higher priority, which can save latency overhead during instruction switching and improve instruction switching efficiency.

[0104] The following section uses a low-power double data rate synchronous dynamic random access memory (LPDDR) as an example to illustrate the latency overhead saved in the embodiments of this application, in conjunction with Tables 1 to 3.

[0105] Table 1 shows the timing requirements for command switching between different ranks. The corresponding settings include DQ ODT ON, NT-ODT ON, CAS-WS_FS Broadcast ON, and Link ECC OFF. These settings can be found in the fifth-generation LPDDR protocol. For example, DQ ODT ON enables the terminating resistor on the data input / output pin.

[0106] Table 1. Timing requirements for command switching between different ranks

[0107]

[0108]

[0109] Table 2 shows a timing requirement table for command switching between the same rank. The corresponding setting information for this timing requirement table includes whether the termination resistors of the data input / output pins are enabled (DQ ODT is enabled).

[0110] Table 2 shows a timing requirement table for command switching between the same rank.

[0111]

[0112] Table 3 shows another timing requirement table for command switching between the same rank. The corresponding setting information for this timing requirement table includes that the termination resistors of the data input / output pins are disabled (DQ ODT is disabled).

[0113] Table 3 shows another timing requirement table for command switching between the same rank.

[0114]

[0115] Tables 1 to 3 show the timing requirements for switching to instructions targeting different ranks and switching to instructions targeting the same rank. The timing requirements in the tables are related to DDR settings. For example, OTDLon, OTDLoff, tOTDLoff(max), and tODTon(min) are all related to the terminating resistor settings. Also, RL is the read latency, and BL is the burst length.

[0116] Referring to Table 1, when switching from a data read instruction to a data write instruction, and the data read instruction and the data write instruction correspond to different ranks, the required delay T1 is 23 clock cycles. The calculation process is as follows.

[0117] T1=RL(19)+BL / n_min(6)+tWCK2DQO(max)(1.6ns)-ODTLon(WL-3)

[0118] -tODTmin(1.5ns)+1+tRPST

[0119] =23 (cycle)

[0120] Similarly, the delay T2 for switching from a data write instruction to a data read instruction of a different rank is 1 clock cycle, and the calculation process is as follows.

[0121] T2=ODTLoff(WL+7)+RU(tODToff(max) / tCK(3.5ns)-RL)+tRPRE

[0122] =1 (cycle)

[0123] Referring to Table 2, when switching from a data read instruction to a data write instruction, and both the data read instruction and the data write instruction correspond to the same rank, the required delay T3 is 23 clock cycles. The calculation process is as follows.

[0124] T3=RL(19)+BL / n_min(6)+tWCK2DQO(max)(1.6ns)-ODTLon(RL+9)-tODTmin(1.5ns)+1

[0125] =23 (cycle)

[0126] Referring to Table 3, the delay T4 for switching from a data write instruction to a data read instruction of the same rank is 16 clock cycles, and the calculation process is as follows.

[0127] T4=WL(9)+BL / n_min(2)+tWTR(6.25ns)=16(cycle)

[0128] In summary, the timing requirement for switching from a data write instruction to a data read instruction of a different rank is 1 clock cycle, while the timing requirement for switching from a data write instruction to a data read instruction of the same rank is 16 clock cycles. Therefore, the arbitration rules of the arbitration module in the memory controller can include switching from a data write instruction to a data read instruction, with instructions of a different rank having higher priority than instructions of the same rank, which can significantly reduce read / write switching latency. In some randomized patterns, a maximum benefit of 20% can be achieved.

[0129] Figure 7 This is a schematic diagram of a storage device provided in an embodiment of this application. The storage device 700 can be the main memory in a computer or electronic device.

[0130] See Figure 7 The storage device 700 includes a dynamic random access memory 710 and a memory controller 720 as described above.

[0131] The above text combined Figures 1 to 7 The device embodiments of this application have been described in detail below, in conjunction with... Figure 8 The present application describes in detail the method embodiments. It should be understood that the description of the method embodiments corresponds to the description of the apparatus embodiments; therefore, any parts not described in detail can be referred to the preceding apparatus embodiments.

[0132] Figure 8 This is a flowchart illustrating a memory access control method provided in an embodiment of this application. The memory access control method 800 is used to control access to dynamic random access memory (DRAM). The DRAM includes multiple rank arrays.

[0133] See Figure 8 The memory access control method 800 includes step S810.

[0134] In step S810, arbitration is performed on data read instructions and / or data write instructions for the dynamic random access memory based on arbitration rules; wherein, the arbitration rules include arbitration rules based on the timing requirements of multiple rank instruction jumps.

[0135] Optionally, the multiple ranks include a first rank and a second rank, and the control method includes: in response to the switching between data read instructions and data write instructions, the priority of instructions for the first rank is higher than that of instructions for the second rank; wherein the timing requirement for switching to instructions for the first rank is less than the timing requirement for switching to instructions for the second rank.

[0136] Optionally, the arbitration rules may also include one or more of the following: arbitration rules based on read / write continuity, arbitration rules based on timer timeout, and arbitration rules based on cache queue empty / full conditions.

[0137] Optionally, the dynamic random access memory is a fifth-generation low-power double data rate memory, and the control method includes: in response to switching from a data write instruction to a data read instruction, in the data read instruction, the instruction with a different rank than the data write instruction has a higher priority than the instruction with the same rank.

[0138] It should be noted that each timing requirement table provided in this application embodiment corresponds to only one timing requirement in a setting state and does not represent the scope of application of this application embodiment.

[0139] It should be noted that the timing requirements information in the embodiments of this application is extracted from the fifth-generation LPDDR protocol.

[0140] It should be understood that in the embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0141] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0142] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0143] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0144] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0145] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0146] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can read or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs, DVDs) or semiconductor media (e.g., solid-state disks, SSDs), etc.

[0147] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory controller, characterized in that, The memory controller is used to access dynamic random access memory, the dynamic random access memory including multiple ranks, and the memory controller includes: The first cache is used to store data read instructions for the dynamic random access memory; The second cache is used to store data write instructions for the dynamic random access memory; The arbitration module arbitrates the data read command and / or the data write command based on arbitration rules; The arbitration rules include arbitration rules based on the timing requirements of the multiple rank instruction jumps; The plurality of ranks includes a first rank and a second rank, and the arbitration module is specifically used for: In response to the switching between the data read instruction and the data write instruction, the instruction for the first rank has a higher priority than the instruction for the second rank; The timing requirements for switching to instructions targeting the first rank are less than the timing requirements for switching to instructions targeting the second rank.

2. The memory controller according to claim 1, characterized in that, The arbitration rules also include one or more of the following: arbitration rules based on read / write continuity, arbitration rules based on timer timeout, and arbitration rules based on cache queue empty / full conditions.

3. The memory controller according to claim 1, characterized in that, The first cache can also be used to store the data address corresponding to the data read instruction, and the second cache can also be used to store the data address corresponding to the data write instruction.

4. The memory controller according to claim 1, characterized in that, The dynamic random access memory is a fifth-generation low-power double data rate memory, and the arbitration module is specifically used for: In response to switching from the data write instruction to the data read instruction, in the data read instruction, the instruction with a different rank than the data write instruction has a higher priority than the instruction with the same rank.

5. A method for controlling memory access, characterized in that, The memory access control method is used to control access to dynamic random access memory (DRAM), which includes multiple rank DRAMs. The control method includes: Arbitration is performed on data read instructions and / or data write instructions for the dynamic random access memory based on arbitration rules; The arbitration rules include arbitration rules based on the timing requirements of the multiple rank instruction jumps; The plurality of ranks includes a first rank and a second rank, and the control method includes: In response to the switching between the data read instruction and the data write instruction, the instruction for the first rank has a higher priority than the instruction for the second rank; The timing requirements for switching to instructions targeting the first rank are less than the timing requirements for switching to instructions targeting the second rank.

6. The memory access control method according to claim 5, characterized in that, The arbitration rules also include one or more of the following: arbitration rules based on read / write continuity, arbitration rules based on timer timeout, and arbitration rules based on cache queue empty / full conditions.

7. The memory access control method according to claim 5, characterized in that, The dynamic random access memory is a fifth-generation low-power double data rate memory, and the control method includes: In response to switching from the data write instruction to the data read instruction, in the data read instruction, the instruction with a different rank than the data write instruction has a higher priority than the instruction with the same rank.

8. A storage device, characterized in that, The storage device includes dynamic random access memory and a memory controller as described in claims 1-4.

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