Anti-interference high-reliability asynchronous host access starting circuit and working method thereof

Abstract

The application discloses an anti-interference high-reliability asynchronous host access starting circuit and a working method thereof, and the circuit is connected by a three-stage D flip-flop and a two-input AND gate. The structure makes the three-stage D flip-flop adopt the global clock of the host interface circuit as the working clock, and the phenomenon that the clock edge of the flip-flop is mis-inverted due to the change of the jitter or the interference glitch on the host access selection signal does not exist; when the jitter or the interference glitch appears on the host access selection signal, the circuit can quickly recover to the initial state and continue to normally complete the identification and starting of the host access, and has the characteristics of strong anti-interference ability and high reliability.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to an anti-interference, high-reliability asynchronous host access startup circuit and its working method. Background Technology

[0002] A computer system contains numerous input / output (I / O) components that interact with the Central Processing Unit (CPU) to perform a variety of functions. The circuit submodule within an I / O component responsible for interacting with the CPU is called the host interface module or circuit. The CPU accesses the I / O component for reading and writing through the host interface circuit. An asynchronous host interface refers to the use of different clocks for data exchange between the host interface and the CPU interface of the I / O component.

[0003] Currently, for high-speed I / O components, the third-generation high-performance I / O bus PCIe (Peripheral Component Interconnect Express) serial bus is often used as the CPU host interface. However, for computer systems with a large number of low-speed I / O components or where the CPU does not integrate a PCIe interface, using the PCIe bus as the host interface not only fails to improve the unique functions and performance of the I / O components, but also significantly increases the circuit logic scale and cost, or causes inconvenience in use. Therefore, for a large number of low-speed I / O components, especially in many embedded computers, parallel buses are still commonly used, with asynchronous access strobe signal CS, parallel address bus Addr, and parallel data bus Data as the CPU access interface. For example, low-speed bus protocol control circuits such as CAN bus, as I / O component interface circuits in embedded computers, implement the data transmission and reception functions of the corresponding bus protocol. They integrate data buffers internally, which can temporarily store the data received on the corresponding bus in the data buffer and send the received data to the CPU through the host interface after reception is completed, or receive parallel data from the CPU through the host interface and temporarily store it in the internal data buffer. After reception is completed, the data temporarily stored in the data buffer is sent to the bus of the corresponding protocol.

[0004] In asynchronous host interfaces, because the CPU and host interface circuits operate on different clocks, the host access initiation circuit becomes a critical module or circuit within the host interface circuitry. In the aforementioned host interface, the asynchronous host access strobe signal CS is the key interface signal for CPU access to I / O components. Generally, when CS is active, the CPU begins accessing the I / O component; after completing the access, the CPU deactivates the strobe signal CS to an inactive level, ending the current access. For asynchronous host interface circuits, depending on the frequency of the host interface circuit's operating clock, the access time during which the host access strobe signal remains active must be greater than a certain number of operating clock cycles. The minimum time for the host access strobe signal to become inactive between two accesses, i.e., the minimum access interval, varies depending on the host interface circuit. A smaller minimum interval provides better CPU adaptability and higher access efficiency. If the minimum access interval required by the host interface circuit is large, for CPUs with relatively high operating frequencies, it often leads to a sharp increase in the complexity of the glue logic design between the CPU and the host interface circuit.

[0005] In existing technologies, especially in host interfaces of many I / O components implemented using FPGA (Field Programmable Gate Array), the access efficiency of the host interface is often sacrificed, supporting only a larger host access interval time, requiring the minimum host access interval time to be greater than two host interface working clock cycles; or, in order to adapt to the minimum interval time of CPU access, the strobe signal CS is used as the clock of the trigger to identify the rapid change of CS.

[0006] Figure 1 The timing diagram shows the relevant information for a host interface circuit that uses the host access strobe signal CS directly as the operating clock of the flip-flop fedge_cs. As shown in the figure, the flip-flop fedge_cs in this host interface circuit operates on a falling edge trigger. Figure 1 When the access strobe signal CS first goes low, the flip-flop fedge_cs toggles once to low on the falling edge of CS. Other timing logic in the circuit detects the change in fedge on the third and subsequent rising edges of the host interface clock Clk, thus initiating the relevant host write or read operation. Normally, the strobe signal CS is generated by decoding the high-order part of the address signal Addr generated by the CPU for accessing I / O components. However, engineering practice has shown that even with a filter circuit on the printed circuit board to ensure the signal integrity of the CS pin, during long-term computer operation, due to unknown system noise and other reasons, occasional glitches on the CS signal in the host interface circuit may still cause the flip-flop to toggle incorrectly, leading to abnormal host interface access. Figure 1As shown, due to signal edge jitter or noise, the host access strobe signal goes low for the second time on the 9th rising edge of CLK to start the second access. However, after going low, a narrow jitter pulse appears. fedge_cs first flips to a high level and then quickly flips to a low level. As a result, the timing logic in the circuit does not sample the toggling of fedge_cs between the 9th and 13th rising edges of CLK, and cannot recognize and start the second host access normally, resulting in access failure. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide an anti-interference, highly reliable asynchronous host access startup circuit to solve the problems of low CPU access efficiency and adaptability of the host interface circuit and low reliability of the host interface circuit in the prior art.

[0008] To achieve the above objectives, the present invention employs the following technical solution:

[0009] An anti-interference, high-reliability asynchronous host access startup circuit includes a first-stage D flip-flop, a second-stage D flip-flop, and a third-stage D flip-flop;

[0010] The data input terminal of the first-stage D flip-flop is connected to a high level, the data output terminal of the first-stage D flip-flop is connected to the data input terminal of the second-stage D flip-flop, and the reset terminal of the first-stage D flip-flop is connected to a host access strobe signal or the inverted signal of the host strobe signal.

[0011] The data output terminal of the second-stage D flip-flop is connected to the data input terminal of the third-stage D flip-flop, and the reset terminal of the second-stage D flip-flop is connected to the global reset signal of the host interface circuit.

[0012] The reset terminal of the third-stage D flip-flop is connected to the global reset signal of the host interface circuit, and the inverting output terminal of the third-stage D flip-flop is connected to one input terminal of a two-input AND gate; a connecting line is provided on the connection line between the data output terminal of the second-stage D flip-flop and the data input terminal of the third-stage D flip-flop, and the connecting line is connected to the other input terminal of the two-input AND gate; the output terminal of the two-input AND gate is connected to the host access circuit.

[0013] The reset terminal of the first-stage D flip-flop is an asynchronous reset function port.

[0014] A further improvement of the present invention is that:

[0015] Preferably, the input clock of the first-stage D flip-flop is connected to the host interface operating clock CLK; the input clock of the second-stage D flip-flop is connected to the host interface operating clock CLK; and the input clock of the third-stage D flip-flop is connected to the host interface operating clock CLK.

[0016] Preferably, when the host access strobe signal is high-level and the reset terminals of the three D flip-flops are active high, the reset terminal of the first-stage D flip-flop is connected to the inverted signal of the host access strobe signal.

[0017] When the host access strobe signal is high and the reset terminals of the three D flip-flops are active low, the reset terminal of the first-stage D flip-flop is connected to the host access strobe signal.

[0018] Preferably, when the host access strobe signal is used for access at a low level and the reset terminal of the first-stage D flip-flop is active low, the reset terminal of the first-stage D flip-flop is connected to the inverted signal of the host access strobe signal.

[0019] When the host access strobe signal is low and the reset terminal of the first-stage D flip-flop is active high, the reset terminal of the first-stage D flip-flop is connected to the host access strobe signal.

[0020] Preferably, a delay filter circuit is provided between the reset terminal of the first-stage flip-flop and the host access strobe signal; the delay filter circuit is composed of a delay unit and a two-input OR gate.

[0021] Preferably, the input clock of the second-stage D flip-flop is connected to the inverted signal of the host interface operating clock CLK.

[0022] Preferably, the minimum interval between two consecutive accesses by the host is logically a time value that is greater than 0ns and infinitely close to 0ns.

[0023] A method for operating an anti-interference, high-reliability asynchronous host access start circuit: when the host access strobe signal jitters or there is an interference pulse, the reset terminal of the first-stage D flip-flop is activated, and the first-stage D flip-flop is reset to its initial level state; when the host access strobe signal jitters or the interference pulse disappears, the first clock is activated, causing the first-stage D flip-flop to go high, and the two-input AND gate generates the host access start signal.

[0024] Preferred, including:

[0025] (1) When the host accesses I / O components, the host access strobe signal output by the CPU becomes valid; when the CPU outputs the host access strobe signal after it becomes valid, the high level on the data input terminal D of the first stage D flip-flop is latched, and the data input terminal D of the first stage D flip-flop outputs the high level to the data output terminal Q.

[0026] (2) When the CPU outputs the second clock after the host access strobe signal is valid, the high level on the data output terminal Q of the first stage D flip-flop is latched onto the data input terminal D of the second stage D flip-flop, and the high level on the data input terminal D of the second stage D flip-flop is output to the data output terminal Q.

[0027] (3) When the CPU outputs the host access strobe signal after the third clock cycle, the high level on the data output terminal Q of the second-stage D flip-flop is latched onto the data input terminal D of the third-stage D flip-flop. The high level on the data input terminal D of the third-stage D flip-flop is then inverted and output to the inverted data output terminal. superior;

[0028] (4) During the second clock cycle after the CPU outputs the host access strobe signal, both inputs of the two-input AND gate are in a high-level state, and the output of the two-input AND gate is high.

[0029] Preferred options also include:

[0030] (1) When the host does not access the I / O component, the host access strobe signal output by the host is in an invalid level state, and the first stage D flip-flop is in a low level state;

[0031] (2) When the host finishes sequential access, the host access strobe signal output by the host becomes invalid and the first-stage D flip-flop becomes low.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] This invention discloses a highly reliable, anti-interference asynchronous host access startup circuit and its operating method. The circuit consists of a three-stage D flip-flop connected to a two-input AND gate. This structure ensures that all three D flip-flops use the global clock of the host interface circuit as their operating clock, eliminating the possibility of clock edge errors caused by jitter or glitches in the host access strobe signal. When jitter or interference glitches occur in the host access strobe signal, the circuit can quickly recover to its initial state and continue to correctly identify and start the host access, exhibiting strong anti-interference capability and high reliability. It can quickly respond to host access and support short host access intervals, providing excellent CPU interface adaptability. It simplifies the design of glue logic between the CPU and the host interface circuit. The use of the global clock of the host interface circuit as the operating clock for all three D flip-flops conforms to the mainstream digital circuit synchronous design concept, facilitating clock constraints, timing checks, and testability design. Attached Figure Description

[0034] Figure 1 The timing diagram for the host access startup circuit in the existing technology is shown below;

[0035] Figure 2 This is a schematic diagram of an anti-interference, high-reliability asynchronous host access startup circuit according to Embodiment 1 of the present invention;

[0036] Figure 3This is a timing diagram of an anti-interference, high-reliability asynchronous host access startup circuit according to Embodiment 1 of the present invention;

[0037] Figure 4 This is a schematic diagram of an anti-interference, high-reliability asynchronous host access startup circuit according to Embodiment 2 of the present invention; Detailed Implementation

[0038] The present invention will now be described in further detail with reference to the accompanying drawings:

[0039] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, unless otherwise explicitly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection or a detachable connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0040] This invention discloses an anti-interference, high-reliability asynchronous host access startup circuit, see [link to relevant documentation]. Figure 2 The circuit mainly consists of a three-stage D flip-flop (q0, q1, and q2) driven by the host interface clock signal CLK, and a two-input AND gate.

[0041] The data input port D of the first-stage D flip-flop is fixed at a high level. The input clock of the first-stage D flip-flop is connected to the host interface working clock CLK. The reset terminal of the first-stage D flip-flop is connected to the host access strobe signal CSn or the inverted signal of the host strobe signal.

[0042] The data input port D of the second-stage D flip-flop is connected to the data output port Q of the first-stage D flip-flop. The input clock of the second-stage D flip-flop is connected to the host interface working clock CLK. The reset terminal of the second-stage D flip-flop is connected to the global reset signal rstn of the host interface circuit.

[0043] The data input port D of the third-stage D flip-flop is connected to the data output port Q of the second-stage D flip-flop. The input clock of the third-stage D flip-flop is connected to the host interface working clock CLK. The reset terminal of the third-stage D flip-flop is connected to the global reset signal rstn of the host interface circuit.

[0044] The output Q of the second-stage D flip-flop and the inverted output of the third-stage D flip-flop The two input terminals are connected to the two input terminals of the two-input AND gate, and the output signal of the two-input AND gate is the host access start signal.

[0045] In the above circuit structure, when the host access strobe signal is high to indicate access and the reset terminals of the three D flip-flops are active high, the reset terminal of the first-stage D flip-flop is connected to the inverted signal of the host access strobe signal; when the host access strobe signal is high to indicate access and the reset terminals of the three D flip-flops are active low, the reset terminal of the first-stage D flip-flop is directly connected to the host access strobe signal.

[0046] When the host access strobe signal is low to indicate access and the reset terminals of the three D flip-flops are active low, the reset terminal of the first-stage D flip-flop is directly connected to the inverted signal of the host access strobe signal; when the host access strobe signal is low to indicate access and the reset terminals of the three D flip-flops are active high, the reset terminal of the first-stage D flip-flop is directly connected to the host access strobe signal.

[0047] In the circuit structure described above, the reset terminal of the first-stage D flip-flop is an asynchronous reset function port. When the host access strobe signal becomes invalid due to the end of host access or due to signal jitter or interference, the first-stage D flip-flop quickly enters the reset state through this reset port.

[0048] The anti-interference principle of a high-reliability asynchronous host access start circuit is as follows: when the host access strobe signal jitters or there is an interference pulse, the jitter or interference pulse makes the reset terminal of the first-stage D flip-flop effective, causing the first-stage D flip-flop to quickly reset to the initial level state; when the jitter or interference pulse disappears, the host interface circuit can continue to work in the normal initial state. On the first clock edge after the jitter or interference pulse disappears, the first-stage D flip-flop can continue to change to the high level state, and the subsequent two-input AND gate can generate an effective host access start signal.

[0049] More specifically, the operation process of this interference-resistant, high-reliability asynchronous host access startup circuit is as follows:

[0050] 1) When the host does not access the I / O components, the host access strobe signal output by the CPU is in an invalid level state. The host access strobe signal or the reverse signal of the host access strobe signal drives the reset terminal of the first stage D flip-flop to be valid, so that the first stage D flip-flop is quickly reset to a low level state.

[0051] 2) When the host accesses I / O components, the host access strobe signal output by the CPU becomes valid, and the first-stage D flip-flop is in clock working mode; on the first clock edge after the host access strobe signal output by the CPU becomes valid, the first-stage D flip-flop latches the high level on the data input terminal D and outputs it to the data output terminal Q.

[0052] 3) When the host access strobe signal output by the CPU is valid, the second clock starts, and the high level on the data output terminal Q of the first stage D flip-flop is latched to the second stage D flip-flop and output to the data output terminal Q.

[0053] 4) When the host access strobe signal output by the CPU is valid, the third clock cycle starts, latching the high level on the data output terminal Q of the second-stage D flip-flop to the third-stage D flip-flop, inverting it, and outputting it to the inverted data output terminal. superior;

[0054] 5) During the second clock cycle after the CPU outputs the host access strobe signal, the input of the Q terminal of the second-stage D flip-flop connected to the two-input AND gate is in a high-level state, and the input of the third-stage D flip-flop connected to the two-input AND gate is in a high-level state. When the input of the terminal is in a high-level state, the output of the two-input AND gate is high-level, that is, the host access start signal is in a high-level active state, indicating that a host access has been detected;

[0055] 6) When the host ends the current access, the host access strobe signal output by the CPU becomes invalid. The host access strobe signal or the reverse signal of the host access strobe signal drives the reset terminal of the first-stage D flip-flop to be valid, so that the first-stage D flip-flop returns to the initial low-level state after reset, and is ready for the next host access.

[0056] As one of the preferred solutions, an anti-interference, high-reliability asynchronous host access startup circuit supports a minimum interval time for two consecutive host accesses that is logically greater than and infinitely close to 0 ns, but the actual time is related to factors such as the process parameters used in the circuit.

[0057] As one of the preferred solutions, in order to further improve the anti-interference capability of the host access strobe signal in the above circuit structure, a delay filtering logic for the host access strobe signal can be added to the host access startup circuit based on the minimum interval time of the host access strobe signal in the target computer system, and then connected to the reset terminal of the first-stage D flip-flop.

[0058] As one of the preferred solutions, in order to reduce the delay time between the valid host access strobe signal and the valid host access start signal in the above circuit structure, the clock terminal of the second-stage D flip-flop can also be improved to be connected to the inverted signal of the host interface clock CLK; in this way, when the data output terminal Q of the first-stage D flip-flop outputs a high level, the second-stage D flip-flop can latch the high level output of the first-stage D flip-flop at the next clock edge, and generate a valid host access start signal in the second half of the first clock cycle after the valid host access strobe signal.

[0059] In the circuit structure described above, reducing the propagation delay from the external pin of the host access strobe signal to the reset terminal of the first-stage D flip-flop in the circuit layout design can reduce the delay time between the host access strobe signal being valid and the host access start signal being valid.

[0060] Example 1

[0061] In the host interface circuit of Embodiment 1 of the present invention, the host access strobe signal CS is a low active access signal. When CS is low, a host access begins, and when CS is high, the current access ends.

[0062] Figure 2 This is a circuit schematic diagram of an embodiment of an anti-interference, high-reliability asynchronous host access startup circuit according to the present invention; as shown below. Figure 2 As shown, an anti-interference high-reliability asynchronous host access startup circuit of an embodiment mainly consists of a three-stage D flip-flop driven by the host interface clock CLK (q0, q1, and q2) and a two-input AND gate.

[0063] The data input port D of the first-stage D flip-flop is fixed at a high level. The input clock is connected to the host interface working clock CLK, and the clock working edge is the rising edge. The reset terminal CLR is connected to the host access strobe signal.

[0064] The data input port D of the second-stage D flip-flop is connected to the data output port Q of the first-stage D flip-flop. The input clock is connected to the host interface working clock CLK, with the clock working edge being the rising edge. The reset terminal CLR is connected to the global reset signal rstn of the host interface circuit.

[0065] The data input port D of the third-stage D flip-flop is connected to the data output port Q of the second-stage D flip-flop. The input clock is connected to the host interface working clock CLK, with the clock working edge being the rising edge. The reset terminal CLR is connected to the global reset signal rstn of the host interface circuit.

[0066] The output Q of the second-stage D flip-flop and the inverted output of the third-stage D flip-flop The terminals are connected to the two input terminals of the two-input AND gate, and the output signal acc_start of the two-input AND gate is the host access start signal.

[0067] In this embodiment, an anti-interference, high-reliability asynchronous host access start-up circuit is provided. The host access strobe signal is low to indicate access and the reset terminal CLR of the D flip-flop is active high. Therefore, the reset terminal CLR of the first-stage D flip-flop is directly connected to the host access strobe signal CSn.

[0068] In the above circuit structure, the reset terminal of the first-stage D flip-flop is an asynchronous reset function port. When the host access strobe signal becomes invalid due to the end of host access or due to signal jitter or interference, the first-stage D flip-flop quickly enters the reset state through this reset port.

[0069] Figure 3 The following is a timing diagram of the relevant circuits in an embodiment of the present invention; such as Figure 3 As shown, the working principle of the interference-resistant high-reliability asynchronous host access startup circuit in this embodiment is as follows:

[0070] 1) When the host is not accessing I / O components, the host access strobe signal output by the CPU is in a high-level state. The host access strobe signal or the inverted signal of the host access strobe signal drives the reset terminal CLR of the first-stage D flip-flop to be valid, so that the first-stage D flip-flop is quickly reset to a low-level state.

[0071] 2) When the host accesses I / O components, the host access strobe signal output by the CPU becomes valid, and the first-stage D flip-flop is in clock working mode; when the host access strobe signal output by the CPU goes low and becomes valid on the first rising edge of the clock, the first-stage D flip-flop latches the high level on the data input terminal D and outputs it to the data output terminal Q.

[0072] 3) On the second rising edge of the clock after the host access strobe signal output by the CPU is valid, the second-stage D flip-flop latches the high level on the data output terminal Q of the first-stage D flip-flop to the second-stage D flip-flop and outputs it to the data output terminal Q.

[0073] 4) On the third rising edge of the clock after the CPU outputs the host access strobe signal, the third-stage D flip-flop latches the high level on the data output terminal Q of the second-stage D flip-flop, inverts it, and outputs it to the output terminal. superior;

[0074] 5) During the second clock cycle after the CPU outputs the host access strobe signal, the input of the Q terminal of the second-stage D flip-flop connected to the two-input AND gate is in a high-level state, and the input of the third-stage D flip-flop connected to the two-input AND gate is in a high-level state. When the input to the terminal is high, the output of the two-input AND gate is high. That is, the host access start signal acc_start is high, indicating that a host access has been detected.

[0075] 6) When the host ends the current access, the host access strobe signal output by the CPU becomes high. The reset terminal of the first-stage D flip-flop driven by the host access strobe signal is valid, so that the first-stage D flip-flop returns to the initial low-level state after reset, which is ready for the next host access.

[0076] The anti-interference principle of the anti-interference high-reliability asynchronous host access startup circuit in this embodiment is as follows: Figure 3 As shown, when the host access strobe signal jitters or there is an interference pulse, the jitter or interference pulse makes the asynchronous reset terminal of the first-stage D flip-flop effective, causing the first-stage D flip-flop to quickly reset to the initial low-level state; when the jitter or interference pulse disappears, the host interface circuit continues to work in the normal initial state. On the first rising edge of the clock after the jitter or interference pulse disappears, the first-stage D flip-flop becomes high-level, and the subsequent two-input AND gate can generate a highly active host access start signal acc_start;

[0077] This embodiment of an anti-interference, high-reliability asynchronous host access startup circuit supports a minimum interval time for two consecutive host accesses. Logically, this interval time is greater than and infinitely close to 0 ns. After implementation using the target process, it supports a minimum interval time of 18 ns. In the circuit layout design of this embodiment, the propagation delay time from the host access strobe signal external pin to the reset terminal of the first-stage D flip-flop in the circuit is minimized. This allows the host access strobe signal to be established 10 ns before the rising edge of the clock and the host access startup signal to be generated after the next rising edge of the clock, resulting in a low delay time.

[0078] Example 2

[0079] The schematic diagram of the host access startup circuit in Embodiment 2 of the present invention is as follows: Figure 4 As shown; In this embodiment, in order to prevent abnormal low pulses caused by noise on the host access strobe signal when the host is not accessing it, and to further improve the anti-interference capability of the host access strobe signal on the host access startup circuit, the host access strobe signal is delayed and filtered by a typical value of 20ns according to the minimum interval time of the host access strobe signal in the target computer system where the circuit of this embodiment is applied, and then connected to the reset terminal of the first-stage D flip-flop; The delay filtering circuit is composed of a delay unit and a two-input OR gate. The host access strobe signal and its delayed signal are logically ORed by the two-input OR gate to generate the filtered host access strobe signal; Under typical temperature and power supply voltage conditions, the host access startup circuit of this embodiment can filter out low pulses with a width of 20ns on the host access strobe signal, and within the full operating temperature and power supply voltage range, it can filter out low pulses with a width of 11ns to 30ns on the host access strobe signal.

[0080] In Embodiment 2 of the present invention, in order to reduce the delay time between the effective host access strobe signal and the effective host access start signal, the clock terminal of the second-stage D flip-flop can also be improved to be connected to the inverse signal of the host interface clock CLK; in this way, when the data output terminal Q of the first-stage D flip-flop outputs a high level, the second-stage D flip-flop can latch the high level output of the first-stage D flip-flop at the next clock edge, and generate an effective host access start signal in the second half of the first clock cycle after the effective host access strobe signal.

[0081] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-reliability, interference-resistant asynchronous host access startup circuit, characterized in that, This includes first-level D flip-flops, second-level D flip-flops, and third-level D flip-flops; The data input terminal of the first-stage D flip-flop is connected to a high level, the data output terminal of the first-stage D flip-flop is connected to the data input terminal of the second-stage D flip-flop, and the reset terminal of the first-stage D flip-flop is connected to a host access strobe signal or the inverted signal of the host strobe signal. The data output terminal of the second-stage D flip-flop is connected to the data input terminal of the third-stage D flip-flop, and the reset terminal of the second-stage D flip-flop is connected to the global reset signal of the host interface circuit. The reset terminal of the third-stage D flip-flop is connected to the global reset signal of the host interface circuit, and the inverting output terminal of the third-stage D flip-flop is connected to one input terminal of a two-input AND gate; a connecting line is provided on the connection line between the data output terminal of the second-stage D flip-flop and the data input terminal of the third-stage D flip-flop, and the connecting line is connected to the other input terminal of the two-input AND gate; the output terminal of the two-input AND gate is connected to the host access circuit. The reset terminal of the first-stage D flip-flop is an asynchronous reset function port; The input clock of the first-stage D flip-flop is connected to the host interface operating clock CLK. The input clock of the second-stage D flip-flop is connected to the host interface operating clock CLK. The input clock of the third-stage D flip-flop is connected to the host interface operating clock CLK.

2. The anti-interference high-reliability asynchronous host access startup circuit according to claim 1, characterized in that, When the host access strobe signal is high and the reset terminals of the three D flip-flops are active high, the reset terminal of the first-stage D flip-flop is connected to the inverted signal of the host access strobe signal. When the host access strobe signal is high and the reset terminals of the three D flip-flops are active low, the reset terminal of the first-stage D flip-flop is connected to the host access strobe signal.

3. The anti-interference high-reliability asynchronous host access startup circuit according to claim 1, characterized in that, When the host access strobe signal is low-level and the reset terminal of the first-stage D flip-flop is active low, the reset terminal of the first-stage D flip-flop is connected to the inverted signal of the host access strobe signal. When the host access strobe signal is low and the reset terminal of the first-stage D flip-flop is active high, the reset terminal of the first-stage D flip-flop is connected to the host access strobe signal.

4. The anti-interference high-reliability asynchronous host access startup circuit according to claim 1, characterized in that, A delay filter circuit is provided between the reset terminal of the first-stage flip-flop and the host access strobe signal; the delay filter circuit is composed of a delay unit and a two-input OR gate.

5. The anti-interference high-reliability asynchronous host access startup circuit according to claim 1, characterized in that, The input clock of the second-stage D flip-flop is connected to the inverted signal of the host interface operating clock CLK.

6. The anti-interference high-reliability asynchronous host access startup circuit according to any one of claims 1-5, characterized in that, Logically, the minimum interval between two consecutive accesses by the host is a time value that is greater than 0ns and infinitely close to 0ns.

7. A method for operating the anti-interference high-reliability asynchronous host access startup circuit as described in claim 1, characterized in that, When the host access strobe signal jitters or there is an interference pulse, the reset terminal of the first-stage D flip-flop is activated, and the first-stage D flip-flop is reset to its initial level state. When the host access strobe signal jitters or the interference pulse disappears, the first clock cycle starts, causing the first-stage D flip-flop to go high, and the two-input AND gate generates the host access start signal.

8. The operating method of the anti-interference high-reliability asynchronous host access startup circuit according to claim 7, characterized in that, include: (1) When the host accesses the I / O component, the host access strobe signal output by the CPU becomes valid; when the CPU outputs the host access strobe signal after the first clock cycle, the high level on the data input terminal D of the first stage D flip-flop is latched, and the data input terminal D of the first stage D flip-flop outputs the high level to the data output terminal Q. (2) When the CPU outputs the second clock after the host access strobe signal is valid, the high level on the data output terminal Q of the first stage D flip-flop is latched onto the data input terminal D of the second stage D flip-flop, and the high level on the data input terminal D of the second stage D flip-flop is output to the data output terminal Q. (3) When the CPU outputs the host access strobe signal after the third clock cycle, the high level on the data output terminal Q of the second stage D flip-flop is latched onto the data input terminal D of the third stage D flip-flop, and the high level on the data input terminal D of the third stage D flip-flop is inverted and output to the inverted data output terminal Q. (4) During the second clock cycle after the CPU outputs the host access strobe signal, both inputs of the two-input AND gate are in a high-level state, and the output of the two-input AND gate is high.

9. The operating method of the anti-interference high-reliability asynchronous host access startup circuit according to claim 8, characterized in that, Also includes: (1) When the host does not access the I / O component, the host access strobe signal output by the host is in an invalid level state, and the first stage D flip-flop is in a low level state; (2) When the host finishes sequential access, the host access strobe signal output by the host becomes invalid and the first stage D flip-flop becomes low.

Images