Pixel circuit, driving method thereof and display device

Abstract

The application provides a pixel circuit, a driving method thereof and a display device, wherein the pixel circuit comprises a first reset transistor, a compensation transistor, a data writing transistor, a second reset transistor and a light emitting control transistor; the first reset transistor is coupled between a gate of a driving transistor and an initialization signal terminal, and the gate is coupled with a first scan control terminal; the compensation transistor is coupled between the gate of the driving transistor and a first electrode, and the gate is coupled with a second scan control terminal; the data writing transistor is coupled between a first electrode of a storage capacitor and a data signal terminal, and the gate is coupled with a third scan control terminal; the second reset transistor is coupled between the first electrode of the storage capacitor and a reference signal terminal, and a second electrode of the storage capacitor is coupled with the gate of the driving transistor; the light emitting control transistor is coupled between a first electrode of the driving transistor and a first electrode of a light emitting device, and the gate is coupled with a light emitting control terminal; the third reset transistor is coupled between the first electrode of the light emitting device and the initialization signal terminal, and the gate is coupled with the first scan control terminal; and a second electrode of the driving transistor is coupled with a first power supply terminal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel circuit, a driving method thereof and a display device. BACKGROUND

[0002] With the development of active matrix organic light emitting diode (AMOLED) technology, people's requirements for its picture quality are also getting higher and higher. In the process of pursuing higher picture quality, the problems caused by manufacturing process, such as the threshold voltage uniformity of driver thin film transistor (DTFT), the hysteresis of DTFT leading to residual image, abnormal first frame brightness, and low gray scale flicker when switching different driving frequencies, need to be solved urgently. SUMMARY

[0003] The present application provides a pixel circuit, a driving method thereof and a display device, for improving the display effect of the display device when driven at low frequency.

[0004] In a first aspect, an embodiment of the present application provides a pixel circuit, comprising:

[0005] a first reset transistor, a compensation transistor, a data writing transistor, a second reset transistor, a light emitting control transistor, a third reset transistor, a driving transistor, a light emitting device and a storage capacitor; wherein:

[0006] the first reset transistor is coupled between the gate of the driving transistor and an initialization signal end, and the gate is coupled with a first scan control end;

[0007] the compensation transistor is coupled between the gate of the driving transistor and a first pole, and the gate is coupled with a second scan control end, wherein the second scan control end and the first scan control end are provided by different stage output ends of a same first gate driving unit, and the first scan control signal received by the first scan control end is earlier than the second scan control signal received by the second scan control end;

[0008] the data writing transistor is coupled between the first pole of the storage capacitor and a data signal end, and the gate is coupled with a third scan control end;

[0009] the second reset transistor is coupled between the first pole of the storage capacitor and a reference signal end, and the second pole of the storage capacitor is coupled with the gate of the driving transistor;

[0010] the light emitting control transistor is coupled between the first pole of the driving transistor and the first pole of the light emitting device, and the gate is coupled with a light emitting control end;

[0011] the third reset transistor is coupled between the first electrode of the light emitting device and the initialization signal terminal, and a gate electrode is coupled with the first scan control terminal;

[0012] a second electrode of the driving transistor is coupled with a first power supply terminal, and a second electrode of the light emitting device is coupled with a second power supply terminal;

[0013] wherein the first reset transistor, the compensation transistor and the third reset transistor are of the same type.

[0014] In a possible implementation, the second reset transistor comprises a first sub-transistor and a second sub-transistor of the same type as the data write transistor, and are coupled between the reference signal terminal and a first electrode of the storage capacitor respectively, a gate electrode of the first sub-transistor is coupled with the light emitting control terminal, and a gate electrode of the second sub-transistor is coupled with a fourth scan control terminal, wherein the fourth scan control terminal and the third scan control terminal are provided by different stage output terminals of a same second gate driving unit, and a fourth scan control signal received by the fourth scan control terminal is earlier than a third scan control signal received by the third scan control terminal.

[0015] In a possible implementation, the second reset transistor is a transistor of the same type as the first reset transistor, and a gate electrode is coupled with a fifth scan control terminal.

[0016] In a possible implementation, the first reset transistor, the compensation transistor and the third reset transistor are all N-type transistors, and the driving transistor, the data write transistor and the light emitting control transistor are all P-type transistors.

[0017] In a possible implementation, the first reset transistor, the compensation transistor and the third reset transistor are all oxide transistors, and the driving transistor, the data write transistor and the light emitting control transistor are all polysilicon transistors.

[0018] In a second aspect, an embodiment of the present application further provides a display device, comprising:

[0019] a plurality of pixel circuits as any one of the above.

[0020] In a third aspect, an embodiment of the present application further provides a driving method of the pixel circuit as any one of the above, comprising:

[0021] According to a current refresh frequency of the display device and a reference refresh frequency, a current display frame of the display device is divided into one refresh frame and N holding frames, where N is an integer greater than 1; wherein the refresh frame comprises a first stage, a second stage and a third stage arranged in sequence, and each holding frame comprises a fourth stage, a fifth stage and a sixth stage arranged in sequence.

[0022] In the fourth stage, the first reset transistor and the third reset transistor are controlled to be turned on, and the potential of the second electrode of the storage capacitor and the first electrode of the light emitting device is reset through the initialization signal end;

[0023] In the fifth stage, the compensation transistor is controlled to be turned on, the threshold voltage of the driving transistor and the voltage of the first power supply end are written into the gate of the driving transistor through the compensation transistor, and are stored to the storage capacitor, and the driving transistor is adjusted from the on state to the off state;

[0024] In the sixth stage, the second reset transistor and the light emitting control transistor are controlled to be turned on, the potential of the first electrode of the storage capacitor is reset through the reference signal end, and the light emitting device is controlled to emit light under the driving of the driving transistor.

[0025] In a possible implementation, for the refresh frame, the method further comprises:

[0026] In the first stage, the first reset transistor, the second reset transistor and the third reset transistor are controlled to be turned on, the potential of the first electrode of the storage capacitor is reset through the reference signal end, and the potential of the second electrode of the storage capacitor and the first electrode of the light emitting device is reset through the initialization signal end;

[0027] In the second stage, the data write transistor and the compensation transistor are controlled to be turned on, the data signal provided by the data signal end is loaded to the first electrode of the storage capacitor, and the threshold voltage of the driving transistor and the voltage of the first power supply end are written into the gate of the driving transistor through the compensation transistor, and are stored to the storage capacitor;

[0028] In the third stage, the second reset transistor and the light emitting control transistor are controlled to be turned on, the potential of the first electrode of the storage capacitor is reset through the reference signal end, and the light emitting device is controlled to emit light.

[0029] In a possible implementation, the second reset transistor comprises a first sub-transistor and a second sub-transistor of the same type as the data write transistor, and is coupled between the reference signal end and the first electrode of the storage capacitor respectively, the gate of the first sub-transistor is coupled with the light-emitting control end, and the gate of the second sub-transistor is coupled with the fourth scan control end; the method further comprises:

[0030] In the first stage, the second sub-transistor is controlled to be turned on, and the potential of the first electrode of the storage capacitor is reset through the reference signal end.

[0031] In a possible implementation, the method further comprises:

[0032] In the third stage, the first sub-transistor is controlled to be turned on, and the potential of the first electrode of the storage capacitor is reset through the reference signal end.

[0033] The present application has the following advantages:

[0034] The embodiment of the present application provides a pixel circuit, a driving method thereof and a display device, wherein the pixel circuit comprises a first reset transistor, a compensation transistor, a data write transistor, a second reset transistor, a light-emitting control transistor, a third reset transistor, a driving transistor, a light-emitting device and a storage capacitor; wherein the first reset transistor is coupled between the gate of the driving transistor and the initialization signal end, and the gate is coupled with the first scan control end, so that the first reset transistor can be turned on under the control of the first scan control end; the compensation transistor is coupled between the gate of the driving transistor and the first electrode, and the gate is coupled with the second scan control end, the second scan control end and the first scan control end are provided by different stage output ends of the same first gate driving unit, and the first scan control signal received by the first scan control end is earlier than the second scan control signal received by the second scan control end, thereby saving the number of gate driving units; the data write transistor is coupled between the first electrode of the storage capacitor and the data signal end, and the gate is coupled with the third scan control end, so that the data write transistor can be turned on under the control of the third scan control end, and when the compensation transistor is turned on, the data signal provided by the data signal end, the threshold voltage of the driving transistor and the voltage signal provided by the first power supply end coupled with the second electrode of the driving transistor can be written into the storage capacitor, thereby realizing compensation of the threshold voltage of the driving transistor and voltage drop compensation of the first power supply end.

[0035] The second reset transistor is coupled between the first terminal of the storage capacitor and the reference signal terminal, and the second terminal of the storage capacitor is coupled to the gate of the driving transistor. Thus, when the second reset transistor is turned on, the potential of the first terminal of the storage capacitor can be reset to the signal potential of the reference signal terminal. Furthermore, the third reset transistor is coupled between the first terminal of the light-emitting device and the initialization signal terminal, and its gate is coupled to the first scan control terminal. Thus, under the control of the first scan control terminal, the third reset transistor can be turned on, resetting the first terminal of the light-emitting device to the signal potential of the initialization signal terminal. When the first terminal of the light-emitting device is anode, the problem of frequency switching flicker is avoided. In addition, the second terminal of the driving transistor is coupled to the first power supply terminal, and the second terminal of the light-emitting device is coupled to the second power supply terminal, thereby ensuring the driving capability of the pixel circuit. Through the pixel circuit provided by this embodiment of the invention, in the refresh frame and hold frame of the entire display frame, not only can the gate potential of the driving transistor be reset, but the number of data write compensations can also be increased, avoiding the problem of charge capture accumulation in the driving transistor. This improves the insufficient brightness of the first frame and the image retention problem during screen switching, and enhances the display effect of the display device when driven at low frequencies. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the structure of one type of pixel circuit used in related technologies;

[0037] Figure 2 for Figure 1 The pixel circuit shown is one of the timing diagrams used in this circuit.

[0038] Figure 3 This is a schematic diagram of one possible structure of a pixel circuit provided in an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of one possible structure of a pixel circuit provided in an embodiment of the present invention;

[0040] Figure 5 This is a schematic diagram of one possible structure of a pixel circuit provided in an embodiment of the present invention;

[0041] Figure 6 for Figure 4 The pixel circuit shown corresponds to one of the timing diagrams of the refresh frame;

[0042] Figure 7 for Figure 4 The pixel circuit shown is one of the timing diagrams for the holding frame.

[0043] Figure 8 for Figure 5 The pixel circuit shown corresponds to one of the timing diagrams of the refresh frame;

[0044] Figure 9 For Figure 5 The pixel circuit shown in the figure corresponds to one of the timing diagrams of the holding frame;

[0045] Figure 10 For Figure 4 The pixel circuit shown in the figure corresponds to one of the timing diagrams of the holding frame;

[0046] Figure 11 For

[0047] Figure 12 For

[0048] Figure 13 For

[0049] Explanation of reference signs:

[0050] T1-first reset transistor; T2-compensation transistor; T3-data writing transistor; T0-second reset transistor; T4-first sub-transistor; T5-second sub-transistor; T6-emission control transistor; T7-third reset transistor; DT-driving transistor; 10-emission device; C-storage capacitor; Vint-initialization signal terminal; N_Gate(n-1)-first scan control terminal; N_Gate(n)-second scan control terminal; P_Gate(n)-third scan control terminal; Vref-reference signal terminal; EM(n)-emission control terminal; ELVDD-first power supply terminal; ELVSS-second power supply terminal; P_Gate(n-1)-fourth scan control terminal; EM_NGate(n)-fifth scan control terminal; t1-first stage; t2-second stage; t3-third stage; t4-fourth stage; t5-fifth stage; t6-sixth stage. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be described clearly and completely below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. And in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Based on the described embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor belong to the protection scope of the present application.

[0052] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. The terms "comprising", "comprises" and "comprised of" as used herein are synonymous with "including", "includes" or "containing", "contains", and allow for the presence of zero, one or more elements, integers, components or objects.

[0053] It should be noted that the size and shape of the various figures in the drawings are not to scale, and are intended merely to illustrate the present disclosure. Identical or similar components or components having identical or similar functions are denoted by identical or similar reference numerals throughout.

[0054] In the related art, pixel circuits such as Figure 1 and timing diagrams such as Figure 2 are often used, in which M3 represents a DTFT, L represents a light emitting device, Cst represents a capacitor, n01, n02 and n03 represent nodes respectively coupled to each pole of the DTFT, M1 and M2 are N-type transistors, M3, M4, M5, M6 and M7 are P-type transistors, M1 and M2 are metal oxide transistors, and M3 to M7 are low temperature polysilicon transistors. The threshold voltage of the DTFT is compensated for, the uniformity of the threshold voltage of the DTFT is ensured, and the problem of low frequency flicker is improved. Still in combination with Figure 1 and Figure 2 , in the 01 stage, the n01 node is reset; in the 02 stage, the data signal is written, and the threshold voltage of the DTFT is compensated for; in the 03 stage, the anode of the light emitting device L (corresponding to the n04 node in Figure 1 ) is reset; and in the 04 stage, the light emitting device L emits light. For the specific working process of the pixel circuit shown in Figure 1 , reference can be made to the specific implementation in the related art, which will not be described in detail here.

[0055] In the pixel circuit shown in Figure 1 , NR and NG are driven by the same group of gate on array (GOA) driving circuits, PG and PR are driven by the same group of GOA driving circuits, and Vinit1 and Vinit2 can use the same signal or different signals. Through the pixel circuit, the threshold voltage of the DTFT can be compensated for. Since M1 and M2 are metal oxide transistors, anode reset can be performed during frame retention, thereby avoiding low frequency flicker. However, in the pixel circuit described in Figure 1 , only the capacitor Cst is reset and charged during refresh frame, and data writing and DTFT threshold voltage compensation, which is easy to cause charge trapping to accumulate in the DTFT, resulting in insufficient first frame brightness and residual image during picture switching and other problems.

[0056] In view of this, the pixel circuit, the driving method thereof and the display device are provided to improve the display effect of the display device in low-frequency driving.

[0057] As shown in Figure 3 The pixel circuit comprises:

[0058] a first reset transistor T1, a compensation transistor T2, a data writing transistor T3, a second reset transistor T0, a light emitting control transistor T6, a third reset transistor T7, a driving transistor DT, a light emitting device 10 and a storage capacitor C; wherein:

[0059] The first reset transistor T1 is coupled between the gate of the driving transistor DT and an initialization signal terminal Vint, and the gate is coupled with a first scan control terminal N_Gate(n-1);

[0060] The compensation transistor T2 is coupled between the gate of the driving transistor DT and a first electrode, and the gate is coupled with a second scan control terminal N_Gate(n), wherein the second scan control terminal N_Gate(n) and the first scan control terminal N_Gate(n-1) are provided by different stage output terminals of the same first gate driving unit, and the first scan control signal received by the first scan control terminal N_Gate(n-1) is earlier than the second scan control signal received by the second scan control terminal N_Gate(n);

[0061] The data writing transistor T3 is coupled between the first electrode of the storage capacitor C and a data signal terminal, and the gate is coupled with a third scan control terminal P_Gate(n);

[0062] The second reset transistor T0 is coupled between the first electrode of the storage capacitor C and a reference signal terminal Vref, and the second electrode of the storage capacitor C is coupled with the gate of the driving transistor DT;

[0063] The light emitting control transistor T6 is coupled between the first electrode of the driving transistor DT and the first electrode of the light emitting device 10, and the gate is coupled with a light emitting control terminal EM(n);

[0064] The third reset transistor T7 is coupled between the first electrode of the light emitting device 10 and the initialization signal terminal Vint, and the gate is coupled with the first scan control terminal N_Gate(n-1);

[0065] The second electrode of the driving transistor DT is coupled with a first power supply terminal ELVDD, and the second electrode of the light emitting device 10 is coupled with a second power supply terminal ELVSS;

[0066] The first reset transistor T1, the compensation transistor T2, and the third reset transistor T7 are of the same type.

[0067] Still in combination Figure 3 As shown in the pixel circuit provided by the embodiment of the present application, the pixel circuit comprises a first reset transistor T1, a compensation transistor T2, a data writing transistor T3, a second reset transistor T0, a light emitting control transistor T6, a third reset transistor T7, a driving transistor DT, a light emitting device 10, and a storage capacitor C. The first reset transistor T1 is coupled between the gate of the driving transistor DT and an initialization signal terminal Vint, and coupled with a first scan control terminal N_Gate(n-1). In this way, when the first reset transistor T1 is turned on, the gate of the driving transistor DT can be reset by the initialization signal terminal Vint. The compensation transistor T2 is coupled between the gate of the driving transistor DT and a first electrode, and coupled with a second scan control terminal N_Gate(n). The data writing transistor T3 is coupled between a first electrode of the storage capacitor C and a data signal terminal, and coupled with a third scan control terminal P_Gate(n). The second electrode of the storage capacitor C is coupled with the gate of the driving transistor DT, the second electrode of the driving transistor DT is coupled with a first power supply terminal ELVDD, and the second electrode of the light emitting device 10 is coupled with a second power supply terminal ELVSS. The first power supply terminal ELVDD can be a high potential power supply terminal, and can provide a constant high potential signal. The second power supply terminal ELVSS can be a low potential power supply terminal, and can provide a constant low potential signal. In this way, when the data writing transistor T3 and the compensation transistor T2 are both turned on, the signal provided by the first power supply terminal ELVDD, the threshold voltage of the driving transistor DT, and the data signal provided by the data signal terminal can be written into the storage capacitor C, so that the threshold voltage of the driving transistor DT is compensated. In addition, the second scan control terminal N_Gate(n) and the first scan control terminal N_Gate(n-1) are provided by different stage output terminals of the same first gate driving unit, and the first scan control signal received by the first scan control terminal N_Gate(n-1) is earlier than the second scan control signal received by the second scan control terminal N_Gate(n). In this way, the storage capacitor C can be reset before the data signal is written into the storage capacitor C, effectively improving the hysteresis problem of the driving transistor DT, and avoiding problems such as residual image and abnormal first frame brightness.

[0068] Still in combination Figure 3As shown, the second reset transistor T0 is coupled between the first pole of the storage capacitor C and the reference signal terminal Vref, and the second pole of the storage capacitor C is coupled with the gate of the driving transistor DT, so that the first pole of the storage capacitor C can be reset by the reference signal terminal Vref when the second reset transistor T0 is turned on. The light emitting control transistor T6 is coupled between the first pole of the driving transistor DT and the first pole of the light emitting device 10, and the gate is coupled with the light emitting control terminal EM(n), so that the light emitting device 10 can be driven to emit light when the second reset transistor T0, the compensation transistor T2 and the light emitting transistor are all turned on. In addition, the first reset transistor T1, the compensation transistor T2 and the third reset transistor T7 are of the same type, and the three transistors can all be N-type oxide transistors, thereby avoiding the problem of leakage current and reducing the power consumption of the pixel circuit.

[0069] In the specific implementation process, the pixel circuit shown in the embodiment of the present application is adopted Figure 3 The pixel circuit shown not only can realize compensation of the threshold voltage of the driving transistor DT, but also can realize reset of the storage capacitor C, and in addition, the number of compensation times of the threshold voltage of the driving transistor DT is increased, thereby effectively improving the hysteresis problem of the driving transistor DT and avoiding the problems of residual image and abnormal first frame brightness.

[0070] In the embodiment of the present application, the second reset transistor T0 in the pixel circuit can have the following setting modes. In one exemplary embodiment, as shown in Figure 4 The second reset transistor T0 includes a first sub-transistor T4 and a second sub-transistor T5 which are of the same type as the data writing transistor T3, and are coupled between the reference signal terminal Vref and the first pole of the storage capacitor C, respectively, the gate of the first sub-transistor T4 is coupled with the light emitting control terminal EM(n), and the gate of the second sub-transistor T5 is coupled with the fourth scan control terminal P_Gate(n-1), wherein the fourth scan control terminal P_Gate(n-1) and the third scan control terminal P_Gate(n) are provided by different stages of the same second gate driving unit, and the fourth scan control signal received by the fourth scan control terminal P_Gate(n-1) is earlier than the third scan control signal received by the third scan control terminal P_Gate(n).

[0071] Still in combination with Figure 4As shown, the second reset transistor T0 includes a first sub-transistor T4 and a second sub-transistor T5 which are of the same type as the data writing transistor T3. In one exemplary embodiment, the data writing transistor T3, the first sub-transistor T4 and the second sub-transistor T5 are all P-type low temperature poly-silicon transistors, thereby improving the electron mobility of the pixel circuit and ensuring the driving capability of the pixel circuit. The first sub-transistor T4 and the second sub-transistor T5 are coupled between the reference signal terminal Vref and the first electrode of the storage capacitor C, so that when either of the first sub-transistor T4 and the second sub-transistor T5 is turned on, the first electrode of the storage capacitor C can be reset by the reference signal terminal Vref, thereby increasing the number of times of resetting the first electrode of the storage capacitor C. In addition, the gate of the first sub-transistor T4 is coupled to the light emitting control terminal EM(n), and the gate of the second sub-transistor T5 is coupled to the fourth scan control terminal P_Gate(n-1), wherein the fourth scan control terminal P_Gate(n-1) and the third scan control terminal P_Gate(n) are provided by different stages of the same second gate driving unit, and the fourth scan control signal received by the fourth scan control terminal P_Gate(n-1) is earlier than the third scan control signal received by the third scan control terminal P_Gate(n). In this way, the first electrode of the storage capacitor C is reset in advance before the data writing of the driving transistor DT, thereby avoiding the accumulation of charge trapping in the driving transistor DT, ensuring the accuracy of threshold voltage compensation, and improving the hysteresis problem of the driving transistor DT.

[0072] In one exemplary embodiment, as shown in Figure 5 The second reset transistor T0 is a transistor of the same type as the first reset transistor T1, and the gate is coupled to the fifth scan control terminal EM_NGate(n).

[0073] Still in combination with Figure 5 The second reset transistor T0 and the first reset transistor T1 are both N-type oxide transistors. In this way, the leakage current of the first electrode and the second electrode of the storage capacitor C is reduced, and the power consumption of the pixel circuit is reduced.

[0074] Still in combination with Figures 3 to 5As shown, the first reset transistor T1, the compensation transistor T2 and the third reset transistor T7 are N-type transistors, and the driving transistor DT, the data write transistor T3 and the light emitting control transistor T6 are P-type transistors. In this way, only when the first scan control signal provided by the first scan control end N_Gate(n-1) is high, the first reset transistor T1 and the third reset transistor T7 are turned on; only when the second scan control signal provided by the second scan control end N_Gate(n) is high, the compensation transistor T2 is turned on; only when the third scan control signal provided by the third scan control end P_Gate(n) is low, the data write transistor T3 is turned on; and only when the light emitting control signal provided by the light emitting control end EM(n) is low, the light emitting control transistor T6 is turned on. In actual application, the first scan control end N_Gate(n-1), the second scan control end N_Gate(n), the third scan control end P_Gate(n) and the light emitting control end EM(n) can be loaded with corresponding signals respectively, so as to control the turn-on and turn-off of the corresponding transistors, thereby improving the control effect of the pixel circuit.

[0075] In the embodiment of the present application, still in combination with Figures 3 to 5 As shown, the first reset transistor T1, the compensation transistor T2 and the third reset transistor T7 are oxide transistors, and the driving transistor DT, the data write transistor T3 and the light emitting control transistor T6 are polysilicon transistors.

[0076] Still in combination with Figures 3 to 5As shown, the first reset transistor T1, the compensation transistor T2 and the third reset transistor T7 are oxide transistors. In an example embodiment, the active layers of the first reset transistor T1, the compensation transistor T2 and the third reset transistor T7 are metal oxide semiconductor materials, and accordingly, the first reset transistor T1, the compensation transistor T2 and the third reset transistor T7 can be N-type transistors with metal oxide semiconductor materials as the active layers, so as to ensure that the first reset transistor T1, the compensation transistor T2 and the third reset transistor T7 have small leakage current and reduce the power consumption of the pixel circuit. The driving transistor DT, the data write transistor T3 and the light emitting control transistor T6 are all polysilicon transistors. In an example embodiment, the driving transistor DT, the data write transistor T3 and the light emitting control transistor T6 can be P-type transistors with low temperature polysilicon materials as the active layers (i.e., LTPS transistors), so as to ensure that the driving transistor DT, the data write transistor T3, the first light emitting control transistor and the second light emitting control transistor have high mobility, and can be made thinner, smaller, lower power consumption, etc. In this way, the pixel circuit provided by the embodiment of the present application is essentially a low temperature polysilicon oxide (Low Temperature Poly-silicon+Oxide, LTPO) pixel circuit prepared by combining the processes of preparing LTPS transistors and oxide transistors, so as to ensure that the gate of the driving transistor DT has small leakage current and low power consumption.

[0077] It should be noted that the light emitting device 10 in the embodiment of the present application can be set as at least one of an electroluminescent diode, such as an organic light emitting diode (Organic Light Emitting Diode, OLED), a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED), and a micro inorganic light emitting diode (micro Light Emitting Diode / Mini Light Emitting Diode), without limitation. The light emitting device 10 can include an anode, a light emitting layer and a cathode which are stacked. Further, the light emitting layer can further include a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, etc. Of course, in actual application, the light emitting device 10 can be designed according to the needs of the actual application environment, without limitation.

[0078] The first and second terminals of the aforementioned transistors can be interchanged depending on their type and the signal at the signal terminal. For example, the first terminal can be the source and the second terminal the drain, or vice versa; no limitation is made here. The transistors can be thin-film transistors (TFTs) or metal-oxide-semiconductor field-effect transistors (MOSs); no limitation is made here. Of course, the specific type of each transistor can be set according to the actual application requirements; no limitation is made here.

[0079] The above are merely illustrative examples illustrating the specific structure of the pixel circuit provided in the embodiments of this disclosure. In specific implementations, the specific structure of the pixel circuit is not limited to the structure provided in the embodiments of this disclosure, but may also be other structures known to those skilled in the art. These are all within the protection scope of this invention, and are not specifically limited here.

[0080] The following is based on Figure 4 The pixel circuit structure shown and Figure 6 and Figure 7 The timing diagram shown is as follows, in which, Figure 6 for Figure 4 The shown pixel circuit corresponds to one type of timing diagram of the refresh frame. Figure 7 for Figure 4The pixel circuit shown corresponds to one of the timing diagrams of the holding frame, and the working process of the pixel circuit provided by the embodiment of the present application is described. The potential signal provided by the first power supply terminal ELVDD is high level, and the potential signal provided by the second power supply terminal ELVSS is low level. In addition, according to the current refresh frequency and the reference refresh frequency of the display device, the current display frame of the display device can be divided into one refresh frame and N holding frames, where N is an integer greater than 1. For example, the current refresh frequency is 1 Hz, the reference refresh frequency is 60 Hz, and the reference refresh frequency is sixty times the current refresh frequency. The current display frame can be divided into one refresh frame and fifty-nine holding frames in turn, and the time length of the refresh frame and the holding frame is 1 / 60s. For another example, the current refresh frequency is 40 Hz, the reference refresh frequency is 120 Hz, and the reference refresh frequency is three times the current refresh frequency. The current display frame can be divided into one refresh frame and two holding frames in turn. For another example, the current refresh frequency is 60 Hz, the reference refresh frequency is 120 Hz, and the reference refresh frequency is twice the current refresh frequency. The current display frame can be divided into one refresh frame and one holding frame in turn. Of course, the current display frame can also be divided according to the actual application requirement, which is not limited herein. One refresh frame includes a first stage t1, a second stage t2 and a third stage t3 arranged in turn. Each holding frame includes a fourth stage t4, a fifth stage t5 and a sixth stage t6 arranged in turn. For the same display frame, the timing of the refresh frame is located before the timing of the holding frame. It should be noted that the embodiment of the present application is to better explain the pixel circuit provided by the present application, and does not limit the specific implementation of the present application. Wherein, "0" represents low level, and "1" represents high level.

[0081] In the first stage t1, P_Gate(n-1)=0, P_Gate(n)=1, N_Gate(n-1)=1, N_Gate(n)=0, and EM(n)=1.

[0082] In the first stage t1, the first reset transistor T1 is turned on under the control of the high level of the first scan control signal provided by the first scan control terminal N_Gate(n-1), and the initialization signal provided by the initialization signal terminal Vint is written into the gate of the driving transistor DT (for example, the gate of the driving transistor DT is connected to the initialization signal terminal Vint). Figure 4the voltage of the initialization signal provided by the initialization signal terminal Vint, so that the initialization of the gate potential of the driving transistor DT is realized, and the open state of the driving transistor DT for the subsequent threshold voltage compensation is ensured; in addition, the third reset transistor T7 is turned on under the control of the high level of the first scan control signal provided by the first scan control terminal N_Gate(n-1), and the initialization signal provided by the initialization signal terminal Vint is written into the first electrode of the light emitting device 10. When the first electrode of the light emitting device 10 is an anode, the dark state brightness is ensured to be dark enough, and the problem of frequency flicker is avoided. The second sub-transistor T5 is turned on under the control of the low level provided by the fourth scan control terminal P_Gate(n-1), and the reference signal provided by the reference signal terminal Vref is written into the first electrode of the storage capacitor C (for example Figure 4 At this time, the voltage of the A node is maintained at the voltage provided by the reference signal terminal Vref.

[0083] In the second stage t2, P_Gate(n-1)=1, P_Gate(n)=0, N_Gate(n-1)=0, N_Gate(n)=1, EM(n)=1;

[0084] In the second stage t2, the data writing transistor T3 is turned on under the control of the low level provided by the third scan control terminal P_Gate(n), and the data signal provided by the data signal terminal is written into the first electrode of the storage capacitor C. Correspondingly, the voltage of the A node is Vdata, and at this time, the driving transistor DT is in an open state; the compensation transistor T2 is turned on under the control of the high level of the second scan control signal provided by the second scan control terminal N_Gate(n), and the threshold voltage of the driving transistor DT and the voltage of the first power supply terminal ELVDD are written into the gate of the driving transistor DT. Correspondingly, the voltage of the B node becomes (ELVDD+Vth). Correspondingly, the voltage of the data signal of the A node and the voltage of the B node are stored in the storage capacitor C.

[0085] In the third stage t3, P_Gate(n-1)=1, P_Gate(n)=1, N_Gate(n-1)=0, N_Gate(n)=0, EM(n)=0;

[0086] In the third stage t3, the first sub-transistor T4 is turned on under the control of the low level of the light emitting control signal provided by the light emitting control terminal EM(n), and the reference signal provided by the reference signal terminal Vref is written into the first electrode of the storage capacitor C, so that the voltage of the A node is rewritten as the voltage of the reference signal provided by the reference signal terminal Vref. At this time, the voltage of the B node changes to (ELVDD+Vth+(Vref-Vdata)), and since the current I flowing through the light emitting device 10 is proportional to (Vgs-Vth)2 , substantially the current I is proportional to ((ELVDD + Vth + Vref - Vdata) - ELVDD - Vth) 2 = (Vref - Vdata) 2 It can be seen that the current I flowing through the light emitting device 10 is irrelevant to the threshold voltage of the driving transistor DT and the voltage of the first power supply terminal ELVDD. On the one hand, the threshold voltage of the driving transistor DT is compensated, and on the other hand, the voltage drop (IRDrop) of the first power supply terminal ELVDD is compensated.

[0087] In the fourth stage t4, P_Gate(n-1) = 1, P_Gate(n) = 1, N_Gate(n-1) = 1, N_Gate(n) = 0, EM(n) = 1 for each holding frame;

[0088] In the fourth stage t4, the first reset transistor T1 is turned on under the control of the high level of the first scan control signal provided by the first scan control terminal N_Gate(n-1), and the initialization signal provided by the initialization signal terminal Vint is written into the second electrode of the storage capacitor C; the data writing transistor T3 is turned off under the control of the high level provided by the third scan control terminal P_Gate(n), and the first sub-transistor T4 is turned off under the control of the high level of the light emitting control terminal EM(n), and the second sub-transistor T5 is turned off under the control of the fourth scan control terminal P_Gate(n-1), at this time, the A node is in a floating state, the voltage of the B node is written into the voltage of the initialization signal provided by the initialization signal terminal Vint through the opening of the first reset transistor T1, and correspondingly, the voltage of the A node will change through the coupling of the storage capacitor C, and the voltage of the A node becomes (Vref + Vint - (ELVDD + Vth + (Vref - Vdata)), therefore, the voltage difference of (ELVDD + Vth - Vdata) is still stored on the storage capacitor C.

[0089] In the fifth stage t5, P_Gate(n-1) = 1, P_Gate(n) = 1, N_Gate(n-1) = 0, N_Gate(n) = 1, EM(n) = 1;

[0090] In the fifth stage t5, the compensation transistor T2 is turned on under the control of the high level of the second scan signal provided at the second scan control end N_Gate(n), at this time, the driving transistor DT is also in the on state. Since the data writing transistor T3 is turned off under the control of the high level provided at the third scan control end P_Gate(n), and the first sub-transistor T4 is turned off under the control of the high level of the light emitting control end EM(n), the second sub-transistor T5 is turned off under the control of the fourth scan control end P_Gate(n-1), at this time, the A node is in the floating state, thus, the voltage of the B node is charged from the initialization signal end Vint to the first power supply end ELVDD, until the voltage of the B node becomes (ELVDD+Vth), the driving transistor DT is turned off, and the driving transistor DT is placed in the OFF-bias state. Since the A node is in the floating state, the voltage of the A node is changed through the coupling of the storage capacitor C, at this time, the voltage of the A node becomes (Vref+Vint-(ELVDD+Vth+(Vref-Vdata)+(ELVDD+Vth-Vint))), i.e. Vdata, thus, the voltage difference of (ELVDD+Vth-Vdata) is still stored on the storage capacitor C.

[0091] In the sixth stage t6, P_Gate(n-1)=1, P_Gate(n)=1, N_Gate(n-1)=0, N_Gate(n)=0, EM(n)=0;

[0092] In the sixth stage t6, the first sub-transistor T4 is turned on under the control of the low level provided at the light emitting control end EM(n), and the initialization signal provided at the initialization signal end Vint is written to the first pole of the storage capacitor C, in this way, the voltage of the A node is re-written as the voltage of the reference signal provided at the reference signal end Vref. In addition, the first reset transistor T1 is turned off under the control of the low level of the first scan control signal provided at the first scan control end N_Gate(n-1), and the compensation transistor T2 is turned off under the control of the low level of the second scan control signal provided at the second scan control end N_Gate(n), at this time, the B node is in the floating state, and changes through the coupling of the storage capacitor C, and the B node also changes again, finally, the voltage of the B node changes to (ELVDD+Vth+(Vref-Vdata)). In this way, since the current flowing through the light emitting device 10 is proportional to (Vgs-Vth) 2 , in essence, the current I is proportional to ((ELVDD+Vth+Vref-Vdata)-ELVDD-Vth) 2 =(Vref-Vdata) 2It can be seen that the current I flowing through the light emitting device 10 is irrelevant to the threshold voltage Vth of the driving transistor DT and the voltage of the first power supply terminal ELVDD, and not only the threshold voltage of the driving transistor DT is compensated, but also the voltage drop of the first power supply terminal ELVDD is compensated.

[0093] When the pixel circuit structure shown in Figure 5 is adopted, the timing diagram shown in Figure 8 and Figure 9 can be adopted, wherein, Figure 8 is the timing diagram of the refresh frame corresponding to the pixel circuit shown in Figure 5 , Figure 9 is the timing diagram of the holding frame corresponding to the pixel circuit shown in Figure 4 , and the working process of the pixel circuit can refer to the implementation process of the foregoing Figures 5 to 7 , and thus will not be described in detail here.

[0094] In one of the exemplary embodiments, the current refresh frequency is 1 Hz, the reference refresh frequency is 60 Hz, and each display frame can be divided into one refresh frame and fifty-nine holding frames in turn, as shown in Figure 10 , Figure 4 The pixel circuit shown in adopts one of the timing diagrams corresponding to the current refresh frequency of 1 Hz, and the time length of each refresh frame and the time length of each holding frame are both 1 / 60 s. Of course, the working timing of the pixel circuit provided in the embodiments of the present application can also be divided according to the actual refresh frequency, which is not limited here.

[0095] Figure 11 Based on the same inventive concept, the present application also provides a display device, as shown in , which comprises a plurality of pixel circuits 100 according to any one of the foregoing. In the specific implementation process, the display device solves the problem by a principle similar to that of the foregoing pixel circuit 100, and thus the implementation of the display device can refer to the implementation of the foregoing pixel circuit 100, and the repeated parts will not be described in detail here.

[0096] In the specific implementation process, the display device provided in the embodiments of the present application can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. The other essential components of the display device are understood by those skilled in the art, and thus will not be described in detail here and should not be regarded as a limitation on the present application.

[0097] Figure 12 Based on the same inventive concept, the present application also provides a driving method of the pixel circuit according to any one of the foregoing, which comprises:

[0098] S101: according to a current refresh frequency of a display device and a reference refresh frequency, dividing a current display frame of the display device into one refresh frame and N holding frames, wherein N is an integer greater than 1; wherein the refresh frame comprises a first stage, a second stage and a third stage arranged in sequence, and each holding frame comprises a fourth stage, a fifth stage and a sixth stage arranged in sequence;

[0099] S102: in the fourth stage, controlling the first reset transistor and the third reset transistor to be turned on, and resetting the potential of the second electrode of the storage capacitor and the first electrode of the light emitting device through the initialization signal end;

[0100] S103: in the fifth stage, controlling the compensation transistor to be turned on, and writing the threshold voltage of the driving transistor and the voltage of the first power supply end into the gate of the driving transistor through the compensation transistor, and storing to the storage capacitor, and adjusting the driving transistor from the turned-on state to the turned-off state;

[0101] S104: in the sixth stage, controlling the second reset transistor and the light emitting control transistor to be turned on, resetting the potential of the first electrode of the storage capacitor through the reference signal end, and controlling the light emitting device to emit light under the driving of the driving transistor.

[0102] In one of the example embodiments, for the specific implementation process of steps S101 to S104, the foregoing pixel circuit shown in Figure 4 and the corresponding part of the timing diagram shown in Figure 7 will not be described here.

[0103] In the embodiment of the application, as shown in Figure 13 , for the refresh frame, the method further comprises:

[0104] S201: in the first stage, controlling the first reset transistor, the second reset transistor and the third reset transistor to be turned on, resetting the potential of the first electrode of the storage capacitor through the reference signal end, and resetting the potential of the second electrode of the storage capacitor and the first electrode of the light emitting device through the initialization signal end;

[0105] S202: in the second stage, controlling the data writing transistor and the compensation transistor to be turned on, and loading the data signal provided by the data signal end to the first electrode of the storage capacitor, and writing the threshold voltage of the driving transistor and the voltage of the first power supply end into the gate of the driving transistor through the compensation transistor, and storing to the storage capacitor;

[0106] S203: In the third stage, the second reset transistor and the light emitting control transistor are controlled to be turned on, the potential of the first pole of the storage capacitor is reset through the reference signal terminal, and the light emitting device is controlled to emit light.

[0107] In one of the example embodiments, for the implementation process of steps S201 to S203, refer to the descriptions of the pixel circuit shown in Figure 4 and the corresponding part of the timing diagram shown in Figure 6 , which will not be repeated here.

[0108] In the embodiment of the present application, the second reset transistor T0 includes a first sub-transistor T4 and a second sub-transistor T5 of the same type as the data writing transistor T3, and are coupled between the reference signal terminal Vref and the first pole of the storage capacitor C, the gate of the first sub-transistor T4 is coupled with the light emitting control terminal EM(n), and the gate of the second sub-transistor T5 is coupled with the fourth scan control terminal; the method further comprises:

[0109] In the first stage t1, the second sub-transistor T5 is controlled to be turned on, and the potential of the first pole of the storage capacitor C is reset through the reference signal terminal Vref.

[0110] In one of the example embodiments, for the implementation process of the first stage t1, refer to the descriptions of the pixel circuit shown in Figure 4 and the corresponding part of the timing diagram shown in Figure 6 , which will not be repeated here.

[0111] In the embodiment of the present application, the method further comprises:

[0112] In the third stage t3, the first sub-transistor T4 is controlled to be turned on, and the potential of the first pole of the storage capacitor C is reset through the reference signal terminal Vref.

[0113] In one of the example embodiments, for the implementation process of the third stage t3, refer to the descriptions of the pixel circuit shown in Figure 4 and the corresponding part of the timing diagram shown in Figure 6 , which will not be repeated here.

[0114] The embodiment of the present application provides a pixel circuit, a driving method thereof and a display device, wherein the pixel circuit comprises a first reset transistor T1, a compensation transistor T2, a data writing transistor T3, a second reset transistor T0, an emission control transistor T6, a third reset transistor T7, a driving transistor DT, an emission device 10 and a storage capacitor C; the first reset transistor T1 is coupled between the gate of the driving transistor DT and an initialization signal terminal Vint, and the gate is coupled with a first scan control terminal N_Gate(n-1), so that the first reset transistor T1 can be turned on under the control of the first scan control terminal N_Gate(n-1); the compensation transistor T2 is coupled between the gate of the driving transistor DT and a first electrode, and the gate is coupled with a second scan control terminal N_Gate(n); the second scan control terminal N_Gate(n) and the first scan control terminal N_Gate(n-1) are provided by different stage output terminals of the same first gate driving unit, and the first scan control signal received by the first scan control terminal N_Gate(n-1) is earlier than the second scan control signal received by the second scan control terminal N_Gate(n), thereby saving the number of gate driving units; the data writing transistor T3 is coupled between the first electrode of the storage capacitor C and a data signal terminal, and the gate is coupled with a third scan control terminal P_Gate(n), so that the data writing transistor T3 can be turned on under the control of the third scan control terminal P_Gate(n), and when the compensation transistor T2 is turned on, the data signal provided by the data signal terminal, the threshold voltage of the driving transistor DT and the voltage signal provided by a first power supply terminal ELVDD coupled with the second electrode of the driving transistor DT can be written into the storage capacitor C, thereby realizing compensation of the threshold voltage of the driving transistor DT and voltage drop compensation of the first power supply terminal ELVDD.

[0115] The second reset transistor T0 is coupled between the first pole of the storage capacitor C and the reference signal terminal Vref, and the second pole of the storage capacitor C is coupled with the gate of the driving transistor DT, so that the potential of the first pole of the storage capacitor C can be reset as the signal potential of the reference signal terminal Vref when the second reset transistor T0 is turned on; and the third reset transistor T7 is coupled between the first pole of the light emitting device 10 and the initialization signal terminal Vint, and the gate is coupled with the first scan control terminal N_Gate(n-1), so that the third reset transistor T7 can be turned on under the control of the first scan control terminal N_Gate(n-1) to reset the first pole of the light emitting device 10 as the signal potential of the initialization signal terminal Vint, thereby avoiding the problem of flicker when the first pole of the light emitting device 10 is the anode; in addition, the second pole of the driving transistor DT is coupled with the first power terminal ELVDD, and the second pole of the light emitting device 10 is coupled with the second power terminal ELVSS, thereby ensuring the driving capability of the pixel circuit. Through the pixel circuit provided by the embodiment of the present application, the gate potential of the driving transistor DT can be reset in the refresh frame and the holding frame of the entire display frame, and the number of data writing compensation can be increased, thereby avoiding the problem of charge trapping accumulated in the driving transistor DT, and improving the problem of insufficient first frame brightness and residual image when the picture is switched, and improving the display effect of the display device when the display device is driven at low frequency.

[0116] Although preferred embodiments of the application have been described, those skilled in the art will be able to make additional changes and modifications without departing from the spirit and scope of the application. Therefore, the appended claims are intended to cover all such changes and modifications that fall within the scope of the application.

[0117] Obviously, various modifications and changes can be made to the present application without departing from the spirit and scope thereof. Accordingly, it is intended that the present application embrace all such modifications and changes as fall within the scope of the appended claims and their equivalents.

Claims

1. A pixel circuit, characterized by comprising: Comprising: a first reset transistor, a compensation transistor, a data write transistor, a second reset transistor, a light emitting control transistor, a third reset transistor, a driving transistor, a light emitting device and a storage capacitor; wherein: the first reset transistor is coupled between the gate of the driving transistor and an initialization signal terminal, and the gate is coupled with a first scan control terminal; the compensation transistor is coupled between the gate of the driving transistor and a first pole, and the gate is coupled with a second scan control terminal, wherein the second scan control terminal and the first scan control terminal are provided by different stage output terminals of a same first gate driving unit, and a first scan control signal received by the first scan control terminal is earlier than a second scan control signal received by the second scan control terminal; the data write transistor is coupled between the first pole of the storage capacitor and a data signal terminal, and the gate is coupled with a third scan control terminal; the second reset transistor is coupled between the first pole of the storage capacitor and a reference signal terminal, and the second pole of the storage capacitor is coupled with the gate of the driving transistor; the light emitting control transistor is coupled between the first pole of the driving transistor and the first pole of the light emitting device, and the gate is coupled with a light emitting control terminal; the third reset transistor is coupled between the first pole of the light emitting device and the initialization signal terminal, and the gate is coupled with the first scan control terminal; the second pole of the driving transistor is coupled with a first power supply terminal, and the second pole of the light emitting device is coupled with a second power supply terminal; wherein the first reset transistor, the compensation transistor and the third reset transistor are of the same type; in a holding frame, the first scan control terminal is configured to provide an effective signal, so that the first reset transistor is turned on, the initialization signal provided by the initialization signal terminal is transmitted to the second pole of the storage capacitor, and the first pole of the storage capacitor is configured to be in a suspended state.

2. The pixel circuit of claim 1, wherein, The second reset transistor comprises a first sub-transistor and a second sub-transistor of the same type as the data write transistor, and is coupled between the reference signal terminal and the first pole of the storage capacitor, respectively, the gate of the first sub-transistor is coupled with the light emitting control terminal, and the gate of the second sub-transistor is coupled with a fourth scan control terminal, wherein the fourth scan control terminal and the third scan control terminal are provided by different stage output terminals of a same second gate driving unit, and a fourth scan control signal received by the fourth scan control terminal is earlier than a third scan control signal received by the third scan control terminal.

3. The pixel circuit of claim 1, wherein, The second reset transistor is a transistor of the same type as the first reset transistor, and the gate is coupled with a fifth scan control terminal.

4. The pixel circuit of any one of claims 1-3, wherein, The first reset transistor, the compensation transistor and the third reset transistor are all N-type transistors, and the driving transistor, the data write transistor and the light emitting control transistor are all P-type transistors.

5. The pixel circuit of claim 4, wherein, The first reset transistor, the compensation transistor and the third reset transistor are all oxide transistors, and the driving transistor, the data write transistor and the light emitting control transistor are all polysilicon transistors.

6. A display device, characterized by comprising: Comprising: A plurality of pixel circuits as claimed in any one of claims 1-5.

7. A driving method of a pixel circuit according to any one of claims 1 to 5, characterized by, Comprising: According to a current refresh frequency of a display device and a reference refresh frequency, a current display frame of the display device is divided into one refresh frame and N holding frames, wherein N is an integer greater than 1; wherein the refresh frame comprises a first stage, a second stage and a third stage arranged in sequence, and each holding frame comprises a fourth stage, a fifth stage and a sixth stage arranged in sequence; In the fourth stage, the first reset transistor and the third reset transistor are controlled to be turned on, and the potential of the second electrode of the storage capacitor and the first electrode of the light emitting device is reset through the initialization signal end; In the fifth stage, the compensation transistor is controlled to be turned on, the threshold voltage of the driving transistor and the voltage of the first power supply end are written into the gate of the driving transistor through the compensation transistor, and are stored to the storage capacitor, and the driving transistor is adjusted from the on state to the off state; In the sixth stage, the second reset transistor and the light emitting control transistor are controlled to be turned on, the potential of the first electrode of the storage capacitor is reset through the reference signal end, and the light emitting device is controlled to emit light under the driving of the driving transistor.

8. The driving method according to claim 7, wherein For the refresh frame, the method further comprises: In the first stage, the first reset transistor, the second reset transistor and the third reset transistor are controlled to be turned on, the potential of the first electrode of the storage capacitor is reset through the reference signal end, and the potential of the second electrode of the storage capacitor and the first electrode of the light emitting device is reset through the initialization signal end; In the second stage, the data write transistor and the compensation transistor are controlled to be turned on, and the data signal provided by the data signal end is loaded to the first electrode of the storage capacitor, and the threshold voltage of the driving transistor and the voltage of the first power supply end are written into the gate of the driving transistor through the compensation transistor, and are stored to the storage capacitor; In the third stage, the second reset transistor and the light emitting control transistor are controlled to be turned on, the potential of the first electrode of the storage capacitor is reset through the reference signal end, and the light emitting device is controlled to emit light.

9. The driving method according to claim 8, wherein The second reset transistor comprises a first sub-transistor and a second sub-transistor of the same type as the data write transistor, and is coupled between the reference signal end and the first electrode of the storage capacitor, the gate of the first sub-transistor is coupled with the light emitting control end, and the gate of the second sub-transistor is coupled with the fourth scan control end; The method further comprises: In the first stage, the second sub-transistor is controlled to be turned on, and the potential of the first electrode of the storage capacitor is reset through the reference signal end.

10. The driving method according to claim 9, wherein The method further comprises: In the third stage, the first sub-transistor is controlled to be turned on, and the potential of the first electrode of the storage capacitor is reset through the reference signal end.

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