A GIP driving circuit

Abstract

The application provides a GIP driving circuit, which comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor Ta, a transistor Tb, a transistor Tc, a capacitor C1 and a capacitor C2; the source of the transistor T1 is connected with the gate of the transistor T2, the drain of the transistor T3, the gate of the transistor T4, the drain of the transistor T7 and one end of the capacitor C1, and is set as a Q point; the source of the transistor T3 is connected with the source of the transistor T7, the drain of the transistor Ta, the drain of the transistor Tb, the source of the transistor Tc and the other end of the capacitor C2, and is set as a T point. The application has the advantages that: on the basis of the original 7T1C GIP driving circuit, 3TIC is added, and the T point is additionally provided; through the voltage control of the T point, the level transmission failure caused by the leakage of the transistor T3 when the Q point is high can be effectively prevented, and the display failure can be prevented.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display technology, in particular to a GIP driving circuit. BACKGROUND

[0002] The display of liquid crystal display panel is completed by controlling the pixel TFT in the panel, specifically, the opening and closing of TFT is controlled by horizontal gate signal (Gate) and the vertical source signal (Source) writes the data that wants to display. The generation of gate signal is generated by the gate driving circuit on both sides of the panel, which is called GIP (Gate In Panel) driving circuit. With the increasing demand for display quality, metal oxide TFT-LCD becomes the darling of LCD industry due to its unique advantages, such as high electron mobility, low leakage and other characteristics. For TFT based on metal oxide, the operation of GIP circuit at high temperature is prone to cause the whole GIP circuit level transmission problem due to the electrical property of some TFT devices being negative. Therefore, for the new type of metal oxide TFT, a GIP circuit different from the traditional a-Si based GIP circuit should be designed to adapt to the unique electrical property of metal oxide TFT.

[0003] The common 7T1C GIP driving circuit is shown in Figure 1 , in which VGH is high level, VGL is low level, CK is clock signal, FW is VGH level, and BW is VGL level. Gn is output terminal. T1-T7 are TFT devices, and C1 is capacitor. V1 is high level. The level refers to the same level, such as FW is VGH level, which means that the signal voltage of FW is equal to VGH.

[0004] VGH, VGL and CK are input signals of GIP circuit; G[n-4], G[n+4] and G[n] are level transmission signals output by GIP driving circuit, which are used to control the opening and closing of pixel TFT in the panel.

[0005] In the LCD of a-Si thin film field effect transistor, in the normal display driving process, GIP is opened step by step, G1-Gn controls each row of the panel, and the state of G1-Gn and Q point is as shown in Figure 2As shown, under this driving architecture, G[n-4] first pre-charges the Q point, and the charging voltage is approximately VGH. When G[n-4] changes from a high level to a low level, the VGH voltage of the Q point is in a holding stage. At this time, the Q point is connected to the drain of the TFT device T3. Since the gate of the TFT device T2 is connected to the Q point, the TFT device T2 is turned on, and the gate and source of the TFT device T3 are both at the VGL level, and its Vgs is approximately equal to 0V. If the electrical properties of the TFT device T3 begin to shift in the negative direction, its Vth<0, then Vgs>Vth, the TFT device T3 is turned on, and the Q point voltage will leak through the TFT device T3. Depending on the degree of leakage at the Q point, two types of level transfer problems will occur. First, if the leakage at the Q point is too severe and directly causes the TFT device T4 to be unable to turn on, then G[n] will have no output at all. At this time, only the first few rows of the LCD panel will light up, and the lower part cannot be driven. Second, if the Q-point voltage is not completely leaked, TFT device T4 is not fully turned on. Although G[n] has output, it cannot reach the set level in this case. The GIP driver circuit drives the pixel in a step-by-step manner. The output of the previous stage is used as the pre-charge for the Q-point of the next stage. Then, the Q-point of the next stage is insufficiently charged. In addition, due to the leakage of TFT device T3, although there is step-by-step transmission, it still cannot be completely transmitted in the end. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a GIP driving circuit that effectively prevents the occurrence of Q-point leakage causing stage transmission failure.

[0007] The present invention is implemented as follows: a GIP driving circuit, comprising:

[0008] Transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor Ta, transistor Tb, transistor Tc, capacitor C1, and capacitor C2;

[0009] The gate of the transistor T1 is connected to the first GIP output signal terminal, the drain of the transistor T1 is connected to the first GIP input signal terminal, and the source of the transistor T1 is connected to the gate of the transistor T2, the drain of the transistor T3, the gate of the transistor T4, the drain of the transistor T7, and one end of the capacitor C1 and is set as the Q point;

[0010] The drain of the transistor T2 is connected to the gate of the transistor T3, the gate of the transistor Tb, the gate of the transistor T5, and the source of the transistor T6 and is set as point P. The source of the transistor T2 is connected to the source of the transistor T5, the source of the transistor Tb, one end of the capacitor C2, and the second GIP input signal terminal;

[0011] The source of the transistor T3 is connected to the source of the transistor T7, the drain of the transistor Ta, the drain of the transistor Tb, the source of the transistor Tc, and the other end of the capacitor C2 and is set as point T;

[0012] The drain of the transistor T4 is connected to the third GIP input signal terminal, and the source of the transistor T4 is connected to the other end of the capacitor C1, the drain of the transistor T5, and the second GIP output signal terminal;

[0013] The gate of the transistor T6 is connected to the drain of the transistor T6 and the fourth GIP input signal terminal;

[0014] The gate of the transistor T7 is connected to the gate of the transistor Tc and the third GIP output signal terminal;

[0015] The gate of the transistor Ta is connected to the first GIP output signal terminal, and the source of the transistor Ta is connected to the fifth GIP input signal terminal;

[0016] The drain of the transistor Tc is connected to the sixth GIP input signal terminal.

[0017] Furthermore, the transistor T1 , the transistor T2 , the transistor T3 , the transistor T4 , the transistor T5 , the transistor T6 , the transistor T7 , the transistor Ta, the transistor Tb and the transistor Tc are all TFT thin film transistors.

[0018] Furthermore, the first GIP output signal terminal is a G[n-4] marking terminal, the second GIP output signal terminal is a G[n] marking terminal, and the third GIP output signal terminal is a G[n+4] marking terminal.

[0019] Furthermore, the first GIP input signal terminal is an FW mark terminal, the second GIP input signal terminal is a VGL mark terminal, the third GIP input signal terminal is a CK mark terminal, the fourth input signal terminal is a V1 mark terminal, the fifth input signal terminal is a VGH mark terminal, and the sixth GIP input signal terminal is a BW mark terminal.

[0020] Furthermore, the VGL mark terminal is connected to a low-level signal, the VGH mark terminal is connected to a high-level signal, the CK mark terminal is connected to a clock signal, the FW mark terminal is connected to a high-level signal, the BW mark terminal is connected to a low-level signal, and the V1 mark terminal is connected to a high-level signal.

[0021] Furthermore, a driver IC is included, and the driver IC is connected to the VGL mark terminal, the VGH mark terminal, the CK mark terminal, the FW mark terminal, the BW mark terminal, and the V1 mark terminal.

[0022] Furthermore, the transistor T1 , the transistor T2 , the transistor T3 , the transistor T4 , the transistor T5 , the transistor T6 , the transistor T7 , the transistor Ta, the transistor Tb, the transistor Tc, the capacitor C1 and the capacitor C2 are all fixedly disposed on the LCD panel.

[0023] The advantages of the present invention are that 3TIC is added to the original 7T1C GIP driving circuit, and a T point is added. By controlling the voltage of the T point, it is possible to effectively prevent the leakage through the transistor T3 when the Q point is at a high level, thereby preventing the stage transmission failure and display defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0025] Figure 1 1 is a schematic structural diagram of a GIP driving circuit in the background art.

[0026] Figure 2 It is a timing diagram of a GIP driving circuit in the background art.

[0027] Figure 3 It is a structural diagram of the GIP driving circuit of the present invention.

[0028] Figure 4 It is a timing diagram of the GIP driving circuit of the present invention. DETAILED DESCRIPTION

[0029] The embodiment of the present invention provides a GIP driving circuit, thereby solving the disadvantage of the GIP driving circuit in the prior art that the stage transmission failure is caused by Q-point leakage, and achieving the technical effect of preventing poor display.

[0030] The technical solution in the embodiments of the present invention addresses the aforementioned shortcomings. The overall concept is as follows: 3TICs are added to the existing 7T1C GIP drive circuit, and a T point is also added. The GIP circuit operates such that while G[n-4] precharges Q, the added transistor Ta also charges T. When G[n-4] completes precharging Q, T is at the VGH level. While the potential at Q is maintained, the gate of transistor T2 is connected to Q, turning on transistor T2. This causes the gate of transistor T3 to be at the VGL level, while the source of transistor T3 is at the VGH level. Consequently, the Vgs voltage of transistor T3 is approximately twice VGL, a level significantly more negative than the Vth of transistor T3, completely turning off transistor T3. This prevents leakage at Q.

[0031] When point Q is high, point T also maintains a high level to prevent leakage and stage failure. When Gout[n+4] is high, point T is first pulled down to VGL through transistor Tc, and the potential of point Q is then reduced to VGL. The potential of point P is raised to VGH, and the gate of transistor Tb is VGH. The low level of point T is maintained by transistor Tb, thus completing the work of the first-level GIP.

[0032] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0033] See Figures 1 to 4 , a preferred embodiment of the present invention.

[0034] A GIP driving circuit includes: a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor Ta, a transistor Tb, a transistor Tc, a capacitor C1, and a capacitor C2; the gate of the transistor T1 is connected to a first GIP output signal terminal, the drain of the transistor T1 is connected to a first GIP input signal terminal, the source of the transistor T1 is connected to the gate of the transistor T2, the drain of the transistor T3, the gate of the transistor T4, the drain of the transistor T7, and one end of the capacitor C1 and is set as a Q point; the drain of the transistor T2 is connected to the gate of the transistor T3, the gate of the transistor Tb, the gate of the transistor T5, and the source of the transistor T6 and is set as a P point; the source of the transistor T2 is connected to the source of the transistor T5, the source of the transistor Tb, one end of the capacitor C2, The second GIP input signal terminal is connected; the source of the transistor T3 is connected to the source of the transistor T7, the drain of the transistor Ta, the drain of the transistor Tb, the source of the transistor Tc, and the other end of the capacitor C2 and is set as point T; the drain of the transistor T4 is connected to the third GIP input signal terminal, and the source of the transistor T4 is connected to the other end of the capacitor C1, the drain of the transistor T5, and the second GIP output signal terminal; the gate of the transistor T6 is connected to the drain of the transistor T6 and the fourth GIP input signal terminal; the gate of the transistor T7 is connected to the gate of the transistor Tc and the third GIP output signal terminal; the gate of the transistor Ta is connected to the first GIP output signal terminal, and the source of the transistor Ta is connected to the fifth GIP input signal terminal; the drain of the transistor Tc is connected to the sixth GIP input signal terminal.

[0035] The transistors T1, T2, T3, T4, T5, T6, T7, Ta, Tb, and Tc are all TFT thin film transistors, which are based on the conduction principle of N-type MOS transistors.

[0036] The first GIP output signal terminal is the G[n-4] labeled terminal, the second GIP output signal terminal is the G[n] labeled terminal, and the third GIP output signal terminal is the G[n+4] labeled terminal. Marking is done on the circuit board to facilitate wiring.

[0037] The first GIP input signal terminal is marked FW, the second GIP input signal terminal is marked VGL, the third GIP input signal terminal is marked CK, the fourth input signal terminal is marked V1, the fifth input signal terminal is marked VGH, and the sixth GIP input signal terminal is marked BW. Markings are made on the circuit board to facilitate wiring.

[0038] The VGL mark terminal is connected to a low level signal, the VGH mark terminal is connected to a high level signal, the CK mark terminal is connected to a clock signal, the FW mark terminal is connected to a high level signal, the BW mark terminal is connected to a low level signal, and the V1 mark terminal is connected to a high level signal.

[0039] The system further includes a driver IC connected to the VGL mark terminal, the VGH mark terminal, the CK mark terminal, the FW mark terminal, the BW mark terminal, and the V1 mark terminal. The driver IC adjusts the output signal.

[0040] The transistor T1 , the transistor T2 , the transistor T3 , the transistor T4 , the transistor T5 , the transistor T6 , the transistor T7 , the transistor Ta, the transistor Tb, the transistor Tc, the capacitor C1 and the capacitor C2 are all fixedly disposed on the LCD panel.

[0041] The working mode of the GIP driving circuit of the present invention is: Figure 3 and Figure 4, VGH is high, VGL is low, CK is the clock signal, FW is VGH, and BW is VGL. When G[n-4] goes high, transistor T1 turns on, and the FW terminal precharges point Q, charging capacitor C1. Simultaneously, transistor Ta turns on, and the VGH terminal charges point T, charging capacitor C2. When G[n-4] goes low, transistors T1 and Ta turn off, completing the precharge of point Q and placing point T at VGH. During the potential hold phase at point Q, the gate of transistor T2 is high, conducting transistor T2. The gate of transistor T3 is at VGL, and the source of transistor T3 is at VGH. Consequently, the Vgs voltage of transistor T3 is approximately twice VGL, a level significantly more negative than transistor T3's Vth, completely turning off transistor T3. When point Q is high, point T also protects the high voltage, preventing leakage from point Q through transistor T3 and causing stage failure. When G[n+4] is at a high level, that is, the gate of transistor Tc is at a high level, the gate of transistor T7 is at a high level, transistor Tc is turned on to pull point T down to VGL, and transistor T7 is turned on to pull point Q down to VGL. At this time, the gate of transistor T2 becomes a low level, and transistor T2 is cut off. Since V1 has been providing a high level through transistor T6, point P is pulled to a high level. The gate of transistor Tb is at a high level, and transistor Tb is turned on, maintaining the low level of point T, thus completing the work of the first-level GIP.

[0042] The present invention adds 3T1C to the existing GIP circuit and forms a T-point. By controlling the voltage at T-point, it effectively prevents Q-point leakage in the existing GIP circuit when Q-point is high, thereby preventing stage failure in the GIP circuit and causing display defects. The GIP signal notation shown in the figures of the present invention is based on a 16CK timing sequence, but the application of this circuit is not limited to 16CK timing and can also be applied to timing sequences such as 4CK and 8CK.

[0043] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A GIP driving circuit, characterized in that: include: Transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor Ta, transistor Tb, transistor Tc, capacitor C1 and capacitor C2; The gate of the transistor T1 is connected to the first GIP output signal terminal, the drain of the transistor T1 is connected to the first GIP input signal terminal, and the source of the transistor T1 is connected to the gate of the transistor T2, the drain of the transistor T3, the gate of the transistor T4, the drain of the transistor T7, and one end of the capacitor C1 and is set as the Q point; The drain of the transistor T2 is connected to the gate of the transistor T3, the gate of the transistor Tb, the gate of the transistor T5, and the source of the transistor T6 and is set as point P. The source of the transistor T2 is connected to the source of the transistor T5, the source of the transistor Tb, one end of the capacitor C2, and the second GIP input signal terminal; The source of the transistor T3 is connected to the source of the transistor T7, the drain of the transistor Ta, the drain of the transistor Tb, the source of the transistor Tc, and the other end of the capacitor C2 and is set as point T; The drain of the transistor T4 is connected to the third GIP input signal terminal, and the source of the transistor T4 is connected to the other end of the capacitor C1, the drain of the transistor T5, and the second GIP output signal terminal; The gate of the transistor T6 is connected to the drain of the transistor T6 and the fourth GIP input signal terminal; The gate of the transistor T7 is connected to the gate of the transistor Tc and the third GIP output signal terminal; The gate of the transistor Ta is connected to the first GIP output signal terminal, and the source of the transistor Ta is connected to the fifth GIP input signal terminal; The drain of the transistor Tc is connected to the sixth GIP input signal terminal; The first GIP signal output terminal is a G[n-4] marking terminal, the second GIP signal output terminal is a G[n] marking terminal, and the third GIP signal output terminal is a G[n+4] marking terminal; The first GIP input signal terminal is an FW mark terminal, the second GIP input signal terminal is a VGL mark terminal, the third GIP input signal terminal is a CK mark terminal, the fourth GIP input signal terminal is a V1 mark terminal, the fifth GIP input signal terminal is a VGH mark terminal, and the sixth GIP input signal terminal is a BW mark terminal; The VGL mark terminal is connected to a low level signal, the VGH mark terminal is connected to a high level signal, the CK mark terminal is connected to a clock signal, the FW mark terminal is connected to a high level signal, the BW mark terminal is connected to a low level signal, and the V1 mark terminal is connected to a high level signal.

2. A GIP driving circuit according to claim 1, characterized in that: The transistor T1 , the transistor T2 , the transistor T3 , the transistor T4 , the transistor T5 , the transistor T6 , the transistor T7 , the transistor Ta, the transistor Tb and the transistor Tc are all TFT thin film transistors.

3. A GIP driving circuit according to claim 1, characterized in that: It also includes a driver IC, which is connected to the VGL mark terminal, the VGH mark terminal, the CK mark terminal, the FW mark terminal, the BW mark terminal, and the V1 mark terminal.

4. A GIP driving circuit according to claim 1, characterized in that: The transistor T1 , the transistor T2 , the transistor T3 , the transistor T4 , the transistor T5 , the transistor T6 , the transistor T7 , the transistor Ta, the transistor Tb, the transistor Tc, the capacitor C1 and the capacitor C2 are all fixedly disposed on the LCD panel.

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