A display driving circuit

Abstract

The application provides a display driving circuit, which comprises a transistor T1, a transistor T2, a transistor T2a, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8 and a capacitor C1; the gate of the transistor T2a is connected with a node Q, the drain is connected with a node T, and the source is connected with a second GIP input signal end; the gate of the transistor T8 is connected with a node P, the drain is connected with a fifth GIP input signal end, and the source is connected with the node T; one end of the capacitor C1 is connected with the node Q, and the other end is connected with a second GIP output signal end. The application has the advantages that: on the basis of the original 7T1C GIP driving circuit, the transistor T8 and the transistor T2a are added, and a node T is formed at the same time; through the voltage control of the node T, when the node P is high, the node P can be effectively prevented from leaking to cause the low level of the output to be insufficient, and the display can be prevented from being poor.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display driving circuit. Background Art

[0002] Liquid crystal display panels display images by controlling the pixel TFTs within the panel. Specifically, horizontal gate signals (Gate) control the on / off switching of the pixel TFTs, while vertical source signals (Source) write the desired display data. The gate signals are generated by gate driver circuits on both sides of the panel, referred to as GIP (Gate In Panel) driver circuits. As demand for display quality continues to rise, metal oxide TFT-LCDs have become a favorite in the LCD industry due to their unique advantages, such as high electron mobility and low leakage. However, for metal oxide-based TFTs, the operation of the GIP circuit at high temperatures is susceptible to negative electrical bias in individual TFT components, which can cause overall GIP circuit level problems. Therefore, for new metal oxide TFTs, a GIP circuit design, different from that based on traditional a-Si, is required to adapt to the unique electrical properties of metal oxides.

[0003] Common 7T1C GIP display driver circuit, such as Figure 1 As shown in the figure, VGH is a high level, VGL is a low level, CK is the clock signal, FW is the VGH level, and BW is the VGL level. Gn is the output terminal. T1-T7 are TFT devices, and C1 is a capacitor. V1 is a high level. Level refers to being at the same level. For example, if FW is at the VGH level, it means that the voltage value of FW is the same as that of VGH.

[0004] VGH, VGL, and CK are the input signals of the GIP driving circuit, and G[n-4], G[n+4], and G[n] are the level transfer signals output by the GIP driving circuit, which are used to control the opening and closing of the pixel TFT in the panel.

[0005] Typically, in a-Si thin film field effect transistor LCDs, during the normal display driving process, GIPs are turned on step by step, with G1 to Gn controlling each row of the panel, i.e., G[1] controls the first row, and G[n] controls the nth row. In addition to transmitting the gate drive signal of the pixel TFT of the corresponding row to the display area, G[n] of the nth-level GIP display drive circuit also participates in the operation of the n+4th-level GIP display drive circuit. The states of G1 to Gn and nodes Q and P are shown in the figure below. Figure 2As shown, under this driving architecture, first G[n-4] performs a pre-charging action on node Q, and the charging voltage is approximately VGH. When G[n-4] changes from a high level to a low level, the VGH voltage of node Q is in a holding stage. When CK changes from a low level to a high level, the potential of node Q is first coupled from the high level of CK to 2 times VGH, transistor T4 is fully turned on, and G[n] starts to output. When CK changes from a high level to a low level, node Q decreases from 2 times VGH to VGH. When G[n+4] is a high level, transistor T7 is turned on, and node Q is pulled down to BW by transistor T7. At this time, the gate of transistor T2 is a low level, and transistor T2 is turned off. Node P starts to charge to a high level by transistor T6, and the gate of transistor T5 is a high level. Transistor T5 is turned on, stabilizing G[n] to BW. When node P is a high level, the gate and source of T2 are both at the VGL level (that is, both are connected to BW). Transistor T2 The Vgs voltage of transistor T2 is approximately 0V. If the electrical bias of transistor T2 is Vth<0, that is, the Vgs of transistor T2 is greater than Vth, transistor T2 is turned on, resulting in leakage at node P. The potential of node P cannot maintain a high level, resulting in insufficient ability of transistor T5 to pull down the G[n] level, causing the low level output by G[n] to be lower than the VGL level. Due to the insufficient low level output by G[n], the pixel TFT in the panel cannot be completely locked at a low level, resulting in crosstalk and display defects. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a display driving circuit that effectively prevents leakage at the node P from causing an insufficient low-level output.

[0007] The present invention is implemented as follows: a display driving circuit comprising:

[0008] Transistor T1, transistor T2, transistor T2a, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8 and capacitor C1;

[0009] The gate of the transistor T1 is connected to the first GIP output signal terminal, the drain is connected to the first GIP input signal terminal, and the source is connected to the node Q;

[0010] The gate of the transistor T2 is connected to the node Q, the drain is connected to the node P, and the source is connected to the node T;

[0011] The gate of the transistor T2a is connected to the node Q, the drain is connected to the node T, and the source is connected to the second GIP input signal terminal;

[0012] The gate of the transistor T3 is connected to the node P, the drain is connected to the node Q, and the source is connected to the second GIP input signal terminal;

[0013] The gate of the transistor T4 is connected with the node Q, the drain is connected with the third GIP input signal end, and the source is connected with the second GIP output signal end;

[0014] The gate of the transistor T5 is connected with the node P, the drain is connected with the second GIP output signal end, and the source is connected with the second GIP input signal end;

[0015] The gate and the drain of the transistor T6 are connected with the fourth GIP input signal end, and the source is connected with the node P;

[0016] The gate of the transistor T7 is connected with the third GIP output signal end, the drain is connected with the node Q, and the source is connected with the second GIP input signal end;

[0017] The gate of the transistor T8 is connected with the node P, the drain is connected with the fifth GIP input signal end, and the source is connected with the node T;

[0018] One end of the capacitor C1 is connected with the node Q, and the other end is connected with the second GIP output signal end.

[0019] Further, the transistor T1, the transistor T2, the transistor T2a, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, and the transistor T8 are TFT thin film transistors.

[0020] Further, the first GIP output signal end is a G[n-4] marked end, the second GIP output signal end is a G[n] marked end, and the third GIP output signal end is a G[n+4] marked end.

[0021] Further, the first GIP input signal end is a FW marked end, the second GIP input signal end is a BW marked end, the third GIP input signal end is a CK marked end, the fourth GIP input signal end is a V1 marked end, and the fifth GIP input signal end is a VSN marked end.

[0022] Further, the FW marked end is connected with a first high-level signal, the BW marked end is connected with a first low-level signal, the CK marked end is connected with a clock signal, the V1 marked end is connected with a second high-level signal, and the VSN marked end is connected with a second low-level signal.

[0023] Further, a driving IC is further included, and the driving IC is connected with the FW marked end, the BW marked end, the CK marked end, the V1 marked end, and the VSN marked end.

[0024] Furthermore, the transistor T1 , the transistor T2 , the transistor T2 a , the transistor T3 , the transistor T4 , the transistor T5 , the transistor T6 , the transistor T7 , the transistor T8 and the capacitor C1 are all fixedly disposed on the LCD panel.

[0025] The advantage of the present invention is that transistors T8 and T2a are added to the existing 7T1C GIP driving circuit to form a node T. By controlling the voltage of node T, when node P is at a high level, leakage at node P can be effectively prevented, which would cause the output low level to be insufficient and thus prevent display defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0027] Figure 1 It is a structural diagram of a display driving circuit in the background art.

[0028] Figure 2 It is a timing diagram of a display driving circuit in the background art.

[0029] Figure 3 It is a schematic structural diagram of the display driving circuit of the present invention.

[0030] Figure 4 It is a timing diagram of the display driving circuit of the present invention. DETAILED DESCRIPTION

[0031] The embodiment of the present invention provides a novel display driving circuit to solve the disadvantage of insufficient low-level output caused by leakage at node P in the display driving circuit in the prior art, thereby achieving the technical effect of preventing display defects.

[0032] The technical solution in the embodiment of the present invention is to solve the above shortcomings. The overall idea is as follows: two transistors are added to the original 7T1C GIP display driver circuit, namely transistor T2a and transistor T8. In the new display driver circuit, the operation mode is that when the node P is at a high level, the transistor T8 will be turned on, and the drain of the transistor T8 is connected to VSN. The voltage of VSN will be transmitted to the node T. When the voltage of VSN is set to -6V and VGL is set to -12V (BW is VGL level, BW is also -12V), the Vg of the transistor T2 is s=-6V. When the TFT electrical characteristics of transistor T2 are in a high-temperature operating state with Vth<0, Vgs=-6V of transistor T2 prevents transistor T2 from turning on. This ensures that when node P is at a high level, no leakage occurs through transistor T2. This prevents the high level of node P from being insufficient, which in turn causes the pull-down device transistor T5 to be insufficiently turned on and weaken the pull-down capability. This prevents the low level output by G[n] from being insufficient to VGL, and prevents the pixel TFTs in the panel from not being fully locked when in the off state, resulting in crosstalk and display defects.

[0033] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0034] See Figures 1 to 4 , a preferred embodiment of the present invention.

[0035] A display driving circuit, comprising:

[0036] Transistor T1, transistor T2, transistor T2a, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8 and capacitor C1;

[0037] The gate of the transistor T1 is connected to the first GIP output signal terminal, the drain is connected to the first GIP input signal terminal, and the source is connected to the node Q;

[0038] The gate of the transistor T2 is connected to the node Q, the drain is connected to the node P, and the source is connected to the node T;

[0039] The gate of the transistor T2a is connected to the node Q, the drain is connected to the node T, and the source is connected to the second GIP input signal terminal;

[0040] The gate of the transistor T3 is connected to the node P, the drain is connected to the node Q, and the source is connected to the second GIP input signal terminal;

[0041] The gate of the transistor T4 is connected to the node Q, the drain is connected to the third GIP input signal terminal, and the source is connected to the second GIP output signal terminal;

[0042] The gate of the transistor T5 is connected to the node P, the drain is connected to the second GIP output signal terminal, and the source is connected to the second GIP input signal terminal;

[0043] The gate and drain of the transistor T6 are both connected to the fourth GIP input signal terminal, and the source is connected to the node P;

[0044] The gate of the transistor T7 is connected to the third GIP output signal terminal, the drain is connected to the node Q, and the source is connected to the second GIP input signal terminal;

[0045] The gate of the transistor T8 is connected to the node P, the drain is connected to the fifth GIP input signal terminal, and the source is connected to the node T;

[0046] One end of the capacitor C1 is connected to the node Q, and the other end is connected to the second GIP output signal terminal.

[0047] The first GIP output signal terminal is the output terminal of the upper-level display driving circuit and participates in the control work of the display driving circuit at this level. The second GIP output signal terminal is the output terminal of the display driving circuit at this level. The third GIP output signal terminal is the output terminal of the lower-level display driving circuit and participates in the control work of the display driving circuit at this level.

[0048] The transistors T1, T2, T2a, T3, T4, T5, T6, T7 and T8 are all TFT thin film transistors, which are based on the conduction principle of N-type MOS transistors.

[0049] The first GIP output signal terminal is labeled G[n-4], the second GIP output signal terminal is labeled G[n], and the third GIP output signal terminal is labeled G[n+4]. Markings are made on the circuit board to facilitate wiring. The G[n] terminal is the output signal terminal of the n-th stage display driver circuit. Where n is a positive integer.

[0050] The first GIP input signal terminal is marked FW, the second GIP input signal terminal is marked BW, the third GIP input signal terminal is marked CK, the fourth GIP input signal terminal is marked V1, and the fifth GIP input signal terminal is marked VSN. Markings are made on the circuit board to facilitate wiring.

[0051] The FW terminal is connected to a first high-level signal, the BW terminal is connected to a first low-level signal, the CK terminal is connected to a clock signal, the V1 terminal is connected to a second high-level signal, and the VSN terminal is connected to a second low-level signal. The VSN terminal is connected to a -6V voltage, and the BW terminal is connected to a -12V voltage. The FW terminal is connected to 13V, and the V1 terminal is connected to 13V. The high level of the CK terminal is 13V, and the low level is -10V.

[0052] The system further includes a driver IC connected to the FW mark terminal, the BW mark terminal, the CK mark terminal, the V1 mark terminal, and the VSN mark terminal. The driver IC adjusts the output signal.

[0053] The transistor T1 , the transistor T2 , the transistor T2 a , the transistor T3 , the transistor T4 , the transistor T5 , the transistor T6 , the transistor T7 , the transistor T8 and the capacitor C1 are all fixedly disposed on the LCD panel.

[0054] A new display driver circuit working mode: combined with Figure 3 and Figure 4, VGH is a high level, VGL is a low level, CK is a clock signal, FW is the VGH level, and BW is the VGL level. Gn is the signal output terminal. T1-T8 and T2a are TFT devices, and C1 is a capacitor. First, G[n-4] pre-charges node Q, and the charging voltage is approximately VGH. FW is the VGH level. When G[n-4] changes from a high level to a low level, the VGH voltage of node Q is in the holding stage. When CK changes from a low level to a high level, the potential of node Q is first coupled from the high level of CK to 2 times VGH. Transistor T4 is fully turned on, and G[n] starts to output. When CK changes from a high level to a low level, node Q decreases from 2 times VGH to VGH. When G[n+4] is a high level, transistor T7 is turned on, and node Q is pulled down to BW by transistor T7. At this time, the gate of transistor T2 is a low level, and transistor T2 is turned off. Node P starts to charge to a high level by transistor T6, and the gate of transistor T5 is a high level. Transistor T5 is turned on, stabilizing G[n] to BW. When node P is a high level, the gate of transistor T8 is a high level. , transistor T8 will turn on, and the drain of transistor T8 is connected to VSN. The voltage of VSN will be transmitted to node T. When the voltage of VSN is set to -6V and VGL is set to -12V (BW is VGL level, BW is also -12V), the Vgs of transistor T2 is -6V. When the TFT electrical characteristics of transistor T2 are in the high-temperature operating state, Vth<0. Since Vgs of transistor T2 is -6V, it prevents transistor T2 from turning on. Therefore, it can ensure that when the node P is at a high level, there will be no leakage through transistor T2, thereby preventing the high level of node P from being insufficient, causing the pull-down device transistor T5 to be insufficiently turned on and weakening the pull-down capability, thus preventing the low level output of G[n] from being less than VGL, and preventing the pixel TFT in the panel from not being fully locked in the off state, resulting in crosstalk and display defects.

[0055] The present invention adds transistors T8 and T2a to the original GIP circuit and forms a node T. By controlling the voltage of node T, leakage of node P can be effectively prevented when node P is at a high level, thereby preventing the display driver circuit from outputting an insufficient low-level voltage, thereby avoiding display defects.

[0056] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A display driving circuit, characterized in that: include: Transistor T1, transistor T2, transistor T2a, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8 and capacitor C1; The gate of the transistor T1 is connected to the first GIP output signal terminal, the drain is connected to the first GIP input signal terminal, and the source is connected to the node Q; The gate of the transistor T2 is connected to the node Q, the drain is connected to the node P, and the source is connected to the node T; The gate of the transistor T2a is connected to the node Q, the drain is connected to the node T, and the source is connected to the second GIP input signal terminal; The gate of the transistor T3 is connected to the node P, the drain is connected to the node Q, and the source is connected to the second GIP input signal terminal; The gate of the transistor T4 is connected to the node Q, the drain is connected to the third GIP input signal terminal, and the source is connected to the second GIP output signal terminal; The gate of the transistor T5 is connected to the node P, the drain is connected to the second GIP output signal terminal, and the source is connected to the second GIP input signal terminal; The gate and drain of the transistor T6 are both connected to the fourth GIP input signal terminal, and the source is connected to the node P; The gate of the transistor T7 is connected to the third GIP output signal terminal, the drain is connected to the node Q, and the source is connected to the second GIP input signal terminal; The gate of the transistor T8 is connected to the node P, the drain is connected to the fifth GIP input signal terminal, and the source is connected to the node T; One end of the capacitor C1 is connected to the node Q, and the other end is connected to the second GIP output signal terminal; The first GIP input signal terminal is an FW mark terminal, the second GIP input signal terminal is a BW mark terminal, the third GIP input signal terminal is a CK mark terminal, the fourth GIP input signal terminal is a V1 mark terminal, and the fifth GIP input signal terminal is a VSN mark terminal; The FW mark terminal is connected to the first high level signal, the BW mark terminal is connected to the first low level signal, the CK mark terminal is connected to the clock signal, the V1 mark terminal is connected to the second high level signal, and the VSN mark terminal is connected to the second low level signal; The VSN marked terminal is connected to a -6V voltage, and the BW marked terminal is connected to a -12V voltage.

2. The display driving circuit according to claim 1, wherein: The transistor T1 , the transistor T2 , the transistor T2 a , the transistor T3 , the transistor T4 , the transistor T5 , the transistor T6 , the transistor T7 , and the transistor T8 are all TFT thin film transistors.

3. The display driving circuit according to claim 1, wherein: The first GIP signal output terminal is a G[n-4] marking terminal, the second GIP signal output terminal is a G[n] marking terminal, and the third GIP signal output terminal is a G[n+4] marking terminal.

4. The display driving circuit according to claim 1, wherein: It also includes a driver IC, which is connected to the FW mark terminal, the BW mark terminal, the CK mark terminal, the V1 mark terminal, and the VSN mark terminal.

5. The display driving circuit according to claim 1, wherein: The transistor T1 , the transistor T2 , the transistor T2 a , the transistor T3 , the transistor T4 , the transistor T5 , the transistor T6 , the transistor T7 , the transistor T8 and the capacitor C1 are all fixedly disposed on the LCD panel.

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