Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a dielectric layer on a surface of the substrate; forming a first opening in the dielectric layer, a second opening in the dielectric layer, and an initial third opening in the substrate, the second opening being located at a bottom of the first opening and communicating with the first opening, a sidewall of the second opening being recessed relative to a sidewall of the first opening, the sidewall of the second opening being recessed relative to a sidewall of the initial third opening, and a bottom of the second opening exposing a top surface of a portion of the substrate; etching a sidewall of the initial third opening and the top surface of the substrate exposed by the bottom of the second opening to form a third opening in the substrate; and forming an epitaxial layer in the third opening, the second opening, and the first opening, thereby avoiding a "undercut" defect caused by etching the substrate only on the sidewall of the initial third opening, and improving performance of a device formed thereby.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] Silicon-based optoelectronic integration is the integration and development of microelectronics technology and photonics technology, and is an important frontier research field of information technology development. Its research content includes silicon-based high-efficiency light source, silicon-based high-speed photodetector, silicon-based high-speed optical modulator, low-loss optical waveguide device, etc. Epitaxial growth of germanium material on silicon substrate is the preferred material for silicon-based high-speed long-wavelength photodetector.

[0003] At present, the main process of growing germanium material on silicon substrate includes the process of growing germanium on silicon patterned substrate, etc. The method of growing germanium on silicon patterned substrate includes: preparing a silicon oxide thin film on a silicon substrate, then photoetching and etching the silicon oxide to expose a window for growing germanium, germanium will selectively grow at the position of silicon exposed by the window, and laterally overgrow to merge on the surface of the silicon oxide, forming a complete germanium epitaxial layer.

[0004] However, the existing process of growing germanium on silicon patterned substrate needs to be further improved. SUMMARY

[0005] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical scheme of the present application provides a semiconductor structure, comprising: a substrate; a dielectric layer located on the surface of the substrate; an epitaxial layer located in the dielectric layer and the substrate, the epitaxial layer comprising a first region, a second region adjacent to the first region and located on the first region, and a third region adjacent to the second region and located on the second region, the first region being located in the substrate, the second region and the third region being located in the dielectric layer, the second region sidewall being convex relative to the third region sidewall, and the second region sidewall being flush with or convex to the first region sidewall.

[0007] Optionally, the material of the epitaxial layer comprises germanium.

[0008] Optionally, the material of the dielectric layer comprises silicon oxide.

[0009] The application also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a first opening in the dielectric layer, a second opening in the dielectric layer, and an initial third opening in the substrate, the second opening is located at the bottom of the first opening and communicates with the first opening, the sidewall of the second opening is recessed relative to the sidewall of the first opening, the sidewall of the second opening is recessed relative to the sidewall of the initial third opening, and the bottom of the second opening exposes part of the top surface of the substrate; etching the inner wall of the initial third opening and the top surface of the substrate exposed by the bottom of the second opening to form a third opening in the substrate; and forming an epitaxial layer in the third opening, the second opening and the first opening.

[0010] Optionally, before forming the dielectric layer, a sacrificial layer is formed on part of the surface of the substrate, and the dielectric layer is located on the sidewall and top surface of the sacrificial layer.

[0011] Optionally, the method for forming the first opening, the second opening and the initial third opening comprises: forming a mask layer on part of the surface of the dielectric layer; etching the dielectric layer with the mask layer as a mask until part of the sacrificial layer is exposed to form the first opening; etching the sacrificial layer and the substrate exposed by the first opening with the mask layer as a mask to form the initial third opening in the substrate and the initial second opening in the dielectric layer, and the sidewall of the initial second opening exposes the sacrificial layer; and removing the remaining sacrificial layer after forming the initial third opening to form the second opening.

[0012] Optionally, the forming process of the first opening comprises one or a combination of dry etching process and wet etching process; and the forming process of the initial third opening and the initial second opening comprises one or a combination of dry etching process and wet etching process.

[0013] Optionally, the process for removing the remaining sacrificial layer is an isotropic etching process.

[0014] Optionally, the material of the sacrificial layer is different from that of the dielectric layer; and the material of the sacrificial layer is different from that of the substrate.

[0015] Optionally, the method for forming the first opening, the second opening and the initial third opening comprises: etching the dielectric layer until part of the sacrificial layer is exposed to form the first opening in the dielectric layer; removing the sacrificial layer after forming the first opening to form the second opening; and etching the substrate exposed by the bottom of the first opening to form the initial third opening after forming the second opening.

[0016] Optionally, the forming process of the first opening comprises one or a combination of dry etching process and wet etching process.

[0017] Optionally, the process of removing the sacrificial layer is an isotropic etching process.

[0018] Optionally, there is a protective layer between the substrate and the dielectric layer.

[0019] Optionally, the material of the protective layer comprises silicon oxide, and the material of the sacrificial layer comprises polysilicon.

[0020] Optionally, the forming process of the protective layer and the sacrificial layer comprises: forming a gate oxide material layer on the substrate; forming a dummy gate material layer on the gate oxide material layer; forming a patterned layer on the dummy gate material layer; etching the dummy gate material layer and the gate oxide material layer with the patterned layer as a mask to form the sacrificial layer and the protective layer.

[0021] Optionally, the gate oxide material layer is etched to form a gate oxide layer and the dummy gate material layer is etched to form a dummy gate at the same time when the sacrificial layer and the protective layer are formed, which is used to form MOS devices in other areas.

[0022] Optionally, the process of etching the top surface of the substrate exposed by the inner wall of the initial third opening and the bottom of the second opening comprises one or a combination of dry etching process and wet etching process.

[0023] Optionally, the process of etching the top surface of the substrate exposed by the inner wall of the initial third opening and the bottom of the second opening is a dry etching process, and the etching gas used in the dry etching process comprises hydrogen chloride.

[0024] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0025] In the forming method of the semiconductor structure provided by the technical scheme, the top surface of the substrate exposed by the inner wall of the initial third opening and the bottom of the second opening is etched to form a third opening in the substrate. In the etching process, since the top surface of the substrate adjacent to the side wall of the initial third opening is also exposed to the etching liquid or etching gas due to the second opening, the top surface of the substrate exposed by the side wall of the initial third opening is etched at the same time, and the top surface of the substrate exposed by the bottom of the second opening is also etched, so that the "undercut" defect caused by etching only the substrate of the side wall of the initial third opening is avoided, and the performance of the formed device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figures 1 to 3is a sectional view of a semiconductor structure formation process;

[0027] Figures 4 to 9 is a structure diagram of each step of a semiconductor structure formation method in an embodiment of the present application;

[0028] Figures 10 to 15 is a structure diagram of each step of a semiconductor structure formation method in another embodiment of the present application. DETAILED DESCRIPTION

[0029] It should be noted that the "surface", "upper", in the specification, are used to describe the relative position relationship in space, and are not limited to whether they are in direct contact.

[0030] As described in the background, the performance of the semiconductor structure formed by using the existing germanium growth process on a silicon patterned substrate needs to be improved. Now a semiconductor structure formation process is described and analyzed.

[0031] Figures 1 to 3 is a sectional view of a semiconductor structure formation process.

[0032] Referring to Figure 1 , a substrate 100 is provided; an oxide layer 101 is formed on the substrate 100.

[0033] Referring to Figure 2 , the oxide layer 101 and the substrate 100 are etched to form an opening 103 in the oxide layer 101 and the substrate 100; and a surface damage layer of the substrate 100 at the bottom surface of the opening 103 is removed.

[0034] Referring to Figure 3 , after removing the damage layer, a germanium material layer 104 is formed in the opening 103.

[0035] In the above method, the material of the substrate 100 is silicon, and the germanium material layer 104 is epitaxially grown on the surface of the substrate 100 at the bottom of the opening 103. In order to prepare for the epitaxial growth of germanium on the surface of silicon, the surface damage layer of the substrate 100 at the bottom surface of the opening 103 needs to be removed, and a HCl gas phase etching polishing process is usually used to remove the damage layer by using the way that HCl gas reacts with silicon at high temperature. During the process, the sidewall of the opening 103 is exposed to the etching gas, which will cause lateral etching to the sidewall of the opening 103 in the substrate 100, forming an "undercut" defect A (as shown in Figure 3 ) at the sidewall of the opening 103. The defect A will affect the performance of the formed germanium photodetector, and the size and depth of the defect A are positively correlated with the dark current of the device. In order to eliminate the influence of the "undercut" defect,

[0036] In an embodiment to solve the above problem, in the HCl gas phase etching polishing process, dichlorosilane (DCS) precursor gas is introduced to remove the damage layer and deposit crystalline silicon on the surface of the opening 103, so that the silicon epitaxially grows on the surface of the silicon 100 substrate exposed by the opening 103, thereby repairing the surface of the substrate 100 exposed by the opening 103 and reducing the size of the undercut defect A. However, the method of introducing the precursor gas cannot completely eliminate the undercut defect A, and the epitaxial growth process has strict requirements on the temperature. If the temperature is too high, the selectivity of the surface of the substrate 100 to the growth of crystalline silicon will be affected, and if the temperature is too low, the quality of the crystalline silicon will be affected.

[0037] To solve the above problem, the present application provides a method for forming a semiconductor structure. The top surface of the substrate exposed by the sidewall of the initial third opening and the bottom of the second opening is etched to form a third opening in the substrate. In the etching process, the top surface of the substrate adjacent to the sidewall of the initial third opening is also exposed to the etching liquid or etching gas due to the second opening, so that the substrate exposed by the sidewall of the initial third opening is etched, and the top surface of the substrate exposed by the bottom of the second opening is also etched, thereby avoiding the undercut defect caused by etching only the substrate of the sidewall of the initial third opening, and improving the performance of the formed device.

[0038] To make the above-mentioned purposes, features and benefits of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0039] Figures 4 to 7 is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present application.

[0040] Please refer to Figure 4 , a substrate 200 is provided; a dielectric layer 201 is formed on the surface of the substrate 200.

[0041] The material of the substrate 200 includes silicon.

[0042] The material of the dielectric layer 201 includes silicon oxide.

[0043] In this embodiment, there is also a protective layer 203 between the substrate 200 and the dielectric layer 201.

[0044] The material of the protective layer 203 includes silicon oxide.

[0045] In this embodiment, before forming the dielectric layer 201, a sacrificial layer 202 is formed on part of the surface of the substrate 200, and the dielectric layer 201 is formed on the sidewall and top surface of the sacrificial layer 202.

[0046] The material of the sacrificial layer 202 includes polysilicon.

[0047] The sacrificial layer 202 is used to occupy space for forming a second opening later, and thus the material of the sacrificial layer 202 can be different from that of the dielectric layer 201. In the etching process for forming the second opening, the sacrificial layer 202 has a larger etching selectivity ratio relative to the dielectric layer 201, so as to reduce the etching damage of the dielectric layer 201. In this embodiment, the material of the sacrificial layer 202 is polysilicon.

[0048] The forming method of the protective layer 203 and the sacrificial layer 202 includes: forming a gate oxide material layer (not shown in the figure) on the substrate 200; forming a pseudo-gate material layer (not shown in the figure) on the gate oxide material layer; forming a patterned layer (not shown in the figure) on the pseudo-gate material layer; and etching the pseudo-gate material layer and the gate oxide material layer to form the sacrificial layer 202 and the protective layer 203, with the patterned layer as a mask.

[0049] In another embodiment, the gate oxide material layer is etched to form a gate oxide layer (not shown in the figure) and the pseudo-gate material layer is etched to form a pseudo-gate (not shown in the figure) at the same time as the sacrificial layer 202 and the protective layer 203 are formed, for forming MOS devices in other areas. The sacrificial layer 202 and the pseudo-gate are formed at the same time, and the protective layer 203 and the gate oxide layer are formed at the same time, thereby saving the process and reducing the production cost.

[0050] Subsequently, a first opening in the dielectric layer, a second opening in the dielectric layer, and an initial third opening in the substrate are formed. The second opening is located at the bottom of the first opening and communicates with the first opening, the sidewall of the second opening is recessed relative to the sidewall of the first opening, the sidewall of the second opening is recessed relative to the sidewall of the initial third opening, and the bottom of the second opening exposes part of the top surface of the substrate.

[0051] In this embodiment, the forming method of the first opening, the second opening, and the initial third opening, please refer to Figures 5 to 7In other embodiments, the method for forming the first opening, the second opening and the initial third opening comprises: forming a mask layer on a part of the surface of the medium layer; etching the medium layer with the mask layer as a mask until a part of the sacrificial layer is exposed to form the first opening; etching the sacrificial layer exposed by the first opening and the substrate with the mask layer as a mask to form the initial third opening in the substrate and an initial second opening in the medium layer, the sidewall of the initial second opening exposing the sacrificial layer; and removing the remaining sacrificial layer after forming the initial third opening to form the second opening.

[0052] Please refer to Figure 5 The medium layer 201 is etched until a part of the sacrificial layer 202 is exposed to form a first opening 205 in the medium layer 201.

[0053] In this embodiment, the method for forming the first opening 205 further comprises: forming a mask layer 204 on a part of the surface of the medium layer 201; etching the medium layer 201 with the mask layer 204 as a mask until a part of the sacrificial layer 202 is exposed to form the first opening 205.

[0054] The material of the mask layer 204 is photoresist.

[0055] Please refer to Figure 6 The sacrificial layer 202 is removed after forming the first opening 205 to form the second opening 206.

[0056] The process for removing the sacrificial layer 202 is isotropic etching process.

[0057] The process for removing the sacrificial layer 202 includes one or a combination of dry etching process and wet etching process. The process for removing the sacrificial layer 202 has a large etching selectivity of the sacrificial layer 202 relative to the medium layer 201, which is beneficial to protect the medium layer 201 from etching damage during the process of removing the sacrificial layer 202.

[0058] In this embodiment, the process for removing the sacrificial layer 202 is wet etching process. The wet etching process uses potassium hydroxide solution. Since the potassium hydroxide solution has a large selectivity for polysilicon material and silicon oxide material, it is beneficial to protect the medium layer 201 and the protective layer 203 from etching damage during the process of removing the sacrificial layer 202, and the protective layer 203 further protects the substrate 200 from etching damage.

[0059] Please refer to Figure 7 The substrate 200 exposed by the bottom of the first opening 205 is etched to form an initial third opening 207 after forming the second opening 206.

[0060] Referring to Figure 8 The inner wall of the initial third opening 207 and the top surface of the substrate 200 exposed by the bottom of the second opening 206 are etched to form a third opening 208 in the substrate 200. Figure 7 The inner wall of the initial third opening 207 and the top surface of the substrate 200 exposed by the bottom of the second opening 206 are etched to form a third opening 208 in the substrate 200.

[0061] The etching process for the inner wall of the initial third opening 207 and the top surface of the substrate 200 exposed by the bottom of the second opening 206 includes one or a combination of dry etching and wet etching.

[0062] The etching process is used to remove the surface damage layer of the substrate 200 exposed by the inner wall of the initial third opening 207, preparing for the subsequent formation of an epitaxial layer in the third opening. At the same time, in the etching process, since the second opening 206 exposes the top surface of the substrate 200 adjacent to the sidewall of the initial third opening 207 to the etching liquid or etching gas, the substrate exposed by the sidewall of the initial third opening 207 is etched while the top surface of the substrate exposed by the bottom of the second opening 206 is etched, thereby avoiding the "undercut" defect caused by etching only the substrate of the sidewall of the initial third opening 207, and further improving the performance of the formed device. In this embodiment, the top surface of the substrate exposed by the bottom of the second opening 206 is etched at the same time, and the protective layer 203 is also etched.

[0063] In this embodiment, the sidewall of the third opening 208 is flush with the sidewall of the second opening 206. In other embodiments, the sidewall of the second opening 206 is recessed relative to the sidewall of the third opening 208, and the topography of the third opening 208 is determined by the etching condition.

[0064] In this embodiment, the process for etching the inner wall of the initial third opening 207 and the top surface of the substrate 200 exposed by the bottom of the second opening 206 is a dry etching process, and the etching gas used in the dry etching process includes hydrogen chloride.

[0065] Subsequently, an epitaxial layer is formed in the third opening 208, the second opening 206, and the first opening 205.

[0066] In this embodiment, the mask layer 204 is also removed before the epitaxial layer is formed.

[0067] Referring to Figure 9 An epitaxial layer 209 is formed in the third opening 208, the second opening 206, and the first opening 205.

[0068] The material of the epitaxial layer 209 includes germanium.

[0069] The substrate 200 exposed by the third opening 208 is used as a seed crystal to generate the epitaxial layer 209 using epitaxial growth technology.

[0070] The epitaxial layer 209 includes a first region (not shown in the figure) located within the third opening 208, a second region (not shown in the figure) located within the second opening 206, and a third region (not shown in the figure) located within the first opening 205. The morphology of the epitaxial layer 209 is determined by the morphology of the first opening 205, the second opening 206, and the third opening 208.

[0071] Accordingly, this invention also provides a semiconductor structure, please refer to [the relevant documentation]. Figure 9 The system includes: a substrate 200; a dielectric layer 201 located on the surface of the substrate 200; and an epitaxial layer 209 located within the dielectric layer 201 and the substrate 200. The epitaxial layer 209 includes a first region (not shown in the figure), a second region (not shown in the figure) adjacent to and located on the first region, and a third region (not shown in the figure) adjacent to and located on the second region. The first region is located within the substrate 200, and the second and third regions are located within the dielectric layer 201. The sidewall of the second region protrudes relative to the sidewall of the third region, and the sidewall of the second region is flush with or protrudes from the sidewall of the first region.

[0072] The material of the epitaxial layer 209 includes germanium.

[0073] The material of the dielectric layer 201 includes silicon oxide.

[0074] In this embodiment, a protective layer 203 is located between the substrate 200 and the dielectric layer 201.

[0075] Figures 10 to 15 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to another embodiment of the present invention.

[0076] In this embodiment, the method for forming the first opening, the second opening, and the initial third opening is described in reference [reference needed]. Figures 10 to 13 .

[0077] Please refer to Figure 10 A substrate 300 is provided; a dielectric layer 301 is formed on the surface of the substrate 300.

[0078] The substrate 300 is made of silicon.

[0079] The material of the dielectric layer 301 includes silicon oxide.

[0080] In this embodiment, before forming the dielectric layer 301, a sacrificial layer 302 is formed on part of the surface of the substrate 300, and the dielectric layer 301 is formed on the sidewall and top surface of the sacrificial layer 302. In other embodiments, a protective layer is formed on the surface of the dielectric layer 301 before forming the sacrificial layer 302.

[0081] The material of the sacrificial layer 302 is different from that of the dielectric layer 301, and the material of the sacrificial layer 302 is different from that of the substrate 300. In this embodiment, the material of the sacrificial layer 302 is silicon nitride.

[0082] The sacrificial layer 302 is used to occupy space for forming a second opening later. In the process of forming the second opening, an etching process with a large selectivity to the sacrificial layer 302 and the dielectric layer 301 can be selected to reduce damage to the dielectric layer 301 in the etching process. In the process of forming the second opening, an etching process with a large selectivity to the sacrificial layer 302 and the substrate 300 can be selected to reduce damage to the substrate 300 in the etching process.

[0083] The method for forming the sacrificial layer 302 includes: forming a sacrificial material layer (not shown in the figure) on the substrate 200; forming a patterned layer (not shown in the figure) on the sacrificial material layer; and etching the sacrificial material layer to form the sacrificial layer 302 by taking the patterned layer as a mask.

[0084] Please refer to Figure 11 A mask layer 303 is formed on part of the surface of the dielectric layer 301, and the dielectric layer 301 is etched by taking the mask layer 303 as a mask until part of the sacrificial layer 302 is exposed to form the first opening 304.

[0085] The material of the mask layer 303 includes photoresist.

[0086] The forming process of the first opening 304 includes one or a combination of dry etching process and wet etching process. In this embodiment, the forming process of the first opening 304 is dry etching process, which is beneficial to form an opening with better morphology.

[0087] Please refer to Figure 12 The sacrificial layer 302 and the substrate 300 exposed by the first opening 304 are etched by taking the mask layer 303 as a mask to form the initial third opening 306 in the substrate 300 and the initial second opening 305 in the dielectric layer 301, and the sidewall of the initial second opening 305 exposes the sacrificial layer 302.

[0088] The formation process of the initial third opening 306 and the initial second opening 305 includes one or a combination of dry etching and wet etching processes. In this embodiment, the initial third opening and the initial second opening 305 are formed by dry etching. Dry etching is beneficial for forming openings with better morphology, and the initial third opening 306 and the initial second opening 305 are formed in the same process, saving process steps and reducing production costs.

[0089] Please refer to Figure 13 After forming the initial third opening 306, the remaining sacrificial layer 302 is removed to form the second opening 307.

[0090] The process for removing the remaining sacrificial layer 302 is an isotropic etching process.

[0091] The process for removing the sacrificial layer 302 includes one or a combination of dry etching and wet etching. The process for removing the sacrificial layer 302 has a high etching selectivity relative to the dielectric layer 301, which helps protect the dielectric layer 301 from etching damage during the removal of the sacrificial layer 302.

[0092] In this embodiment, the process for removing the sacrificial layer 302 is a wet etching process. The wet etching process uses a phosphoric acid solution. Because the phosphoric acid solution has a high selectivity for silicon nitride and silicon oxide materials, it helps to prevent etching damage to the dielectric layer 301 during the removal of the sacrificial layer 302. Simultaneously, because the phosphoric acid solution has a high selectivity for silicon oxide and silicon materials, it helps to protect the substrate 300 from etching damage during the removal of the sacrificial layer 302.

[0093] Please refer to Figure 14 For the initial third opening 306 (e.g. Figure 13 (as shown) inner wall and second opening 307 (as shown) Figure 13 The top surface of the substrate 300 exposed at the bottom (as shown) is etched to form a third opening 308 within the substrate 300.

[0094] The etching process for the inner wall of the initial third opening 207 and the top surface of the substrate 200 exposed at the bottom of the second opening 206 includes one or a combination of dry etching and wet etching processes.

[0095] The etching process is used to remove the surface damage layer of the substrate 200 exposed by the inner wall of the initial third opening 207, and to prepare for forming an epitaxial layer in the third opening subsequently. Meanwhile, in the etching process, the top surface of the substrate 200 adjacent to the sidewall of the initial third opening 207 is also exposed to the etching liquid or etching gas due to the second opening 206, so that the substrate exposed by the sidewall of the initial third opening 207 is etched while the top surface of the substrate exposed by the bottom of the second opening 206 is etched, thereby avoiding the "undercut" defect caused by etching the substrate only on the sidewall of the initial third opening 207, and further improving the performance of the formed device.

[0096] In the embodiment, the process of etching the top surface of the substrate 200 exposed by the inner wall of the initial third opening 207 and the bottom of the second opening 206 is a dry etching process, and the etching gas used in the dry etching process includes hydrogen chloride.

[0097] Subsequently, an epitaxial layer is formed in the third opening 308, the second opening 307 and the first opening 304.

[0098] In the embodiment, the mask layer 204 is removed before forming the epitaxial layer.

[0099] Please refer to Figure 15 An epitaxial layer 309 is formed in the third opening 308, the second opening 307 and the first opening 304.

[0100] The material of the epitaxial layer 309 includes germanium. The substrate 200 exposed by the third opening 308 is used as a seed crystal to generate the epitaxial layer 309 by epitaxial growth technology.

[0101] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope defined in the claims.​

Claims

1. A semiconductor structure, characterized by, The method comprises: providing a substrate; forming a dielectric layer on the substrate; forming a first opening in the dielectric layer, a second opening in the dielectric layer, and a third opening in the substrate, the second opening being located at the bottom of the first opening and communicating with the first opening, the sidewall of the second opening being recessed relative to the sidewall of the first opening, the sidewall of the second opening being recessed relative to the sidewall of the third opening or being flush with the sidewall of the third opening, the third opening being formed by etching the top surface of the substrate exposed at the bottom of the second opening and the inner wall of the initial third opening after forming the first opening, the second opening, and the initial third opening in the substrate, the initial third opening and the first opening communicating with each other; forming an epitaxial layer in the first opening, the second opening, and the third opening, the epitaxial layer comprising a first region, a second region adjacent to the first region and located on the first region, and a third region adjacent to the second region and located on the second region, the first region being located in the third opening, the second region being located in the second opening, and the third region being located in the first opening, the sidewall of the second region being convex relative to the sidewall of the third region, the sidewall of the second region being flush with or convex relative to the sidewall of the first region.

2. The semiconductor structure of claim 1, wherein, The material of the epitaxial layer comprises germanium.

3. The semiconductor structure of claim 1, wherein, The material of the dielectric layer comprises silicon oxide.

4. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate; forming a dielectric layer on the substrate; forming a first opening in the dielectric layer, a second opening in the dielectric layer, and an initial third opening in the substrate, the second opening being located at the bottom of the first opening and communicating with the first opening, the sidewall of the second opening being recessed relative to the sidewall of the first opening, the sidewall of the second opening being recessed relative to the sidewall of the initial third opening, and the bottom of the second opening exposing a part of the top surface of the substrate; etching the inner wall of the initial third opening and the top surface of the substrate exposed at the bottom of the second opening to form a third opening in the substrate; forming an epitaxial layer in the third opening, the second opening, and the first opening.

5. The method of forming a semiconductor structure of claim 4, wherein, Before forming the dielectric layer, a sacrificial layer is formed on a part of the surface of the substrate, and the dielectric layer is located on the sidewall and the top surface of the sacrificial layer.

6. The method of forming a semiconductor structure of claim 5, wherein, The method for forming the first opening, the second opening, and the initial third opening comprises: forming a mask layer on a part of the surface of the dielectric layer; etching the dielectric layer with the mask layer as a mask until a part of the sacrificial layer is exposed to form the first opening; etching the sacrificial layer and the substrate exposed at the first opening with the mask layer as a mask to form the initial third opening in the substrate and the initial second opening in the dielectric layer, the sidewall of the initial second opening exposing the sacrificial layer; and removing the remaining sacrificial layer after forming the initial third opening to form the second opening.

7. The method of forming a semiconductor structure of claim 6, wherein, The forming process of the first opening comprises one or a combination of dry etching process and wet etching process; the forming process of the initial third opening and the initial second opening comprises one or a combination of dry etching process and wet etching process.

8. The method of forming a semiconductor structure of claim 6, wherein, The process of removing the remaining sacrificial layer is an isotropic etching process.

9. The method of forming a semiconductor structure of claim 5, wherein, The material of the sacrificial layer is different from the material of the dielectric layer; the material of the sacrificial layer is different from the material of the substrate.

10. The method of forming a semiconductor structure of claim 5, wherein, The forming method of the first opening, the second opening and the initial third opening comprises: etching the dielectric layer until part of the sacrificial layer is exposed, forming a first opening in the dielectric layer; after forming the first opening, removing the sacrificial layer to form the second opening; after forming the second opening, etching the substrate exposed at the bottom of the first opening to form the initial third opening.

11. The forming method of the semiconductor structure according to claim 10, wherein the forming process of the first opening comprises one or a combination of dry etching process and wet etching process.

12. The forming method of the semiconductor structure according to claim 10, wherein the process of removing the sacrificial layer is an isotropic etching process.

13. The method of forming a semiconductor structure of claim 10, wherein, There is also a protective layer between the substrate and the dielectric layer.

14. The method of forming a semiconductor structure of claim 13, wherein, The material of the protective layer comprises silicon oxide; the material of the sacrificial layer comprises polysilicon.

15. The method of forming a semiconductor structure of claim 13, wherein, The forming method of the protective layer and the sacrificial layer comprises: forming a gate oxide material layer on the substrate; forming a pseudo gate material layer on the gate oxide material layer; forming a patterned layer on the pseudo gate material layer; etching the pseudo gate material layer and the gate oxide material layer with the patterned layer as a mask to form the sacrificial layer and the protective layer.

16. The method of forming a semiconductor structure of claim 15, wherein, The gate oxide material layer is also etched to form a gate oxide layer and the pseudo gate material layer is also etched to form a pseudo gate when the sacrificial layer and the protective layer are formed, which are used to form MOS devices in other areas.

17. The method of forming a semiconductor structure of claim 4, wherein, The process of etching the inner wall of the initial third opening and the top surface of the substrate exposed at the bottom of the second opening comprises one or a combination of dry etching process and wet etching process.

18. The method of forming a semiconductor structure of claim 17, wherein, The process of etching the inner wall of the initial third opening and the top surface of the substrate exposed at the bottom of the second opening is a dry etching process, and the etching gas used in the dry etching process comprises hydrogen chloride.

Images