Digital-to-analog converter and digital-to-analog conversion method thereof

Abstract

The present application provides a digital-to-analog converter and a digital-to-analog conversion method. The digital-to-analog conversion method comprises converting a digital data signal into an analog data signal in a first period according to a clock signal, resetting the analog data signal according to a reset signal corresponding to a first reset level in a second period according to the clock signal, compensating a voltage level of the reset analog data signal according to a second reset level in the second period, and making the voltage level of the reset analog data signal be at the second reset level, wherein the second reset level is higher or lower than the first reset level.

Description

Technical Field

[0001] The present invention relates to a digital-to-analog converter, and more particularly to a digital-to-analog converter that provides a compensation voltage when performing a zero-conversion. Background Technology

[0002] Electronic products are often affected by adverse effects during operation, such as noise and harmonics, causing them to malfunction as expected. This can range from minor issues affecting user experience to serious problems impacting the product's original functionality. For example, with audio products like microphones and speakers, even when there is no sound input, the audio product may produce sound output at certain frequencies due to harmonics (idle tone). This results in the user continuously hearing sound from the speaker even when no sound is being emitted, rendering the audio product unusable. Therefore, adverse effects such as noise and harmonics have a significant impact on the operation of electronic products. Summary of the Invention

[0003] In some embodiments, a digital-to-analog converter (DAC) includes a DAC circuit and a compensation circuit. The DAC circuit receives a clock signal, a digital data signal, and a reset signal corresponding to a first reset level. The DAC circuit is used to convert the digital data signal into an analog data signal in a first cycle according to the clock signal, and to reset the analog data signal according to the first reset level in a second cycle according to the clock signal. The compensation circuit is coupled to the DAC circuit. In the second cycle, the compensation circuit compensates for the voltage level of the reset analog data signal according to a second reset level, so that the voltage level of the reset analog data signal is at the second reset level, wherein the second reset level is higher or lower than the first reset level.

[0004] In some embodiments, a digital-to-analog conversion method includes receiving a digital data signal in a first cycle according to a clock signal, converting the digital data signal into an analog data signal, resetting the analog data signal according to a reset signal corresponding to a first reset level in a second cycle according to the clock signal, and compensating the voltage level of the reset analog data signal according to a second reset level in the second cycle, so that the voltage level of the reset analog data signal is at the second reset level, wherein the aforementioned second reset level is higher or lower than the first reset level. Attached Figure Description

[0005] Figure 1 This is a block diagram of some embodiments of the digital-to-analog converter coupled signal generation device according to the present invention;

[0006] Figure 2 for Figure 1 A circuit diagram of an embodiment of a digital-to-analog converter operating in the second cycle;

[0007] Figure 3 for Figure 1 A waveform diagram of an embodiment of a digital-to-analog converter performing digital-to-analog conversion and return-to-zero conversion;

[0008] Figure 4 for Figure 1 A circuit diagram of an embodiment of a digital-to-analog converter operating in the first cycle;

[0009] Figure 5 This is a schematic diagram of an embodiment of the reset signal and digital data signal according to the present invention;

[0010] Figure 6 This is a circuit diagram of the current unit of a compensation circuit or the current unit of a digital-to-analog converter circuit according to one embodiment.

[0011] Figure 7A and Figure 7B This is a flowchart illustrating a digital-to-analog conversion method according to one embodiment. Detailed Implementation

[0012] Figure 1 For block diagrams of some embodiments of the digital-to-analog converter 1 according to the present invention, please refer to... Figure 1 A digital-to-analog converter 1 can be coupled to a signal generating device 2. The signal generating device 2 generates a digital data signal D, which can include any number of bits (e.g., 1 bit, 2 bits, or more than 3 bits), and generates a clock signal CLK, a reset signal RZ, and a compensation input signal S1. The signal generating device 2 sends the digital data signal D, the clock signal CLK, the reset signal RZ, and the compensation input signal S1 to the digital-to-analog converter 1. Depending on the different levels of the clock signal CLK, the digital-to-analog converter 1 can perform digital-to-analog conversion of the digital data signal D, or it can perform a return-to-zero conversion based on the compensation input signal S1 and the reset signal RZ. The digital-to-analog converter 1 performs both digital-to-analog conversion and return-to-zero conversion to generate an analog data signal A with a corresponding voltage level.

[0013] like Figure 2 As shown, the digital-to-analog converter 1 may include a digital-to-analog conversion circuit 11 and a compensation circuit 12, with the digital-to-analog conversion circuit 11 coupled to the compensation circuit 12. The digital-to-analog conversion circuit 11 can receive a digital data signal D and a reset signal RZ, and the compensation circuit 12 can receive a compensation input signal S1. Please refer to the combined diagram. Figures 1 to 3According to the clock signal CLK, the digital-to-analog converter 11 can receive the digital data signal D during the period when the clock signal CLK is at the first level (hereinafter referred to as the first period), and the digital-to-analog converter 11 converts the digital data signal D into an analog data signal A with a corresponding voltage level; and the digital-to-analog converter 11 can receive the reset signal RZ during the period when the clock signal CLK is at the second level (hereinafter referred to as the second period), and the digital-to-analog converter 11 performs the zero-reset conversion of the analog data signal A according to the reset level L1 (hereinafter referred to as the first reset level L1) corresponding to the reset signal RZ.

[0014] Furthermore, in the aforementioned second cycle, the compensation circuit 12 can receive the compensation input signal S1, and the compensation circuit 12 generates a compensation output signal S2 based on the compensation input signal S1. The compensation output signal S2 can compensate the voltage level of the analog data signal A after the zero-reset conversion. That is, through the compensation output signal S2 generated by the compensation circuit 12, the digital-to-analog converter 1 can generate an analog data signal A with a higher reset level L2 (hereinafter referred to as the second reset level L2) when performing the zero-reset conversion. The voltage level of the compensated and reset analog data signal A is at the second reset level L2, and as... Figure 3 As shown, the second reset level L2 is higher than the aforementioned first reset level L1. In another embodiment, the second reset level L2 is lower than the aforementioned first reset level L1.

[0015] Based on this, the compensation circuit 12 can compensate for the voltage level of the reset analog data signal A during the zero-reset transition according to a higher reset level. In other words, the digital-to-analog converter 1 can perform a zero-reset transition on the analog data signal A according to a higher reset level, so that the reset analog data signal A is at a higher reset level, resulting in an offset voltage in the analog data signal A. Depending on the product application, taking the digital-to-analog converter 1 applied to audio products as an example, the harmonics generated by the digital-to-analog converter 1 with a higher offset voltage occur outside the audio range inaudible to the human ear (e.g., an audio range greater than 20kHz). This avoids the problem of audio products outputting sound when no audio is received.

[0016] In some embodiments, taking the digital data signal D as an example, which includes at least four bits, please refer to the following: Figure 2 and Figure 3The digital-to-analog converter circuit 11 may include four current units 111, 112, 113, and 114, an amplifier circuit 115, and feedback resistors R1 and R2. The current units 111, 112, 113, and 114 are coupled to the input terminals of the amplifier circuit 115. Each current unit 111, 112, 113, and 114 includes input terminals I1 and I2, current sources C1 and C2, transistor switches P1 and P2, and transistor switches N1 and N2. Transistor switches P1 and P2 may be P-type transistors, and transistor switches N1 and N2 may be N-type transistors. Current source C1 is coupled to the source terminals of transistor switches P1 and P2; current source C2 is coupled to the source terminals of transistor switches N1 and N2. The drain terminal of transistor switch P1 is coupled to the drain terminal of transistor switch N1, and the drain terminal of transistor switch P2 is coupled to the drain terminal of transistor switch N2. Furthermore, the connection point Z1 between transistor switch P1 and transistor switch N1 is coupled to one input terminal of amplifier circuit 115, the connection point Z2 between transistor switch P2 and transistor switch N2 is coupled to the other input terminal of amplifier circuit 115, and the feedback resistors R1 and R2 are coupled between the input terminal and the output terminal of amplifier circuit 115.

[0017] Based on this, in the first cycle, the input terminals I1 of current units 111, 112, 113, and 114 can each receive one bit of the digital data signal D, and the input terminal I2 receives the inverted signal of the bit received by input terminal I1. For example, the input terminal I1 of current unit 111 can receive the first bit of the digital data signal D, the input terminal I2 of current unit 111 can receive the inverted signal of the first bit of the digital data signal D, the input terminal I1 of current unit 112 can receive the second bit of the digital data signal D, the input terminal I2 of current unit 112 can receive the inverted signal of the second bit of the digital data signal D, the input terminal I1 of current unit 113 can receive the third bit of the digital data signal D, the input terminal I2 of current unit 113 can receive the inverted signal of the third bit of the digital data signal D, the input terminal I1 of current unit 114 can receive the fourth bit of the digital data signal D, and the input terminal I2 of current unit 114 can receive the inverted signal of the fourth bit of the digital data signal D.

[0018] Therefore, the signals received by input terminals I1 and I2 are inverses of each other. When the bit of the digital data signal D received by input terminal I1 is "0", transistor switches P1 and N2 are in the on state, and transistor switches P2 and N1 are in the off state. The current signal provided by current source C1 forms a current path between transistor switch P1, connection point Z1, input terminal of amplifier circuit 115, feedback resistor R1 and output terminal of amplifier circuit 115, and forms a corresponding voltage on feedback resistor R1. Furthermore, the current signal provided by current source C2 forms a current path between the output terminal of amplifier circuit 115, feedback resistor R2, input terminal of amplifier circuit 115, connection point Z2 and transistor switch N2, and forms a corresponding voltage on feedback resistor R2, so as to generate voltage V0 at the output terminal of amplifier circuit 115. This voltage V0 is the aforementioned analog data signal A. On the other hand, when the input terminal I1 receives a "1" bit in the digital data signal D, transistor switches P2 and N1 are in the on state, and transistor switches P1 and N2 are in the off state. The current signal provided by current source C2 forms a current path between transistor switch N1, connection point Z1, input terminal of amplifier circuit 115, feedback resistor R1, and output terminal of amplifier circuit 115, and forms a corresponding voltage on feedback resistor R1. Similarly, the current signal provided by current source C1 forms a current path between the output terminal of amplifier circuit 115, feedback resistor R2, input terminal of amplifier circuit 115, connection point Z2, and transistor switch P2, and forms a corresponding voltage on feedback resistor R2. Based on the voltages formed by the digital data signal D on feedback resistors R1 and R2, current units 111, 112, 113, and 114 generate the corresponding analog data signal A (i.e., V0 in the diagram) at the output terminal of amplifier circuit 115.

[0019] Similarly, in the second cycle, the input terminals I1 of current units 111, 112, 113, and 114 can each receive one bit of the reset signal RZ, and the input terminal I2 receives the inverted signal of the bit received by input terminal I1. The transistor switches P1, P2, N1, and N2 of current units 111, 112, 113, and 114 are turned on or off according to whether the bit of the reset signal RZ is "1" or "0", so as to form the aforementioned current path, so that the current signal provided by current sources C1 and C2 flows through feedback resistors R1 and R2, and the output terminal of amplifier circuit 115 generates the corresponding analog data signal A (i.e., V0 in the diagram), which will not be described in detail here.

[0020] In some embodiments, taking a 1-bit digital signal as an example, the compensation circuit 12 may include a current unit, and the current unit of the compensation circuit 12 may have the same circuit structure as each current unit 111, 112, 113, 114. Figure 2As shown, the compensation circuit 12 may include input terminals I3 and I4, current sources C3 and C4, transistor switches P3 and P4, and transistor switches N3 and N4. Current source C3 is coupled to the source terminals of transistor switches P3 and P4; current source C4 is coupled to the source terminals of transistor switches N3 and N4. The drain terminal of transistor switch P3 is coupled to the drain terminal of transistor switch N3, and the drain terminal of transistor switch P4 is coupled to the drain terminal of transistor switch N4. The connection point Z3 between transistor switches P3 and N3 is coupled to one input terminal of amplifier circuit 115, and the connection point Z4 between transistor switches P4 and N4 is coupled to the other input terminal of amplifier circuit 115.

[0021] In the second cycle, the input terminal I3 of the compensation circuit 12 can receive the compensation input signal S1, for example, the compensation input signal S1 of "1", and the input terminal I4 receives the inverted signal of the compensation input signal S1, for example, "0". The transistor switches P4 and N3 are in the on state, and the transistor switches P3 and N4 are in the off state. The current signal provided by the current source C4 forms a compensation current S21 in the current path between the transistor switch N3, the connection point Z3, the input terminal of the amplifier circuit 115, the feedback resistor R1 and the output terminal of the amplifier circuit 115. The compensation current S21 forms a corresponding voltage on the feedback resistor R1. In addition, the current signal provided by the current source C3 forms a compensation current S22 in the current path between the output terminal of the amplifier circuit 115, the feedback resistor R2, the input terminal of the amplifier circuit 115, the connection point Z2 and the transistor switch P4. The compensation current S22 forms a corresponding voltage on the feedback resistor R2 (i.e., the compensation voltage for compensating the first reset level L1). Based on the total voltage formed on the feedback resistors R1 and R2 by the digital compensation input signal S1, the output of the amplifier circuit 115 generates an analog data signal A (i.e., V0 in the diagram) at the second reset level L2 in the second cycle.

[0022] In some embodiments, taking the current unit of the aforementioned compensation circuit 12 and each of the current units 111, 112, 113, and 114 having the same circuit structure as an example, in the first cycle, the compensation circuit 12 can perform digital-to-analog conversion according to one bit of the digital data signal D, so that the output terminal of the amplifier circuit 115 generates the corresponding analog data signal A. More specifically, as... Figure 4As shown, the input terminal I3 of the compensation circuit 12 can receive one bit of the digital data signal D, and generate data currents D11 and D12 flowing through the feedback resistors R1 and R2 in the first cycle to form a voltage across the feedback resistors R1 and R2; and the input terminal I1 of the current units 111, 112, 113, and 114 of the digital-to-analog converter circuit 11 receives the other bits of the digital data signal D to form the current paths of the aforementioned data currents D9 and D10 flowing through the feedback resistors R1 and R2, so that the digital-to-analog converter circuit 11 generates an analog data signal A based on the total voltage formed across the feedback resistors R1 and R2. Wherein, as Figure 4 As shown, data currents D9 and D10 are the currents flowing into the connection point Z1 of current units 111, 112, 113, and 114 and the currents flowing out of the connection point Z2 of current units 111, 112, 113, and 114, respectively. Data currents D11 and D12 are the currents flowing into the connection point Z3 of the compensation circuit 12 and the currents flowing out of the connection point Z4 of the compensation circuit 12, respectively.

[0023] For example, such as Figure 5 As shown, taking three digital data signals D[1], D[2], and D[3] using data weighted averaging (DWA) technology, and with each signal having five bits, D[1], D[2], and D[3] can be 5'b10001, 5'b01101, and 5'b11011 respectively. Please refer to the combined results. Figures 2 to 4 In the first cycle, the input terminal I1 of the current units 111, 112, 113, and 114 receives the first, second, third, and fourth bits of the digital data signal D[1], which are “1”, “0”, “0”, and “0” respectively. The input terminal I3 of the compensation circuit 12 receives the fifth bit (i.e., “1”) of the digital data signal D[1]. The current units 111, 112, 113, and 114 and the compensation circuit 12 generate data currents D9, D10, D11, and D12 that flow through the feedback resistors R1 and R2. Meanwhile, the input terminals I2 of current units 111, 112, 113, and 114 receive the inverted signal of the digital data signal D[1]. That is, the input terminals I2 of current units 111, 112, 113, and 114 and the input terminal I4 of compensation circuit 12 receive “0”, “1”, “1”, “1”, and “0” respectively. The data currents D9, D10, D11, and D12 generated by current units 111, 112, 113, and 114 and compensation circuit 12 flow through feedback resistors R1 and R2. Based on the total voltage generated by the five voltages of the digital data signal D[1] on the feedback resistors R1 and R2, the output terminal of amplifier circuit 115 generates the analog data signal A corresponding to the digital data signal D[1].

[0024] In the second first cycle, the input terminal I1 of the current units 111, 112, 113, and 114 receives the first, second, third, and fourth bits of the digital data signal D[2], which are “0”, “1”, “1”, and “0” respectively. The input terminal I3 of the compensation circuit 12 receives the fifth bit of the digital data signal D[2], which is “1”. The current units 111, 112, 113, and 114 and the compensation circuit 12 generate data currents D9, D10, D11, and D12, which flow through the feedback resistors R1 and R2. Meanwhile, the input terminals I2 of current units 111, 112, 113, and 114 receive the inverted signal of the digital data signal D[1]. That is, the input terminals I2 of current units 111, 112, 113, and 114 and the input terminal I4 of compensation circuit 12 receive “1”, “0”, “0”, “1”, and “0” respectively. The data currents D9, D10, D11, and D12 generated by current units 111, 112, 113, and 114 and compensation circuit 12 flow through feedback resistors R1 and R2. Based on the total voltage generated by the five digital data signals D[2] on the feedback resistors R1 and R2, the output terminal of amplifier circuit 115 generates the analog data signal A corresponding to the digital data signal D[2]. In the third first cycle, the input terminal I1 of the current units 111, 112, 113, and 114 receives the first, second, third, and fourth bits of the digital data signal D[3], which are “1”, “1”, “0”, and “1” respectively. The input terminal I3 of the compensation circuit 12 receives the fifth bit of the digital data signal D[3], which is “1”. The current units 111, 112, 113, and 114 and the compensation circuit 12 generate data currents D9, D10, D11, and D12, which flow through the feedback resistors R1 and R2. Meanwhile, the input terminals I2 of current units 111, 112, 113, and 114 receive the inverted signal of the digital data signal D[1]. That is, the input terminals I2 of current units 111, 112, 113, and 114 and the input terminal I4 of compensation circuit 12 receive “0”, “0”, “1”, “0”, and “0” respectively. The data currents D9, D10, D11, and D12 generated by current units 111, 112, 113, 114 and compensation circuit 12 flow through feedback resistors R1 and R2. Based on the total voltage generated by the five voltages of the digital data signal D[3] on the feedback resistors R1 and R2, the output terminal of amplifier circuit 115 generates the analog data signal A corresponding to the digital data signal D[3]. Based on this, with the addition of compensation circuit 12, the digital-to-analog converter 1 can handle a large number of digital-to-analog conversions.

[0025] In some embodiments, the compensation input signal S1 can be combined with the reset signal RZ corresponding to the first reset level L1 to generate another reset signal RZ corresponding to the second reset level L2, such that the reset signal RZ corresponding to the second reset level L2 and the digital data signal D may have the same number of bits, and the reset signal RZ may include two reset signals RZA and RZB with the same number of bits (hereinafter referred to as the first reset signal RZA and the second reset signal RZB). The compensation circuit 12 can generate compensation currents S21 and S22 successively according to one of the bits of the reset signals RZA and RZB, and the digital-to-analog conversion circuit 11 performs two zero-reset conversions (hereinafter referred to as the first zero-reset conversion and the second zero-reset conversion) according to the other bits of the reset signals RZA and RZB in the second cycle.

[0026] In detail, such as Figure 5 As shown, the digital data signals D[1], D[2], and D[3] and the reset signals RZA and RZB corresponding to the second reset level L2 each have five bits. The reset signals RZA and RZB can be 5'b11001 and 5'b00111, respectively. The first four bits of the reset signals RZA and RZB correspond to the first reset level L1. That is, the first four bits of the first reset signal RZA and the compensation input signal S1, which is "1", can be combined into another first reset signal RZA with five bits, so that the other first reset signal RZA corresponds to the first reset level L1. The first four bits of the second reset signal RZB and the compensation input signal S1, which is "1", can be combined into another second reset signal RZB with five bits, so that the other second reset signal RZB corresponds to the second reset level L2. Please refer to the combined reference. Figure 2 , Figure 3 , Figure 5During the first zero-reset transition in the second cycle, the input terminals I1 of current units 111, 112, 113, and 114 receive the first, second, third, and fourth bits of the first reset signal RZA, which are "1", "1", "0", and "0" respectively (i.e., current units 111, 112, 113, and 114 perform the first zero-reset transition according to the corresponding first reset level L1 to reset the analog data signal A). This causes voltages corresponding to the four bits of the first reset signal RZA (i.e., the first reset level L1) to be formed on the feedback resistors R1 and R2. Furthermore, the input terminal I3 of the compensation circuit 12 receives the fifth bit of the first reset signal RZA, which is "1", and generates compensation currents S21 and S22. This further causes voltages corresponding to the fifth bit of the first reset signal RZA (i.e., the compensation voltage) to be formed on the feedback resistors R1 and R2, so that the output terminal of the amplifier circuit 115 generates an analog data signal at the second reset level L2. A; In the second zero-reset transition in the second cycle, the input terminal I1 of the current units 111, 112, 113, and 114 receives the first, second, third, and fourth bits of the second reset signal RZB, which are “0”, “0”, “1”, and “1” respectively (i.e., the current units 111, 112, 113, and 114 perform the second zero-reset transition according to the corresponding first reset level L1 to reset the analog data signal A), so that the feedback resistors R1 and R2 form voltages corresponding to the four bits of the second reset signal RZB (i.e., the first reset level L1). The input terminal I3 of the compensation circuit 12 receives the fifth bit of the second reset signal RZB, which is “1”, and generates compensation currents S21 and S22, so that the feedback resistors R1 and R2 further form voltages corresponding to the fifth bit of the second reset signal RZB (i.e., compensation voltage), so that the output terminal of the amplifier circuit 115 generates the analog data signal A at the second reset level L2.

[0027] In some embodiments, the bits received by current units 111, 112, 113, and 114 in the reset signals RZA and RZB are inverted (i.e., the reset signals corresponding to the first reset level L1 are inverted). Taking the aforementioned reset signals RZA and RZB as 5'b11001 and 5'b00111 respectively as examples, the first to fourth bits of the first reset signal RZA and the first to fourth bits of the second reset signal RZB are inverted. Furthermore, by Figure 4 It can be seen that the fifth bit of the reset signals RZA and RZB, as well as the fifth bit of the digital data signals D[1], D[2], and D[3], are all "1", and the compensation currents S21 and S22 and the data currents D11 and D12 can all form additional compensation voltages on the feedback resistors R1 and R2. In some embodiments, the fifth bit of the reset signals RZA and RZB, as well as the fifth bit of the digital data signals D[1], D[2], and D[3], are all "0".

[0028] In some embodiments, the number of bits in the compensation input signal S1 may be equal to or greater than two. Taking a compensation input signal S1 with two bits as an example, the compensation input signal S1 may exist in the reset signals RZA and RZB corresponding to the second reset level L2. For example, in the first reset signal RZA, the compensation input signal S1 may be 2'b11, and in the second reset signal RZB, the compensation input signal S1 may be 2'b01. Thus, the compensation circuit 12 may include two current units, which may respectively receive 2'b11 and 2'b01, and the two current units of the compensation circuit 12 may respectively generate corresponding compensation currents S21 and S22 in the second cycle. Furthermore, as mentioned earlier, the compensation input signal S1 can exist in the reset signals RZA and RZB. The two-bit compensation input signal S1 makes the reset signals RZA and RZB corresponding to the second reset level L2 six bits each. The compensation input signal S1 is the fifth and sixth bits of the reset signals RZA and RZB, that is, the reset signals RZA and RZB can be 2'b110011 and 2'b001101 respectively. Based on this, the fifth bit of the first reset signal RZA and the fifth bit of the second reset signal RZB are "1" and "0" respectively. The fifth bit of the first reset signal RZA and the fifth bit of the second reset signal RZB are inverted. Based on the inverted fifth bit, the compensation current generated by the two current units of the compensation circuit 12 can be regarded as canceling each other out. The sixth bit of both reset signals RZA and RZB is "1". Based on the sixth bit being "1", the compensation current generated by the two current units of the compensation circuit 12 will not cancel each other out. Therefore, the compensation input signal S1 of 2'b11 and 2'b01 can be regarded as logic "1", that is, the compensation input signal S1 can be logic "1".

[0029] In some embodiments, Figure 2 , Figure 4 The current switches in the current units 111, 112, 113, and 114 of the compensation circuit 12 and the digital-to-analog converter circuit 11 shown in the example are implemented using complementary N-type transistors and P-type transistors. However, the present invention is not limited to this, and the current switches in the current units 111, 112, 113, and 114 of the compensation circuit 12 and the digital-to-analog converter circuit 11 can also be implemented using NMOS transistors, such as... Figure 6 As shown, it can be implemented using a PMOS transistor.

[0030] In some embodiments, the magnitude of the current provided by current sources C1, C2, C3, and C4, and the resistance values ​​of feedback resistors R1 and R2, can be adjusted according to the magnitude of the required compensation voltage. The compensation voltage is proportional to the harmonic frequency and the reference voltage used by the digital-to-analog converter 1 during digital-to-analog conversion, and inversely proportional to the signal sampling frequency during digital-to-analog conversion. Based on the aforementioned harmonic frequency, reference voltage, and signal sampling frequency, the designer of the digital-to-analog converter 1 can calculate the compensation voltage, and then design the magnitude of the current provided by the corresponding current sources C1, C2, C3, and C4, and the resistance values ​​of the feedback resistors R1 and R2 accordingly. For example, in the field of audio products, the designer can design the compensation voltage based on the harmonic frequency of 20kHz, the highest audible audio value.

[0031] Please refer to Figure 7A and Figure 7B , Figure 7A and Figure 7B This is a flowchart illustrating a digital-to-analog conversion method according to one embodiment. Please refer to... Figures 2 to 5 Reading. Digital-to-analog conversion methods include:

[0032] Step S60: Convert a digital data signal into an analog data signal in a first cycle according to a clock signal;

[0033] Step S62: Reset the analog data signal according to a reset signal corresponding to a first reset level in a second cycle based on the clock signal; and

[0034] Step S64: In the second cycle, the voltage level of the analog data signal after the reset is compensated according to a second reset level, so that the voltage level of the analog data signal after the reset is at the second reset level.

[0035] The second reset level is higher or lower than the first reset level.

[0036] In some embodiments, step S64, which involves compensating the voltage level of the reset analog data signal according to the second reset level, is performed by a compensation circuit. The digital-to-analog conversion method further includes:

[0037] Step S61A: The compensation circuit also receives a portion of the digital data signal during the first cycle; and

[0038] Step S61B: The compensation circuit performs digital-to-analog conversion in the first cycle to convert the analog data signal of the bit generation part.

[0039] In some embodiments, step S60, converting the digital data signal into the analog data signal, includes: transmitting a current signal through a feedback resistor of an amplifier circuit according to the digital data signal to generate the analog data signal (step S60'). Step S64, compensating for the voltage level of the reset analog data signal according to the second reset level, includes: the compensation circuit generating a compensation current through the feedback resistor according to the second reset level in the second cycle, causing the output of the amplifier circuit to generate the analog data signal at the second reset level (step S64').

[0040] In some embodiments, step S64' of generating the compensation current includes:

[0041] Step S640: Provide the compensation current in the second cycle using a current source; and

[0042] Step S642: A transistor switch is turned on in the second cycle according to the second reset level to deliver the compensation current to the feedback resistor.

[0043] In some embodiments, the digital-to-analog conversion method further includes:

[0044] Step S66: Provide a data current using the current source during the first cycle; and

[0045] Step S68: The transistor switch is turned on according to a portion of the digital data signal in the first cycle, so as to transmit the data current in the first cycle and flow through the feedback resistor, so as to convert the analog data signal of the portion of the bit generation portion.

[0046] In some embodiments, the step of turning on the transistor switch in step S642 according to the second reset level in the second cycle includes turning on the transistor switch according to a compensation input signal in the second cycle. The compensation input signal is combined with the reset signal to form another reset signal corresponding to the second reset level. In some embodiments, the logic level of the compensation input signal is 1 or 0.

[0047] In some embodiments, the reset signal includes a first reset signal and a second reset signal that are inversely related and have the same number of bits. The compensation input signal and the first reset signal are combined to form another first reset signal corresponding to the second reset level, and the compensation input signal and the second reset signal are combined to form another second reset signal corresponding to the second reset level.

[0048] In some embodiments, step S64, which involves compensating the voltage level of the reset analog data signal according to the second reset level, includes:

[0049] Step S646: In the second cycle, a compensation current is generated according to the second reset level; and

[0050] Step S648: Generate a compensation voltage based on the compensation current, so that the voltage level of the reset analog data signal is at the second reset level.

[0051] In some embodiments, step S64, which involves compensating the voltage level of the reset analog data signal according to the second reset level, is performed by a compensation circuit. The digital-to-analog conversion method further includes: the compensation circuit generating a data current based on a portion of the digital data signal during the first cycle to generate a portion of the analog data signal.

[0052] In summary, according to some embodiments of the digital-to-analog converter of the present invention, the digital-to-analog converter circuit generates a reset analog data signal based on the compensation voltage corresponding to the compensation current when performing a zero-reset conversion, so that the analog data signal is at a higher reset level, thereby causing the analog data signal A to have an offset voltage. When the digital-to-analog converter is applied to audio products, the harmonics generated by the digital-to-analog converter with a higher offset voltage occur in the audio range that is inaudible to the human ear (e.g., the audio range greater than 20KHz), thus avoiding the problem that the human ear hears the sound output when the audio product does not receive audio.

[0053] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

[0054] Explanation of reference numerals in the attached figures:

[0055] 1: Digital-to-Analog Converter

[0056] 11: Digital-to-Analog Conversion Circuit

[0057] 111: Current Unit

[0058] 112: Current Unit

[0059] 113: Current Unit

[0060] 114: Current Unit

[0061] 115: Amplifier Circuit

[0062] 12: Compensation Circuit

[0063] 2: Signal generating device

[0064] A: Analog data signal

[0065] CLK: Clock signal

[0066] D: Digital data signal

[0067] D9: Data Current

[0068] D10: Data Current

[0069] D11: Data Current

[0070] D12: Data Current

[0071] R1, R2: Feedback resistors

[0072] RZ: Reset signal

[0073] RZA: First reset signal

[0074] RZB: Second reset signal

[0075] S1: Compensation input signal

[0076] S2: Compensation output signal

[0077] S21, S22: Compensation current

[0078] L1: First reset level

[0079] L2: Second reset level

[0080] Z1, Z2, Z3, Z4: Connection points

[0081] I1, I2, I3, I4: Input terminals

[0082] C1, C2, C3, C4: Current sources

[0083] P1, P2, P3, P4: Transistor switches

[0084] N1, N2, N3, N4: Transistor switches

Claims

1. A digital-to-analog converter, comprising: A digital-to-analog converter circuit is used to receive a clock signal, a digital data signal, and a reset signal corresponding to a first reset level. The digital-to-analog converter circuit is used to convert the digital data signal into an analog data signal according to the clock signal in a first cycle, and to reset the analog data signal according to the clock signal in a second cycle according to the first reset level. and A compensation circuit, coupled to the digital-to-analog converter circuit, is used to compensate the voltage level of the reset analog data signal according to a second reset level in the second cycle, such that the voltage level of the reset analog data signal is at the second reset level, wherein the second reset level is higher or lower than the first reset level, and the analog data signal at the second reset level has an offset voltage; wherein a compensation current is generated in the second cycle, the compensation current flowing through a feedback resistor of the digital-to-analog converter circuit to compensate the voltage level of the reset analog data signal.

2. The digital-to-analog converter according to claim 1, characterized in that, The compensation circuit also receives a portion of the digital data signal during the first cycle, and performs digital-to-analog conversion during the first cycle to convert the portion of the digital data signal into a portion of the analog data signal.

3. The digital-to-analog converter according to claim 1, characterized in that, The digital-to-analog converter circuit includes: An amplifier circuit includes an input terminal and an output terminal; The feedback resistor is coupled between the input terminal and the output terminal; A current source for providing a current signal; and A transistor switch, coupled to the current source, is used to turn on or off according to the digital data signal, and when on, transmits the current signal through the feedback resistor, so that the output terminal generates the analog data signal; The compensation circuit causes the output terminal to generate the analog data signal at the second reset level.

4. The digital-to-analog converter according to claim 3, characterized in that, The compensation circuit includes: Another current source is used to provide the compensation current during the second cycle; and Another transistor switch, coupled to the other current source, is turned on in the second cycle to transmit the compensation current and flow through the feedback resistor in the second cycle, causing the output to generate the analog data signal at the second reset level.

5. The digital-to-analog converter according to claim 4, characterized in that, The other current source also provides a data current in the first cycle, and the other transistor switch is also turned on in the first cycle according to a portion of the digital data signal to transmit the data current and flow through the feedback resistor in the first cycle, so that the compensation circuit performs digital-to-analog conversion in the first cycle to convert the analog data signal of the portion of the bit generation portion.

6. The digital-to-analog converter according to claim 4, characterized in that, The other transistor switch is turned on in the second cycle according to a compensation input signal, which is combined with the reset signal to form another reset signal corresponding to the second reset level.

7. The digital-to-analog converter according to claim 6, characterized in that, The logic level of the compensation input signal is 1.

8. The digital-to-analog converter according to claim 6, characterized in that, The reset signal includes a first reset signal and a second reset signal that are inverted and have the same number of bits. The compensation input signal is combined with the first reset signal to form another first reset signal corresponding to the second reset level, and the compensation input signal is combined with the second reset signal to form another second reset signal corresponding to the second reset level.

9. The digital-to-analog converter according to claim 1, characterized in that, The compensation circuit includes: A current source for providing the compensation current during the second cycle; and A transistor switch, coupled to the current source, is used to turn on according to a compensation input signal in the second cycle, and when turned on, transmits the compensation current to the digital-to-analog converter circuit, so that the digital-to-analog converter circuit generates a compensation voltage, so that the voltage level of the reset analog data signal is at the second reset level; The current source also provides a data current in the first cycle, and the compensation circuit is also turned on according to a portion of the digital data signal in the first cycle, and transmits the data current to the digital-to-analog converter circuit when it is turned on, so that the digital-to-analog converter circuit generates the analog data signal.

10. A digital-to-analog conversion method, comprising: A digital data signal is converted into an analog data signal in a first cycle based on a clock signal; The analog data signal is reset according to a reset signal corresponding to a first reset level in a second cycle based on the clock signal; and During the second cycle, the voltage level of the reset analog data signal is compensated according to a second reset level, so that the voltage level of the reset analog data signal is at the second reset level; Wherein, the second reset level is higher or lower than the first reset level, and the analog data signal at the second reset level has an offset voltage; wherein, a compensation current is generated in the second cycle, the compensation current flowing through a feedback resistor of the digital-to-analog converter circuit to compensate for the voltage level of the reset analog data signal.

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