High-speed dual-channel data real-time acquisition and accumulation circuit and method

Abstract

The application discloses a high-speed double-channel data real-time collection and accumulation circuit and method, comprising a double-channel analog-to-digital converter (ADC), a field programmable gate array (FPGA), a trigger signal, a clock generation unit and an Ethernet unit. The real-time accumulation method is realized in the FPGA, comprising a clock control module, a JESD204B data analysis module, an accumulation control module, a double-port RAM, an adder and a communication module. The double-channel data real-time collection and accumulation method is completely realized by using a pipeline, and the accumulation operation is performed at the same time of data collection, thereby shortening the overall processing time. The application uses a ping-pong storage scheme, realizes parallel execution of data collection and accumulation and processing result sending, and the circuit and method provided by the application can realize real-time, complete non-loss data collection, accumulation and data transmission.

Description

Technical Field

[0001] This invention relates to a high-speed dual-channel real-time data acquisition and accumulation circuit and method, specifically to a high-speed dual-channel real-time data accumulation circuit and method based on FPGA. Background Technology

[0002] The task of a data acquisition circuit is to acquire various types of analog signals, convert them into digital signals, and then input them into a processor for data processing to obtain specific data results. A high-speed data acquisition card refers to a data acquisition card with a high sampling rate, typically greater than 100 MS / s. Due to the excellent timing characteristics and parallel processing capabilities of FPGAs, high-speed data acquisition cards generally use FPGAs as processors, with FPGA processing frequencies typically reaching hundreds of MHz.

[0003] High-speed data acquisition circuits are widely used in various fields such as high-end instruments, scientific research, laser communication, and radar detection. For some applications, high-speed data acquisition cards also need to have an accumulation function to eliminate the influence of significant environmental or system noise.

[0004] Currently, there are two main accumulation schemes for high-speed data acquisition circuits: The first is to first acquire data, temporarily store the acquisition results in RAM, perform data accumulation processing after acquisition is complete, and finally send the data. This serial processing method is not only slow but also results in the loss of a large amount of data. The second method performs data accumulation processing simultaneously with data acquisition. However, accumulating a single data point often requires multiple cycles of reading from the buffer, accumulation, and writing back to the buffer, resulting in a complex structure and requiring either a very high processing clock speed or a low data sampling rate. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-speed dual-channel real-time data acquisition and accumulation circuit and method, which enables real-time data acquisition, accumulation and transmission without data loss for dual-channel signals with a sampling rate of 1GS / s.

[0006] The technical solution adopted in this invention is: a high-speed dual-channel real-time data acquisition and accumulation circuit, comprising: a dual-channel ADC, an FPGA, a trigger signal, a clock generation unit, and an Ethernet unit;

[0007] The clock generation unit provides the required clock source to the dual-channel ADC and FPGA; the dual-channel ADC is used to complete the analog-to-digital conversion of the dual-channel signal and transmit the conversion result to the FPGA; the trigger signal is connected to the FPGA to trigger a round of FPGA receiving ADC signal and accumulation processing; the FPGA performs real-time accumulation of the signal and sends the accumulation result to the Ethernet unit to realize network data output.

[0008] Preferably, the FPGA includes a clock control module, a data parsing module, an accumulation control module, a dual-port RAM, an adder, and a communication module;

[0009] The clock control module is used to configure the parameters of the clock generation unit according to the communication format of the clock generation unit;

[0010] The data parsing module is used to receive the analog-to-digital conversion results of the dual-channel ADC and output the core clock core_clk and the ADC data obtained from parsing the two channels.

[0011] The accumulation control module is used to control the adder to accumulate the parsed ADC data according to the configuration information, and store the accumulation result in RAM;

[0012] The dual-port RAM is used to cache intermediate accumulation values ​​and accumulation results;

[0013] The adder is used to add the ADC data and the accumulated intermediate value read from RAM;

[0014] The communication module is used to encapsulate the accumulated results cached in the dual-port RAM into an Ethernet communication format and send it to the Ethernet unit; at the same time, it receives configuration information from the host computer, including the sampling length N and the number of accumulations accu_num.

[0015] Preferably, the dual-channel ADC uses a JESD204B interface to output the analog-to-digital conversion result. The data parsing module is a JESD204B data parsing module. The core clock core_clk output by the JESD204B data parsing module has a frequency of 1 / L of the dual-channel ADC sampling clock. The bit width of the L ADC data parsed from each channel is the same as the number of bits of the dual-channel ADC. L is an integer greater than 1, and its specific value is related to the hardware implementation of the FPGA, AD, etc.

[0016] Preferably, the phases of the L ADC data parsed by each channel of the JESD204B data parsing module differ sequentially by (360 / L)°.

[0017] Preferably, the L ADC data obtained from each channel are accumulated by one adder, and the parameters of the L adders are exactly the same.

[0018] Preferably, the bit width of the first input terminal of the adder is w_accu bit, the bit width of the second input terminal is the same as the bit width w_adc of the dual-channel ADC, the bit width of the output terminal is the same as the bit width of the first input terminal, and it has a bypass input terminal; when the bypass input terminal is enabled, the adder directly outputs the value of the second input terminal;

[0019] The bit width w_accu bit of the first input terminal of the adder must meet the following conditions:

[0020] w_accu≥ceil[log2(accu_num max )]+w_adc

[0021] Where ceil represents rounding up, and accu_num max Set an upper limit for the number of times the sum can be accumulated.

[0022] Preferably, each channel has two dual-port RAMs, denoted as RAM A and RAM B, with identical parameters for alternating storage and transmission; the data width of the dual-port RAM is w_ram bit.

[0023] The dual-port RAM bit width w_ram must meet the following condition: w_ram = w_accu * L.

[0024] A high-speed dual-channel real-time data acquisition and accumulation method includes:

[0025] (1) Receive configuration information sent by the host computer, including sampling length and number of accumulations;

[0026] (2) A round of signal acquisition and accumulation calculation begins on the rising edge of the trigger signal; if it is the first round of accumulation calculation, the bypass function of the adder is enabled; the specific process is as follows:

[0027] (2.1) At the rising edge of the core clock core_clk, the FPGA inputs the L ADC data obtained from the parsing of one channel to the second input of the L adders respectively, and the sampling point counter increments by L;

[0028] At the rising edge of the core clock core_clk, the FPGA reads a w_ram bit of data from the current read address of the dual-port RAM A (or RAM B) of this channel, divides the data into L equal parts, and inputs them sequentially to the first input of the L adders. The current read address value of the current dual-port RAM is incremented by 1.

[0029] At the rising edge of the core clock core_clk, the FPGA concatenates the outputs of the L adders into w_rambit, writes it back to the current write address of the corresponding dual-port RAM, and increments the current write address value of the dual-port RAM by 1.

[0030] (2.2) Determine the number of sampling points. If the value of the sampling point counter is equal to the sampling length, proceed to step (2.3); otherwise, return to step (2.1).

[0031] (2.3) Increment the repetition count counter by 1;

[0032] (2.4) If the value of the repetition counter is equal to the accumulated count, then proceed to step (2.5); otherwise, return to step (2).

[0033] (2.5) If the above accumulation operation is performed on RAM A, then the subsequent accumulation operation is performed on RAM B, and the data in RAM A is sent to the host computer via Ethernet; if the above accumulation operation is performed on RAM B, then the subsequent accumulation operation is performed on RAM A, and the data in RAM B is sent to the host computer via Ethernet.

[0034] (3) Repeat step (2).

[0035] Preferably, the driving operation of each core clock core_clk in step (2.1) is implemented using pipelined implementation.

[0036] Preferably, the dual-channel ADC data uses the same processing steps, the read address of the dual-port RAM of the two channels is uniformly controlled, the write address of the dual-port RAM of the two channels is uniformly controlled, and the bypass input of the adder of the two channels is uniformly controlled.

[0037] Preferably, in step (2.1), at the rising edge of the core clock core_clk, the FPGA concatenates the output results of the L adders into a w_ram bit. Specifically, the outputs of the adders are concatenated to the corresponding bits of the w_ram bit result in the same order as the inputs to the first inputs of the L adders.

[0038] The beneficial effects of this invention compared to the prior art are:

[0039] (1) The dual-port RAM of the present invention is implemented using the block RAM inside the FPGA, which can perform write and read operations simultaneously, and the write and read operations are fast, thus shortening the overall processing time.

[0040] (2) The present invention uses a pipeline to realize the accumulation operation, which can perform the accumulation operation at the same time as data acquisition, that is, real-time accumulation, which shortens the overall processing time.

[0041] (3) The present invention uses a ping-pong storage scheme, using dual-port RAM A and dual-port RAM B with identical parameters to alternately perform accumulation and data transmission operations. The two are executed in parallel without data conflict, thereby realizing data acquisition and accumulation without data loss and fast data transmission.

[0042] (4) The present invention decomposes the high-speed ADC data conversion result into 4 low-speed ADC data for parallel processing, which improves the processing bandwidth and is more conducive to timing optimization. Attached Figure Description

[0043] Figure 1 This is a block diagram of the high-speed dual-channel real-time data acquisition and accumulation circuit of the present invention;

[0044] Figure 2 A timing diagram of the data output by the JESD204B data parsing module;

[0045] Figure 3 This is a flowchart of the high-speed dual-channel real-time data acquisition and accumulation method of the present invention;

[0046] Figure 4 This is a timing diagram of the first round of data acquisition and accumulation under a certain configuration of the present invention;

[0047] Figure 5 This is a timing diagram of the second round of data acquisition and accumulation under a certain configuration of the present invention;

[0048] Figure 6 This is a timing diagram of the last round of data acquisition and accumulation under a certain configuration of the present invention. Detailed Implementation

[0049] The present invention will now be described in more detail with reference to the accompanying drawings and FPGA simulation timing diagrams. The illustrative description below is provided to facilitate understanding of the invention by those skilled in the art; however, it should be understood that the invention is not limited to the specific embodiments described.

[0050] like Figure 1 As shown, this invention proposes a high-speed dual-channel real-time data acquisition and accumulation circuit, including: a dual-channel ADC, an FPGA, a trigger signal, a clock generation unit, and an Ethernet unit.

[0051] The dual-channel ADC is used to complete the analog-to-digital conversion of dual-channel signals and transmit the conversion results to the FPGA; the trigger signal is connected to the FPGA to trigger a round of FPGA receiving ADC signals and accumulation processing; the FPGA performs real-time accumulation of the signals and sends the accumulation results to the Ethernet unit to realize network data output; the clock generation unit is used to provide the required co-current clock for the ADC and FPGA; the Ethernet unit is used to implement Ethernet physical layer functions.

[0052] The dual-channel ADC has a sampling rate of 1 GS / s and a bit depth of 14 bits, and outputs the analog-to-digital conversion results using the JESD204B interface. The specific parameters of the JESD204B interface are: number of converters M = 2, number of links L = 4, number of bytes per frame F = 1, number of frames K = 32, and bit depth N' = 16 after each sample is encapsulated.

[0053] The FPGA includes a clock control module, a JESD204B data parsing module, an accumulation control module, a dual-port RAM, an adder, and a communication module.

[0054] The clock control module configures the parameters of the clock generation unit according to the communication format of the clock generation unit.

[0055] The JESD204B data parsing module receives the analog-to-digital conversion results from the ADC, uses the JESD204B IP core to perform data parsing, and outputs the core clock core_clk and four ADC data points (ch1_data0, ch1_data1, ch1_data2, ch1_data3) obtained from channel 1 parsing, and four ADC data points (ch2_data0, ch2_data1, ch2_data2, ch2_data3) obtained from channel 2 parsing. The bit width of the four ADC data points parsed from each channel is 14 bits.

[0056] like Figure 2 As shown, data0, data1, data2, and data3 are synchronized with the rising edge of the core clock core_clk in the FPGA. However, the actual sampling point positions are four consecutive data points synchronized with the rising edge of the ADC's device clock AD_dclk (which is also the sampling clock). Therefore, the frequency of the core clock core_clk is 1 / 4 of the ADC sampling clock. In the clock domain of the core clock core_clk, data0, data1, data2, and data3 are logically 90° out of phase.

[0057] The accumulation control module uses an adder to accumulate the parsed ADC data and stores the accumulation result in RAM. Each ADC data point has a bit width of 14 bits, and the accumulation result has a bit width of 32 bits.

[0058] The dual-port RAM is used to buffer intermediate accumulation values ​​and accumulation results. Each channel has one dual-port RAMA and one dual-port RAMB, with identical parameters, used to implement alternating storage and transmission. The data width of the dual-port RAM is 128 bits.

[0059] The adder adds the ADC data to the accumulated intermediate value read from RAM. Each channel has four adders: adder0, adder1, adder2, and adder3. All four adders have identical parameters: a 32-bit first input, a 14-bit second input, and a 32-bit output. They also have a bypass input. When the bypass input is enabled, the adder directly outputs the value from the second input.

[0060] The communication module encapsulates the accumulated results cached in RAM into an Ethernet communication format and sends it to the Ethernet unit; simultaneously, it receives configuration information from the host computer. The configuration information mainly includes: sampling length, i.e., the number of sampling points required to trigger a single collection; and accumulation count, i.e., the number of times the corresponding points of the sampled data are added together.

[0061] The clock generation unit generates the following clocks: the device clock AD_dclk and reference signal AD_sysref required by the ADC, and the device clock FPGA_dclk and reference signal FPGA_sysref required by the FPGA.

[0062] like Figure 3 As shown, based on the above-mentioned high-speed dual-channel data real-time acquisition and accumulation circuit, this invention also proposes a high-speed dual-channel data real-time acquisition and accumulation method, characterized by the following steps:

[0063] (1) Receive configuration information sent by the host computer, mainly including sampling length and number of accumulations.

[0064] (2) Start a round of signal acquisition and accumulation operation at the rising edge of the trigger signal.

[0065] (3) If it is the first round of cumulative calculation, enable the bypass function of the adder.

[0066] (4) At the rising edge of the core clock core_clk, the FPGA inputs the four data data of one channel, data0, data1, data2, and data3, to the second input terminals of the four adders, adder0, adder1, adder2, and adder3 respectively, and the sampling point counter is incremented by 4.

[0067] (5) On the rising edge of the core clock core_clk, the FPGA reads a 128-bit data from the current read address of the dual-port RAM A (or RAM B), and inputs [31:0] bits to the first input of adder0, [63:32] bits to the first input of adder1, [95:64] bits to the first input of adder2, and [127:96] bits to the first input of adder3. The current read address value of the dual-port RAM A (or RAM B) is incremented by 1.

[0068] For the first round of accumulation calculation, the bypass function of the adder is enabled. At this time, the first input terminal of each adder is silenced, which means that the ADC data is added to zero.

[0069] (6) At the rising edge of the core clock core_clk, the FPGA concatenates the output results of the four adders into a 128-bit array and writes it back to the current write address of the dual-port RAM A (or RAM B). The current write address value of the dual-port RAM A (or RAM B) is incremented by 1.

[0070] The specific concatenation method is as follows: concatenate the output of adder0 to the [31:0]th bit of the 128-bit result, concatenate the output of adder1 to the [63:32]th bit of the 128-bit result, concatenate the output of adder2 to the [95:64]th bit of the 128-bit result, and concatenate the output of adder3 to the [127:96]th bit of the 128-bit result.

[0071] (7) If the value of the sampling point counter is equal to the sampling length, then proceed to step (8); otherwise, return to step (4).

[0072] (8) Increment the repetition count counter by 1.

[0073] (9) If the value of the repetition counter is equal to the accumulated count, then proceed to step (10); otherwise, return to step (2).

[0074] (10) If the above accumulation operation is RAM A, then the subsequent accumulation operation is RAM B, and the data in RAM A is sent to the host computer via Ethernet; if the above accumulation operation is RAM B, then the subsequent accumulation operation is RAM A, and the data in RAM B is sent to the host computer via Ethernet.

[0075] (11) Repeat steps (2)-(10).

[0076] Steps (4)-(6) are implemented using pipelined methods under the drive of the core clock core_clk.

[0077] The dual-channel ADC data uses the same processing steps, the read address of the dual-port RAM of the two channels is controlled in a unified manner, the write address of the dual-port RAM of the two channels is controlled in a unified manner, and the bypass input of the adder of the two channels is controlled in a unified manner.

[0078] Example:

[0079] The sampling length N is set to 100 and the accumulation count accu_num is set to 10. Simulation is performed on an FPGA. The ADC data is set to be cleared to zero when the trigger signal is received, and incremented by 1 on the rising edge of the sampling clock AD_dclk. Therefore, during each round of sampling and accumulation, the ADC data increments exactly from 1 to 100.

[0080] With the ADC data bit width set to w_adc as 14 bits, the first input bit width of the adder w_accu as 32 bits, and L = 4, the bit width of the dual-port RAM w_ram is 128 bits.

[0081] The timing diagram for the first round of accumulation is as follows: Figure 4 As shown. When the adder bypass signal flag_bypass_adder is enabled, the first input of the adder does not receive data, and the output value of the adder is equal to the input value at the second input, i.e., the ADC data. The data written to the dual-port RAM, ram_wr_data, is equal to 1-100.

[0082] The timing diagram for the second round of accumulation is as follows: Figure 5 As shown, the adder bypass signal flag_bypass_adder is initially disabled. The first input of the adder receives read data ram_rd_data from the dual-port RAM, and the second input receives ADC data, completing the accumulation at the corresponding point. The data written to the dual-port RAM, ram_wr_data, is equal to 2-200.

[0083] The cumulative timing diagram for the 10th round (i.e., the final round) is as follows: Figure 6 As shown. The data written to the dual-port RAM, ram_wr_data, is equal to 10-1000, which is the sum of ten iterations from 1 to 100. When all sampling points have been received, the ping-pong storage conversion flag, flag_pq, is inverted. After the accumulated result is completely written to the dual-port RAM, the Ethernet transmit trigger signal, eth_send_en, is enabled.

[0084] Depend on Figures 4-6 It can be seen that the accumulation circuit and method implemented by the present invention can realize real-time data acquisition, accumulation and transmission without data loss.

[0085] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A high-speed dual-channel real-time data acquisition and accumulation circuit, characterized in that... include: Dual-channel ADC, FPGA, trigger signal, clock generation unit, and Ethernet unit; The clock generation unit provides the required co-current clock to the dual-channel ADC and the FPGA; the dual-channel ADC performs analog-to-digital conversion of the dual-channel signal and transmits the conversion result to the FPGA; the trigger signal is connected to the FPGA to trigger a round of FPGA receiving ADC signals and accumulation processing; the FPGA performs real-time accumulation of the signal and sends the accumulation result to the Ethernet unit to realize network data output; the FPGA includes a clock control module, a data parsing module, an accumulation control module, a dual-port RAM, an adder, and a communication module; The clock control module is used to configure the parameters of the clock generation unit according to the communication format of the clock generation unit; The data parsing module is used to receive the analog-to-digital conversion results of the dual-channel ADC and output the core clock core_clk and the ADC data obtained from parsing the two channels. The accumulation control module is used to control the adder to accumulate the parsed ADC data according to the configuration information, and store the accumulation result in RAM; The dual-port RAM is used to cache intermediate accumulation values ​​and accumulation results; The adder is used to add the ADC data and the accumulated intermediate value read from RAM; The communication module is used to encapsulate the accumulated results cached in the dual-port RAM into an Ethernet communication format and send it to the Ethernet unit; simultaneously, it receives configuration information from the host computer, including the sampling length. N and cumulative count accu_num The dual-channel ADC uses a JESD204B interface to output the analog-to-digital conversion result. The data parsing module is a JESD204B data parsing module, and the core clock core_clk output by the JESD204B data parsing module has a frequency that is 1 / 3 of the sampling clock of the dual-channel ADC. L Each channel is parsed to obtain L The bit width of each ADC data is the same as the bit width of a dual-channel ADC; The bit width of the first input terminal of the adder is w_accu bit, the bit width of the second input terminal and the number of bits of the dual-channel ADC w_adc Similarly, the output bit width is the same as the first input bit width, and it has a bypass input; when the bypass input is enabled, the adder directly outputs the value of the second input. The bit width of the first input terminal of the adder w_accu The bit must meet the following conditions: Here, ceil represents rounding up. Set an upper limit for the number of times the sum can be accumulated.

2. The high-speed dual-channel real-time data acquisition and accumulation circuit according to claim 1, characterized in that: The JESD204B data parsing module parses each channel's data... L The phases of the ADC data differ sequentially by (360 / L )°.

3. The high-speed dual-channel real-time data acquisition and accumulation circuit according to claim 1, characterized in that: Each channel is parsed to obtain L Each ADC data point is accumulated using a separate adder. L Each adder has exactly the same parameters.

4. The high-speed dual-channel real-time data acquisition and accumulation circuit according to claim 1, characterized in that: Each channel has two dual-port RAMs, denoted as RAM A and RAM B. The two RAMs have identical parameters and are used to implement alternating storage and transmission. The data bit width of the dual-port RAM is... w_ram bit; The dual-port RAM bit width w_ram The following conditions must be met: w_ram = w_accu L。 5. A method for real-time acquisition and accumulation of high-speed dual-channel data, characterized in that... include: (1) Receive configuration information sent by the host computer, including sampling length and number of accumulations; (2) A round of signal acquisition and accumulation calculation begins on the rising edge of the trigger signal; if it is the first round of accumulation calculation, the bypass function of the adder is enabled; the specific process is as follows: (2.1) At the rising edge of the core clock core_clk, the FPGA will analyze the data obtained from one channel. L Each ADC data is input to... L The second input of the adder is used to count the number of sample points. L ; On the rising edge of the core clock core_clk, the FPGA reads a value from the current read address of either dual-port RAM A or RAM B of that channel. w_ram The data is divided into bits and then divided into equal parts. L Enter the data in order. L The first input of the adder increments the current read address value of the dual-port RAM by 1. At the rising edge of the core clock core_clk, the FPGA will L The outputs of the adders are concatenated into w_ram The bit is written back to the current write address of the corresponding dual-port RAM, and the current write address value of the dual-port RAM is incremented by 1; (2.2) Determine the number of sampling points. If the value of the sampling point counter is equal to the sampling length, then execute step (2.3); otherwise, return to step (2.1). (2.3) Increment the repetition count counter by 1; (2.4) If the value of the repetition counter is equal to the accumulated count, then proceed to step (2.5); otherwise, return to step (2). (2.5) If the above accumulation operation is performed on RAM A, then the subsequent accumulation operation is performed on RAM B, and the data in RAM A is sent to the host computer via Ethernet; if the above accumulation operation is performed on RAM B, then the subsequent accumulation operation is performed on RAM A, and the data in RAM B is sent to the host computer via Ethernet. (3) Repeat step (2).

6. The high-speed dual-channel real-time data acquisition and accumulation method according to claim 5, characterized in that: The core clock core_clk driving operations in step (2.1) are implemented using pipelined implementation.

7. The high-speed dual-channel real-time data acquisition and accumulation method according to claim 5, characterized in that: The dual-channel ADC data uses the same processing steps, the read address of the dual-port RAM of the two channels is controlled in a unified manner, the write address of the dual-port RAM of the two channels is controlled in a unified manner, and the bypass input of the adder of the two channels is controlled in a unified manner.

8. The high-speed dual-channel real-time data acquisition and accumulation method according to claim 5, characterized in that: In step (2.1), at the rising edge of the core clock core_clk, the FPGA will... L The outputs of the adders are concatenated into w_ram bit, specifically: according to the input L The outputs of the adders are concatenated in the same order from their first inputs. w_ram The corresponding bit of the bit result.

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