Method, apparatus, and system for memory management

Abstract

The present disclosure relates to almost ready memory management. A method includes determining, via a status poll at a first interval, an indicator of an almost ready status of a set of memory cells of a memory device, determining, based on the indicator of the almost ready status, that the set of memory cells of the memory device is almost ready to complete performance of an operation on the set of memory cells of the memory device, and in response to determining that the set of memory cells of the memory device is almost ready to complete performance of the operation, performing a status poll at a second interval.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically, to almost-ready memory management. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at and retrieve data from the memory devices. SUMMARY

[0003] Aspects of the present disclosure provide a method for almost-ready memory management, wherein the method comprises; determining, via a status polling at a first interval, an indicator of an almost-ready state of a set of memory cells of a memory device; based on the indicator of the almost-ready state, determining that the set of memory cells of the memory device is almost ready to complete performance of an operation on the set of memory cells of the memory device; and in response to determining that the set of memory cells of the memory device is almost ready to complete performance of the operation, performing a status polling at a second interval.

[0004] Another aspect of the present disclosure provides an apparatus for almost-ready memory management, wherein the apparatus comprises: an almost-ready memory management component configured to: determine a current completion level of an operation on a set of memory cells of a memory device; determine that the current completion level satisfies an almost-ready threshold; in response to the determination that the current completion level satisfies the almost-ready threshold, store a value in a register associated with the set of memory cells to indicate that the set of memory cells is almost ready to complete the operation; determine, via a status polling at a first interval, the value stored in the register; and in response to the determination that the value stored in the register indicates that the set of memory cells is almost ready, perform a status polling of the register at a second interval that is shorter than the first interval.

[0005] Another aspect of the disclosure provides a system for near-ready memory management, where the system comprises: a non-volatile memory device including a plurality of memory components arranged to form a stackable cross-grid array of a plurality of blocks of NAND memory cells; and a processing device coupled to the plurality of memory components, the processing device to perform operations comprising: performing a status poll of a plurality of registers associated with the plurality of blocks of NAND memory cells at a first interval to determine respective values of the registers; determining, based on values stored in registers of the plurality of registers associated with a block of NAND memory cells, that the block of NAND memory cells is near ready to complete performance of an operation on the block of NAND memory cells; and in response to determining that the block of NAND memory cells is near ready to complete performance of the operation, performing a status poll of the registers associated with the block of NAND memory cells at a second interval. BRIEF DESCRIPTION OF DRAWINGS

[0006] The disclosure will be more fully understood from the following detailed description taken in connection with the accompanying drawings, with the various embodiments of the disclosure described in the context of a specific implementation.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the disclosure is illustrated.

[0008] Figure 2 An example controller including registers according to some embodiments of the disclosure is illustrated.

[0009] Figure 3 A flowchart corresponding to a method for near-ready memory management according to some embodiments of the disclosure is illustrated.

[0010] Figure 4 A flowchart corresponding to a method for near-ready memory management according to some embodiments of the disclosure is illustrated.

[0011] Figure 5 A block diagram of an example computer system in which embodiments of the disclosure can operate is illustrated. DETAILED DESCRIPTION

[0012] Aspects of the disclosure relate to near-ready memory management, in particular, to a memory subsystem including a near-ready memory management component. The memory subsystem can be a storage system, a storage device, a memory module, or a combination of these. An example of a memory subsystem is a storage system such as a solid state drive (SSD). The following description is made in connection with a storage system such as a SSD, but the disclosure is not limited to SSDs. Figure 1And other instances describing storage devices and memory modules. Generally, a host system may utilize a memory subsystem, which includes one or more components, such as memory devices for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0013] Memory devices can be non-volatile memory devices. An example of a non-volatile memory device is a NAND flash memory device (also known as flash memory). The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. Planes may be divided into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Hereinafter, a block refers to a unit of a memory device used to store data and may contain groups of memory cells, groups of word lines, word lines, or individual memory cells. For some memory devices, a block (hereinafter also referred to as a “memory block”) is the smallest area compared to an erasable region. Pages cannot be erased individually; only the entire block can be erased.

[0014] Each memory device may contain one or more arrays of memory cells. Depending on the cell type, one or more bits of binary information can be written into the cell, and each bit has various logical states associated with the number of bits being stored. Logical states can be represented by binary values ​​(e.g., "0" and "1") or combinations of such values. Various types of cells exist, such as single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC). For example, an SLC can store one bit of information and has two logical states.

[0015] Some NAND memory devices employ a floating gate architecture, where memory access is controlled based on the relative voltage variation between the bit line and the word line. Other examples of NAND memory devices may employ a replacement gate architecture, which may include the use of a word line layout that allows for the capture of charge corresponding to data values ​​within the memory cell based on the properties of the material used to construct the word lines.

[0016] Media management operations can be performed on a memory block. Non-limiting examples of media management operations can include error correction operations, wear leveling operations, read disturb mitigation operations, and / or garbage collection operations. Media management operations can be performed in the "foreground" (e.g., during utilization of an interface associated with a memory sub-system by a host) and / or in the "background" (e.g., when a host is not utilizing an interface associated with a memory sub-system). In this document, media management operations can alternatively be referred to as "memory management operations."

[0017] Media management operations or other types of operations can occur in response to a command. For example, a controller can issue a command to perform an operation (e.g., a read operation, a write operation, an erase operation, etc.) on a memory device. However, before the controller can issue the command to the memory device, the controller must wait for the memory device to indicate that it is ready to receive the command. For example, a ready state of the memory device can indicate that the memory device is ready to receive the command. Conversely, a not ready state of the memory device can indicate that the memory device is not ready to receive the command. For example, the memory device can have a not ready state (e.g., asserted in response to a status poll) when an operation is being performed on the memory device.

[0018] The state of a memory device can be determined by performing a status poll of the memory device. For example, a status poll can be performed by sending a read status command to the memory device. The read status command can elicit a response from the memory device, such as a response including status information stored in a register associated with the memory device. For example, the register can return a binary value, such as a "0" indicating that the memory device is not ready (i.e., busy) or can return a "1" indicating that the memory device is ready, among other possible values. For example, the register can return a "0" during an actual programming operation on the memory device, indicating that the memory device is busy.

[0019] Some approaches can perform a status poll at regular intervals (i.e., the same interval). However, there can be an amount of delay between the occurrence of a ready state of the memory device and the determination of the ready state due to polling at regular intervals. This delay can decrease memory system performance at least in part due to the memory device remaining idle (e.g., not receiving a command) during the delay.

[0020] Accordingly, some other approaches attempt to perform a status poll constantly. However, constantly performing a status poll can inherently increase overhead (e.g., bus traffic and / or computational requirements), also decreasing memory system performance. Furthermore, constantly performing a status poll can increase an amount of power consumption, increasing an amount of cost associated with operation of the memory system and / or decreasing memory system performance by limiting an amount of power available for other operations / aspects of the memory system and / or a device including the memory system.

[0021] Some other approaches attempt to estimate an operation completion time and then strive to perform a status poll only at and / or after the estimated operation completion time. However, such approaches can inaccurately estimate the operation completion time. For example, such approaches can fail to account for timing variations in operations, e.g., attributable to different types of memory devices, different memory device architectures, and / or different types of operations. As a result, such approaches can also impose a delay between a ready state of a memory device occurring and a ready state being determined by a status poll performed at / based on an inaccurate estimated operation completion time.

[0022] Latency imposed by such approaches can be undesirable, especially in critical applications and / or in applications where extremely high memory subsystem performance is expected, e.g., in applications where requirements are very high. Moreover, such degraded performance that can be exhibited in such approaches can be further exacerbated in mobile (e.g., smartphones, Internet of Things, etc.) memory deployments where, as compared to traditional computing architectures, the amount of space available to house a memory subsystem is limited.

[0023] Aspects of the present disclosure address the above and other deficiencies of previous approaches by employing a near-ready state. As used herein, a “near-ready state” generally refers to a condition where an operation involving a memory cell of a memory device is in progress (e.g., being performed) and has not yet completed, but a current completion level of the operation satisfies a threshold for near-readiness, as detailed herein. In this way, a status polling interval can be varied based on a near-ready state (whether a memory device has a near-ready state) to achieve an improved balance between bus overhead / power consumption and underutilization of a memory device (e.g., a NAND memory device). For example, as compared to approaches that perform a status poll at regular intervals / constantly and / or approaches that estimate an operation completion time, near-ready memory management can improve (e.g., reduce) any delay between a memory device becoming ready (having a ready state) and a ready state being determined by reducing a status polling interval in response to a near-ready state of the memory device. However, as compared to approaches that perform a status poll at regular intervals / constantly and / or approaches that estimate an operation completion time, near-ready memory management can also improve (e.g., reduce) an amount of bus traffic / computational overhead and / or reduce power consumption associated with status polling by performing a status poll at a first interval in response to the memory device not having a near-ready state. As a result, memory subsystem performance can be improved as compared to approaches that do not employ near-ready memory management. Embodiments herein can be applied in mobile memory deployments to further improve reliability of memory subsystems deployed in mobile computing architectures.

[0024] Accordingly, the present disclosure relates to almost-ready memory management. Almost-ready memory management can determine, via a status poll at a first interval (e.g., every 50 ps), an indicator of an almost-ready status of a set of memory cells of a memory device. Based on the indicator, almost-ready memory management can determine that the set of memory cells of the memory device is almost ready to complete performance of an operation, and in response to determining that the set of memory cells of the memory device is almost ready to complete performance of the operation, perform the status poll at a second interval (e.g., once every 1 ps). Accordingly, almost-ready status polling can reduce latency between a memory device being ready and determining a ready status by performing the status poll at the more frequent second interval when the set of memory cells is almost ready, and can still avoid unnecessary increased overhead by performing the status poll at the less frequent first interval when the memory device is not almost ready. In other words, almost-ready memory management can provide an improved balance between bus overhead / power consumption and underutilization of a memory device (e.g., a NAND memory device) as compared to approaches that do not employ almost-ready memory management.

[0025] Figure 1 An example computing system 100 including a memory sub-system 110 in accordance with some embodiments of the present disclosure is described. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination of such.

[0026] The memory sub-system 110 can be a storage device, a memory module, or a mix of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0027] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device including memory and a processing device.

[0028] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1 An example of a host system 120 coupled to one memory sub-system 110 is illustrated. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0029] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, memory controllers (e.g., SSD controllers), and storage protocol controllers (e.g., PCIe controllers, SATA controllers). The host system 120 uses the memory sub-system 110, e.g., to write data to and read data from the memory sub-system 110.

[0030] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, a Dual In-Line Memory Module (DIMM) interface (e.g., a DIMM socket interface that supports Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 through a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., memory devices 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1 A memory sub-system 110 is illustrated as an example. In general, a host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0031] Memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory devices 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0032] Some examples of non-volatile memory devices (e.g., memory devices 130) include negative- and (NAND) type flash memories and in-place write memories, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory can incorporate stackable cross-gridded data access arrays to store bits based on changes in bulk resistance. Additionally, cross-point non-volatile memories can perform in-place write operations, where a non-volatile memory cell can be programmed without first erasing the non-volatile memory cell, as compared to many flash-based memories. NAND type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0033] Each of memory devices 130, 140 can include one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLCs), can store one bit per cell. Other types of memory cells, for example, multi-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs), can store multiple bits per cell. In some embodiments, each of memory devices 130 can include one or more arrays of memory cells, such as SLCs, MLCs, TLCs, QLCs, or any combination of such arrays of memory cells. In some embodiments, a particular memory device can include an SLC portion of memory cells, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of memory devices 130 can be grouped into pages, which can refer to logical units of a memory device for storing data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0034] Although non-volatile memory components are described, e.g., non-volatile memory cells and three-dimensional cross-point arrays of NAND-type memory (e.g., 2D NAND, 3D NAND), the memory devices 130 can be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-volatile (NOR) flash memory and electrically erasable programmable read-only memory (EEPROM).

[0035] The memory sub-system controller 115 (or simply the controller 115) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, among other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0036] The memory sub-system controller 115 can include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0037] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing microcode. Although Figure 1 The example memory sub-system 110 in FIG. 1 has been illustrated as including the memory sub-system controller 115, but in another embodiment of the disclosure, the memory sub-system 110 does not include the memory sub-system controller 115 and can instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system).

[0038] In general, memory sub-system controller 115 can receive commands or operations from host system 120 and can convert the commands or operations into instructions or appropriate commands to effectuate the desired accesses to memory devices 130 and / or memory devices 140. Memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), name space) and a physical address (e.g., physical block address, physical media location, etc.) associated with memory devices 130. Memory sub-system controller 115 can further include host interface circuitry to communicate with host system 120 via a physical host interface. The host interface circuitry can convert commands received from a host system into command instructions to access memory devices 130 and / or memory devices 140 as well as convert responses associated with memory devices 130 and / or memory devices 140 into information for host system 120.

[0039] Memory sub-system 110 can also include additional circuitry or components not illustrated. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive an address from memory sub-system controller 115 and decode the address to access memory devices 130 and / or memory devices 140.

[0040] In some embodiments, memory devices 130 include a local media controller 135 that operates in conjunction with memory sub-system controller 115 to perform operations on one or more memory units of memory devices 130. An external controller (e.g., memory sub-system controller 115) can externally manage memory devices 130 (e.g., perform media management operations on memory devices 130). In some embodiments, memory devices 130 are managed memory devices that are original memory devices combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0041] Memory sub-system 110 can include a nearly-ready memory management component 113. Although Figure 1The almost-ready memory management component 113 is not shown, but in order not to clutter the figures, can include various circuitry to facilitate determining, via a status polling at a first interval (e.g., every 50 ps), an indicator of an almost-ready status of a set of memory cells of a memory device; based on the indicator, determining that the set of memory cells of the memory device is almost ready to complete performance of an operation; and in response to determining that the set of memory cells of the memory device is almost ready to complete the operation, performing a status polling at a second interval (e.g., once every 1 ps). In some embodiments, the almost-ready memory management component 113 can include special-purpose circuitry in the form of ASICs, FPGAs, state machines, and / or other logic circuitry, which can allow the almost-ready memory management component 113 to coordinate and / or perform operations to determine, via a status polling at a first interval, an indicator of an almost-ready status of a set of memory cells of a memory device (e.g., memory device 130 and / or memory device 140); based on the indicator, determine that the set of memory cells of the memory device is almost ready to complete performance of an operation; and in response to determining that the set of memory cells of the memory device is almost ready to complete the operation, perform a status polling at a second interval.

[0042] In various embodiments, the second interval is shorter than the first interval. In some embodiments, the memory sub-system controller 115 includes at least a portion of the almost-ready memory management component 113. For example, the memory sub-system controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the almost-ready memory management component 113 is part of the memory sub-system 110, an application, or an operating system.

[0043] In a non-limiting example, a device (e.g., computing system 100) can include a memory sub-system almost-ready memory management component 113, which can be referred to herein for brevity as “almost-ready memory management component” 113 or “memory management component” 113. The almost-ready memory management component 113 can reside on the memory sub-system 110. As used herein, the term “reside on” refers to something being physically located on a particular component. For example, the almost-ready memory management component 113 “resides on” the memory sub-system 110 refers to a condition in which hardware circuitry comprising the almost-ready memory management component 113 is physically located on the memory sub-system 110. The term “reside on” can be used interchangeably herein with other terms such as “deployed on” or “located on.”

[0044] The almost-ready memory management component 113 can be configured to determine an indicator of an almost-ready state of a set of memory cells of a memory device. In some embodiments, the indicator of the almost-ready state can be a value stored in a register (e.g., the register 221 described in Figure 2 The almost-ready memory management component 113 can be configured to determine an indicator of an almost-ready state of a set of memory cells of a memory device. In some embodiments, the indicator of the almost-ready state can be a value stored in a register (e.g., the register 221 described in

[0045] Similarly, the almost-ready memory management component 113 can be configured to perform a status poll at a second interval, e.g., a second interval that is shorter than the first interval, as detailed herein. For example, the almost-ready memory management component 113 can be configured to perform a status poll at the second interval in response to determining that a set of memory cells of a memory device is almost ready to complete execution of an operation. The almost-ready memory management component 113 can determine that a set of memory cells of a memory device is almost ready to complete execution of an operation during execution of the operation, or in some cases, prior to execution of the operation, as detailed herein. In any case, making the second interval shorter than the first interval can provide an improved balance between bus overhead / power consumption and underutilization of a memory device (e.g., a NAND memory device) compared to approaches that do not employ an almost-ready state and / or a status poll based on the almost-ready state.

[0046] In some embodiments, the almost-ready memory management component 113 can be configured to store a value in a register in a memory device to indicate whether a cell of the memory device is almost ready to complete execution of an operation. The almost-ready memory management component 113 can be configured to store the value in the register based on a type of the operation, a type of the memory cell of the memory device, or both, as detailed herein. In this way, the almost-ready memory management component 113 can account for completion time differences for different types of operations and / or memory cells to improve memory system functionality compared to approaches that do not employ an almost-ready state.

[0047] For example, short operations (e.g., read operations) can have a corresponding value stored in a register to indicate an almost ready state. Examples of short operations include read / write operations, operations involving SLC, and / or other types of operations that do not include a verify step. Because such operations are relatively short in length, a value can be stored in a register prior to performing the operation and maintained in the register for at least the duration of the operation to indicate an almost ready state. Storing a corresponding value in a register prior to performing an operation to indicate an almost ready state and maintaining the value for at least the duration of a short operation can result in performing a status poll substantially at or entirely at the second interval for the duration of a short operation and can thus reduce any latency associated with determining a ready state once the short operation is complete.

[0048] Conversely, long operations (e.g., erase operations) can have a corresponding value stored in a register to indicate an un-almost ready state (e.g., an un-almost ready state of a set of memory cells on which a long operation is being / could be performed) at least initially. Examples of long operations include erase operations, operations involving MLC, TLC, QLC, etc., and / or operations that include a verify step. Storing a corresponding value in a register prior to performing an operation to indicate an un-almost ready state and maintaining the value for at least a portion of the duration of a long operation can result in performing a status poll at least initially at the first interval and can thus improve efficiency (e.g., reduce bus traffic / power consumption) while still allowing a status poll to be performed at the second interval subsequently upon determining an almost ready state, thus reducing any latency associated with determining a ready state once the long operation is complete as well.

[0049] For example, the almost ready memory management component 113 can be configured to set a value in a register to indicate whether a cell of a memory device and / or the memory device is almost ready based on a current completion level of an operation (e.g., a long operation). During performance of an operation, the almost ready memory management component 113 can determine a current completion level of the operation (e.g., a long operation). The current completion level of an operation can be equal to a current number of cycles and / or a current voltage. Examples of cycles include program / erase and / or verify cycles of a cell on which an operation is performed. The almost ready memory management component 113 can increment a counter or otherwise track a certain number of current cycles. Alternatively or additionally, the almost ready memory management component 113 can determine a current voltage. For example, a verify step can be performed by issuing a number of read commands to determine a current voltage of a cell on which an operation is performed.

[0050] The almost-ready memory management component 113 can compare the current completion level (e.g., a certain amount of current cycles) to the almost-ready threshold. The comparison can allow a determination of whether the current completion level satisfies the almost-ready threshold, and thus whether to store / change an indicator of the almost-ready state. For example, when the current completion level of the operation (e.g., 6 cycles) exceeds the almost-ready threshold (e.g., 5 cycles), the almost-ready memory management component 113 can then store a value indicating the almost-ready state of the cell on which the operation is performed in a register.

[0051] The almost-ready memory management component 113 can be configured to determine the almost-ready threshold, for example, based on a type of the operation (e.g., read operation, erase operation, etc.) and / or a type of the memory cell on which the operation is / will be performed (e.g., SLC, MLC, etc.). Similar to the current completion level as detailed herein, the almost-ready threshold can be a threshold number of cycles and / or a threshold voltage. For example, the almost-ready threshold can be equal to a threshold number of cycles (e.g., 5 cycles). The threshold number of cycles can be less than a total number of cycles (e.g., 6 cycles) expected to complete the operation. For example, in some embodiments, the almost-ready threshold can be equal to a value corresponding to a last cycle of the total number of cycles expected to complete the operation, among other possibilities. In some embodiments, the almost-ready threshold can be an almost-ready threshold voltage. The almost-ready threshold voltage can be less than a completion threshold voltage (e.g., a target program voltage for the cell when completing the operation).

[0052] In some embodiments, the almost-ready threshold can be a predetermined value, which is included in a table, such as a lookup table, or otherwise stored or accessed by the memory sub-system. For example, the almost-ready memory management component 113 can be configured to determine the almost-ready threshold for the operation to be equal to a stored value (e.g., stored in a lookup table), which corresponds to a type of the operation and / or a type of the memory cell on which the operation is / will be performed. In this way, the almost-ready threshold can account for completion time differences of different types of operations and / or one type of memory cell compared to approaches that do not employ an almost-ready state, which can improve memory system functionality.

[0053] As mentioned, the almost-ready memory management component 113 can determine whether the current completion level of the operation satisfies the almost-ready threshold. In some embodiments, the almost-ready memory management component 113 can determine that the current completion level does not satisfy the almost-ready threshold. In such cases, the almost-ready memory management component 113 can perform / continue to perform status polling of the memory device at a first interval. Further, the almost-ready memory management component 113 can determine an updated current completion level of the operation based on performing the status polling at the first interval. The updated current completion level can be determined in response to each status polling performed at the first interval. In this way, the updated completion level can be compared to the almost-ready threshold in a sequential manner until it is determined that the updated completion level satisfies the almost-ready threshold. In response to determining that the updated completion level satisfies the almost-ready threshold, the almost-ready memory management component 113 can perform status polling of the memory device at a second interval.

[0054] In some embodiments, the almost-ready memory management component 113 can perform status polling of the memory device at least at the second interval until the ready state is determined. For example, the almost-ready memory management component 113 can perform status polling of the memory device at least at the second interval until the ready state is determined in response to a read status command or otherwise determined.

[0055] In some embodiments, the almost-ready memory management component 113 can maintain the stored value indicating the almost-ready state at least until the ready state is determined. For example, in some embodiments, the almost-ready memory management component 113 can maintain the stored value for at least some period of time after the ready state is determined.

[0056] In some embodiments, the first interval can be greater than 40 microseconds (ps). For example, the first interval can be in a range of 40 ps to 200 ps. Included are all individual values and sub-ranges from 40 ps to 200 ps. For example, the first interval can be in a range of 40 ps to 200 ps, 50 ps to 200 ps, 40 ps to 150 ps, 50 ps to 100 ps, and / or 50 ps to 75 ps. In some embodiments, the first interval can be substantially equal to 50 ps or can be equal to 50 ps. As used herein, the term “substantially” means that the characteristic need not be absolute, but is close enough to the intended characteristic to achieve the benefit of the intended characteristic. For example, “substantially equal to 50 ps” is not limited to a value that is absolutely equal to 50. For example, “substantially equal to 50 ps” herein can be within 0.5%, 1%, 2%, 5%, 10%, or 20% or the like of 50 ps.

[0057] In some embodiments, the second interval can be less than 40 microseconds (μβ). For example, the second interval can be in a range of 0.5 μβ to 40 μβ. Including all individual values and sub-ranges from 0.5 μβ to 40 μβ. For example, the second interval can be in a range of 0.5 μβ to less than 40 μβ, 1 μβ to less than 40 μβ, 1 μβ to 20 μβ, 1 μβ to 10 μβ, 1 μβ to 5 μβ, 1 μβ to 2 μβ, and / or 0.5 μβ to 1.5 μβ. In some embodiments, the second interval can be substantially equal to 1 μβ or can be equal to 1 μβ. For example, "substantially equal to 1 μβ" can be within 0.5%, 1%, 2%, 5%, 10%, or 20% of 1 μβ, or the like.

[0058] In some embodiments, the first interval can be at least twice as long as the second interval, the first interval can be at least five times as long as the second interval, and / or the first interval can be at least 10 times as long as the second interval. For example, the first interval can be fifty times longer than the second interval, as well as other possible relative values. Making the first interval at least twice as long as the second interval, at least five times as long as the second interval, and / or at least 10 times as long as the second interval can provide an improved balance between bus overhead / power consumption and underutilization of a memory device (e.g., a NAND memory device) as compared to approaches that do not employ a nearly ready state.

[0059] Figure 2 is an example controller 215 including registers according to some embodiments of the present disclosure. The registers 221 (e.g., status registers) can store status information according to a number of embodiments described herein. In some embodiments, the memory sub-system controller 215 can be similar to the memory sub-system controller 115 as described in Figure 1 , for example. The registers 221 can be included in the local memory 119 as described in Figure 1 , among other possibilities.

[0060] As an example, the status information associated with the registers 221 can include program instruction related status information, such as program counter status information, breakpoints, illegal instructions, and the like, as well as various other exceptions. The status information associated with the registers 221 can include status information related to error conditions detected in microcode instructions, invalid circuit states, and the like. The status information can also include control flow information and debug information, among other status information. Notably, in some embodiments, the status information associated with the registers 221 can include ready / not ready status information and nearly ready / not nearly ready status information. The generated status information can be provided (e.g., reported) to a host (e.g., the host 120 as described in Figure 1 .

[0061] Register 221 can store state information (e.g., a status message) that can include a number of bits (e.g., 8 bits, 64, 128, etc.). For example, as explained in Figure 2 Register 221 can store a total of 8 bits, including first bit 222-1, second bit 222-2, third bit 222-3, fourth bit 222-4, fifth bit 222-5, sixth bit 222-6, seventh bit 222-7, and eighth bit 222-B.

[0062] Each bit can have a number of fields 223-1, 223-2, 223-3, 223-4, 223-5, 223-6, 223-7, 223-8, 223-9, 223-10, 223-11, 223-12, 223-13, 223-14, 223-15, 223-16, 223-17, 223-18, 223-19, 223-20, 223-21, 223-22, 223-23, 223-24, 223-25, 223-26, 223-27, 223-28, 223-29, 223-30, 223-31, 223-32, 223-33, 223-34, 223-35, 223-36, 223-37, 223-38, 223-39, to 223-F that can store state information. For example, fifth bit 222-5 can include fields 223-21, 223-22, 223-23 to 225-24 that can store state information related to a ready / not ready status of a set of memory cells of the memory device. Fifth bit 222-5 can store a binary value, such as a "0" indicating that the memory device is not ready or a "1" indicating that the memory device is ready, among other possible values. Notably, the value of a bit can correspond to almost ready state information. For example, in some embodiments, fourth bit 222-4 can store a binary value, such as a "0" indicating that the memory device is not almost ready or can store a "1" indicating that the memory device is almost ready, among other possible values.

[0063] Although described herein as storing ready state information at fifth bit 222-5 and almost ready state information at fourth bit 222-4, this state information can be stored elsewhere, such as in different bits or different sets of bits in register 221, among other possibilities. Moreover, although described as storing a total of 8 bits with a respective number of fields, it should be understood that the total number of registers, bits, and / or fields can be increased or decreased. Figure 2 Although described as individual registers 221 with a total of 8 bits having a respective number of fields, it should be understood that the total number of registers, bits, and / or fields can be increased or decreased.

[0064] Figure 3is a diagram of a flow 331 corresponding to almost ready memory management in accordance with some embodiments of the present disclosure. For example, as detailed herein, the flow 331 can be applicable at least for long operations. At operation 332, a current completion level of an operation on a set of memory cells of a memory device can be determined. The current completion level can be determined by an almost ready memory management component, such as the almost ready memory management component 113 described in Figure 1 the almost ready memory management component 113 described in

[0065] At operation 333, the current completion level can be determined to satisfy an almost ready threshold, as described herein. In some embodiments, the current completion level can be determined prior to and / or after initiating the operation on the memory device. For example, for long operations, the current completion level can be determined at least after initiating the operation on the memory device (e.g., during performance of the operation on the set of memory cells of the memory device).

[0066] At operation 334, a value can be stored in a register associated with the set of memory cells to indicate that the set of memory cells is almost ready to complete the operation. For example, in response to determining that the current completion level satisfies the almost ready threshold, a value can be stored in a register associated with the set of memory cells to indicate that the set of memory cells is almost ready to complete the operation.

[0067] For example, at operation 335, the value stored in the register can be determined via a status poll at a first interval. At operation 336, the status poll can be performed at a second interval that is shorter than the first interval. For example, in response to determining that the value stored in the register indicates that the set of memory cells is almost ready, the status poll can be performed at a second interval that is shorter than the first interval. In various embodiments, the status poll can be performed at the second interval until a ready status is determined, thereby expediting determination of a ready status of the memory device.

[0068] In some embodiments, a memory device can be included in a plurality of memory devices. In such embodiments, a status poll of a first subset of memory devices in the plurality of memory devices (e.g., those memory devices in which the almost ready state threshold is satisfied and / or the indicator indicates the almost ready state) can be performed at a second interval, substantially simultaneously with a status poll of a second subset of memory devices (e.g., those memory devices in which the almost ready state threshold is not satisfied and / or the indicator indicates the not almost ready state) performed at a first interval that is less frequent than the second interval. Performing status polls of a plurality of memory devices substantially simultaneously at different intervals (e.g., at the first interval or at the second interval) can also improve the overall balance on a memory system between bus overhead / power consumption and underutilization of memory devices (e.g., NAND memory devices) compared to approaches that do not employ an almost ready state. Similarly, in some embodiments, a status poll of a first subset of memory cells of a memory device (e.g., an SLC portion of memory cells) at a second interval is substantially simultaneous with a status poll of a second subset of memory cells of the memory device (e.g., a TLC portion of memory cells) performed at a first interval.

[0069] Figure 4 is a flow diagram corresponding to method 450 for almost ready memory management in accordance with some embodiments of the present disclosure. Method 450 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 450 is performed by almost ready memory management component 113 of FIG. 1. Figure 1 of FIG. 1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, it is to be understood that the illustrated embodiments are merely examples, and that steps can be performed in a different order, and / or concurrently with each other. Additionally, one or more steps can be omitted in various embodiments. Thus, not all steps are necessarily required, nor is the order of the steps necessarily required for the practice of the implementations. Other steps can be provided before, after, or in between existing steps.

[0070] At operation 451, an indicator of an almost ready state of a set of memory cells of a memory device can be determined via a status poll at a first interval. Here, the memory device can be, for example, a NAND memory device. Figure 1The memory devices 130 and 140 described herein are memory devices. In some embodiments, method 450 may include an indicator determining the near-ready state of a collection of NAND memory cells (e.g., one or more blocks of NAND memory cells) in a memory subsystem. As described above, memory components may be memory dies or memory packages coupled to each other to create an array of memory cells, such as a three-dimensional stackable cross-mesh array of memory cells used by the memory subsystem to store data.

[0071] At operation 453, it can be determined that the set of memory cells of the memory device is almost ready to complete an operation on the set of memory cells of the memory device. For example, method 450 may include determining that the set of memory cells of the memory device is almost ready to complete an operation on the set of memory cells of the memory device based on an indicator of an almost ready state. As mentioned, in some embodiments, the indicator of the almost ready state may be a value stored in a register associated with the set of memory cells.

[0072] At operation 455, a second interval may be used to perform status polling (e.g., status polling of blocks of NAND memory cells). For example, status polling may be performed at a second interval in response to determining that a set of memory cells in a memory device is nearly ready to complete an operation. In some embodiments, method 450 may include performing status polling at a second interval on a corresponding number of planes, pages, and / or memory dies grouped into a given set of NAND memory cells.

[0073] Figure 5 This is a block diagram of an example computer system 500 in which embodiments of the present disclosure are operable. For example, Figure 5 An example machine illustrating computer system 500 is described, within which an instruction set for causing the machine to perform any one or more of the methods discussed herein is executable. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110), or may be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1 (Operation of the nearly ready memory management component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0074] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0075] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 418, which communicate with each other via a bus 530.

[0076] Processing device 502 represents one or more general -purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 502 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 can further include a network interface device 508 to communicate over the network 520.

[0077] The data storage system 518 can include a machine-readable storage medium 524 (also known as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 can also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution thereof by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, data storage system 518, and / or main memory 504 can correspond to memory subsystem 110 of Figure 1

[0078] In one embodiment, the instructions 526 include instructions to implement a memory management component (e.g., a memory management component 120) corresponding to a near-ready memory management component (e.g., a near-ready memory management component 120) as described herein. Figure 1 ​instructions to perform functions of the almost ready memory management component 113) of the example embodiments. While the machine-readable storage medium 524 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0079] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. In this context, and for the purposes of brevity and clarity, an algorithm or process is conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0080] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0081] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, or it can comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0082] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0083] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as a read only memory (“ROM”), a random access memory (“RAM”), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0084] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made to the disclosure without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A method (450) for near-ready memory management, the method comprising: An indicator of the near-ready state of the memory cell set of the memory device (130, 140) is determined by polling the state at a first interval, wherein the indicator further includes a value in a register (221) in the memory device. Based on the current completion level of the operations on the set of memory cells, the value is stored in the register by the following operation: Determine that the current completion level of the operation meets the near-ready threshold; and In response to determining that the current completion level of the operation satisfies the near-ready threshold, the value is stored in the register; Based on the indicator of the near-ready state, it is determined that the memory cell set of the memory device is almost ready to complete the execution of the operation on the memory cell set of the memory device; and In response to determining that the set of memory cells of the memory device is almost ready to complete the execution of the operation, the status of the register is polled at a second interval.

2. The method of claim 1, further comprising storing the value in the register based on the type of the operation, the type of the memory cell of the memory device, or both.

3. The method of claim 1, wherein the current completion level of the operation is the current cycle among a plurality of expected cycles for completing the operation.

4. The method of claim 1, wherein the current completion level of the operation is a current voltage associated with the memory device.

5. The method of claim 4, wherein the near-ready threshold further comprises a near-ready threshold voltage.

6. The method of claim 5, wherein determining that the indicator satisfies the near-ready threshold further comprises determining that the voltage associated with the memory device is greater than the near-ready threshold voltage but less than the completion threshold voltage.

7. The method of claim 1, further comprising: It was determined that the memory cell set of the memory device was not nearly ready to complete the execution of the operation; and Continue polling the status at the first interval.

8. The method of claim 7, further comprising: Based on the continuation status polling performed at the first interval, the current completion level of the operation update is determined; Determine that the completion level of the update satisfies the near-ready threshold; and In response to determining that the completion level of the update meets the near-ready threshold, the state polling of the memory device is performed at the second interval.

9. The method of claim 1, further comprising performing the state polling of the memory device at least at the second interval until a ready state of the memory device is determined.

10. A device (110) for near-ready memory management, the device comprising: A nearly ready memory management component (113), configured to: Determine the current completion level of the operations on the set of memory cells of the memory devices (130, 140); Determine that the current completion level meets the near-ready threshold; In response to determining that the current completion level meets the near-ready threshold, a value is stored in a register (221) associated with the memory cell set to indicate that the memory cell set is almost ready to complete the operation; The value stored in the register is determined by polling the state at a first interval; and In response to the determination that the value stored in the register indicates that the memory cell set is almost ready, the status of the register is polled at a second interval shorter than the first interval.

11. The device of claim 10, wherein the memory device is a NAND memory device.

12. The device of claim 10, wherein the nearly ready memory management component is further configured to: The status polling is performed at the first interval by providing multiple read status commands at the first interval; and The status polling is performed at the second interval by providing multiple read status commands at the second interval.

13. The device according to any one of claims 10 to 12, wherein the nearly ready memory management component is further configured to: The state polling of the first subset of the memory cells of the memory device is performed substantially simultaneously with the state polling of the second subset of the memory cells of the memory device at the second interval.

14. A system (110) for near-ready memory management, the system comprising: A non-volatile memory device (130) comprising a plurality of memory components in a stackable cross-mesh array arranged to form a plurality of blocks of NAND memory cells; and Processing device (117), coupled to the plurality of memory components, the processing device being configured to perform operations including: Determine the current completion level of the operations on the NAND memory cell blocks of the plurality of blocks of NAND memory cells; Determine that the current completion level of the operation meets the near-ready threshold; In response to determining that the current completion level of the operation satisfies the near-ready threshold, a value is stored in register (221) of a plurality of registers associated with the plurality of blocks of NAND memory cells, wherein the registers are associated with the NAND memory cell blocks; The status of the plurality of registers associated with the plurality of blocks of NAND memory cells is polled at a first interval to determine the corresponding values ​​of the registers; Based on the value stored in register (221) among the plurality of registers associated with the NAND memory cell block, it is determined that the NAND memory cell block is almost ready to complete the execution of the operation on the NAND memory cell block; and In response to determining that the NAND memory cell block is almost ready to complete the operation, the status polling of the registers associated with the NAND memory cell block is performed at a second interval.

15. The system of claim 14, wherein the processing means further performs the state polling of the register at the first interval in response to initiating the operation on the NAND memory cell block.

16. The system of claim 14 or 15, wherein the first interval is greater than or equal to 40 microseconds (μs) and wherein the second interval is less than 40 μs.

17. The system of claim 16, wherein the second interval is substantially equal to 1 μs.

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