PCIe interface and interface system

Abstract

This invention relates to an apparatus comprising a transceiver configured to transmit and receive data; and Skip Ordered Set (SKP OS) control logic, communicating with the transceiver and configured to generate an SKP OS and control the transceiver to transmit the SKP OS and data blocks to a link connected to an external device and comprising multiple channels. The SKP OS control logic is configured to increase or decrease the transmission interval of the SKP OS based on the transmission history of the SKP OS in response to the link entering a recovery state, the recovery state being used to recover the link from errors.

Description

[0001] Cross-reference to related applications

[0002] This patent document claims priority and benefit to Korean patent application No. 10-2021-0044151, filed on April 5, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] The technology and embodiments disclosed in this patent document relate to an electronic device, and more particularly, to a high-speed peripheral component interconnect (PCIe) interface and interface system. Background Technology

[0004] Advances in semiconductor processing and logic design have allowed for an increase in the amount of logic that can exist on an integrated circuit device. Consequently, computer system configurations have evolved from a single or multiple integrated circuits in a system to multi-core, multi-hardware-thread, and multi-logic processors not only on a single integrated circuit, but also to other interfaces integrated into such processors. A processor or integrated circuit typically comprises a single physical processor die. A processor die can include any number of cores, hardware threads, logic processors, interfaces, memory controller hubs, etc.

[0005] The proliferation of compact computing devices has increased as the technological capability to pack more processing power into smaller packages has become more concentrated. However, data storage and complex processing beyond the form factor performed by compact devices rely on external devices. Therefore, the ability of interconnect architectures to communicate with other devices has become increasingly important. Summary of the Invention

[0006] The embodiments provide an improved high-speed peripheral component interconnect (PCIe) interface and an interface system including the PCIe interface.

[0007] According to one aspect of the disclosed technology, an apparatus is provided, comprising: a transceiver configured to transmit and receive data; and Skip Ordered Set (SKP OS) control logic communicating with the transceiver and configured to generate an SKP OS and control the transceiver to transmit the SKP OS and data blocks to a link connected to an external device and including multiple lanes, wherein the SKP OS control logic is configured to increase or decrease the transmission interval of the SKP OS based on the transmission history of the SKP OS in response to the link entering a recovery state for recovering the link from an error.

[0008] According to another aspect of the disclosed technology, an interface system is provided, comprising: a first high-speed peripheral component interconnect (PCIe) device and a second PCIe device, the second PCIe device being connected to and communicating with the first PCIe device via a link including multiple channels, wherein the first PCIe device is configured to generate skipped ordered sets (SKP OS) and, in response to the link entering a recovery state, to increase or decrease the transmission interval of the SKP OS based on the state of the elastic buffer of the second PCIe device. Attached Figure Description

[0009] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings.

[0010] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements. The same reference numerals always denote the same element.

[0011] Figure 1 This is a diagram illustrating a high-speed peripheral component interconnect (PCIe) system according to an embodiment of the disclosed technology.

[0012] Figure 2 This is a diagram illustrating a channel according to an embodiment of the disclosed technology.

[0013] Figure 3 This is a diagram illustrating a differential signal according to an embodiment of the disclosed technology.

[0014] Figure 4 This is a diagram illustrating a PCIe interface according to an embodiment of the disclosed technology.

[0015] Figure 5 This is a diagram illustrating the configuration of a data packet according to an embodiment of the disclosed technology.

[0016] Figure 6 This is a diagram illustrating a data flow according to an embodiment of the disclosed technology.

[0017] Figure 7 This is a diagram illustrating the link state of a PCIe system according to an embodiment of the disclosed technology.

[0018] Figure 8 This is a diagram illustrating the state of a resilient buffer according to an embodiment of the disclosed technology.

[0019] Figure 9 This is a diagram illustrating the state of a resilient buffer according to an embodiment of the disclosed technology.

[0020] Figure 10This is a diagram illustrating the configuration of the physical layer according to an embodiment of the disclosed technology.

[0021] Figure 11 This is a diagram illustrating the Skip Ordered Set (SKP OS) control logic according to an embodiment of the disclosed technology.

[0022] Figure 12 This is a diagram illustrating an operation method of a PCIe system according to an embodiment of the disclosed technology.

[0023] Figure 13 This is a diagram illustrating an operation method of a PCIe system according to an embodiment of the disclosed technology. Detailed Implementation

[0024] Devices and systems based on the disclosed technology can be implemented as high-speed computer bus standards based on the high-speed peripheral component interconnect (PCIe) interface to receive and transmit data. Figure 1 This is a diagram illustrating a high-speed peripheral component interconnect (PCIe) system according to an embodiment of the disclosed technology.

[0025] Reference Figure 1 A PCIe system may include a PCIe host and a PCIe interface. Specifically, a first PCIe system 1000 may include a first PCIe interface 100 and a first PCIe host 300, and a second PCIe system 2000 may include a second PCIe interface 200 and a second PCIe host 400.

[0026] The first PCIe system 1000 or the second PCIe system 2000 can be an electronic device that supports communication using a PCIe interface. For example, the first PCIe system 1000 can be a PC, a laptop computer, or a mobile computing device. Furthermore, the second PCIe system 2000 can represent an expansion card, expansion board, adapter card, plug-in card, or accessory card, and each of these can represent a printed circuit board (PCB) that can be inserted into an electrical connector or expansion slot on the motherboard of the first PCIe system 1000 to provide additional functionality to the first PCIe system 1000 via an expansion bus. Moreover, the second PCIe system 2000 can be a storage device such as a solid-state drive (SSD), and can be a graphics card, network card, or USB card.

[0027] The first PCIe system 1000 or the second PCIe system 2000 can perform communication using the first PCIe interface 100 or the second PCIe interface 200. Specifically, the first PCIe system 1000 or the second PCIe system 2000 can convert data received from the first PCIe host 300 or the second PCIe host 400 into a communication-suitable protocol using the first PCIe interface 100 or the second PCIe interface 200. The first PCIe system 1000 or the second PCIe system 2000 can form a link and communicate with each other through the link. For example, the first PCIe system 1000 or the second PCIe system 2000 can transmit and / or receive data packets through the link.

[0028] Figure 2 This is a diagram illustrating a channel according to an embodiment of the disclosed technology.

[0029] Reference Figure 2 The diagram illustrates a first transmitter TX1, a second transmitter TX2, a first receiver RX1, and a second receiver RX2. A channel may include paths comprising differential drive signal pairs, such as a transmission path pair configured for transmission and a receive path pair configured for reception. A PCIe system may include transmission logic for transmitting data to another PCIe system and receive logic for receiving data from another PCIe system. For example, the channel may include two transmission paths connected to the first transmitter TX1 and two receive paths connected to the first receiver RX1.

[0030] The transmission path can be used to transmit data and is configured to include a transmission line, copper wire, optical fiber, wireless communication channel, infrared communication link, or any other communication path. The receiving path can be used to receive data and is configured to include a receiving line, copper wire, optical fiber, wireless communication channel, infrared communication link, or any other communication path.

[0031] A connection between two devices (e.g., a first PCIe system 1000 and a second PCIe system 2000) can be designated as a link. A link can support one or more channels. In some implementations, each channel can represent a set of differential signal pairs (one pair for transmission and another for reception). A link can include multiple channels to adjust bandwidth. For example, a link can include 1 channel, 2 channels, 4 channels, 8 channels, 12 channels, 32 channels, 64 channels, etc.

[0032] Figure 3 This is a diagram illustrating a differential signal according to an embodiment of the disclosed technology.

[0033] Reference Figure 3The diagram illustrates a differential signal pair (Sig1 and Sig2). PCIe systems can use differential signal pairs for transmission and / or reception. A differential signal pair consists of two signals with the same frequency and amplitude but opposite phases. For example, when the first signal is at the rising edge of its transition from 0 to V+, the second signal can be at the falling edge of its transition from 0 to V-. PCIe systems can utilize differential signals to improve signal integrity, such as more desirable electrical characteristics like cross-coupling, voltage overshoot / undershoot, and ringing. PCIe systems are also able to adjust transmission frequencies more quickly.

[0034] Figure 4 This is a diagram illustrating a PCIe interface according to an embodiment of the disclosed technology.

[0035] Reference Figure 4 The diagram shows the first PCIe interface 100 and the second PCIe interface 200.

[0036] The PCIe layers included in a PCIe interface may include three separate logical layers. For example, a first PCIe interface 100 may include a PCIe core 110, a transaction layer 120, a data link layer 130, and a physical layer 140. A second PCIe interface 200 may include a PCIe core 210, a transaction layer 220, a data link layer 230, and a physical layer 240. Each of layers 120, 130, 140, 220, 230, and 240 may include two parts, namely Tx and Rx. One part, Tx, handles outbound (or transmission) information, and the other part, Rx, handles inbound (or reception) information. In some embodiments, the PCIe interface may use data packets to communicate with other PCIe interfaces.

[0037] PCIe cores 110 or 210 typically control PCIe interfaces 100 or 200. For example, PCIe cores 110 or 210 may include a software layer for operating the interface. In some implementations, PCIe cores 110 or 210 may transmit addresses, transaction types, data, etc., to transaction layers 120 or 220, and / or receive addresses, transaction types, data, etc., from transaction layers 120 or 220.

[0038] Transaction layer 120 or 220 may correspond to an upper layer in the PCIe interface architecture. Transaction layer 120 or 220 can provide an interface connection between the PCIe host 300 or 400 in the PCIe system 1000 or 2000 and the interconnect architecture (e.g., data link layer 130 or 230 and physical layer 140 or 240). The primary function of transaction layer 120 or 220 may be, or include, the assembly and decomposition of transaction layer packets (TLPs). In some implementations, transaction layer 120 or 220 may implement split transactions, i.e., allowing a transaction where another traffic is transmitted over the link while the target system assembles the data required for a response. For example, transaction layer 120 or 220 may implement transactions that temporarily separate requests and responses from each other. In embodiments, the four transaction address spaces may include a configuration address space, a memory address space, an input / output address space, and a message address space. A memory space transaction may include one or more read and write requests to transfer data to / from a memory-mapped location. In embodiments, memory space transactions can use two different address formats, such as a short address format like a 32-bit address, or a long address format like a 64-bit address. Configuration space transactions can be used to access the configuration space of a PCIe device. Transactions targeting the configuration space can include read and write requests. Message space transactions (or messages) can be defined to support in-band communication between PCIe systems.

[0039] Transaction layer 120 or 220 may store link configuration information, etc., received from PCIe kernel 110 or 210. In some implementations, transaction layer 120 or 220 may generate a TLP requested from PCIe kernel 110 or 210, or convert the received TLP into payload or status information.

[0040] Data link layer 130 or 230 may correspond to an intermediate layer in the PCIe interface architecture and perform the functions of an intermediate level between transaction layer 120 or 220 and physical layer 140 or 240. The main functions of data link layer 130 or 230 may include link management and data integrity, including error detection and correction. Specifically, the transmitting side of data link layer 130 or 230 may accept a TLP assembled in transaction layer 120 or 220, provide a data protection code, or calculate a TLP sequence number. In some implementations, the transmitting side of data link layer 130 or 230 may transmit the data protection code and TLP sequence number to physical layer 140 or 240, enabling transmission of the data protection code and TLP sequence number over the link. The receiving side of data link layer 130 or 230 may check the data integrity of the TLP received from physical layer 140 or 240 and transmit the TLP to transaction layer 120 or 220 for further processing.

[0041] Physical layer 140 or 240 may include circuitry for interface operation. This circuitry may include drivers, input buffers, series-to-parallel converters, parallel-to-series converters, phase-locked loops (PLLs), and impedance matching circuitry.

[0042] In some implementations, physical layer 140 or 240 may include logical subblocks and electrical subblocks that physically transmit data packets to an external PCIe system. The logical subblocks may perform roles necessary for the "digital" functions of the physical layer. Relatedly, the logical subblocks may include a transmission section and a reception section, wherein the transmission section prepares transmit information to be transmitted by the physical subblock, and the reception section identifies and prepares received information before it is transmitted to data link layer 130 or 230. Physical layer 140 or 240 may include a transmitter (TX) and a receiver (RX). The transmitter (TX) can receive symbols from the logical subblocks to be serialized by the transmitter and transmitted to an external device. Additionally, the receiver (RX) can receive serialized symbols from an external device and convert the received symbols into a bit stream. The bit stream can be deserialized to be supplied to the logical subblocks. That is, physical layer 140 or 240 can convert TLPs received from data link layer 130 or 230 into a serialized format and convert data packets received from external devices into a deserialized format. Furthermore, physical layer 140 or 240 may include logical functions associated with interface initialization and maintenance.

[0043] The structure of PCIe interface 100 or 200 is in Figure 4 The example shown is valid and can be modified. For example, the structure of the PCIe interface 100 or 200 can include any form, such as a fast path interconnect structure, a next-generation high-performance computing interconnect structure, or another hierarchical structure.

[0044] Figure 5 This is a diagram illustrating the configuration of a data packet according to an embodiment of the disclosed technology.

[0045] Reference Figure 5Each part of packet 50 can be processed sequentially at each layer of the PCIe interface. Specifically, packet 50 can be configured using different protocols to be processed at each layer. For example, transaction layer packets (TLPs) can be generated and processed at transaction layer 120 or 220. A TLP may include a header field, a data field, and an end-to-end cyclic redundancy check (ECRC) field. The header field may include the type of the TLP, information about whether data will be included, information about whether cyclic redundancy check (CRC) will be included, etc. Additionally, the data field may include data to be transmitted or received, and the ECRC field may include an ECRC value representing information about the endpoint. In some implementations, the data field and the ECRC field may not be included in the TLP.

[0046] Furthermore, Data Link Layer Packets (DLLPs) can be generated and processed at Data Link Layer 130 or 230. In addition to the TLP, the DLLP may also include a sequence number field and a Link Cyclic Redundancy Check (LCRC) field. The sequence number field can be a field that includes information about the sequence number of the TLP, and the LCRC field can be a field that includes information about the LCRC.

[0047] In addition, physical layer packets (PLPs) can be generated and processed in physical layer 140 or 240. Besides DLLPs, PLPs may also include framing fields. Framing fields can be fields that include information about the serialization format.

[0048] Figure 6 This is a diagram illustrating a data flow according to an embodiment of the disclosed technology.

[0049] Reference Figure 6 This illustrates the data stream transmitted over an x8 link. The data stream may include transmissions that skip ordered sets (SKPs).

[0050] The data stream can begin with the transmission of the synchronization header Sync Hdr H1H = 10b, representing a data block. Therefore, the Start of TLP (STP) framing token can be transmitted as the zeroth symbol, indicating the start of the TLP stream in channels 0 through 3. Additionally, the TLP header and TLP data can be transmitted as the first and second symbols. Link Cyclic Redundancy Check (LCRC) can be transmitted after the TLP data, and the SDP header indicating that DLLP data will be transmitted after the LCRC can be transmitted as the third symbol. Furthermore, Cyclic Redundancy Check (CRC) data associated with the DLLP data can also be provided.

[0051] Subsequently, a Logical Idle Token (IDL) can be transmitted, indicating that no data has been transmitted over the link. Additionally, an EDS token can be transmitted to indicate that the data has been changed to SKP OS data on the channel. For example, another synchronization data can be transmitted, encoded as "01b" indicating that the subsequent block will be an SKP OS data block.

[0052] The SKP OS may include parity bits indicating the parity status of each of the channels in the link (e.g., channels 0 through 7). The SKP OS may also include a layout predefined and recognizable by the receiver. For example, in the case of 128b / 130b encoding in PCIe, the SKP OS may include 16 basic symbols. Four SKP symbol groups can be added or removed via ports, and the SKP OS may include 8 symbols, 12 symbols, 16 symbols, 20 symbols, 24 symbols, etc. Furthermore, an SKP_END symbol may be provided to indicate the end position of the SKP OS on the channel and the position of the next block of synchronization headers transmitted through the channel.

[0053] Figure 7 This is a diagram illustrating the link state of a PCIe system according to an embodiment of the disclosed technology.

[0054] exist Figure 7 The image shows the link status of the PCIe system, including detection status, polling status, configuration status, hot reset status, disabled status, and L0 status.

[0055] The detection state is the initial state after a power-on reset. For example, the detection state can be entered from the configuration state, hot reset state, disabled state, L2 state, loopback state, and recovery state. The detection and disabled states typically enable ultra-low power while maintaining the channel's configuration settings.

[0056] During the polling state, channels that can be used for data communication are identified among the detected channels. Polarity reversal can be checked during the polling state, including checking Rx+ and Rx-.

[0057] During the configuration state, the channel width available for data communication is confirmed. Channel reversal can be checked during the configuration state. The configuration state can be entered from the polling state. Optionally, the configuration state can be entered after entering the L0 state for channel reduction and channel width increase.

[0058] The recovery state can be used to reconfigure link bandwidth. In recovery state, the link bandwidth can be changed. During recovery state, at least one of bit lock, symbol lock, and / or channel-to-channel de-skew can be reset. Recovery state can be entered when an error occurs in L0 state. After error recovery to recovery state, the recovery state can be changed back to L0 state.

[0059] The L0 state can be a normal operating state, in which data and data packets can be transmitted and received via the link. For example, the L0 state can be the operating state of a physical bus interface, through which data and control data packets can be transmitted and received.

[0060] The L0s state can be a power-saving state, enabling the physical bus interface to quickly enter a power-hold state and to recover from the power-hold state without going through any recovery state.

[0061] The L1 state can be a power-saving state, in which power can be actively conserved. Most transmitters and receivers may be turned off. Main power and clock cannot be guaranteed, but auxiliary power can be used.

[0062] The loopback state can be used for testing and fault isolation. The loopback state operates only on a channel-by-channel basis and selects and configures the loopback receive channel.

[0063] The disabled state is used to disable the setup link until further notification. The hot reset state can be triggered solely by the downstream port. The downstream port can use a training sequence (e.g., TS1 or TS2) to propagate the hot reset.

[0064] Figure 8 This is a diagram illustrating the state of a resilient buffer according to an embodiment of the disclosed technology.

[0065] Reference Figure 8 The diagram illustrates the first to third states 81 to 83 of a resilient buffer when communication is performed between PCIe systems. The resilient buffer can temporarily store data to be transmitted or data to be received. In some implementations, the resilient buffer can be included in each of the transmitting and receiving sides. The resilient buffer can temporarily store SKP OS and data blocks.

[0066] Each PCIe system can include clocks on both the transmitting and receiving sides, and these clocks can operate at different frequencies across different PCIe systems. Different frequencies can lead to overflow or underflow errors. For example, the first state 81 of the resilient buffer is a case where the transmitting side transmits data blocks faster than the receiving side receives and processes them, and an overflow can occur on the receiving side. That is, the first state 81 of the resilient buffer can be a case where the transmitting side clock is faster than the receiving side clock, and the PCIe system can enter a recovery state to resolve the overflow error. This means that communication between PCIe systems may be suspended, and significant performance degradation and data loss may occur within the PCIe system.

[0067] The second state 82 of the resilient buffer is when the receiving side receives and processes data blocks faster than the transmitting side transmits data blocks, and it can be a state where an underflow occurs on the receiving side. In other words, the second state 82 of the resilient buffer is when the clock on the receiving side is faster than the clock on the transmitting side, and the PCIe system can enter a recovery state to resolve the underflow error. Therefore, significant performance degradation can occur in PCIe systems.

[0068] To prevent overflow or underflow errors caused by clock differences between PCIe systems, PCIe systems can use the addition or removal of special symbols. Specifically, PCIe systems can prevent overflow or underflow by using the SKP OS. In the third state 83 of the elastic buffer, the SKP OS generated on the transmitting side can be transmitted to the receiving side. The SKP OS can be transmitted between data block transmissions.

[0069] The rules and contents of SKP OS will be described below.

[0070] Clock tolerance compensation

[0071] The SKP OS can be used to compensate for frequency differences between bit rates at both ends of a link. The resilient buffer performing the compensation can be included in a logical sub-block of the physical layer on the receiving side. The transmission interval of the SKP OS can be set based on the absolute value of the pre-designed transmission and reception clock frequency difference. This specification supports two clocks with different transmitter Tx and receiver Rx reference clock (Refclk) speeds. One clock is a separate reference clock without an SSC (SRNS), allowing a maximum difference of 600 ppm without any separate reference clock (SSC). The other clock is a separate reference clock with an independent SSC (SRIS), allowing a difference of 5600 ppm relative to a separate Refclk using an independent SSC. However, the Refclk architecture typically uses the same Refclk as the transmitter Tx and receiver Rx; therefore, there may not be any difference between the Refclk speeds of the transmitter Tx and receiver Rx.

[0072] A specific form factor specification may use only SRIS or only SRNS, and is allowed to provide mechanisms for selecting the clock architecture. The upstream port can implement support for all combinations of SRIS and SRNS (including any support for either SRIS or SRNS), but must comply with all relevant form factor specifications.

[0073] Downstream ports supporting SRIS are used to support SRNS, provided that the downstream port is not solely connected to modify the specific form factor targeted by these requirements. The port configuration used to meet the requirements of a specific relevant form factor can be varied depending on the implementation. When the average clock tolerance error is 600 ppm, the clock of each of the transmitter Tx and receiver Rx can be advanced by one clock cycle every 1666 clock cycles. When the clock tolerance error is 5600 ppm, the clock of each of the transmitter Tx and receiver Rx can be advanced by one clock cycle every 178 clock cycles.

[0074] When the receiver operates using an SKP OS generated at the speed used in the SRNS, the port can set bits at the appropriate data rate in the speed vector, supporting reception of the lower SKP OS in the field of the Link Capability 2 register, even if the port is operating in the SRIS. Similarly, when the transmitter operates using an SKP OS generated at the speed used in the SRNS, the port can set bits at the appropriate data rate in the speed vector, supporting reception of the lower SKP OS in the field of the Link Capability 2 register, even if the port is operating in the SRIS. The system software can check whether any bits are set in the lower SKP OS reception support speed vector field before setting the appropriate data rate bit in the lower SKP OS generation vector activation field of the link partner in the Link Control 3 register. All software extension devices (e.g., repeaters) present in the link can support lower SKP OS generation, allowing the system software to set bits in the lower SKP OS generation vector activation field. The configuration of the software supported in the extension devices can be varied depending on the implementation. When the enable bit for the data rate of the execution link is set in the lower SKP OS generation vector activation field, the transmitter can maintain the generation of SKP OS in the L0 state at the rate used in the SRNS, regardless of the clock architecture of the execution link. Scheduling of the SKP OS in the Link Training and State Mechanism (LTSSM) state can be performed at a rate suitable for the clock architecture.

[0075] Compared to designs that only support SRNS, components that support SRIS allow for a greater number of demands on elastic buffers. These demands can result in additional time being needed to schedule the SKP OS when it is transmitted just after a packet with the maximum payload size.

[0076] SKP for 8b / 10b encoding OS

[0077] When using 8b / 10b encoding, except where SKP OS is permitted in the loopback slave device during loopback activity, the transmitted SKP OS can have three SKP symbols following the COM symbol. The received SKP OS can have one to five SKP symbols following the COM symbol.

[0078] SKP for 128b / 130b encoding OS

[0079] When using 128b / 130b encoding, the transmitted SKP OS can have 16 symbols, and the received SKP OS can have 8, 12, 16, 20, or 24 symbols.

[0080] As shown in Tables 1 and 2, two SKP OS formats can be defined for 128b / 130b encoding. Both formats can include 1 to 5 groups configured using 4 SKP symbols, with the last group, configured using 4 symbols and designated as SKP_END or SKP_END_CTL, located last. When the PCIe system operates at 8.0 GT / s, only the standard SKP OS can be used. When the PCIe system operates at 16.0 GT / s, both the standard SKP OS and the control SKP OS can be used. All states of the specification that do not pertain to a specific SKP OS format can be applied to both formats. When an SKP OS is transmitted, all channels can transmit the same type of SKP OS. All channels can transmit either the standard SKP OS or the control SKP OS.

[0081] Information following the SKP_END symbol based on the LTSSM state and block sequence can be included in the standard SKP OS. In the polling compliance state, the symbol can include channel error status information. Otherwise, when SKPOS follows a data block, the symbol can include the LFSR value and data parity bits. The control SKP OS can include three data parity bits and additional information following the SKP_END_CTL symbol.

[0082] When a PCIe system operates at a data rate of 8.0 GT / s, the parity bit of the standard SKP OS can be the parity check of the even-numbered data block payloads of all data blocks in the channel communication, and can be calculated independently for each channel. The upstream and downstream port transmitters can calculate the parity as follows.

[0083] In this embodiment, parity can be initialized when transmitting SDS OS.

[0084] In one embodiment, after scrambling is performed, parity can be updated for each bit of the data block payload.

[0085] In this embodiment, the parity bit of the standard SKP OS data transmitted adjacent to the data block can be set as the current parity bit.

[0086] In this embodiment, parity checking can be initialized after the transmission of the standard SKP OS.

[0087] Upstream and downstream port receivers can calculate parity and operate.

[0088] In this embodiment, parity checking can be initialized when an SDS OS is received.

[0089] In one embodiment, parity can be updated for each bit of the data block payload before descrambling is performed.

[0090] In this embodiment, when a standard SKP OS is received immediately after a data block, each channel can compare the received data parity bit with the calculated parity. Upon sensing an inconsistency, the receiver can set a channel error status register bit corresponding to the channel's basic channel number. Inconsistency is not considered an error by the receiver, and link retraining may not be performed due to the inconsistency.

[0091] In this embodiment, parity is initialized when a standard SKP OS is received.

[0092] When a PCIe system operates at a data rate of 16.0 GT / s, the parity bits for both the standard SKP OS and the control SKP OS can be the parity check for even-numbered data block payloads of all data blocks in the channel communication, and can be calculated independently for each channel. The upstream and downstream port transmitters can calculate the parity as follows.

[0093] In this embodiment, parity can be initialized when the LTSSM is in the Recovery.Speed ​​state.

[0094] In this embodiment, parity can be initialized when transmitting SDS OS.

[0095] In one embodiment, after scrambling is performed, parity can be updated for each bit of the data block payload.

[0096] In one embodiment, the parity bit of the standard SKP OS data transmitted immediately after the data block can be set as the current parity bit.

[0097] In this embodiment, the data parity check controlling the SKP OS, the first timer data parity check, and the second timer parity check can all be set as the current parity check.

[0098] In one embodiment, parity can be initialized after the Transport Control Program (SKP) OS. However, parity may not be initialized after the Transport Standard Program (SKP) OS.

[0099] The upstream and downstream port receivers can calculate parity and operate as follows.

[0100] In this embodiment, parity can be initialized when the LTSSM is in recovery speed state.

[0101] In this embodiment, parity checking can be initialized when an SDS OS is received.

[0102] In one embodiment, parity can be updated for each bit of the data block payload before descrambling is performed.

[0103] In this embodiment, upon receiving control SKP OS, each channel can compare the parity bit of the received first-level timer data with the calculated parity. When an inconsistency is sensed, the receiver can set a bit in a register indicating the inconsistency status of the first-level timer data parity of the port corresponding to the channel's basic channel number. Inconsistency is not considered an error by the receiver, and link retraining may not be performed due to the inconsistency.

[0104] In this embodiment, upon receiving control SKP OS, each channel can compare the parity bit of the received second-level timer data with the calculated parity. When an inconsistency is sensed, the receiver can set a bit in a register indicating the inconsistency status of the second-level timer data parity for the port corresponding to the channel's base channel number. Inconsistency is not considered an error by the receiver, and due to the inconsistency, link retraining may not be performed.

[0105] In this embodiment, when a standard SKP OS is received just after a data block, the receiver can compare the received data parity bits with the calculated parity. However, the comparison result has no effect on the state of the registers representing the channel error status.

[0106] In this embodiment, parity can be initialized upon receiving a control SKP OS. However, parity may not be initialized upon receiving a standard SKP OS.

[0107] Table 1

[0108] Table 1: Standard SKP OS in 128b / 130b Encoding

[0109]

[0110] The control SKP OS can differ from the standard SKP OS configured using the last four symbols. In addition to the data parity bits calculated by the upstream and downstream ports, parity bits calculated by each retimer can be used for communication. Furthermore, as described below, parity bits can be used for channel margin in the retimer receiver.

[0111] Table 2

[0112] Table 2: Control SKP OS in 128b / 130b Encoding

[0113]

[0114] The 'remaining CRC[4:0]' can be calculated as follows: bits [6:0] of symbol 4N+2 (d[0] can be bit 0 of symbol 4N+2, d[1] can be bit 1 of symbol 4N+2, ..., and d[6] can be bit 6 of symbol 4N+2), and bits [7:0] of symbol 4N+3 (d[7] can be bit 0 of symbol 4N+3, d[8] can be bit 1 of symbol 4N+3, ..., and d

[14] can be bit 7 of symbol 4N+3).

[0115] Margin CRC[0]=d[0]^d[3]^d[5]^d[6]^d[9]^d

[10] ^d

[11] ^d

[12] ^d

[13]

[0116] Margin CRC[1]=d[0]^d[4]^d[6]^d[7]^d

[10] ^d

[11] ^d

[12] ^d

[13] ^d

[14]

[0117] Margin CRC[2]=d[0]^d[2]^d[3]^d[6]^d[7]^d[8]^d[9]^d

[10] ^d

[14]

[0118] Margin CRC[3]=d[1]^d[3]^d[4]^d[7]^d[8]^d[9]^d

[10] ^d

[11]

[0119] Margin CRC[4]=d[2]^d[4]^d[5]^d[8]^d[9]^d

[10] ^d

[11] ^d

[12]

[0120] "Roundup parity check" can be a parity check of the even-numbered bits [4:0] of symbol 4N+1, the bits [6:0] of symbol 4N+2, and the bits [7:0] of symbol 4N+3. (That is, roundup parity check = roundup CRC[0]^roundup CRC[1]^roundup CRC[2]^roundup CRC[3]^roundup CRC[4]^d[0]^d[1]^d[2]^d[3]^d[4]^d[5]^d[6]^d[7]^d[8]^d[9]^d

[10] ^d

[11] ^d

[12] ^d

[13] ^d

[14] ).

[0121] Controlling SKP OS error protection

[0122] The 21 bits of symbols 4N+1 (bits [4:0]), 4N+2 (bits [7:0]), and 4N+3 (bits [7:0]) can include a 5-bit CRC and a 1-bit parity check, with the remaining 15 bits used for information transmission. While the parity bit provides sensing for bit flips of odd-numbered bits (e.g., bit 1 or bit 3), the CRC provides assurance sensing for 1-bit and 2-bit flips. Therefore, sensing for 3-bit flips and burst errors of length 5 can be ensured for the 21 bits. The 5-bit CRC can be derived from a polynomial, i.e., x 5 +x 2 Export from +1.

[0123] This 21-bit information is not part of the TLP, therefore, transmission can be ensured when the same content is repeatedly transmitted. This can be achieved through structured registers. When a downstream command is available for transmission from a downstream port reflecting the contents of the structured registers, the upstream status, having passed the error test, can be updated via the downstream port's status register. Therefore, there may be a mechanism in the software to execute a command and wait for feedback on the status again before executing a new command. Thus, the 15-bit information can be used as a micro-data packet.

[0124] Transmitter Standard

[0125] In this embodiment, all channels can transmit symbols at the same frequency (the difference in bit rate between all multi-channel links can be 0 ppm).

[0126] In this embodiment, except for cases where the loopback slave device is allowed to be in the loopback-activated LTSSM state during transmission, SKP OS of the same length can be transmitted simultaneously in all channels of a multi-channel link.

[0127] In the embodiment, when using 8b / 10b encoding:

[0128] - When the link is not operating in SRIS, or when the bit corresponding to the current link speed is set in the lower SKP OS generator vector activation field and the LTSSM is in L0 state, the SKP OS can be scheduled to transmit at intervals of 1118 to 1538 symbol times.

[0129] - When the link is operating in SRIS, the bit corresponding to the current link speed can be cleared in the low SKP OS generator vector activation field, or the LTSSM is not in the L0 state, the SKP OS can be scheduled to transmit at intervals of less than 154 symbol times.

[0130] In the embodiment, when using 128b / 130b encoding:

[0131] - When the link is not operating in SRIS, or when the bit corresponding to the current link speed is set in the lower SKP OS generator vector activation field, and the LTSSM is in L0 state, the SKP OS can be scheduled to transmit at intervals of 370 to 375 blocks. The loopback slave can operate to meet this requirement until the loopback slave begins to retransmit the received bit stream.

[0132] - When the link is operating in SRIS, the bit corresponding to the current link speed can be cleared in the lower SKP OS generator vector activation field, or the LTSSM is not in L0 state, allowing SKP OS to be scheduled for transmission at intervals shorter than 38 blocks. Loopback slaves can operate to meet this requirement until the loopback slave begins retransmitting the received bit stream.

[0133] - When the LTSSM is in loopback mode and the link is not operating in SRIS, the loopback master can be scheduled to transmit two SKP OSs spaced apart from each other in intervals of 370 to 375 blocks, with a maximum of two blocks per block.

[0134] - When the LTSSM is in the loopback state and the link is operating in SRIS, the loopback master can be scheduled to transmit two SKP OSs spaced apart from each other in intervals of less than 38 blocks and in a manner of up to two blocks.

[0135] - The control SKP OS can only be transferred at the following times.

[0136] When the data rate is 16.0 GT / s and the data stream is being transmitted, the standard SKP OS and the control SKP OS can be transmitted alternately relative to the SKPOS transmitted within the data stream.

[0137] When the data rate is 16.0 GT / s, and the LTSSM is in either Configuration.Idle or Recovery.Idle state, the aforementioned minimum constant interval requirement may not apply to the immediate transmission of control over the SKP OS. After the transmitter transmits a control instance of the SKP OS, the transmitter can reset the SKP OS's scheduling interval timer.

[0138] In this embodiment, scheduled SKP OSs are transmitted even when a data packet or ordered set (OS) is not in progress. Otherwise, SKP OSs can be accumulated. Therefore, SKP OSs can be continuously inserted into the boundaries of the next data packet or the next OS. For reference, when using 128b / 130b encoding, SKP OSs cannot be transmitted in consecutive blocks within the data stream.

[0139] In an embodiment, when monitoring consecutive symbols or OSs, the SKP OS may not be able to be calculated due to pauses (e.g., 8 consecutive TS1 OSs in a polling active state).

[0140] In the embodiments, when using 8b / 10b encoding: When compliance mode or a modified compliance mode is polling for compliance, and the compliance SOS bit in the link control 2 register is 0b, the SKP OS may not be transmitted. When using 8b / 10b encoding, and the compliance SOS bit in the link control 2 register is 1b, while compliance mode or a modified compliance mode is in progress, two (instead of one) consecutive SKP OSs may be transmitted for all scheduled SKP OS time intervals.

[0141] In this embodiment, when using 128b / 130b encoding: the compliance SOS register bits are unaffected. During the polling of compliance status, the transmitter may only transmit the SKP OS that is designated as a specific portion in the modified compliance mode.

[0142] In an embodiment, when the transmitter is electrically idle, the counter used to retain the SKP OS or another mechanism can be reset.

[0143] Receiver rules

[0144] In this embodiment, when using 8b / 10b encoding, the receiver can identify the received SKP OS in a predetermined manner. When using 128b / 130b encoding, the receiver can identify the received SKPOS in a predetermined manner.

[0145] In the embodiments, except for what happens during the Loopback.Active state, the length of the received SKP OS may remain unchanged for each channel of the multi-channel link.

[0146] In the embodiments, when the link in a lower SKP OS receiver supporting the velocity vector field is not operating in SRIS, or when the link is not operating with the bits used to set the current link speed, and when using 8b / 10b encoding, the receiver can receive and process SKP OS at an average interval of 1180 to 1538 symbol times. Furthermore, when using 128b / 130b encoding, the receiver can receive and process SKP OS at an average interval of 370 to 375 blocks. When the link is operating in SRIS and when using 8b / 10b encoding, the receiver can receive and process SKP OS at an average interval of 154 symbol times. Furthermore, when using 128b / 130b encoding, the receiver can receive and process SKP OS at an average interval of less than 38 blocks.

[0147] In some implementations, a transmitter that is electrically idle does not need to reset the time-based scheduling mechanism of the SKP OS. Therefore, after the receiver becomes electrically idle, it can receive and process the first scheduled SKP OS within a shorter time than the average time interval of the SKP OS.

[0148] In an embodiment, at a data rate of 8.0 GT / s or higher, the receiver in L0 state can check for the presence of any data blocks with EDS tokens before each SKP OS.

[0149] In this embodiment, the receiver can continuously receive and process SKP OS at data rates of 2.5GT / s and 5.00GT / s.

[0150] The receiver can receive and process SKP OS at the maximum interval, depending on the Max_Payload_Size supported by the receiver's components. At data rates of 2.5 GT / s and 5.00 GT / s, the formula for the maximum number of symbols N between SKP OSes can be N = 1538 + (Max_payload_size_byte + 28). For example, when Max_Payload_Size is 4096 bytes, N = 1538 + 4096 + 28 = 5662.

[0151] Figure 9 This is a diagram illustrating the state of a resilient buffer according to an embodiment of the disclosed technology.

[0152] Reference Figure 9 The diagram shows the first to third states 91 to 93 of the elastic buffer when communication is performed between PCIe systems.

[0153] A resilient buffer can temporarily store data to be transmitted or received. Specifically, a resilient buffer can be included in each of the transmitting and receiving sides. The resilient buffer can temporarily store SKP OS and data blocks. PCIe systems can prevent overflow or underflow by using SKP OS. Specifically, in Gen3 or higher of the Gen3 / 4 / 5 PCIe-based specifications, with a common reference clock or SRNS, the PCIe system can transmit SKP OS every 370 to 375 data blocks. With SRIS, the PCIe system can transmit SKP OS every 37 data blocks. However, transmitting SKP OS without considering the clock difference between PCIe systems can lead to performance degradation caused by unnecessary SKP OS. Specifically, with SRNS clock differences of 600 ppm or greater between PCIe systems, overflow or underflow cannot be prevented. Furthermore, with SRIS clock differences of 5600 ppm or greater between PCIe systems, overflow or underflow cannot be prevented.

[0154] According to embodiments of the disclosed technology, the optimal SKP OS interval can be applied in real time, regardless of the common reference clock, SRNS, or SRIS. In embodiments, when the PCIe system uses SRNS or SRIS mode, performance can be improved by removing unnecessary SKP OS. Optionally, when further SKP OS is needed, the PCIe system can be prevented from entering a recovery state by adding an optimal number of SKP OS, and data loss can be prevented by preventing link down.

[0155] Referring to the first state 91 of the elastic buffer, the PCIe system on the transmitting side can transmit data blocks and SKP OS by adding more SKP OSs than the traditional number of SKP OSs, and the elastic buffer on the receiving side can remove the added SKP OSs. When the clock on the transmitting side is faster than the clock on the receiving side in SRIS or SRNS, the elastic buffer on the receiving side removes the added SKP OSs, thereby preventing overflow. Additionally, generating additional SKP OSs on the transmitting side can reduce the data block transmission speed. Furthermore, it can prevent data loss or entering a recovery state. When removing SKP OSs, the PCIe system cannot remove all SKP OSs existing in the elastic buffer. The PCIe system can reduce the length of the SKP OSs by removing only some of the SKP OSs existing in the elastic buffer according to PCI / PCIe rules.

[0156] Referring to the second state 92 of the elastic buffer, the receiver-side elastic buffer can prevent underflow by increasing the length of the received SKP OS. Specifically, when the receiver-side clock is faster than the transmitter-side clock in SRIS or SRNS, the receiver-side elastic buffer can prevent underflow by adding SKP OS. In some implementations, the receiver-side elastic buffer can add SKP OS only when it receives SKP OS from the transmitter side.

[0157] Referring to the third state 93 of the elastic buffer, the PCIe system at the transmitting end can transmit fewer SKP OSs than the traditional SKP OSs, thereby achieving maximum PCIe efficiency. Specifically, when there is almost no clock difference between the transmitting and receiving sides (e.g., in the case of a common reference clock), the probability of overflow or underflow is extremely low. Therefore, transmitting data blocks instead of SKP OSs maximizes communication efficiency.

[0158] Figure 10 This is a diagram illustrating the configuration of the physical layer according to an embodiment of the disclosed technology.

[0159] Reference Figure 10 Physical layer 140 may include components for transmitting data packets to external PCIe systems. Specifically, physical layer 140 may include encoder / decoder 150, SKP OS control logic 160, elastic buffer 170, transceiver 180, and clock signal generator 190.

[0160] The encoder / decoder 150 can be a component used to encode and decode data packets for serialization and deserialization purposes. For example, the encoder / decoder 150 can encode DLLPs received from the data link layer 130, and the physical layer 140 can convert the encoded DLLPs into a serialization format. Furthermore, the encoder / decoder 150 can decode data packets received from external devices.

[0161] SKP OS control logic 160 can generate SKP OS and control the transmission interval. In some implementations, SKP OS control logic 160 can generate SKP OS. SKP OS control logic 160 can control transceiver 180 to control the transmission interval. (See also...) Figure 11 Detailed description of SKP OS control logic 160.

[0162] The elastic buffer 170 can temporarily store data packets received from external devices. For example, the elastic buffer 170 can temporarily store SKP OS and data blocks received via transceiver 180. Furthermore, the elastic buffer 170 can remove or add received SKP OS. For example, because a PCIe system may enter a recovery state from an overflow or underflow state, the elastic buffer 170 can remove temporarily stored SKP OS to prevent the capacity from reaching the maximum overflow state. Conversely, the elastic buffer 170 can add received SKP OS to prevent the capacity from reaching the minimum underflow state.

[0163] Transceiver 180 may include a phase-locked loop (PLL) circuit, a transmitter Tx, and a receiver Rx. The PLL circuit can generate a clock signal to be supplied to the transmitter Tx or the receiver Rx using a clock signal provided from a clock signal generator 190. The PLL circuit can generate a clock signal with a changed frequency by multiplying the signal received from the clock signal generator 190. For example, the PLL circuit can multiply a reference clock signal REFCLK with a frequency of 100 MHz to a clock signal with a frequency of 2.5 GHz. The transmitter Tx can convert a parallel data signal into a serial data signal using the output signal of the PLL circuit and transmit the serial data signal to an external device, such as an external PCIe system. The receiver Rx can receive the serial data signal transmitted from the external device and, by using the output signal of the PLL circuit, generate a clock signal for recovering the received serial data signal and a clock signal for converting the recovered serial data signal into a parallel data signal.

[0164] Clock generator 190 can generate a reference clock signal REFCLK for operation of the PCIe interface. The PCIe interface can communicate with external devices. For example, clock generator 190 can automatically detect whether a clock signal is being provided from the PCIe system and generate an internal clock signal based on the detection result. When a clock signal is being provided from the PCIe system, clock generator 190 can use the clock signal received from the PCIe system. In some embodiments, clock generator 190 can transmit the reference clock signal REFCLK to SKP OS control logic 160 and transceiver 180.

[0165] Figure 11 This is a diagram illustrating the SKP OS control logic according to an embodiment of the disclosed technology.

[0166] Reference Figure 11 The SKP OS control logic 160 may include a central processing unit (CPU) 161, a register 163, and an SKPOS counter 165.

[0167] CPU 161 typically controls operations used for creating and removing SKP OS. For example, CPU 161 can control the transceiver to increase or decrease the SKP OS transmission interval. In some embodiments, CPU 161 can control the SKP OS transmission interval in response to a recovery state entry or a recovery state entry request. In some embodiments, CPU 161 can calculate the frequency of recovery state entry corresponding to the transmission interval. CPU 161 can increase or decrease the SKP OS transmission interval based on the frequency of recovery state entry. CPU 161 can increase or decrease the transmission interval by a predetermined amount. When the PCIe system does not enter recovery state within a predetermined time, CPU 161 can store the current SKP OS transmission interval in register 163 and fix the SKP OS transmission interval.

[0168] CPU 161 can determine whether a recovery state has been entered due to an increase or decrease in the transmission interval of the SKP OS. In some embodiments, the link state of the PCIe system can enter a recovery state upon request from another PCIe system linked to it. For example, when the PCIe system receives a training sequence TS1 transmitted from another PCIe system, the PCIe system can enter a recovery state. When the PCIe system enters a recovery state, CPU 161 can examine the reason for the PCIe system entering the recovery state. In some embodiments, CPU 161 can examine the reason for the PCIe system entering the recovery state due to another PCIe system in the following order. In some embodiments, when the recovery state does not correspond to the following, CPU 161 can identify that the PCIe system entered the recovery state due to an increase or decrease in the transmission interval of the SKP OS:

[0169] 1. Speed ​​change request

[0170] 2. Rebalancing request

[0171] 3. Channel reduction or channel configuration upgrade (upconfigure) request.

[0172] 4. Hot reset, disable, or loopback request

[0173] 5. Replay timeout or replay flip.

[0174] Speed ​​change requests can be made by any of the connected ports to request a speed change (e.g., a speed change request from Gen1 to Gen3). Any of the connected ports can request a speed change by setting the speed change bit of TS1 or TS2 to 1. Rebalancing requests can be made by any of the connected ports to request a change in the EQ coefficients. Any of the connected ports can request rebalancing by setting the request equalization bit of TS2 to 1. Additionally, channel reduction or channel configuration upgrade requests can be made by any of the connected ports to request an increase or decrease in channel width. For example, a channel reduction or channel configuration upgrade request can request a change from channel 1 to channel 4 or from channel 4 to channel 1. Hot reset, disable, or loopback requests are state change requests made by any of the connected ports. A state change can be requested by setting the hot reset bit, disable bit, or loopback bit. When an LCRC error occurs, a replay timeout or replay flip can be performed to request a return to the recovery state of the status port from a port receiving a certain number or more negative acknowledgments (NAK).

[0175] When the recovery state enters a phase corresponding to an increase in the transmission interval of the SKP OS, CPU 161 can reduce the transmission interval by half the increment. In some embodiments, the CPU determines the increase in the transmission interval corresponding to the SKP OS based on whether the CPU previously increased the transmission interval. When the recovery state enters a phase corresponding to a decrease in the transmission interval of the SKP OS, CPU 161 can increase the transmission interval by half the decrease. In some embodiments, the CPU determines the decrease in the transmission interval corresponding to the SKP OS based on whether the CPU previously decreased the transmission interval. CPU 161 can control the transmission interval based on the elastic buffer state of an external device.

[0176] Register 163 can store the transmission history of the SKP OS. In some implementations, register 163 can store the transmission history, which includes the transmission interval of the SKP OS, the number of transmission interval control operations of the SKP OS counted by the SKP OS counter 165, each change of the transmission interval of the SKP OS, the frequency of recovery state entry per unit time, etc.

[0177] The SKP OS counter 165 can count the transmissions of SKP OS. The SKP OS counter 165 can provide information to the CPU 161 or register 163 indicating that an SKP OS has been transmitted. In some implementations, the CPU 161 can calculate the SKP OS transmission interval based on the information provided by the SKP OS counter 165.

[0178] Figure 12This is a diagram illustrating a method of operating a PCIe system according to an embodiment of the disclosed technology.

[0179] Figure 12 The method of operation performed when the PCIe system receives a recovery request is illustrated. The PCIe system and an external device physically connected to the PCIe system (e.g., another PCIe system) can enter the linked and L0 states (S1210).

[0180] When the PCIe system receives a recovery state entry request from the PCIe kernel or PCIe host (S1220 - Yes), the PCIe system can calculate the recovery state entry frequency (S1230). In some implementations, the PCIe system can calculate the entry requests or entry frequency for entering the recovery state per unit time. The recovery state entry request can be made based on the SKP OS or the elastic buffer state on the receiving side.

[0181] The PCIe system can determine whether to increase or decrease the SKP OS transmission interval based on the SKP OS transmission history (S1240). The transmission history may include at least one of a change in the transmission interval or a recovery state entering the frequency corresponding to the transmission interval. When the PCIe system does not control the SKP OS transmission interval (S1240 - No), the PCIe system can decrease the SKP OS transmission interval (S1250).

[0182] In some implementations, when the PCIe system controls the SKP OS transfer interval (S1240 - Yes), the PCIe system can determine whether the SKP OS transfer interval was increased just before the entry request to enter the recovery state (S1245). If the PCIe system did not increase the SKP OS transfer interval just before the entry request to enter the recovery state (S1245 - No), the PCIe system can decrease the SKP OS transfer interval (S1250).

[0183] In some implementations, when the PCIe system increases the SKP OS transfer interval just before the entry request to enter the recovery state (S1245-Yes), the PCIe system can reduce the SKP OS transfer interval by exactly half of the increment before the entry request to enter the recovery state (S1260). Reducing the SKP OS transfer interval means that the PCIe system transfers SKP OS more frequently. Therefore, reducing the SKP OS transfer interval can mean that the PCIe system transfers a larger amount of SKP OS.

[0184] Figure 13 This is a diagram illustrating a method of operating a PCIe system according to an embodiment of the disclosed technology.

[0185] Figure 13 The method of operation performed when the PCIe system does not receive a request to enter the recovery state is illustrated. The PCIe system and external devices physically connected to the PCIe system (e.g., another PCIe system) can enter the linked and L0 states (S1210). Furthermore, even when the PCIe system does not receive a recovery state entry request from the PCIe kernel or the PCIe host, the PCIe system can control the transfer interval of the SKP OS (S1220 - No).

[0186] The PCIe system can maintain a stable state if it does not enter a recovery state for a predetermined time T. The stable state is the L0 state, which can be a state in which the PCIe system smoothly communicates with external devices while the link is active. When the stable state is maintained for a longer period than the predetermined time T (S1310 - Yes), the PCIe system can compare the increase / decrease in the SKP OS transmission interval with a predetermined number N (S1320).

[0187] When the increase / decrease in the transmission interval of the SKP OS exceeds a predetermined number (S1320 - Yes), the PCIe system can suspend the control of the transmission interval of the SKP OS. On the other hand, when the increase / decrease in the transmission interval of the SKP OS is less than the predetermined number (S1320 - No), the PCIe system can determine whether the transmission interval of the SKP OS has decreased just before the recovery state entry request (S1330).

[0188] When the PCIe system does not reduce the SKP OS transmission interval (S1330 - No), the PCIe system can increase the SKP OS transmission interval to increase communication efficiency (S1340). Alternatively, when the PCIe system reduces the SKP OS transmission interval (S1330 - Yes), the PCIe system can increase the SKP OS transmission interval by exactly half the amount reduced before the recovery state entry request, to increase communication efficiency (S1350). Increasing the SKP OS transmission interval means that the PCIe system transmits less SKP OS. Therefore, increasing the SKP OS transmission interval means that the PCIe system transmits less SKPOS.

[0189] The protocol using PCIe has been described in detail in this specification. However, the disclosed techniques can be applied to protocols other than PCIe that use virtual data corresponding to the SKP OS. That is, it will be apparent that the disclosed techniques can be modified and implemented in protocols other than PCIe to control virtual data or free data in order to prevent underflow or overflow of the elastic buffer.

[0190] According to the disclosed technology, an improved PCIe interface and an interface system including the PCIe interface can be provided.

[0191] Although the present disclosure has been shown and described with reference to specific exemplary embodiments of the disclosed technology, those skilled in the art will understand that various changes in form and detail may be made to the disclosed technology without departing from the spirit and scope of the disclosed technology as defined by the appended claims and their equivalents. Therefore, the scope of the disclosed technology should not be limited to the exemplary embodiments described above, but should be determined not only by the appended claims but also by their equivalents.

[0192] In the above embodiments, all or some of the steps may be selectively performed, and these steps may be omitted. In each embodiment, these steps are not necessarily performed in the described order and may be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to facilitate understanding of the disclosed technology, and the disclosed technology is not limited thereto. That is, those skilled in the art should understand that various modifications can be made based on the technical scope of the disclosed technology.

[0193] Exemplary embodiments of the disclosed technology are described in the accompanying drawings and specification. Based on what is disclosed and shown in this patent document, variations and enhancements to the disclosed embodiments and other embodiments are possible.

Claims

1. A high-speed peripheral component interconnect device, i.e., a PCIe device, comprising: Transceiver, used for transmitting and receiving data; as well as Skipping the ordered set control logic, i.e., the SKP OS control logic, it communicates with the transceiver, generates the SKP OS, and controls the transceiver to transmit the SKP OS and data blocks to a link that connects to external devices and includes multiple channels. The SKP OS control logic, in response to the link entering a recovery state, increases or decreases the SKP OS transmission interval based on the SKP OS's transmission history. This recovery state is used to recover the link from errors. The SKP OS control logic includes an SKP OS counter, which counts the transmission intervals of the SKP OS.

2. The PCIe device according to claim 1, wherein the SKP OS control logic further comprises: The central processing unit, i.e., the CPU, controls the transceiver to increase or decrease the transmission interval of the SKP OS; as well as The register stores the transmission history.

3. The PCIe device according to claim 1, wherein the transmission history includes at least one of the transmission interval of the SKP OS, the change of the transmission interval, and the frequency of occurrence of entering the recovery state corresponding to the transmission interval.

4. The PCIe device of claim 1, wherein the SKP OS control logic further calculates the frequency at which the state of entry into recovery occurs corresponding to the transmission interval, and increases or decreases the transmission interval of the SKP OS based on the frequency.

5. The PCIe device of claim 1, wherein the SKP OS control logic increases or decreases the transmission interval up to a predetermined number.

6. The PCIe device according to claim 1, wherein the SKP OS control logic further fixes the transmission interval if no request to enter the recovery state is received within a predetermined time.

7. The PCIe device of claim 1, wherein, upon entering a recovery state corresponding to the increase in the transmission interval, the SKP OS control logic reduces the transmission interval by half of the increment of the transmission interval.

8. The PCIe device of claim 1, wherein when entering a recovery state corresponding to the reduction of the transmission interval, the SKP OS control logic increases the transmission interval by half of the reduction in the transmission interval.

9. The PCIe device of claim 1, wherein the SKP OS control logic increases or decreases the SKP OS transmission interval based on the state of the elastic buffer of the external device.

10. The PCIe device of claim 1, wherein the SKP OS comprises a format according to a protocol based on the PCIe bus interface standard.

11. A high-speed peripheral component interconnect system, i.e., a PCIe system, comprising: The first high-speed peripheral component interconnect device, namely the first PCIe device, and The second PCIe device is connected to and communicates with the first PCIe device via a link that includes multiple channels. The first PCIe device generates a skipped ordered set, i.e., SKP OS, and in response to the link entering a recovery state, increases or decreases the transmission interval of the SKP OS based on the state of the elastic buffer of the second PCIe device. The first PCIe device includes an SKP OS counter, which counts the transmission intervals of the SKP OS.

12. The system of claim 11, wherein the resilient buffer temporarily stores the SKP OS received from the first PCIe device.

13. The system of claim 11, wherein the states of the resilient buffer include an overflow state where the capacity of the resilient buffer becomes maximum, an underflow state where the capacity of the resilient buffer becomes minimum, and a normal state where there are no errors for a predetermined time or longer.

14. The system of claim 13, wherein the resilient buffer removes the SKP OS to prevent the overflow state.

15. The system of claim 13, wherein the resilient buffer is added to the SKP OS to prevent the underflow state.

16. The system of claim 13, wherein when the resilient buffer is in the overflow state or the underflow state, the first PCIe device reduces the transmission interval of the SKP OS in response to entering the recovery state.

17. The system of claim 13, wherein after entering the recovery state, while the resilient buffer is in the normal state, the first PCIe device increases the transmission interval of the SKP OS.

18. The system of claim 11, wherein the first PCIe device increases or decreases the transmission interval of the SKP OS based on the transmission history of the SKP OS.

19. The system of claim 18, wherein the transmission history includes at least one of the transmission interval of the SKP OS, the change of the transmission interval, and the frequency of occurrence of entering the recovery state corresponding to the transmission interval.

20. The system of claim 11, wherein the SKP OS comprises a format according to a PCIe-based protocol.

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