Hash table processing method, apparatus, device, and computer-readable storage medium

Abstract

The present disclosure relates to a hash table processing method, device, equipment and computer readable storage medium. According to the present disclosure, the memory space is allocated for the target hash table according to the obtained configuration information, so that the memory space can be reasonably allocated for the target hash table according to the configuration information, and the waste of memory resources is avoided. Further, the present disclosure acquires multiple instructions for the target hash table in parallel through multiple instruction channels, improves the efficiency of acquiring instructions, then accesses the memory space through a read memory channel, serially reads the first data in the target hash table corresponding to each instruction, and compares the first data with the second data corresponding to each instruction, and according to the comparison result, the execution mode of each instruction is processed in parallel, which improves the efficiency of processing the execution mode of each instruction. Therefore, based on the improvement of the efficiency of acquiring instructions and the improvement of the efficiency of processing the execution mode of each instruction, the overall processing efficiency of the hash table processing instruction is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of databases, and in particular, to a hash table processing method and device, equipment and a computer readable storage medium. BACKGROUND

[0002] With the development of science and technology, data information is becoming more and more abundant, and the amount of data is also increasing. In order to manage a large amount of data, a database is usually used to manage data. Since the hash table can concisely and efficiently process insertion instructions, deletion instructions and query instructions, realize the insertion, deletion and query of data, and meet the user's demand for managing a large amount of data, the hash table has been widely used.

[0003] However, due to different hash table structure designs and different data processing methods, in the prior art, the hash table mainly has the following problems in processing data. 1. The allocated memory of each hash table may not be fully used, resulting in waste of memory resources. 2. When processing each instruction, the hash table processes one instruction and then processes another instruction, resulting in low processing efficiency. SUMMARY

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a hash table processing method, device, equipment and computer readable storage medium.

[0005] In a first aspect, the present disclosure provides a hash table processing method, comprising:

[0006] In response to an operation of configuring a hash table structure, obtaining configuration information of a target hash table, and allocating a memory space corresponding to the configuration information to the target hash table;

[0007] After allocating the memory space, a plurality of instructions for the target hash table are obtained in parallel through a plurality of instruction channels; wherein the instruction types obtained by each instruction channel are different;

[0008] Accessing the memory space through a read memory channel to serially read first data in the target hash table corresponding to each instruction;

[0009] Comparing the first data in the target hash table corresponding to each instruction with second data corresponding to each instruction, and processing the execution mode of each instruction in parallel based on the comparison result;

[0010] Serially executing each instruction based on the execution mode of each instruction.

[0011] In a second aspect, the present disclosure provides a hash table processing device, comprising:

[0012] The obtaining and allocating module is configured to, in response to an operation of configuring a hash table structure, obtain configuration information of a target hash table, and allocate a memory space corresponding to the configuration information to the target hash table;

[0013] The parallel receiving module is configured to, after the memory space is allocated, receive a plurality of instructions for the target hash table in parallel through a plurality of instruction channels; each instruction channel obtains instructions of different types;

[0014] The serial reading module is configured to access the memory space through a reading memory channel, and read first data in the target hash table corresponding to each instruction in series.

[0015] The data comparison module is configured to compare the first data in the target hash table corresponding to each instruction with second data corresponding to each instruction, and process an execution mode of each instruction in parallel based on a comparison result.

[0016] The serial execution module is configured to execute each instruction in series based on the execution mode of each instruction.

[0017] In a third aspect, the present disclosure provides a hash table processing device, comprising:

[0018] A processor;

[0019] A memory configured to store executable instructions;

[0020] The processor is configured to read the executable instructions from the memory and execute the executable instructions to implement the hash table processing method of the first aspect.

[0021] In a fourth aspect, the present disclosure provides a computer readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the processor implements the hash table processing method of the first aspect.

[0022] The technical solution provided by the embodiments of the present disclosure has the following advantages compared with the prior art:

[0023] The hash table processing method, apparatus, device, and computer-readable storage medium disclosed in this invention allocate memory space for a target hash table based on acquired configuration information, enabling reasonable allocation of memory space according to the configuration information and avoiding waste of memory resources. Furthermore, this invention improves the efficiency of instruction acquisition by acquiring multiple instructions for the target hash table in parallel through multiple instruction channels; then, it accesses the memory space through a read memory channel, serially reading the first data in the target hash table corresponding to each instruction; and compares the first data with the second data corresponding to each instruction, processing the execution mode of each instruction in parallel based on the comparison result, thus improving the efficiency of processing the execution mode of each instruction. Therefore, based on the improved efficiency of instruction acquisition and the improved efficiency of processing the execution mode of each instruction, the overall processing efficiency of hash table processing instructions is improved. Attached Figure Description

[0024] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0025] Figure 1 A flowchart illustrating a hash table processing method provided in an embodiment of this disclosure;

[0026] Figure 2 A schematic diagram of a hash table structure provided in an embodiment of this disclosure;

[0027] Figure 3 A schematic diagram illustrating the implementation principle of a hash table processing method provided in this embodiment of the disclosure;

[0028] Figure 4 A flowchart illustrating another hash table processing method provided in this embodiment of the disclosure;

[0029] Figure 5 A schematic diagram illustrating the implementation principle of another hash table processing method provided in this embodiment of the disclosure;

[0030] Figure 6 This is a schematic diagram of the structure of a hash table processing device provided in an embodiment of the present disclosure;

[0031] Figure 7 This is a schematic diagram of the structure of a hash table processing device provided in an embodiment of the present disclosure. Detailed Implementation

[0032] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0033] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0034] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0035] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0036] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0037] With the development of science and technology, data information is becoming increasingly abundant and the volume of data is growing larger. To manage large amounts of data, database management systems are typically used. Hash tables are widely used because they can concisely and efficiently handle insert, delete, and query commands, enabling data insertion, deletion, and retrieval, and meeting users' needs for managing large amounts of data.

[0038] However, existing technologies for processing data using hash tables have several problems: 1. When designing a hash table, memory space is evenly allocated to each hash table, which means that the allocated memory for each hash table may not be fully utilized, resulting in wasted memory resources. 2. When processing instructions, each instruction is executed completely serially, leading to low processing efficiency.

[0039] To address the aforementioned problems, this disclosure provides a hash table processing method, apparatus, device, and computer-readable storage medium. The hash table processing method will first be described below with reference to specific embodiments.

[0040] Figure 1 This is a flowchart illustrating the hash table processing method provided in this embodiment. The hash table processing method in this embodiment can be executed by a hash table processing device, which can be an electronic device or a server. Electronic devices include, but are not limited to, smartphones, PDAs, tablets, wearable devices with displays, desktop computers, laptops, all-in-one computers, smart home devices, etc. Servers can be independent servers or clusters of multiple servers, and can include servers built locally and servers hosted in the cloud.

[0041] Before introducing the hash table processing method provided in the embodiments of this disclosure, the hash table structure applicable to the embodiments of this disclosure will be introduced first.

[0042] Figure 2 A schematic diagram of a hash table structure applicable to embodiments of this disclosure is provided, such as... Figure 2 As shown, for any hash table, each hash table consists of an array and a doubly linked list. Specifically, the array can be a collection of multiple hash buckets, with one array element corresponding to one hash bucket. Each hash bucket corresponds to a different hash value, and each hash bucket stores data with the same hash value.

[0043] When the data carried in an instruction to be processed collidees with data already stored in a hash bucket, the data carried in the instruction will be stored in a node of the doubly linked list corresponding to that hash bucket. It can be understood that when the data carried in multiple instructions all collide with data already stored in a hash bucket, the data carried in the multiple instructions will be stored sequentially in multiple nodes of the doubly linked list.

[0044] For any doubly linked list node, each doubly linked list node specifically includes: the storage address of the previous doubly linked list node (prev), the storage address of the next doubly linked list node (next), the hash code of the current doubly linked list node, the flag indicating whether the data of the current doubly linked list node is valid, and the data stored in the current doubly linked list node (data).

[0045] Figure 3 The following is a schematic diagram illustrating the implementation principle of the hash table processing method provided in this embodiment of the disclosure. Figure 2 and Figure 3 right Figure 1 The hash table processing method shown will be introduced, such as... Figure 1 As shown, this hash table processing method includes the following steps:

[0046] S101. In response to the operation of configuring the hash table structure, obtain the configuration information of the target hash table and allocate memory space corresponding to the configuration information for the target hash table.

[0047] Typically, when users allocate memory space to hash tables, they distribute the memory space evenly across all hash tables based on the number of hash tables. This ensures that each hash table receives the same amount of memory. However, in practical applications, the amount of data stored in each hash table is usually different, which may result in some hash tables receiving insufficient memory while others do not fully utilize the allocated memory.

[0048] Furthermore, in the embodiments of this disclosure, such as Figure 3 As shown, the hash table processing device receives and responds to a configuration hash table structure request through the configuration hash table channel. Based on the hash table identification information carried in the request, it determines the target hash table for which memory space needs to be allocated, and allocates the memory space corresponding to the configuration information to the target hash table based on the configuration information carried in the request.

[0049] The configuration information of the target hash table includes, but is not limited to, the number of hash buckets, the size of the hash buckets, and the number of doubly linked list nodes.

[0050] The number of hash buckets is the total number of hash buckets that can be included in the target hash table. The hash bucket size is the amount of space that each hash bucket in the hash table can store data in. The number of doubly linked list nodes is the total number of nodes that each doubly linked list can include.

[0051] Based on the above configuration information, the memory space allocated for the target hash table can be calculated.

[0052] Optionally, the memory space allocated to the target hash table can be calculated based on the number of hash buckets, the size of the hash buckets, and the number of nodes in the doubly linked list. Specifically, the memory space allocated to the target hash table can be calculated as: number of hash buckets × hash bucket size × number of nodes in the doubly linked list.

[0053] It is understandable that this step allocates memory space corresponding to the configuration information of the target hash table. This includes allocating memory space corresponding to the configuration information of the target hash table when creating a new hash table, and also allocating memory space corresponding to the configuration information of the target hash table when modifying the configuration information of the target hash bucket.

[0054] It should be noted that this step is a prerequisite for processing each instruction and is executed only after the hash table channel receives the request to configure the hash table structure. Once the hash table configuration is complete, this step does not need to be executed every time subsequent steps S102-S105 are performed.

[0055] S102. After allocating memory space, multiple instructions for the target hash table are received in parallel through multiple instruction channels; wherein, the instruction type obtained by each instruction channel is different.

[0056] Because the target hash table can handle three types of instructions: insert, delete, and query.

[0057] To improve the efficiency of hash table processing, in this embodiment of the disclosure, multiple instruction channels are configured to receive instructions, and the instruction types received by each instruction channel are set to be different.

[0058] For example, such as Figure 3 As shown, two command channels can be configured to receive commands: command channel 0 and command channel 1. Command channel 0 is configured to receive insert and delete commands, while command channel 1 receives query commands.

[0059] Alternatively, three command channels can be set up to receive commands: command channel 2, command channel 3, and command channel 4. Command channel 2 can be set to receive insert commands, command channel 3 to receive delete commands, and command channel 4 to receive query commands.

[0060] The above command channels are merely illustrative examples. In actual use, they can be set as needed, and this disclosure does not limit them.

[0061] It is understood that, since the embodiments of this disclosure are configured with multiple instruction channels to receive instructions, the multiple instruction channels can receive multiple instructions of different instruction types in parallel in the embodiments of this disclosure.

[0062] S103. Access the memory space through the memory read channel to serially read the first data in the target hash table corresponding to each instruction.

[0063] In this embodiment of the disclosure, when the hash table processes an insert instruction, a delete instruction, or a query instruction, it calculates the hash value corresponding to the key value based on the key value included in the data carried in the instruction, finds the hash bucket address that is equal to the hash value from the target hash table, and determines the hash bucket based on the hash bucket address.

[0064] Then, the data in the hash bucket corresponding to the hash bucket address or the data of the doubly linked list node are read from the memory space, and the read data is used as the first data.

[0065] Since existing technologies use only one memory channel for processing hash tables, this embodiment reads the first data corresponding to each instruction serially, i.e., reading the first data corresponding to each instruction from the target hash table sequentially according to the instruction priority. The instruction priority can be customized, and this embodiment does not limit this setting.

[0066] like Figure 3 As shown, the instruction channel includes instruction channel 0 and instruction channel 1, and there is only one memory read channel. Therefore, the first data corresponding to the instruction can be read from the target hash table in order according to the priority of the instruction.

[0067] S104. Compare the first data in the target hash table corresponding to each instruction with the second data corresponding to each instruction, and process the execution mode of each instruction in parallel based on the comparison result.

[0068] In this embodiment of the disclosure, comparing the first data in the target hash table corresponding to each instruction with the second data corresponding to each instruction can specifically involve comparing the key values ​​included in the first data and the key values ​​included in the second data. The comparison of key values ​​is prior art and will not be elaborated upon here.

[0069] In some embodiments, the second data corresponding to each instruction may be the data carried in each instruction.

[0070] In other embodiments, the second data corresponding to each instruction may also be obtained by adjusting the bit width of the data carried in each instruction.

[0071] Specifically, typically, the bit width of each instruction channel in step S102 is different from the bit width of the read memory channel in step S103. Specifically, the number of bits of data that each instruction channel can transmit within one clock cycle is different from the number of bits of data that the read memory channel can transmit.

[0072] Furthermore, the bit width of the read memory channel is usually greater than the bit width of each instruction channel. That is, the amount of data that can be transferred in one clock cycle of the read memory channel is greater than the amount of data that can be transferred in one clock cycle of each instruction channel.

[0073] Therefore, before proceeding to subsequent steps after obtaining the data carried in each instruction through each instruction channel, the bit width of this data can be adjusted to be the same as the bit width of the read memory channel. For example, each instruction channel has a bit width of 8 bits, meaning that the instruction channel can transmit 8 bits of data in one clock cycle, and the read memory channel has a bit width of 64 bits, meaning that the read memory channel can transmit 64 bits of data in one clock cycle. Therefore, in this embodiment of the disclosure, to improve the processing efficiency of instructions, the 8-bit data can be adjusted to 64 bits after the instruction channel obtains the data carried in each instruction.

[0074] In some embodiments, the comparison result may be determining whether the key value included in the first data and the key value included in the second data are equal.

[0075] In other embodiments, the comparison result may include, in addition to whether the key values ​​included in the first data and the key values ​​included in the second data are equal, information such as pre, next, and flag included in the first data. This avoids multiple interactions between the hash table processing device and the memory space.

[0076] Specifically, in general, when processing instructions, it is necessary to parse the key value included in the first data and the key value included in the second data, as well as the pre, next, and flag included in the first data, to determine the execution method of the instruction.

[0077] Furthermore, when the comparison result only includes whether the key values ​​are equal, if the key values ​​are equal, it is necessary to interact with the memory space again to obtain the pre, next, and flag information corresponding to the key value. When the comparison result includes the pre, next, and flag information, it is not necessary to interact with the memory space again, thus improving the processing efficiency of instructions.

[0078] The following sections will describe how to execute the insert, delete, and query commands.

[0079] A. Insert command.

[0080] The insertion instruction can be executed in several ways: inserting at an array position, insertion failing, inserting at a doubly linked list node, or reading the next doubly linked list node.

[0081] Specifically, as described above, each hash table consists of an array and a doubly linked list. Both array and doubly linked list nodes can store data, and each node in the doubly linked list stores data that has hash collisions. Therefore, for the insertion instruction, if the flag of the data corresponding to the node containing the first data is invalid, it means that the data at this position is invalid, i.e., the position is free and data can be inserted. Therefore, the second data is inserted into this node. Alternatively, if the flag of the node containing the first data is valid, it means that the data is valid, i.e., the position is occupied. Furthermore, if the next parameter of the node containing the first data has no value, it means that the node containing the first data has no next node. Therefore, the second data is inserted into the next node of the node containing the first data.

[0082] The insertion position can be a node in an array or a doubly linked list. Therefore, the insertion instruction can be executed in two ways: inserting at an array or inserting at a node in a doubly linked list.

[0083] When the next node of the node containing the first data has a value, it means that the node containing the first data already has a next node, that is, the next node at this position has already stored data. The hash table processing device will then continue to read the next node of the doubly linked list. Therefore, the execution of the insertion instruction also includes reading the next doubly linked list node.

[0084] When the hash table is out of memory, the network connection times out, or other reasons cause data insertion to fail, it means that the second data insertion has failed. Therefore, the execution mode of the insertion instruction also includes insertion failure.

[0085] B. Delete command.

[0086] The deletion command can be executed in several ways, including deleting from an array, deleting from the last node of a doubly linked list, deleting from a node in the middle of a doubly linked list, deletion failing, and reading the next node in the doubly linked list.

[0087] As described above, each hash table consists of an array and a doubly linked list. Both array and doubly linked list nodes can store data, and each node in the doubly linked list stores data that has hash collisions. Therefore, for a deletion instruction, if the key value of the first data is equal to the key value of the second data, and the flag of the node containing the first data is valid, it indicates that the second data is to be deleted at that position. This position may be a node in the array or a node in the doubly linked list. Therefore, the deletion instruction can be executed in three ways: deleting the data at the array position, deleting the data at the last node of the doubly linked list, or deleting the data at the middle node of the doubly linked list.

[0088] If the key value of the first data is not equal to the key value of the second data, or if the key value of the first data is equal to the key value of the second data, but the flag of the node where the first data is located is invalid, it means that the position is not the second data to be deleted. The hash table processing device will continue to read the next doubly linked list node. Therefore, the execution method of the deletion instruction also includes reading the next doubly linked list node.

[0089] When the key values ​​of the first and second data are different after traversing all nodes, or due to network or other reasons, data deletion may fail, indicating that there is no second data to be deleted in the hash table. Therefore, the execution of the deletion command may also include deletion failure.

[0090] C. Query command.

[0091] The query command can be executed in several ways: query successful, query failed, or the next doubly linked list node is read.

[0092] As described above, each hash table consists of an array and a doubly linked list. Therefore, for a query command, if the key value of the first data is equal to the key value of the second data and the flag of the node containing the first data is valid, it indicates that the location contains the data to be queried. Thus, the execution of a query command can result in a successful query.

[0093] If the key value of the first data is not equal to the key value of the second data, or if the key value of the first data is equal to the key value of the second data but the flag of the first data is invalid, it means that the position is not the data to be queried. The hash table processing device will continue to read the next doubly linked list node. Therefore, the execution method for query instructions also includes reading the next doubly linked list node.

[0094] When the key values ​​of the first and second data in all nodes of a doubly linked list are not equal, or due to network connection timeouts or other reasons, data query failure will occur, indicating that the second data has not been found in the current hash table. Therefore, the execution method of the query instruction also includes the execution method for query failure.

[0095] In this embodiment of the disclosure, after determining the execution mode of each instruction, instructions with different execution modes are processed in parallel.

[0096] Specifically, the aforementioned different types of instructions include different execution methods. Each instruction must correspond to an execution method within a specific type. Therefore, in this embodiment, instructions with different execution methods are processed in parallel.

[0097] For insertion instructions, the instructions that are executed in parallel are those that insert at an array position, those that insert at a doubly linked list node, and those that read the next doubly linked list node.

[0098] For deletion instructions, the following instructions are processed in parallel: deletion at an array position, deletion at the last node of a doubly linked list, deletion at a middle node of a doubly linked list, and reading the next node of a doubly linked list.

[0099] For query commands, commands that execute successfully and read the next doubly linked list node will be processed in parallel.

[0100] It should be noted that the execution methods for the different types of instructions described above all include execution methods for handling failures, namely, the cases of insertion failure, deletion failure, and query failure. In this embodiment of the disclosure, the execution methods for handling failures will be processed in parallel with the other execution methods described above.

[0101] It should also be noted that in practical applications, when processing each instruction with different execution methods in parallel, a mechanism must be added to prevent simultaneous processing of the same array or doubly linked list node. For example, when deletion and insertion instructions process the same doubly linked list node in parallel, a mechanism must be added to prevent simultaneous operation on the same node. This mechanism to prevent simultaneous operation on the same node is existing technology and will not be elaborated upon here.

[0102] S105. Based on the execution method of each instruction, each instruction is executed serially.

[0103] For insertion instructions, when the execution method is to insert at an array or at a doubly linked list node, data needs to be inserted at the corresponding position.

[0104] For deletion commands, when the execution method is to delete at an array, at the last node of a doubly linked list, or at a middle node of a doubly linked list, the data at the corresponding position needs to be deleted.

[0105] The above-described execution methods for insertion and deletion instructions both require writing to a memory channel. However, there is only one memory channel for writing; therefore, when parallel insertion and deletion instructions are executed via the memory channel, each instruction must be executed serially.

[0106] Step S105 involves executing each type of instruction in sequence based on the execution method of each type of instruction. Specifically, this may include: selecting the execution method corresponding to each type of instruction in sequence based on the pre-configured processing priority of different instruction types, and executing the corresponding instructions in sequence based on the selected execution method.

[0107] Specifically, different command types have pre-set processing priorities. For example, the priority of query commands is set to be higher than that of insert commands, and the priority of insert commands is set to be higher than that of delete commands.

[0108] Since insert and delete instructions require data insertion and deletion, in this embodiment of the disclosure, the execution method that requires data processing through a memory channel is determined for the insert and delete instructions.

[0109] Specifically, for the insertion command, when the execution mode is to insert at an array or at a doubly linked list node, data needs to be inserted. For the deletion command, when the execution mode is to delete at an array, at the last node of the doubly linked list, or at a node in the middle of the doubly linked list, data needs to be deleted.

[0110] Therefore, in this embodiment of the disclosure, the priority of the insertion instruction is greater than that of the deletion instruction, and the priority of the insertion position in the array and the insertion position in the doubly linked list node is determined to be higher than the priority of the deletion position in the array, the deletion position in the last node of the doubly linked list, and the deletion position in the middle node of the doubly linked list.

[0111] Furthermore, the priority of the insertion position in the array and the insertion position in the doubly linked list node can be randomly determined or preset. For example, the priority of the insertion position in the array is set to be higher than the priority of the insertion position in the doubly linked list node, and the insertion position is determined according to the preset priority of the insertion position in the array and the insertion position in the doubly linked list node.

[0112] Similarly, the methods for determining the priority of deletion positions in the array, the last node of the doubly linked list, and the middle node of the doubly linked list are based on the same principle as the methods for determining the priority of insertion positions in the array and the doubly linked list, and will not be repeated here.

[0113] Since the execution methods determined in step S104 include multiple types, such as Figure 3 As shown, there is only one write memory channel. Therefore, when the execution mode needs to insert or delete data through the write memory channel, each instruction is executed serially.

[0114] As can be seen, the embodiments of this disclosure can allocate memory space for the target hash table according to the acquired configuration information, enabling reasonable allocation of memory space for the target hash table based on the configuration information and avoiding waste of memory resources. Furthermore, this disclosure improves the efficiency of instruction acquisition by acquiring multiple instructions for the target hash table in parallel through multiple instruction channels; then, it accesses the memory space through a read memory channel, serially reading the first data in the target hash table corresponding to each instruction; and compares the first data with the second data corresponding to each instruction, processing the execution method of each instruction in parallel based on the comparison result, thus improving the efficiency of processing the execution method of each instruction. Therefore, based on the improved efficiency of instruction acquisition and the improved efficiency of processing the execution method of each instruction, the overall processing efficiency of hash table instructions is improved.

[0115] In some embodiments, before step S103 above, the method further includes: selecting second data corresponding to each type of instruction in sequence based on the processing priority of different instruction types that are pre-configured, and caching the second data selected in sequence and the instructions corresponding to the second data selected in sequence; and performing this step again.

[0116] Specifically, the priorities corresponding to different instruction types are preset.

[0117] For example, the priority of query commands can be set to be higher than that of insert commands, and the priority of insert commands can be set to be higher than that of delete commands.

[0118] Since step S102 is executed in parallel and step S103 is executed serially, according to the pre-set priority, the second data corresponding to each type of instruction is selected in sequence, and the selected second data and the instruction corresponding to the selected second data are cached.

[0119] Because this embodiment of the disclosure caches the second data and the instructions corresponding to the sequentially selected second data, subsequent processing steps can directly retrieve the second data and the corresponding instructions from the cache when they require them. Furthermore, this step can be repeated after the data is cached, without waiting for subsequent steps to process the second data and the corresponding instructions.

[0120] As shown above, the delete command is to delete data, and after the data is deleted, the memory space occupied by the deleted data is empty.

[0121] Therefore, in some embodiments, if the instruction type is a delete instruction, and the instruction is executed in a manner where the delete position is at the last node of the target hash table doubly linked list or at the middle node of the hash table doubly linked list, then the space occupied by the node corresponding to the delete position is reclaimed from the memory space.

[0122] The application to reclaim the space occupied by the node corresponding to the deletion location is existing technology, and will not be described in detail in this embodiment.

[0123] As mentioned above, the insertion instruction is to insert data. When inserting data, a space needs to be allocated for the data. Therefore, in this embodiment of the disclosure, for any instruction, if the instruction type is an insertion instruction and the execution method of the instruction is to insert at a node of the doubly linked list of the hash table, then the space occupied by the doubly linked list node of the hash table is allocated from the memory space.

[0124] The application for the space occupied by this node is based on existing technology, and will not be described in detail in this embodiment.

[0125] This embodiment of the disclosure achieves dynamic and real-time management of the space occupied by doubly linked list nodes by applying for and reclaiming the space occupied by doubly linked list nodes, thereby improving the efficiency of memory space utilization.

[0126] Figure 4 This is a flowchart illustrating another hash table processing method provided in an embodiment of this disclosure. Figure 5 The following is a schematic diagram illustrating the implementation principle of the hash table processing method provided in this embodiment of the disclosure. Figure 5 rightFigure 4 This section introduces hash table processing methods. For example... Figure 4 As shown, this hash table processing method includes the following steps:

[0127] S401. In response to the operation of configuring the hash table structure, obtain the configuration information of the target hash table and allocate memory space corresponding to the configuration information for the target hash table.

[0128] In this embodiment of the disclosure, this step is the same as step S101 described above, and will not be repeated here.

[0129] S402. Receive multiple instructions for the target hash table in parallel through multiple instruction channels; wherein, the instruction type obtained by each instruction channel is different.

[0130] like Figure 5 As shown, the instruction channel includes instruction channel 0 and instruction channel 1. Instruction channel 0 processes insert and delete instructions, while instruction channel 1 processes query instructions.

[0131] When instruction channel 0 or instruction channel 1 receives an instruction, it can cache the received instruction into its corresponding data cache unit. That is, after receiving an instruction, instruction channel 0 caches the data carried in the received instruction into its instruction channel 0 data cache unit. After receiving an instruction, instruction channel 1 caches the data carried in the instruction into its instruction channel 1 data cache unit.

[0132] Understandably, because the data carried in each instruction is cached in the corresponding data cache unit, subsequent units that need to process the data can retrieve the data from the cache unit for processing. Instruction channel 0 and instruction channel 1 can repeatedly and continuously receive instructions, thus improving the efficiency of receiving instructions.

[0133] S403. Adjust the bit width of the data carried by each type of instruction to be the same as the bit width of the read memory channel to obtain the second data corresponding to each type of instruction; cache the second data; and execute again to obtain multiple types of instructions for the target hash table in parallel through multiple instruction channels.

[0134] like Figure 5 As shown, when data is available in the instruction channel 0 data cache unit and the instruction channel 1 data cache unit, the instruction channel 0 data adjustment unit and the instruction channel 1 data adjustment unit obtain their respective corresponding data. The bit width of the data carried in the adjustment instruction is the same as the bit width of the read memory channel, thus obtaining their respective second data. These second data are then cached in the bit-width 0 channel data cache unit and the bit-width 1 channel data cache unit, respectively.

[0135] It is understood that in this embodiment of the disclosure, the data adjustment unit caches the second data in the bit-width channel data cache unit. The unit that needs to process the data can obtain the data from the bit-width channel data cache unit for processing. At the same time, the data adjustment unit can repeatedly and continuously adjust the bit width of the data carried in the instruction, thereby improving the instruction processing efficiency.

[0136] S404. Based on the pre-configured processing priorities of different instruction types, select the second data corresponding to each type of instruction in sequence, cache the selected second data and the instruction corresponding to the selected second data, and execute this step again.

[0137] like Figure 5 As shown, since there is only one read memory channel and two instruction channels, when there are multiple instructions, the read data selection unit selects data from the bit-width 0 channel data cache unit and the bit-width 1 channel data cache unit. The read request carried in the instruction is cached in the read request cache unit, and the second data is cached in the bit-width data cache unit.

[0138] The data selection unit selects data based on the priority of pre-set instruction types; that is, higher priority instructions are selected and processed first. For example, the priority of query instructions is pre-set to be higher than that of insert instructions, and insert instructions are pre-set to be higher than those of delete instructions.

[0139] Understandably, because the read request cache unit and the bit-width data cache unit cache the read request and the second data, subsequent units that need to process the data can retrieve the data from the read request cache unit and the bit-width data cache unit for processing. Therefore, the read data selection unit can repeatedly and continuously select data, improving instruction processing efficiency.

[0140] S405. Access the memory space through the memory read channel to serially read the first data in the target hash table corresponding to each instruction.

[0141] like Figure 5 As shown, when the read request cache unit and the bit width data cache unit have cached requests and data, the read memory channel obtains the read request cached by the read request cache unit and the data cached by the bit width data cache unit, queries the hash table configuration information, determines the first data in the hash table corresponding to the instruction, and caches the first data in the read memory data cache unit.

[0142] Understandably, because the read memory data cache unit caches the first data, subsequent units that need to process the first data can retrieve it from the read memory data cache. Therefore, the read memory data cache unit can repeatedly and continuously cache the first data, improving instruction processing efficiency.

[0143] S406. Compare the first data in the target hash table corresponding to each instruction with the second data corresponding to each instruction, and process the execution mode of each instruction in parallel based on the comparison result.

[0144] like Figure 5 As shown, after the read memory data cache unit has the first data, the data comparison unit compares the second data cached in the bit-width channel data cache unit with the first data cached in the read memory data cache unit. Specifically, it compares the key value of the first data with the key value of the second data.

[0145] After comparing the first data with the second data, depending on the instruction type, the first data and the comparison result between the first data and the second data are cached in the instruction data cache unit and instruction comparison result unit corresponding to the instruction type.

[0146] Specifically, for a query command, there are corresponding insert command data cache unit and insert command comparison result unit. The insert command data cache unit is used to store the first data read based on the insert command, and the insert command comparison result unit is used to cache the comparison result between the first data read based on the insert command and the second data.

[0147] For a delete instruction, there are corresponding delete instruction data cache unit and delete instruction comparison result unit. The delete instruction data cache unit is used to store the first data read based on the delete instruction; the delete instruction comparison result unit is used to cache the comparison result between the first data read based on the delete instruction and the second data.

[0148] For a query command, there are corresponding query command data cache unit and query command comparison result unit. The query command data cache unit is used to store the first data read based on the query command; the query command comparison result unit is used to cache the comparison result between the first data read based on the query command and the second data.

[0149] Understandably, because the instruction data cache unit caches the first data and the instruction comparison result unit caches the comparison result between the first and second data, subsequent units that need to process the comparison result of the first and second data can obtain data from the instruction data cache unit and the instruction comparison result unit. Therefore, the instruction data cache unit can repeatedly and continuously cache the first data, and the instruction comparison result unit can repeatedly and continuously compare the first and second data and cache the comparison result, thus improving instruction processing efficiency.

[0150] In this embodiment of the disclosure, after determining the comparison result of the first data and the second data, it is necessary to parse the comparison result to obtain the execution mode of each instruction.

[0151] Therefore, as Figure 5 As shown, an instruction comparison result parsing unit is set up, and different instruction types correspond to different comparison result parsing units.

[0152] For each insert instruction, there is a corresponding insert instruction comparison result parsing unit. This unit parses the first data cached in the insert instruction data cache unit and the result of comparing the first data cached in the insert instruction comparison result unit with the second data cached in the insert instruction comparison result unit to obtain the execution method of the insert instruction.

[0153] For each deletion instruction, there is a corresponding deletion instruction comparison result parsing unit. This unit parses the first data cached in the deletion instruction data cache unit and the result of comparing the first data cached in the deletion instruction comparison result unit with the second data cached in the deletion instruction comparison result unit to obtain the execution method of the deletion instruction.

[0154] For each query command, there is a corresponding query command comparison result parsing unit. This unit parses the first data cached in the query command data caching unit and the result of comparing the first data cached in the query command comparison result unit with the second data cached in the query command comparison result unit to obtain the execution method of the query command.

[0155] The method of obtaining each instruction can adopt the technical solution described in step S104 for determining the execution method of insert instructions, delete instructions, and query instructions, which will not be elaborated here.

[0156] After the above process, the execution mode of each instruction can be obtained. In this embodiment of the disclosure, instructions with different execution modes are processed in parallel.

[0157] like Figure 5 As shown, for the insertion instruction, the instructions with the following execution modes are processed in parallel: insertion position in the array, insertion position in the doubly linked list node, and reading the next doubly linked list node.

[0158] For deletion instructions, the following instructions are processed in parallel: deletion position in the array, deletion position at the last node of the doubly linked list, deletion position at the middle node of the doubly linked list, and reading the next node of the doubly linked list.

[0159] For query commands, commands that execute with the following methods are processed in parallel: query successful, read the next doubly linked list node.

[0160] It should be noted that since the insert, delete, and query instructions all involve reading the next doubly linked list node, when the above three instruction types are executed to read the next doubly linked list node, they will return to the read data selection unit in step S404 to continue execution.

[0161] S407. Based on the pre-configured processing priorities of different instruction types, the execution mode corresponding to each type of instruction is selected in sequence, and the corresponding instructions are executed serially based on the sequentially selected execution mode.

[0162] like Figure 6 As shown, the write data selection unit selects the execution mode as insertion position in the array, insertion position in a doubly linked list node, deletion position in the array, deletion position in the last node of the doubly linked list, or deletion position in the middle node of the doubly linked list, and performs insertion or deletion processing on the instruction according to the selected execution mode.

[0163] Understandably, since the execution method of the query instruction does not involve writing data to the hash table, the execution method corresponding to the query instruction will not go through the write data selection unit.

[0164] At the same time, for the insertion instruction, when the insertion position is in a doubly linked list node, space occupied by the hash table doubly linked list node will be allocated for that node.

[0165] For deletion commands, if the deletion location is the last node of the doubly linked list, or if the deletion location is a node in the middle of the doubly linked list, then the space occupied by the aforementioned node should be reclaimed.

[0166] As can be seen, the embodiments of this disclosure improve the instruction processing efficiency of the hash table by setting different instruction channels to receive different types of instructions. Furthermore, the instruction processing flow of the hash table is divided, with different processing units handling different tasks. After some processing units have completed their processing, the processed data is cached, so that the processing units do not need to wait for subsequent units to process the data and can repeatedly and continuously process the instructions, thereby improving the instruction processing efficiency of the hash table.

[0167] Figure 6 This is a schematic diagram of the structure of a hash table processing apparatus provided in an embodiment of the present disclosure. The hash table processing apparatus 60 provided in this embodiment can execute the processing flow provided in the hash table processing method embodiment, such as… Figure 6 As shown, the hash table processing device 60 includes:

[0168] The allocation module 61 is used to obtain the configuration information of the target hash table in response to the operation of configuring the hash table structure, and allocate the memory space corresponding to the configuration information to the target hash table.

[0169] The parallel receiving module 62 is used to receive multiple instructions for the target hash table in parallel through multiple instruction channels after allocating the memory space; wherein each instruction channel receives instructions of a different type.

[0170] The serial read module 63 is used to access the memory space through the read memory channel to serially read the first data in the target hash table corresponding to each instruction.

[0171] The data comparison module 64 is used to compare the first data in the target hash table corresponding to each instruction with the second data corresponding to each instruction, and to process the execution mode of each instruction in parallel based on the comparison result.

[0172] The serial execution module 65 is used to execute each instruction serially based on the execution mode of each instruction.

[0173] In some embodiments, the hash table processing device 60 further includes a bit width adjustment module, a first cache module, and a first execution module.

[0174] The bit width adjustment module is used to adjust the bit width of the data carried by each type of instruction to be the same as the bit width of the memory channel, so as to obtain the second data corresponding to each type of instruction.

[0175] The data caching module is used to cache the second data.

[0176] The re-execution module is used to re-execute various types of instructions that are retrieved in parallel from multiple instruction channels for the target hash table.

[0177] In some embodiments, the hash table processing device 60 further includes: a data selection module, a second cache module, and a second execution module.

[0178] The data selection module is used to select the second data corresponding to each type of instruction in turn, based on the processing priority of different pre-configured instruction types.

[0179] The second cache module is used to cache the sequentially selected second data and the instructions corresponding to the sequentially selected second data.

[0180] The second execution module is used to re-execute the processing priority based on the pre-configured different instruction types, sequentially select the second data corresponding to each type of instruction, and cache the sequentially selected second data and the instructions corresponding to the sequentially selected second data.

[0181] In some embodiments, the serial execution module 65 is used to execute each instruction serially based on the execution mode of each instruction, specifically by: selecting the execution mode corresponding to each type of instruction in sequence according to the pre-configured processing priority of different instruction types, and executing the corresponding instructions serially based on the sequentially selected execution mode.

[0182] In some embodiments, the hash table processing device 60 further includes a request and reclamation module, which, for any instruction, if the instruction type is a deletion instruction and the instruction is executed in a manner where the deletion position is at the last node of the doubly linked list of the target hash table or at the middle node of the doubly linked list of the hash table, requests and reclaims the space occupied by the node corresponding to the deletion position from the memory space.

[0183] In some embodiments, the hash table processing device 60 further includes a space allocation module, which, for any instruction, if the instruction type is an insertion instruction and the instruction is executed in a manner where the insertion position is at a node of the doubly linked list of the hash table, allocates space occupied by the doubly linked list node of the hash table from the memory space.

[0184] It should be noted that, Figures 1 to 5 The hash table processing device 60 shown can perform... Figures 1 to 5 The various steps in the method embodiment shown are implemented. Figure 7 The processes and effects in the method embodiments shown are not described in detail here.

[0185] This disclosure also provides a hash table processing device, which may include a processor and a memory, the memory being used to store executable instructions. The processor can be used to read the executable instructions from the memory and execute the executable instructions to implement the hash table processing method in the above embodiments.

[0186] Figure 7 A schematic diagram of a hash table processing device provided in an embodiment of this disclosure is shown. It illustrates a structural schematic diagram suitable for implementing the hash table processing device 70 in the embodiments of this disclosure.

[0187] The hash table processing device 70 in this embodiment can be an electronic device or a server. Electronic devices include, but are not limited to, smartphones, PDAs, tablets, wearable devices with displays, desktop computers, laptops, all-in-one computers, smart home devices, etc. Servers can be standalone servers or clusters of multiple servers, and can include locally located servers and cloud-based servers.

[0188] It should be noted that, Figure 7 The hash table processing device 70 shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0189] like Figure 7 As shown, the hash table processing device 70 may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 71, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 72 or a program loaded from storage device 78 into random access memory (RAM) 73. The RAM 73 also stores various programs and data required for the operation of the hash table processing device 70. The processing unit 71, ROM 72, and RAM 73 are interconnected via a bus 74. An input / output (I / O) interface 75 is also connected to the bus 74.

[0190] Typically, the following devices can be connected to the I / O interface 75: input devices 76 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 77 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 78 including, for example, magnetic tapes, hard disks, etc.; and communication devices 79. Communication device 79 allows hash table processing device 70 to communicate wirelessly or wiredly with other devices to exchange data. Although ​ A hash table processing device 70 with various means is shown; however, it should be understood that implementation or possession of all the means shown is not required. More or fewer means may be implemented alternatively.

[0191] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, causes the processor to implement the hash table processing method described in the above embodiments.

[0192] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 79, or installed from a storage device 78, or installed from a ROM 72. When the computer program is executed by the processing device 71, it performs the functions defined in the hash table processing method of embodiments of this disclosure.

[0193] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0194] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP, and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and end-to-end networks (e.g., ad hoc end-to-end networks), as well as any currently known or future-developed networks.

[0195] The aforementioned computer-readable medium may be included in the aforementioned hash table processing device; or it may exist independently and not assembled into the hash table processing device.

[0196] The aforementioned computer-readable medium carries one or more programs that, when executed by the hash table processing device, cause the hash table processing device to perform the following:

[0197] In response to the operation of configuring the hash table structure, the system obtains the configuration information of the target hash table and allocates memory space corresponding to the configuration information for the target hash table. After allocating the memory space, it receives multiple instructions for the target hash table in parallel through multiple instruction channels, where each instruction channel obtains instructions of a different type. The system accesses the memory space through the read memory channel to serially read the first data in the target hash table corresponding to each instruction. The system compares the first data in the target hash table corresponding to each instruction with the second data corresponding to each instruction, and processes the execution mode of each instruction in parallel based on the comparison result. Based on the execution mode of each instruction, the system executes each instruction serially.

[0198] In embodiments of this disclosure, computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof. These programming languages ​​include, but are not limited to, object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0199] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0200] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0201] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0202] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0203] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0204] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0205] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A hash table processing method, characterized in that, The method includes: In response to the operation of configuring the hash table structure, the configuration information of the target hash table is obtained, and memory space corresponding to the configuration information is allocated to the target hash table; After allocating the memory space, multiple instructions for the target hash table are received in parallel through multiple instruction channels; wherein, each instruction channel receives instructions of a different type. The memory space is accessed via a read memory channel to serially read the first data in the target hash table corresponding to each instruction; The first data in the target hash table corresponding to each instruction is compared with the second data corresponding to each instruction, and the execution mode of each instruction is processed in parallel based on the comparison result; wherein, the second data corresponding to each instruction is the data carried in each instruction; Based on the execution method of each instruction, each instruction is executed serially.

2. The method according to claim 1, characterized in that, After acquiring multiple types of instructions for the target hash table in parallel through multiple instruction channels, the method further includes: Adjust the bit width of the data carried by each type of instruction to be the same as the bit width of the read memory channel to obtain the second data corresponding to each type of instruction; Cache the second data; The process of retrieving multiple types of instructions for the target hash table in parallel through multiple instruction channels is executed again.

3. The method according to claim 2, characterized in that, Before accessing the memory space via the memory read channel to serially read data from the target hash table corresponding to each type of instruction, the method further includes: Based on the pre-configured processing priorities of different instruction types, the second data corresponding to each type of instruction is selected in sequence, and the selected second data and the instruction corresponding to the selected second data are cached, and this step is executed again.

4. The method according to claim 3, characterized in that, The execution method based on each type of instruction, executing each type of instruction sequentially, includes: Based on the pre-configured processing priorities of different instruction types, the execution mode corresponding to each instruction type is selected in sequence, and the corresponding instructions are executed serially based on the sequentially selected execution mode.

5. The method according to claim 3, characterized in that, The method further includes: For any instruction, if the instruction type is a delete instruction, and the execution method of the instruction is to delete at the last node of the doubly linked list of the target hash table or at the middle node of the doubly linked list of the hash table, then the memory space occupied by the node corresponding to the delete position is reclaimed from the memory space.

6. The method according to claim 3, characterized in that, The method further includes: For any instruction, if the instruction type is an insertion instruction and the execution method of the instruction is to insert at a node in the doubly linked list of the hash table, then the space occupied by the doubly linked list node of the hash table is requested from the memory space.

7. A hash table processing apparatus, characterized in that, The device includes: The allocation module is used to obtain the configuration information of the target hash table in response to the operation of configuring the hash table structure, and allocate the memory space corresponding to the configuration information to the target hash table; A parallel receiving module is used to receive multiple instructions for the target hash table in parallel through multiple instruction channels after allocating the memory space; wherein, each instruction channel receives instructions of a different type; A serial read module is used to access the memory space through a read memory channel to serially read the first data in the target hash table corresponding to each instruction; The data comparison module is used to compare the first data in the target hash table corresponding to each instruction with the second data corresponding to each instruction, and to process the execution mode of each instruction in parallel based on the comparison result; wherein, the second data corresponding to each instruction is the data carried in each instruction; The serial execution module is used to execute each instruction serially based on the execution mode of each instruction.

8. The apparatus according to claim 7, characterized in that, The device further includes: The bit width adjustment module is used to adjust the bit width of the data carried by each type of instruction to be the same as the bit width of the read memory channel, so as to obtain the second data corresponding to each type of instruction; The data caching module is used to cache the second data; The re-execution module is used to re-execute the various types of instructions obtained in parallel through multiple instruction channels for the target hash table.

9. A hash table processing device, characterized in that, include: processor; Memory, used to store executable instructions; The processor is configured to read the executable instructions from the memory and execute the executable instructions to implement the hash table processing method according to any one of claims 1-6.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, causes the processor to implement the hash table processing method according to any one of claims 1-6.

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