Display device

Abstract

A display device is provided. The display device includes a pixel including first and second sub-pixels that emit light of different colors from each other and a first power supply line that applies a first power supply voltage, a repair circuit configured adjacent to the pixel, and a first repair circuit connection pattern extending across the pixel and the repair circuit, each of the first and second sub-pixels including a light emitting element, a first transistor, and a second transistor, the repair circuit including a first repair transistor and a second repair transistor, a first source / drain electrode of the first transistor of the first and second sub-pixels is electrically connected to the first power supply line, a second source / drain electrode of the first transistor of the first and second sub-pixels overlaps the first repair circuit connection pattern, a first source / drain electrode of the first repair transistor is electrically connected to the first power supply line, and a second source / drain electrode of the first repair transistor overlaps the first repair circuit connection pattern.

Description

Technical Field

[0001] This invention relates to a display device. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs.

[0003] Display devices include light-receiving display devices such as liquid crystal display devices, field emission display devices, and light-emitting display devices; organic light-emitting display devices including organic light-emitting elements; inorganic light-emitting display devices including inorganic light-emitting elements such as inorganic semiconductors; and ultra-miniature light-emitting display devices including ultra-miniature light-emitting elements.

[0004] Organic light-emitting display devices include thin-film transistors (TFTs), wiring connected to them, and organic electroluminescent elements driven by the TFTs to realize images. Because the various wirings connected to the TFTs are formed with narrow line widths, open-circuit defects may occur during the manufacturing process, where a portion of the wiring cannot be properly formed. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a display device and a method for repairing defective pixels (or sub-pixels) that can repair defects, thereby improving yield and saving process costs.

[0006] The subject matter of this invention is not limited to the subject matter mentioned above, and those skilled in the art will clearly understand from the following description other technical subject matter not mentioned.

[0007] A display device according to an embodiment for solving the aforementioned problem includes: a pixel, including a first sub-pixel and a second sub-pixel emitting light of different colors from each other, and a first power line electrically connected to the first sub-pixel and the second sub-pixel to apply a first power supply voltage to each of the first sub-pixel and the second sub-pixel; a repair circuit disposed adjacent to the pixel; and a first repair circuit connection pattern extending across the pixel and the repair circuit, each of the first sub-pixel and the second sub-pixel including a light-emitting element, a first transistor connected to the light-emitting element, and a second transistor connected to the gate electrode of the first transistor, the repair circuit including a first repair transistor and a second repair transistor connected to the gate electrode of the first repair transistor, a first source / drain electrode of the first transistor of the first sub-pixel and the second sub-pixel being electrically connected to the first power line, a second source / drain electrode of the first transistor of the first sub-pixel and the second sub-pixel overlapping the first repair circuit connection pattern, a first source / drain electrode of the first repair transistor being electrically connected to the first power line, and a second source / drain electrode of the first repair transistor overlapping the first repair circuit connection pattern.

[0008] The light-emitting element may include an anode electrode, a light-emitting layer, and a cathode electrode stacked sequentially. The first source / drain electrode and the second source / drain electrode of the first transistor, as well as the first source / drain electrode and the second source / drain electrode of the first repair transistor, constitute a first conductive layer. The first repair circuit connection pattern and the anode electrode of the light-emitting element constitute a second conductive layer different from the first conductive layer.

[0009] Alternatively, the display device may further include: a via layer disposed on the first conductive layer, wherein the via layer is disposed between the first conductive layer and the second conductive layer.

[0010] Alternatively, the via layer may include a first recessed pattern and a second recessed pattern defined by removing at least a portion in the thickness direction. The first recessed pattern is disposed in the region where the second source / drain electrode of the first transistor of the first sub-pixel and the first repair circuit connection pattern overlap, and the second recessed pattern is disposed in the region where the second source / drain electrode of the first transistor of the repair circuit overlaps with the first repair circuit connection pattern.

[0011] Alternatively, at least a portion of the first repair circuit connection pattern may be disposed inside at least one of the first recessed pattern and the second recessed pattern.

[0012] Alternatively, the first power line may form a third conductive layer that is different from the first conductive layer and the second conductive layer, and may be disposed below the first conductive layer and the second conductive layer.

[0013] Alternatively, the display device may further include: a fourth conductive layer, which is different from the first conductive layer, the second conductive layer and the third conductive layer, and the fourth conductive layer includes the gate electrodes of the first transistor and the second transistor of the first sub-pixel and the second sub-pixel, and the gate electrodes of the first repair transistor and the second repair transistor.

[0014] Alternatively, in the region where each of the second source / drain electrodes of the first transistor of the first sub-pixel and the second sub-pixel overlaps with the first repair circuit connection pattern, at least one insulating film is at least partially disposed between each of the second source / drain electrodes of the first transistor of the first sub-pixel and the second sub-pixel and the first repair circuit connection pattern, so that each of the second source / drain electrodes of the first transistor of the first sub-pixel and the second sub-pixel and the first repair circuit connection pattern are electrically insulated from each other.

[0015] The display device may further include: a first data line and a second data line, which are adjacent to each other and extend in the same direction; and a second repair circuit connection pattern, which extends across the first data line and the second data line and overlaps with the first data line and the second data line, wherein the second transistor of the first sub-pixel is electrically connected to the first data line, the second transistor of the second sub-pixel is electrically connected to the second data line, and the second repair transistor is electrically connected to the second repair circuit connection pattern.

[0016] Alternatively, the first data line, the second data line, and the first power line may constitute a first conductive layer, and the second repair circuit connection pattern, the first source / drain electrode and the second source / drain electrode of the first transistor, and the first source / drain electrode and the second source / drain electrode of the first repair transistor may constitute a second conductive layer different from the first conductive layer.

[0017] Alternatively, the display device may further include: an insulating film disposed between the first conductive layer and the second conductive layer, and including a first recessed pattern and a second recessed pattern defined by removing at least a portion thereof, the first recessed pattern being disposed in the region where the second repair circuit connection pattern and the first data line overlap, and the second recessed pattern being disposed in the region where the second repair circuit connection pattern and the second data line overlap.

[0018] Alternatively, the insulating film may include a buffer layer and an interlayer insulating film stacked sequentially.

[0019] Alternatively, the pixels and the repair circuits may be provided as a plurality of units, each of the plurality of repair circuits being configured between two adjacent pixels among the plurality of pixels, and the two pixels adjacent to the repair circuits each having a shape symmetrical to each other.

[0020] The display device may further include: a display area for displaying an image; and a non-display area disposed around the display area, wherein a plurality of the pixels and a plurality of the repair circuits are disposed in the display area.

[0021] A display device according to an embodiment for solving the aforementioned problem includes: a pixel, including a first sub-pixel and a second sub-pixel emitting light of different colors from each other, and a first power line electrically connected to at least one of the first sub-pixel and the second sub-pixel; a repair circuit, configured adjacent to the pixel, and including a first repair transistor and a second repair transistor electrically connected to the gate electrode of the first repair transistor; and a first repair circuit connection pattern extending across the pixel and the repair circuit, wherein the first sub-pixel includes a first transistor electrically connected to a first light-emitting element and a second transistor electrically connected to the gate electrode of the first transistor, the second sub-pixel includes a second light-emitting element different from the first light-emitting element, a first source / drain electrode of the first transistor of the first sub-pixel is electrically connected to the first power line, a second source / drain electrode of the first transistor of the first sub-pixel overlaps with and is electrically insulated from the first repair circuit connection pattern, the first source / drain electrode of the first repair transistor is electrically connected to the first power line, the second source / drain electrode of the first repair transistor overlaps with the first repair circuit connection pattern, and the second source / drain electrode of the first repair transistor is electrically connected to the first repair circuit connection pattern in the region overlapping with the first repair circuit connection pattern.

[0022] The light-emitting element may include an anode electrode, a light-emitting layer, and a cathode electrode stacked sequentially. The first source / drain electrode and the second source / drain electrode of the first transistor, as well as the first source / drain electrode and the second source / drain electrode of the first repair transistor, constitute a first conductive layer. The first repair circuit connection pattern and the anode electrode of the light-emitting element constitute a second conductive layer different from the first conductive layer.

[0023] The display device may further include: a first data line and a second data line, which are adjacent to each other and extend in the same direction; and a second repair circuit connection pattern, which overlaps with the first data line and the second data line and is electrically connected to the second repair transistor, wherein the second repair circuit connection pattern is electrically insulated from the first data line and is electrically connected to the second data line in the area where it overlaps with the second data line.

[0024] Alternatively, the first data line, the second data line, and the first power line may constitute a first conductive layer, and the second repair circuit connection pattern, the first source / drain electrode and the second source / drain electrode of the first transistor, the first source / drain electrode and the second source / drain electrode of the first repair transistor, and the first source / drain electrode and the second source / drain electrode of the second repair transistor may constitute a second conductive layer different from the first conductive layer.

[0025] Alternatively, the first repair circuit connection pattern and the second source / drain electrode of the first repair transistor can be electrically connected in the area where the first repair circuit connection pattern and the second source / drain electrode of the first repair transistor overlap.

[0026] Alternatively, the second sub-pixel may further include a first transistor of the second sub-pixel that is electrically connected to the second light-emitting element and electrically disconnected from the first power line.

[0027] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0028] According to one embodiment of the display device and the method for repairing the display device, defective pixels (or sub-pixels) can be repaired, thereby improving yield and saving process costs.

[0029] The effects of the embodiments are not limited to those illustrated above, and many more effects are included in this specification. Attached Figure Description

[0030] Figure 1 This is a plan view of a display device according to one embodiment.

[0031] Figure 2 This is an equivalent circuit diagram of the pixels and repair circuit of a display device according to one embodiment.

[0032] Figure 3 This is a layout diagram of the first conductive layer and semiconductor layer of a pixel according to one embodiment.

[0033] Figure 4This is a layout diagram of a first conductive layer, a semiconductor layer, and a second conductive layer of a pixel according to an embodiment.

[0034] Figure 5 This is a layout diagram of a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer of a pixel according to an embodiment.

[0035] Figure 6 It is magnification Figure 5 An enlarged view of region A.

[0036] Figure 7 This is a layout diagram of a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer of a pixel according to an embodiment.

[0037] Figure 8 It is along Figure 7 A cross-sectional view taken from line VII-VII'.

[0038] Figure 9 This is a cross-sectional view of a region having first to third recessed patterns according to an embodiment.

[0039] Figure 10 This is a cross-sectional view of a region configured with a fourth recessed pattern according to an embodiment.

[0040] Figure 11 This is a cross-sectional view of the region having the fifth to seventh recessed patterns according to one embodiment.

[0041] Figure 12 This is an equivalent circuit diagram of pixels and repair circuitry according to an embodiment for illustrating a method of repairing a display device.

[0042] Figure 13 This is a layout diagram of pixels and repair circuitry according to an embodiment for illustrating a method of repairing a display device.

[0043] Figure 14 It is magnification Figure 13 A magnified view of region B.

[0044] Figure 15 This is a cross-sectional view of a region with first to third recessed patterns, according to an embodiment of a method for repairing a display device.

[0045] Figure 16 This is a cross-sectional view of a region with a fourth recessed pattern, according to an embodiment of a method for repairing a display device.

[0046] Figure 17 This is a cross-sectional view of the region with the fifth to seventh recessed patterns, according to an embodiment of a method for repairing a display device.

[0047] Figure 18 This is an equivalent circuit diagram of pixels and repair circuitry according to another embodiment for illustrating a method of repairing a display device.

[0048] Figure 19 This is a layout diagram of pixels and repair circuitry according to another embodiment for illustrating a method of repairing a display device.

[0049] Figure 20 It is magnification Figure 19 A magnified view of region C.

[0050] Figure 21 This is a layout diagram of pixels and repair circuitry for illustrating a method of repairing a display device, according to yet another embodiment.

[0051] (Explanation of reference numerals in the attached diagram)

[0052] SUB: Substrate 100: First conductive layer

[0053] SC: Semiconductor layers ACT1-ACT9: First to ninth semiconductor patterns

[0054] 101: Buffer layer; 200: Second conductive layer

[0055] 102: Gate insulating film; 300: Third conductive layer

[0056] 103: Interlayer insulating film; 104: Passivation film

[0057] 105: Through-hole layer; 400: Fourth conductive layer

[0058] PX: Pixel; DP: Repair Circuit

[0059] 410: Connection diagram of the first repair circuit

[0060] DCE3: Connection diagram of the second repair circuit Detailed Implementation

[0061] References and Attachments Figure 1 The advantages and features of the invention, as well as the methods of implementing them, will become clear from the detailed embodiments described below. However, the invention is not limited to the embodiments disclosed below and can be implemented in various forms that differ from each other. These embodiments are provided merely to make the disclosure of the invention complete and to fully convey the scope of the invention to those skilled in the art to which it pertains. The invention is defined only by the scope of the claims.

[0062] The designation "on" other elements or layers includes all cases where an element is directly on top of another element or where another layer or other element is in between. Throughout this specification, the same reference numerals refer to the same constituent elements.

[0063] The terms "first," "second," etc., are used to describe various constituent elements, but it is clear that these constituent elements are not limited to these terms. These terms are used merely to distinguish one constituent element from others. Therefore, it is obvious that the first constituent element mentioned below can also be a second constituent element within the scope of the technical concept of this invention.

[0064] The following description refers to the accompanying drawings.

[0065] Figure 1 This is a plan view of a display device according to one embodiment.

[0066] Reference Figure 1 The display device 1, as a device for displaying dynamic or still images, can be used not only as a display screen for portable electronic devices such as mobile phones, smartphones, tablet PCs (personal computers), smartwatches, smartwatch phones, mobile communication terminals, electronic notebooks, e-books, PMPs (portable multimedia players), navigators, and UMPCs (ultra-portable mobile PCs), but also as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things.

[0067] According to one embodiment, the display device 1 can be configured as a substantially rectangular shape on a plane. The display device 1 can be a rectangle with perpendicular corners on a plane. However, it is not limited to this; the display device 1 can also be a rectangle with rounded corners on a plane.

[0068] In the accompanying drawings, the first direction DR1 represents the lateral direction of the display device 1 in a plan view, and the second direction DR2 represents the longitudinal direction of the display device 1 in a plan view. Additionally, the third direction DR3 represents the thickness direction of the display device 1. The first direction DR1 and the second direction DR2 intersect each other perpendicularly, and the third direction DR3 intersects both the first direction DR1 and the second direction DR2 perpendicularly in the direction intersecting the plane containing both directions. However, it should be understood that the directions mentioned in the embodiments refer to relative directions, and the embodiments are not limited to the mentioned directions.

[0069] Unless otherwise defined, in this specification, "above," "on top," and "upper side" as referenced to a third party DR3 mean the side of the display surface referenced to display device 1, and "below," "under," and "lower side" mean the opposite side of the display surface referenced to display device 1.

[0070] The display device 1 may include a display panel 10. The display panel 10 may be an organic light-emitting display panel. The following embodiments illustrate the use of an organic light-emitting display panel as the display panel 10, but it is not limited thereto. Other types of display panels, such as liquid crystal displays (LCDs), quantum dot organic light-emitting display panels (QD-OLEDs), quantum dot liquid crystal displays (QD-LCDs), quantum nano light-emitting display panels (nano NEDs), and micro LEDs, may also be used.

[0071] The display panel 10 may include a display area DA for displaying the image and a non-display area NDA that does not constitute a display area. The display panel 10 can be divided into the display area DA and the non-display area NDA in a plan view. The non-display area NDA can be configured to surround the display area DA. The non-display area NDA can form a border.

[0072] The planar shape of the display panel 10 and the display area DA of the display panel 10 can correspond to the shape on the plane of the display device 1. For example, the display panel 10 and the display area DA can be a rectangle with vertical corners or a rectangle with rounded corners on the plane. However, the planar shape of the display panel 10 and the display area DA is not limited to a rectangle, and can be circular, elliptical or other various shapes.

[0073] The display area DA may include multiple pixels. These pixels may be arranged in a matrix shape. Each pixel may include a light-emitting layer and a circuit layer that controls the amount of light emitted by the light-emitting layer. The circuit layer may include wiring, electrodes, and at least one transistor. The light-emitting layer may contain an organic light-emitting material. The light-emitting layer may be sealed by an encapsulation film.

[0074] Figure 2 This is an equivalent circuit diagram of the pixels and repair circuit of a display device according to one embodiment. Figure 2 Two adjacent pixels PX and a repair circuit DP configured between the two pixels PX are shown.

[0075] Reference Figure 2 According to one embodiment, the display device may include a plurality of pixels PX and a repair circuit DP disposed between adjacent pixels PX.

[0076] First, let's explain the pixel PX.

[0077] A pixel PX refers to the smallest repeating unit used for display. Each pixel PX can be repeated in the matrix direction (first direction DR1 and second direction DR2), and each sub-pixel PXS1, PXS2, and PXS3 can be alternated in the matrix direction (first direction DR1 and second direction DR2).

[0078] To display full color, each of the multiple pixels PX can include a first sub-pixel PXS1, a second sub-pixel PXS2, and a third sub-pixel PXS3. Each sub-pixel PXS1, PXS2, and PXS3 can emit light of a different color than the others. For example, the first sub-pixel PXS1 can emit light of a first color, and the second sub-pixel PXS2 can emit light of a second color, different from the first color. Additionally, the third sub-pixel PXS3 can emit light of a third color, different from both the first and second colors. However, this is not a limitation; for example, the first sub-pixel PXS1 of each pixel PX can emit blue light, the second sub-pixel PXS2 can emit green light, and the third sub-pixel PXS3 can emit red light.

[0079] Each of the sub-pixels PXS1, PXS2, and PXS3 of each pixel PX includes a light-emitting element EMD, multiple transistors T1, T2, and T3, and a storage capacitor CST. Data signals, scan signals, sensing signals, a first power supply voltage, a second power supply voltage, and an initialization voltage are applied to the circuitry of each pixel PX.

[0080] The light-emitting element (EMD) includes a first electrode (or anode electrode) and a second electrode (or cathode electrode). The storage capacitor (CST) includes a first electrode and a second electrode.

[0081] The light-emitting element (EMD) emits light according to the current supplied through the first transistor T1. The EMD can be implemented using an organic light-emitting diode (OLED), a miniature OLED, a nano-LED, etc. Alternatively, the anode electrode of the EMD can be connected to the second source electrode of the first transistor T1, and the cathode electrode can be connected to a second power supply line ELVSL, which is supplied with a low potential voltage (second power supply voltage) lower than the high potential voltage (first power supply voltage) of the first power supply line ELVDL.

[0082] The plurality of transistors T1, T2, and T3 may include first to third transistors T1, T2, and T3. Each transistor T1, T2, and T3 includes a gate electrode, a first source / drain electrode, and a second source / drain electrode. Either the first source / drain electrode or the second source / drain electrode of each transistor T1, T2, and T3 is designated as the source electrode, and the other is designated as the drain electrode.

[0083] Each transistor T1, T2, and T3 can be formed by a thin-film transistor. Specifically, the first transistor T1 can be a driving transistor, and the second and third transistors T2 and T3 can be switching transistors, but this is not a limitation. The main point is that each transistor T1, T2, and T3 can be formed by an N-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), but this is not a limitation. That is, at least one of transistors T1, T2, and T3 can also be formed by a P-type MOSFET.

[0084] The first transistor T1 adjusts the current flowing from the first power supply line ELVDL, which is supplied with a first power supply voltage, to the light-emitting element EMD based on the voltage difference between its gate electrode and the second source / drain electrode. The gate electrode of the first transistor T1 is connected to the first electrode of the storage capacitor CST and the second source / drain electrode of the second transistor T2. Alternatively, the first source / drain electrode of the first transistor T1 can be connected to the first power supply line ELVDL, which is supplied with the first power supply voltage, and the second source / drain electrode can be connected to the anode electrode of the light-emitting element EMD.

[0085] The second transistor T2 connects the data line DL to the gate electrode of the first transistor T1 by being turned on by the scan signal of the scan line SCL. Alternatively, the gate electrode of the second transistor T2 can be connected to the scan line SCL, the first source / drain electrode can be connected to the data line DL, and the second source / drain electrode can be connected to the gate electrode of the first transistor T1. The data line DL can include first to third sub-data lines DL1, DL2, and DL3. Each first sub-data line DL1 can be connected to the second transistor T2 of each sub-pixel PXS1, PXS2, or PXS3.

[0086] The third transistor T3 is turned on by the sensing signal of the sensing line SSL, thereby connecting the reference voltage line RVL to the second source / drain electrode of the first transistor T1. Alternatively, the gate electrode of the third transistor T3 may be connected to the sensing line SSL, the first source / drain electrode may be connected to the reference voltage line RVL, and the second source / drain electrode may be connected to the second source / drain electrode of the first transistor T1.

[0087] A storage capacitor CST is disposed between the gate electrode of the first transistor T1 and the second source / drain electrode of the first transistor T1. The storage capacitor CST stores the voltage difference between the gate voltage and the second source / drain voltage of the first transistor T1.

[0088] Next, the repair circuit DP will be explained.

[0089] Multiple repair circuits DP can be provided. Each of the multiple repair circuits DP can be configured between two adjacent pixels PX, but is not limited thereto. The repair circuit DP may include a first repair transistor DT1, a second repair transistor DT2, and a repair capacitor DCST. It is possible that the first repair transistor DT1 is a driving transistor and the second repair transistor DT2 is a switching transistor, but is not limited thereto.

[0090] Each of the first repair transistor DT1 and the second repair transistor DT2 includes a gate electrode, a first source / drain electrode, and a second source / drain electrode. Either the first source / drain electrode or the second source / drain electrode of each repair transistor DT1 and DT2 is designated as the source electrode, and the other is designated as the drain electrode. The repair capacitor DCST includes a first electrode and a second electrode.

[0091] The gate electrode of the first repair transistor DT1 is connected to the first electrode of the repair capacitor CST and the second source / drain electrode of the second repair transistor DT2. Alternatively, the first source / drain electrode of the first repair transistor DT1 can be connected to the first power line ELVDL to which a first power supply voltage is applied, and the second source / drain electrode can be connected to the second electrode of the repair capacitor DCST. As will be described below, during repair, the second source / drain electrode of the first repair transistor DT1 can be connected to the anode electrode of the light-emitting element EMD. A detailed description of this will follow.

[0092] The gate electrode of the second repair transistor DT2 is connected to the scan line SCL. The second source / drain electrode of the second repair transistor DT2 can be connected to the gate electrode of the first transistor T1. As will be described below, when repair is performed, the first source / drain electrode of the second repair transistor DT2 can be connected to the data line DL. A detailed description of this will be provided below.

[0093] The repair capacitor DCST is configured between the gate electrode of the first repair transistor DT1 and the second source / drain electrode of the first repair transistor DT1. The repair capacitor DCST stores the voltage difference between the gate voltage and the second source / drain voltage of the first repair transistor DT1.

[0094] It is possible that the first repair transistor DT1 of the repair circuit DP has substantially the same configuration and structure as the first transistor T1 of each sub-pixel PXS1, PXS2, and PXS3. It is also possible that the second repair transistor DT2 of the repair circuit DP has substantially the same configuration and structure as the second transistor T2 of each sub-pixel PXS1, PXS2, and PXS3. Furthermore, it is possible that the repair capacitor DCST of the repair circuit DP has substantially the same configuration and structure as the storage capacitor CST of each sub-pixel PXS1, PXS2, and PXS3. However, it is not limited to these embodiments.

[0095] Furthermore, the connection relationship of the first repair transistor DT1, the second repair transistor DT2, and the repair capacitor DCST in the repair circuit DP can be substantially the same as the connection relationship of the first transistor T1, the second transistor T2, and the storage capacitor CST in each sub-pixel PXS1, PXS2, and PXS3. However, it is not limited to this.

[0096] Figure 3 This is a layout diagram of the first conductive layer and semiconductor layer of a pixel according to one embodiment. Figure 4 This is a layout diagram of a first conductive layer, a semiconductor layer, and a second conductive layer of a pixel according to an embodiment. Figure 5 This is a layout diagram of a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer of a pixel according to an embodiment. Figure 6 It is magnification Figure 5 An enlarged view of region A. Figure 7 This is a layout diagram of a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer of a pixel according to an embodiment. Figure 8 It is along Figure 7 A cross-sectional view taken from line VII-VII'.

[0097] Reference Figures 2 to 8 Display device 1 (refer to) Figure 1 The device includes a substrate SUB that performs the function of supporting the structure above, and includes a semiconductor layer SC, multiple conductive layers, and multiple insulating layers disposed on the substrate SUB. The multiple conductive layers may include a first conductive layer 100, a second conductive layer 200, a third conductive layer 300, and a fourth conductive layer 400. The multiple insulating layers may include a buffer layer 101, a gate insulating film 102, an interlayer insulating film 103, a passivation film 104, and a via layer 105.

[0098] In the following text, for ease of explanation, the terms "and" will be used. Figure 2 The essentially the same composition gives rise to new reference numerals.

[0099] First, let's explain the one-pixel PX.

[0100] Yes, the substrate SUB is an insulating substrate and contains a transparent material.

[0101] A first conductive layer 100 is disposed on a substrate SUB. The first conductive layer 100 may include first to third lower light-shielding patterns 111, 112, 113, and a first power line 120. Figure 2 (ELVDL), first to third data lines 131, 132, 133 ( Figure 2 (DL1, DL2, DL3), reference voltage line 140 ( Figure 2 'RVL') and the second voltage line 150 ( Figure 2 (e.g., 'ELVSL'). The first conductive layer 100 may be composed of a Ti / Cu double film consisting of a titanium layer and a copper layer, but is not limited thereto.

[0102] The first lower light-shielding pattern 111, the second lower light-shielding pattern 112, and the third lower light-shielding pattern 113 can perform the function of protecting the semiconductor layer SC from the influence of external light. The first lower light-shielding pattern 111, the second lower light-shielding pattern 112, and the third lower light-shielding pattern 113 have patterned shapes. The first lower light-shielding pattern 111, the second lower light-shielding pattern 112, and the third lower light-shielding pattern 113 can be configured to cover at least the channel region of the upper semiconductor layer SC from below, and can be configured to cover the entire semiconductor layer SC.

[0103] The first power line 120 can transmit a first power supply voltage to each sub-pixel PXS1, PXS2, and PXS3. The first power line 120 may be positioned on one side of the first direction DR1, for example, the left side, with the center of the pixel PX as a reference, and extends towards the second direction DR2. The first power line 120 may extend to another pixel PX adjacent to it in the second direction DR2. The first power line 120 may overlap with the first to third semiconductor patterns ACT1, ACT2, and ACT3, but is not limited thereto.

[0104] The first power line 120 can be electrically connected to each of the first to third semiconductor patterns ACT1, ACT2, and ACT3 via the fourth to sixth data conductive patterns 344, 345, and 346. This allows the first power supply voltage to be transmitted to the first transistor T1 of each sub-pixel PXS1, PXS2, and PXS3.

[0105] The first to third data lines 131, 132, and 133 can transmit data signals to each sub-pixel PXS1, PXS2, and PXS3. Alternatively, the first to third data lines 131, 132, and 133 can be configured on one side of the first direction DR1, for example, the right side, with the center of pixel PX as a reference, and extend towards the second direction DR2. The first to third data lines 131, 132, and 133 can also extend to another pixel PX adjacent to it in the second direction DR2.

[0106] The first data line 131 can be electrically connected to the fourth semiconductor pattern ACT4 via the first contact pattern CE1. This allows data signals to be transmitted to the second transistor T2 of the first sub-pixel PXS1. The second data line 132 can be electrically connected to the fifth semiconductor pattern ACT5 via the second contact pattern CE2. This allows data signals to be transmitted to the second transistor T2 of the second sub-pixel PXS2. The third data line 133 can be electrically connected to the sixth semiconductor pattern ACT6 via the third contact pattern CE3. This allows data signals to be transmitted to the second transistor T2 of the third sub-pixel PXS3.

[0107] The reference voltage line 140 can transmit reference voltages to each sub-pixel PXS1, PXS2, and PXS3. Alternatively, the reference voltage line 140 can be positioned on one side of the first power line 120 in the first direction DR1, for example, on the left side, and extend towards the second direction DR2. The reference voltage line 140 can also extend to another pixel PX adjacent to it in the second direction DR2.

[0108] The reference voltage line 140 can be electrically connected to each of the seventh to ninth semiconductor patterns ACT7, ACT8, and ACT9 via the seventh contact pattern CE7. This allows the transmission of a reference voltage to the third transistor T3 of each sub-pixel PXS1, PXS2, and PXS3.

[0109] The second voltage line 150 can transmit a second power supply voltage to each sub-pixel PXS1, PXS2, and PXS3. The second voltage line 150 may be positioned on one side of the reference voltage line 140 in the first direction DR1, for example, on the left, and extend towards the second direction DR2. The second voltage line 150 can also extend to another pixel PX adjacent to it in the second direction DR2.

[0110] A buffer layer 101 is disposed on the first conductive layer 100. The buffer layer 101 may be configured to cover the entire surface of the substrate SUB on which the first conductive layer 100 is disposed. The buffer layer 101 may comprise silicon nitride, silicon oxide, or silicon oxynitride, etc. In one embodiment, the buffer layer 101 may comprise SiN. x / SiO x The double membrane.

[0111] A semiconductor layer SC is disposed on the buffer layer 101. The semiconductor layer SC may include first to ninth semiconductor patterns ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, ACT7, ACT8, and ACT9.

[0112] It is possible that the first to third semiconductor patterns ACT1, ACT2, and ACT3 are the active layers of the first transistor T1 included in a pixel PX, the fourth to sixth semiconductor patterns ACT4, ACT5, and ACT6 are the active layers of the second transistor T2, and the third semiconductor patterns ACT7, ACT8, and ACT9 are the active layers of the third transistor T3.

[0113] The first to ninth semiconductor patterns ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, ACT7, ACT8, and ACT9 may extend in the first direction DR1, i.e., the lateral direction shown in the figure, and have a rectangular shape or a shape that expands to have wider ends. Each of the first to ninth semiconductor patterns ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, ACT7, ACT8, and ACT9 may include a channel region that overlaps with the gate electrode in the thickness direction (the third direction DR3) and conductive regions located on one side and the other side of the channel region. The conductive regions may have higher conductivity and lower resistance than the channel regions. The conductive regions of each of the first to ninth semiconductor patterns ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, ACT7, ACT8, and ACT9 may include the source electrode and drain electrode (or, a first source / drain electrode and a second source / drain electrode) of each transistor T1, T2, and T3 in the region overlapping with the third conductive layer 300.

[0114] The first to third semiconductor patterns ACT1, ACT2, and ACT3 can be located near the center of a pixel PX with reference to the first direction DR1. With reference to the second direction DR2, the first semiconductor pattern ACT1 can be located closer to the upper part of the image than the second semiconductor pattern ACT2 and the third semiconductor pattern ACT3, and the second semiconductor pattern ACT2 can be located closer to the upper part of the image than the third semiconductor pattern ACT3. Each of the first to third semiconductor patterns ACT1, ACT2, and ACT3 can be the active layer of the first transistor T1 of each of the first to third sub-pixels PXS1, PXS2, and PXS3.

[0115] The fourth to sixth semiconductor patterns ACT4, ACT5, and ACT6 can be located on the right side of the image within a pixel PX, with the first direction DR1 as a reference. With the second direction DR2 as a reference, the fourth semiconductor pattern ACT4 can be located closer to the upper part of the image than the fifth semiconductor pattern ACT5 and the sixth semiconductor pattern ACT6, and the fifth semiconductor pattern ACT5 can be located closer to the upper part of the image than the sixth semiconductor pattern ACT6. Each of the fourth to sixth semiconductor patterns ACT4, ACT5, and ACT6 can be the active layer of the second transistor T2 of each of the first to third sub-pixels PXS1, PXS2, and PXS3.

[0116] The seventh to ninth semiconductor patterns ACT7, ACT8, and ACT9 can be located on the left side of the image within a pixel PX, with the first direction DR1 as a reference. With the second direction DR2 as a reference, the seventh semiconductor pattern ACT7 can be located closer to the upper part of the image than the eighth semiconductor pattern ACT8 and the ninth semiconductor pattern ACT9, and the eighth semiconductor pattern ACT8 can be located closer to the upper part of the image than the ninth semiconductor pattern ACT9. Each of the seventh to ninth semiconductor patterns ACT7, ACT8, and ACT9 can be the active layer of the third transistor T3 of each of the first to third sub-pixels PXS1, PXS2, and PXS3.

[0117] The semiconductor layer SC may comprise an oxide semiconductor. The oxide semiconductor may include indium-tin oxide (ITO), indium-gallium-tin oxide (ITGO), indium-gallium-zinc oxide (IGZO), or indium-gallium-zinc-tin oxide (IGZTO). However, it is not limited to these; the semiconductor layer SC may also be composed of polycrystalline silicon, monocrystalline silicon, or amorphous silicon.

[0118] A gate insulating film 102 is disposed on the semiconductor layer SC. In a planar plane, the gate insulating film 102 may include a pattern substantially identical to that of the second conductive layer 200. In other words, the gate insulating film 102 may include a pattern corresponding to the pattern of the second conductive layer 200. Alternatively, the pattern of the gate insulating film 102 may include a pattern substantially identical to that of the second conductive layer 200, but the pattern of the gate insulating film 102 may have a shape enlarged from the pattern of the second conductive layer 200. In this case, the entire region of the second conductive layer 200 may completely overlap with the gate insulating film 102, or only a portion of the gate insulating film 102 may overlap with the second conductive layer 200.

[0119] The gate insulating film 102 may contain silicon compounds, metal oxides, etc. For example, the gate insulating film 102 may contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

[0120] A second conductive layer 200 is disposed on the gate insulating film 102. The second conductive layer 200 may contain one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second conductive layer 200 may be a single-layer film or a multilayer film.

[0121] The second conductive layer 200 may include first to fifth gate conductive patterns 211, 212, 213, 214, 215 and first to sixth overlapping conductive patterns 221, 222, 223, 224, 225, 226.

[0122] Each of the first to fifth gate conductive patterns 211, 212, 213, 214, 215 may partially overlap with the first to ninth semiconductor patterns ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, ACT7, ACT8, ACT9. The first to fifth gate conductive patterns 211, 212, 213, 214, 215 may include the gate electrodes of each transistor T1, T2, T3 of each sub-pixel PXS1, PXS2, PXS3 in the overlapping region.

[0123] In other words, the first gate conductive pattern 211 may overlap with a portion of the first semiconductor pattern ACT1 to include the gate electrode of the first transistor T1 of the first sub-pixel PXS1. The first gate conductive pattern 211 may overlap at least with the channel region of the first semiconductor pattern ACT1. Similarly, the second gate conductive pattern 212 may overlap with a portion of the second semiconductor pattern ACT2, and the third gate conductive pattern 213 may overlap with a portion of the third semiconductor pattern ACT3. They may respectively include the gate electrode of the first transistor T1 of the second sub-pixel PXS2 and the gate electrode of the first transistor T1 of the third sub-pixel PXS3.

[0124] Alternatively, each of the first to third gate conductive patterns 211, 212, 213 may overlap with the first to third data conductive patterns 341, 342, 343, and the overlapping region may include the first electrode of the storage capacitor CST of each sub-pixel PXS1, PXS2, PXS3. The first electrode of the storage capacitor CST of each sub-pixel PXS1, PXS2, PXS3 may be formed by each of the first to third gate conductive patterns 211, 212, 213 itself, or it may be formed by a portion extending from the gate electrode of each transistor T1, T2, T3.

[0125] The fourth gate conductive pattern 214 may overlap with a portion of each of the fourth to sixth semiconductor patterns ACT4, ACT5, and ACT6 to include the gate electrode of the second transistor T2 of each of the first to third sub-pixels PXS1, PXS2, and PXS3. The fourth gate conductive pattern 214 may overlap with the channel region of each of the fourth to sixth semiconductor patterns ACT4, ACT5, and ACT6. The fourth gate conductive pattern 214 may be electrically connected to the scan line 310.

[0126] The fifth gate conductive pattern 215 may overlap with a portion of each of the seventh to ninth semiconductor patterns ACT7, ACT8, and ACT9, and include the gate electrode of the third transistor T3 of each of the first to third sub-pixels PXS1, PXS2, and PXS3. The fifth gate conductive pattern 215 may overlap with the channel region of each of the seventh to ninth semiconductor patterns ACT7, ACT8, and ACT9. The fifth gate conductive pattern 215 may be electrically connected to the sensing line 320.

[0127] The first to sixth overlapping conductive patterns 221, 222, 223, 224, 225, and 226 may overlap with at least one of the first power line 120, the second power line 150, the scan line 310, and the sensing line 320, and be electrically connected through contact holes, etc. This can reduce the resistance of each wiring, allowing for smoother signal and voltage transmission. For example, the first to third overlapping conductive patterns 221, 222, and 223 may overlap with the first power line 120 and be electrically connected to it through contact holes, etc. The fourth overlapping conductive pattern 224 may overlap with the second power line 150 and be electrically connected to it through contact holes, etc. The fifth overlapping conductive pattern 225 may overlap with the scan line 310 and be electrically connected to it through contact holes, etc. The sixth overlapping conductive pattern 225 may overlap with the sensing line 320 and be electrically connected to it through contact holes, etc.

[0128] An interlayer insulating film 103 is disposed on the second conductive layer 200. The interlayer insulating film 103 may contain inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and zinc oxide.

[0129] A third conductive layer 300 is disposed on the interlayer insulating film 103. The third conductive layer 300 may contain one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer 300 may be a single-layer film or a multilayer film. For example, the third conductive layer 300 may include a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0130] The third conductive layer 300 may include scan lines 310. Figure 2 'SCL'), sensor line 320 ( Figure 2 (SSL), first power line 330, first to sixth data conductive patterns 341, 342, 343, 344, 345, 346 and first to seventh contact patterns CE1, CE2, CE3, CE4, CE5, CE6, CE7.

[0131] Scan line 310 can transmit scan signals to the gate electrode of the second transistor T2 of each sub-pixel PXS1, PXS2, and PXS3. Scan line 310 is located above a pixel PX in the figure and extends in the first direction DR1. Scan line 310 can extend to another pixel PX that is adjacent to the pixel PX in the first direction DR1.

[0132] The scan line 310 may overlap with the fourth gate conductive pattern 214 in at least a portion of the region. In the overlapping region, the scan line 310 may be electrically connected to the fourth gate conductive pattern 214 by exposing the contact hole CNT1 of the fourth gate conductive pattern 214 through the interlayer insulating film 103.

[0133] Sensing line 320 can transmit sensing signals to the third transistor T3 of each sub-pixel PXS1, PXS2, and PXS3. Sensing line 320 is located below a pixel PX in the figure and extends in the first direction DR1. Sensing line 320 can extend to another pixel PX that is adjacent to the pixel PX in the first direction DR1.

[0134] The sensing line 320 may overlap with the fifth gate conductive pattern 215 in at least a portion of the region. In the overlapping region, the sensing line 320 may be electrically connected to the fifth gate conductive pattern 215 by exposing the contact hole CNT2 of the fifth gate conductive pattern 215 through the interlayer insulating film 103.

[0135] The scan line 310 and sensing line 320 extending in the first direction DR1 can be split into two lines in the region where they intersect with the first to third data lines 131, 132, 133 and the reference voltage line 140 extending in the second direction DR2, and then extend in the first direction DR1. In other words, the scan line 310 and sensing line 320 can extend as a single wiring in the first direction DR1 on one side and the other side of the first to third data lines 131, 132, 133 and the reference voltage line 140, and split into two lines in the region where they intersect with the first to third data lines 131, 132, 133 and the reference voltage line 140, and then extend in the first direction DR1.

[0136] The sub-first power line 330 may extend in a first direction DR1 and be supplied with a first power supply voltage. The sub-first power line 330 may be configured between the scan line 310 and the sensing line 320. The sub-first power line 330 may extend to another pixel PX disposed adjacent to it in the first direction DR1 of the pixel PX.

[0137] The first power line 330 can form a mesh structure together with the first power line 120, and can be electrically connected to the first power line 120 by a contact hole CNT3 that exposes a portion of the first power line 120 through the interlayer insulating film 103 and the buffer layer 101 in the thickness direction (third direction DR3).

[0138] The first to sixth data conductive patterns 341, 342, 343, 344, 345, and 346 can be configured between the first power line 120 and the first to third data lines 131, 132, and 133. The fourth to sixth data conductive patterns 344, 345, and 346 can be configured on one side of the first direction DR1 (e.g., the left side) of the first to third data conductive patterns 341, 342, and 343.

[0139] The first to third data conductive patterns 341, 342, and 343 can overlap with the first to third semiconductor patterns ACT1, ACT2, and ACT3, respectively. In the overlapping region, each of the first to third data conductive patterns 341, 342, and 343 can be electrically connected to the first to third semiconductor patterns ACT1, ACT2, and ACT3 through contact holes CNT4, CNT5, and CNT6 that expose a portion of the first to third semiconductor patterns ACT1, ACT2, and ACT3 through the interlayer insulating film 103. The first to third data conductive patterns 341, 342, and 343 can include the second source / drain electrode of the first transistor T1 of each sub-pixel PXS1, PXS2, and PXS3.

[0140] The first to third conductive data patterns 341, 342, and 343 may include regions protruding in the first direction DR1 in at least a portion of their area. These protruding regions may cross the first power line 120 and extend to one side of the first direction DR1 (e.g., the left side). In this case, the protruding regions may overlap with the first power line 120 in at least a portion of their area, and be insulated from the first power line 120 in the overlapping area by a buffer layer 101 and an interlayer insulating film 103.

[0141] Alternatively, the protruding region of the first data conductive pattern 341 may be located on the second direction DR2 side of the fourth data conductive pattern 344 and disposed between the fourth data conductive pattern 344 and the scan line 310. The protruding region of the second data conductive pattern 342 may be disposed between the fourth data conductive pattern 344 and the fifth data conductive pattern 345. The protruding region of the third data conductive pattern 343 may be disposed between the fifth data conductive pattern 345 and the sixth data conductive pattern 346.

[0142] In the protruding region of each of the first to third data conductive patterns 341, 342, and 343, each of the first to third data conductive patterns 341, 342, and 343 may overlap with the seventh to ninth semiconductor patterns ACT7, ACT8, and ACT9. In the overlapping region, each of the first to third data conductive patterns 341, 342, and 343 may be electrically connected to the seventh to ninth semiconductor patterns ACT7, ACT8, and ACT9 by exposing a portion of the contact holes CNT7, CNT8, and CNT9 through the interlayer insulating film 103. The first to third data conductive patterns 341, 342, and 343 may include the second source / drain electrode of the third transistor T3 of each sub-pixel PXS1, PXS2, and PXS3.

[0143] Each of the first to third data conductive patterns 341, 342, and 343 may overlap with each of the first to third gate conductive patterns 211, 212, and 213. In the overlapping region, each of the first to third data conductive patterns 341, 342, and 343 may include the second electrode of the storage capacitor CST of each sub-pixel PXS1, PXS2, and PXS3. That is, in the portion that does not overlap with the first to third semiconductor patterns ACT1, ACT2, and ACT3 but overlaps with the first to third gate conductive patterns 211, 212, and 213, each of the first to third data conductive patterns 341, 342, and 343 may include the second electrode of the storage capacitor CST of each sub-pixel PXS1, PXS2, and PXS3.

[0144] The fourth to sixth data conductive patterns 344, 345, and 346 can overlap with the seventh to ninth semiconductor patterns ACT7, ACT8, and ACT9, respectively. In the overlapping region, each of the fourth to sixth data conductive patterns 344, 345, and 346 can be electrically connected to the seventh to ninth semiconductor patterns ACT7, ACT8, and ACT9 through contact holes CNT10, CNT11, and CNT12 that expose a portion of the seventh to ninth semiconductor patterns ACT7, ACT8, and ACT9 via the interlayer insulating film 103. The fourth to sixth data conductive patterns 344, 345, and 346 can include the first source / drain electrode of the first transistor T1 of each sub-pixel PXS1, PXS2, and PXS3.

[0145] It is possible that each of the fourth to sixth data conductive patterns 344, 345, 346 overlaps with the first to third overlapping patterns 221, 222, 223, and is electrically connected through a contact hole in the overlapping area.

[0146] Each of the fourth to sixth conductive data patterns 344, 345, and 346 can overlap with the first power line 120. In the overlapping area, the contact holes CNT25, CNT26, and CNT27 of the first power line 120 can be exposed through the interlayer insulating film 103 and the buffer layer 101 to electrically connect with the first power line 120.

[0147] That is, the first power line 120 and the first to third semiconductor patterns ACT1, ACT2, and ACT3 can be electrically connected through the fourth to sixth data conductive patterns 344, 345, and 346.

[0148] Each of the first to third contact patterns CE1, CE2, and CE3 may overlap with the fourth to sixth semiconductor patterns ACT4, ACT5, and ACT6. In the overlapping area, each of the first to third contact patterns CE1, CE2, and CE3 may be electrically connected to the fourth to sixth semiconductor patterns ACT4, ACT5, and ACT6 through contact holes CNT13, CNT14, and CNT15 that expose a portion of the fourth to sixth semiconductor patterns ACT4, ACT5, and ACT6 via the interlayer insulating film 103. Each of the first to third contact patterns CE1, CE2, and CE3 may include the first source / drain electrode of the second transistor T2 of each sub-pixel PXS1, PXS2, and PXS3.

[0149] Each of the first to third contact patterns CE1, CE2, and CE3 may overlap with the first to third data lines 131, 132, and 133. In the overlapping area, each of the first to third contact patterns CE1, CE2, and CE3 may be electrically connected to the first to third data lines 131, 132, and 133 by exposing contact holes CNT16, CNT17, and CNT18 that penetrate the interlayer insulating film 103 and the buffer layer 101.

[0150] That is, the fourth to sixth semiconductor patterns ACT4, ACT5, ACT6 and the first to third data lines 131, 132, 133 can be electrically connected through the first to third contact patterns CE1, CE2, CE3.

[0151] Alternatively, the second contact pattern CE2 may span the first data line 131, and the third contact pattern CE3 may span both the first data line 131 and the second data line 132. Alternatively, a buffer layer 101 and an interlayer insulating film 103 may be disposed in the areas where the second contact pattern CE2 overlaps with the first data line 131 and the areas where the third contact pattern CE3 overlaps with both the first and second data lines 131 and 132, thereby insulating the second contact pattern CE2 from the first data line 131 and the third contact pattern CE3 from both the first and second data lines 131 and 132.

[0152] Each of the fourth to sixth contact patterns CE4, CE5, and CE6 may overlap with the fourth to sixth semiconductor patterns ACT4, ACT5, and ACT6. In the overlapping area, each of the first to third contact patterns CE1, CE2, and CE3 may be electrically connected to the fourth to sixth semiconductor patterns ACT4, ACT5, and ACT6 through contact holes CNT19, CNT20, and CNT21 that expose a portion of the fourth to sixth semiconductor patterns ACT4, ACT5, and ACT6 through the interlayer insulating film 103.

[0153] Each of the fourth to sixth contact patterns CE4, CE5, and CE6 may overlap with the first to third gate conductive patterns 211, 212, and 213. In the overlapping area, each of the first to third contact patterns CE1, CE2, and CE3 may expose contact holes CNT22, CNT23, and CNT24 that are part of the first to third gate conductive patterns 211, 212, and 213 through the interlayer insulating film 103, thus electrically connecting to the first to third gate conductive patterns 211, 212, and 213.

[0154] That is, the fourth to sixth semiconductor patterns ACT4, ACT5, and ACT6 and the first to third gate conductive patterns 211, 212, and 213 can be electrically connected through the fourth to sixth contact patterns CE4, CE5, and CE6. The fourth to sixth contact patterns CE4, CE5, and CE6 may include the second source / drain electrodes of the second transistor T2 of each sub-pixel PXS1, PXS2, and PXS3.

[0155] The seventh contact pattern CE7 may overlap with the reference voltage line 140. In the overlapping area, the seventh contact pattern CE7 may be electrically connected to the reference voltage line 140 by exposing a portion of the reference voltage line 140 through a contact hole CNT28 that penetrates the interlayer insulating film 103 and the buffer layer 101.

[0156] The seventh contact pattern CE7 may overlap with each of the seventh to ninth semiconductor patterns ACT7, ACT8, and ACT9. In the overlapping region, the seventh contact pattern CE7 may electrically connect to the seventh to ninth semiconductor patterns ACT7, ACT8, and ACT9 by exposing contact holes CNT29, CNT30, and CNT31 through the interlayer insulating film 103. The seventh contact pattern CE7 may include the first source / drain electrode of the third transistor T3 of each sub-pixel PXS1, PXS2, and PXS3.

[0157] That is, the reference voltage line 140 and the seventh to ninth semiconductor patterns ACT7, ACT8, and ACT9 can be electrically connected through the seventh contact pattern CE7.

[0158] A passivation film 104 may be disposed on the third conductive layer 300. The passivation film 104 serves to cover and protect the third conductive layer 300. The passivation film 104 may contain inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and zinc oxide.

[0159] A via layer 105 is disposed on the passivation film 104. The via layer 105 can completely cover the top surface of the passivation film 104. When the via layer 105 is composed of an organic film, its top surface can be flat despite the presence of a step below. The via layer 105 can include inorganic insulating materials or organic insulating materials such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylenether resin, polyphenylenesulfide resin, or benzocyclobutene (BCB).

[0160] A fourth conductive layer 400 may be disposed on the via layer 105. The fourth conductive layer 400 may include a first pixel electrode PXE1, a second pixel electrode PXE2, and a third pixel electrode PXE3. Specifically, the first pixel electrode PXE1 may include the anode electrode of the light-emitting element EMD of the first sub-pixel PXS1, the second pixel electrode PXE2 may include the anode electrode of the light-emitting element EMD of the second sub-pixel PXS2, and the third pixel electrode PXE3 may include the anode electrode of the light-emitting element EMD of the third sub-pixel PXS3.

[0161] The first pixel electrode PXE1 can be disposed adjacent to the right side of the center of pixel PX. The first pixel electrode PXE1 can be disposed at a position overlapping with the first to third data lines 131, 132, and 133. The second pixel electrode PXE2 can be disposed near the center of pixel PX. The second pixel electrode PXE2 can be disposed overlapping with the first to third data conductive patterns 341, 342, and 343. The third pixel electrode PXE3 can be disposed on the left side of pixel PX, based on the center of pixel PX. The third pixel electrode PXE3 can be disposed overlapping with the first power line 120, the reference voltage line 140, and the second power line 150. However, it is not limited to this.

[0162] Each of the first to third pixel electrodes PXE1, PXE2, and PXE3 can overlap with the first to third data conductive patterns 341, 342, and 343. In the overlapping area, each of the first to third pixel electrodes PXE1, PXE2, and PXE3 can expose a portion of the contact holes CNT32, CNT33, and CNT34 of the first to third data conductive patterns 341, 342, and 343 through the through-hole layer 105 and the passivation film 104 to be electrically connected to the first to third data conductive patterns 341, 342, and 343.

[0163] A pixel defining film (PDL) can be disposed on the fourth conductive layer 400. Multiple openings defined by the PDL can be disposed therein. Each of the multiple openings can expose a portion of any one of the first to third pixel electrodes PXE1, PXE2, and PXE3.

[0164] An emissive layer (EML) is disposed on the first to third pixel electrodes PXE1, PXE2, and PXE3 exposed by the pixel defining film (PDL) and on the PDL itself. The EML may include an organic layer containing organic matter. Specifically, the organic layer may include an organic emissive layer, and depending on the application, an auxiliary layer for assisting light emission may further include a hole injection / transport layer and / or an electron injection / transport layer.

[0165] A common electrode CME (or cathode electrode) can be configured on the light-emitting layer EML. The common electrode CME can be connected without distinguishing between individual pixels (PX) and sub-pixels (PXS1, PXS2, PXS3). The common electrode CME can also be a fully configured electrode that does not distinguish between individual pixels (PX) and sub-pixels (PXS1, PXS2, PXS3). The common electrode CME can be a light-emitting element (see reference). Figure 4 The second electrode of the 'EMD' can be, for example, a cathode electrode.

[0166] The first to third pixel electrodes PXE1, PXE2, PXE3, the emissive layer EML, and the common electrode CME can constitute a light-emitting element (e.g., an organic light-emitting element). Light emitted from the emissive layer EML can be emitted upwards and outwards through the common electrode CME.

[0167] An encapsulation film may also be disposed above the common electrode CME. The encapsulation film may include at least one encapsulation layer. For example, the encapsulation layer may include a first inorganic film, an organic film, and a second inorganic film.

[0168] Next, the repair circuit DP will be explained.

[0169] The first conductive layer 100 may further include a repaired lower light-shielding pattern 160, a repaired first power supply pattern 170, and a repaired connection pattern 180. The repaired lower light-shielding pattern 160, the repaired first power supply pattern 170, and the repaired connection pattern 180 may be configured between the first to third data lines 131, 132, and 133 of two adjacent pixels PX. Alternatively, the repaired lower light-shielding pattern 160, the repaired first power supply pattern 170, and the repaired connection pattern 180 may be configured in the display area DA, but not overlapping with the anode electrodes of each sub-pixel PXS1, PXS2, and PXS3.

[0170] The repair lower light-shielding pattern 160 can perform the function of protecting the first repair semiconductor pattern DACT1 from the influence of external light. The repair lower light-shielding pattern 160 has a patterned shape. The repair lower light-shielding pattern 160 can be configured to cover the channel region of the first repair semiconductor pattern DACT1, and can also be configured to cover the entire first repair semiconductor pattern DACT1.

[0171] The repair lower light-shielding pattern 160 can be configured at the center of the repair circuit DP. In other words, the repair lower light-shielding pattern 160 can be located at the center of the repair circuit DP with reference to the second direction DR2.

[0172] The repair first power supply pattern 170 can be located on the other side (lower side) of the second direction DR2 of the repair lower light-shielding pattern 160. The repair first power supply pattern 170 can be configured below the repair circuit DP. The repair first power supply pattern 170 can overlap with the first repair semiconductor pattern DACT1, but is not limited thereto.

[0173] The repair first power pattern 170 can overlap and intersect with the scan line 310, the sensing line 320, and the sub-first power line 330 on a plane. In the overlapping area, a buffer layer 101 and an interlayer insulating film 103 can be disposed between the repair first power pattern 170 and the scan line 310, the sensing line 320, and the sub-first power line 330 to insulate each other.

[0174] The repaired first power pattern 170 can overlap with the sub-first power line 330. In the overlapping area, the repaired first power pattern 170 can be electrically connected to the sub-first power line 330 by exposing its contact holes CNT35 through the interlayer insulating film 103 and the buffer layer 101. That is, the repaired first power pattern 170 can be electrically connected to the first power line 120 through the sub-first power line 330.

[0175] The repair connection pattern 180 can be located on the second direction DR2 side (upper side) of the repair lower light-shielding pattern 160. When the repair connection pattern 180 is configured, the first repair contact patterns DCE1 of two adjacent pixels PX can be separated. Thus, it is possible to make a smoother electrical connection with either of the two adjacent pixels PX while being electrically insulated from the other.

[0176] The semiconductor layer SC may also include a first repair semiconductor pattern DACT1 and a second repair semiconductor pattern DACT2. The first repair semiconductor pattern DACT1 and the second repair semiconductor pattern DACT2 may be disposed in the display area DA, but do not overlap with the anode electrodes of each sub-pixel PXS1, PXS2, and PXS3.

[0177] Alternatively, the first repair semiconductor pattern DACT1 can be the active layer of the first repair transistor DT1, and the second repair semiconductor pattern DACT2 can be the active layer of the second repair transistor DT2. Alternatively, the first repair semiconductor pattern DACT1 and the second repair semiconductor pattern DACT2 can be disposed in the display area DA, but do not overlap with the anode electrodes of each sub-pixel PXS1, PXS2, and PXS3.

[0178] Each of the first repair semiconductor pattern DACT1 and the second repair semiconductor pattern DACT2 may include a channel region configured to overlap with the gate electrode in the thickness direction (third direction DR3) and conductive regions located on one side and the other side of the channel region. The conductive regions may be more conductive and have lower resistance than the channel region. The conductive regions of each of the first repair semiconductor pattern DACT1 and the second repair semiconductor pattern DACT2 may include the source electrode and drain electrode (or, a first source / drain electrode and a second source / drain electrode) of each repair transistor DT1, DT2 in the region overlapping with the third conductive layer 300.

[0179] The first repair semiconductor pattern DACT1 and the second repair semiconductor pattern DACT2 can be respectively configured on the other side (lower side) and one side (upper side) of the second direction DR2 in the repair circuit DP.

[0180] The second conductive layer 200 may further include a first repair gate conductive pattern 231 and a second repair gate conductive pattern 232. The first repair gate conductive pattern 231 and the second repair gate conductive pattern 232 may be disposed in the display area DA, but do not overlap with the anode electrodes of each sub-pixel PXS1, PXS2, and PXS3.

[0181] The first repair gate conductive pattern 231 can be disposed at the center of the repair circuit DP. In other words, the first repair gate conductive pattern 231 can be located at the center of the repair circuit DP with reference to the second direction DR2.

[0182] Each of the first repair gate conductive pattern 231 and the second repair gate conductive pattern 232 may partially overlap with the first repair semiconductor pattern DACT1 and the second repair semiconductor pattern DACT2. Each of the first repair gate conductive pattern 231 and the second repair gate conductive pattern 232 may include the gate electrode of the first repair transistor DT1 and the second repair transistor DT2 in the overlapping region.

[0183] In other words, the first repair gate conductive pattern 231 may overlap with a portion of the first repair semiconductor pattern DACT1, and the gate electrode of the first repair transistor DT1 may be included in the overlapping region. The first repair gate conductive pattern 231 may overlap with at least the channel region of the first repair semiconductor pattern DACT1.

[0184] Alternatively, the first repair gate conductive pattern 231 may overlap with the repair data conductive pattern 350, and the first electrode of the repair capacitor DCST may be included in the overlapping region. That is, the first electrode of the repair capacitor DCST may be formed by the first repair gate conductive pattern 231 itself, or it may be formed by a portion extending from the gate electrode of the first repair transistor DT1.

[0185] The first repair gate conductive pattern 231 may include a region protruding in a second direction DR2 from the region overlapping with the repair data conductive pattern 350. The protruding region may overlap with and be electrically connected to the first repair contact pattern DCE1. That is, the first repair gate conductive pattern 231 can be electrically connected to the second repair semiconductor pattern DACT2 through the first repair contact pattern DCE1.

[0186] The second repair gate conductive pattern 232 can be configured on the second direction DR2 side of the first repair gate conductive pattern 231. The second repair gate conductive pattern 232 can be configured on the second direction DR2 side (upper side) of the repair circuit DP.

[0187] The second repair gate conductive pattern 232 can overlap with the scan line 310. In the overlapping area, the second repair gate conductive pattern 232 can be electrically connected to the scan line 310 by exposing the contact hole CNT36 of the second repair gate conductive pattern 232 through the interlayer insulating film 103.

[0188] The second repair gate conductive pattern 232 may extend from the region overlapping with the scan line 310 to the other side of the second direction DR2, and may cross the repair connection pattern 180 and at least partially overlap with the second repair semiconductor pattern DACT2. The second repair gate conductive pattern 232 may include the gate electrode of the second repair transistor DT2 in the overlapping region. The second repair gate conductive pattern 232 may at least overlap with the channel region of the second repair semiconductor pattern DACT2.

[0189] The third conductive layer 300 may also include a repair data conductive pattern 350 and first to fourth repair contact patterns DCE1, DCE2, DCE3, and DCE4. The repair data conductive pattern 350 and the first to fourth repair contact patterns DCE1, DCE2, DCE3, and DCE4 may be configured in the display area DA, but do not overlap with the anode electrodes of each sub-pixel PXS1, PXS2, and PXS3.

[0190] The repair data conductive pattern 350 may overlap with the first repair semiconductor pattern DACT1. In the overlapping area, the repair data conductive pattern 350 may be electrically connected to the first repair semiconductor pattern DACT1 through a contact hole CNT37 that exposes a portion of the first repair semiconductor pattern DACT1 through the interlayer insulating film 103. The repair data conductive pattern 350 may include the second source / drain electrode of the second repair transistor DT2 of the repair circuit DP.

[0191] The repair data conductive pattern 350 may overlap with the first repair gate conductive pattern 231. In the overlapping region, the repair data conductive pattern 350 may include the second electrode of the repair capacitor DCST. That is, in the portion that does not overlap with the first repair semiconductor pattern DACT1 but overlaps with the first repair gate conductive pattern 231, the repair data conductive pattern 350 may include the second electrode of the repair capacitor DCST.

[0192] The repair data conductive pattern 350 may include a region protruding in a second direction DR2 from a region overlapping with the first repair gate conductive pattern 231. This protruding region may overlap with the repair circuit connection pattern 410, and a fourth recessed pattern RC4 may be configured in the overlapping region. A detailed description thereof will follow.

[0193] The first repair contact pattern DCE1 can be configured on the second direction DR2 side of the repair data conductive pattern 250. The first repair contact pattern DCE1 can overlap with the second repair semiconductor pattern DACT2. In the overlapping region, the first repair contact pattern DCE1 can expose the contact hole CNT38 of the second repair semiconductor pattern DACT2 through the interlayer insulating film 103 and contact the second repair semiconductor pattern DACT2. In addition, the first repair contact pattern DCE1 can overlap with the first repair gate conductive pattern 231. In the overlapping region, the first repair contact pattern DCE1 can expose the contact hole CNT39 of the first repair gate conductive pattern 231 through the interlayer insulating film 103 and contact the first repair gate conductive pattern 231.

[0194] That is, the second repair semiconductor pattern DACT2 can be electrically connected to the first repair gate conductive pattern 231 through the first repair contact pattern DCE1. The first repair contact pattern DCE1 may include the second source / drain electrode of the second repair transistor DT2.

[0195] The second repair contact pattern DCE2 can be disposed on the other side (right side) of the first repair contact pattern DCE1 in the first direction DR1. The second repair contact pattern DCE2 can be disposed on the other side of the first repair contact pattern DCE1 in the first direction DR1 with the second repair gate conductive pattern 232 placed in the middle. The second repair contact pattern DCE2 can overlap with the second repair semiconductor pattern DACT2. In the overlapping region, the second repair contact pattern DCE2 can expose the contact hole CNT40 of the second repair semiconductor pattern DACT2 through the interlayer insulating film 103 and contact the second repair semiconductor pattern DACT2. Additionally, the second repair contact pattern DCE2 can overlap with the repair connection pattern 180. In the overlapping region, the second repair contact pattern DCE2 can expose the contact hole CNT41 of the repair connection pattern 180 through the interlayer insulating film 103 and the buffer layer 101 and contact the repair connection pattern 180.

[0196] That is, the second repair semiconductor pattern DACT2 can be electrically connected to the repair connection pattern 180 through the second repair contact pattern DCE2. The second repair contact pattern DCE2 may include the first source / drain electrode of the second repair transistor DT2.

[0197] The third repair contact pattern DCE3 (or the second repair circuit connection pattern) can be configured on the second direction DR2 side of the first repair contact pattern DCE1. The third repair contact pattern DCE3 can overlap with the repair connection pattern 180. In the overlapping area, the third repair contact pattern DCE3 can expose the contact hole CNT42 of the repair connection pattern 180 through the interlayer insulating film 103 and the buffer layer 101 to contact the repair connection pattern 180.

[0198] The third repair contact pattern DCE3 may extend from the portion that contacts the repair connection pattern 180 toward the first direction DR1 side and cross the first to third data lines 131, 132, and 133 of the pixel PX disposed on the first direction DR1 side of the repair circuit DP. The third repair contact pattern DCE3 may overlap with the first to third data lines 131, 132, and 133, and the first to third recessed patterns RC1, RC2, and RC3 may be disposed in each of the overlapping regions.

[0199] To illustrate the first to third recessed patterns RC1, RC2, and RC3 in more detail, please refer to further... Figure 9 .

[0200] Figure 9 This is a cross-sectional view of a region having first to third recessed patterns according to an embodiment.

[0201] Further reference Figure 9 The first to third recessed patterns RC1, RC2, and RC3 can be defined by removing at least a portion of the insulating film disposed between each of the first to third data lines 131, 132, and 133 and the third repair contact pattern DCE3. For example, the first to third recessed patterns RC1, RC2, and RC3 can be defined by removing the interlayer insulating film 103. However, it is not limited to this; the first to third recessed patterns RC1, RC2, and RC3 can also be defined by removing the buffer layer 101, which is not the interlayer insulating film 103, or by removing a portion above the interlayer insulating film 103 and the buffer layer 101.

[0202] Meanwhile, the first to third recessed patterns RC1, RC2, RC3 are shown as through holes penetrating the interlayer insulating film 103 in the thickness direction, but are not limited thereto. The first to third recessed patterns RC1, RC2, RC3 may also include a groove shape by removing a portion above the interlayer insulating film 103.

[0203] A third repair contact pattern DCE3 can be configured within the first to third recessed patterns RC1, RC2, and RC3. When the first to third recessed patterns RC1, RC2, and RC3 are configured, the thickness direction (third direction DR3) distance between the third repair contact pattern DCE3 and each of the first to third data lines 131, 132, and 133 can be reduced. Therefore, during the repair of the display device as described below, the welding (or fusion) between the third repair contact pattern DCE3 and the first to third data lines 131, 132, and 133 can be made smoother.

[0204] Before soldering, in each overlapping area of ​​the third repair contact pattern DCE3 and the first to third data lines 131, 132, 133, each of the third repair contact pattern DCE3 and the first to third data lines 131, 132, 133 can be electrically insulated by at least one insulating film configured between them.

[0205] Refer again Figures 2 to 8 The fourth repair contact pattern DCE4 can be configured on the other side (below) of the second direction DR2 of the repair data conductive pattern 350. The fourth repair contact pattern DCE4 can overlap with the repair first power pattern 170. In the overlapping area, the fourth repair contact pattern DCE4 can expose the contact hole CNT43 of the repair first power pattern 170 through the interlayer insulating film 103 and the buffer layer 101 to contact the repair first power pattern 170.

[0206] That is, the repaired first power supply pattern 170 and the first repaired semiconductor pattern DACT1 can be electrically connected through the fourth repaired contact pattern DCE4. The fourth repaired contact pattern DCE4 may include the first source / drain electrode of the first repaired transistor DT1.

[0207] The fourth conductive layer 400 may also include a repair circuit connection pattern 410 (or a first repair circuit connection pattern). The repair circuit connection pattern 410 may overlap with the second source / drain electrode of the first transistor T1 of each of the first to third sub-pixels PXS1, PXS2, and PXS3, and also overlap with the second source / drain electrode of the first repair transistor DT1.

[0208] The repair circuit connection pattern 410 may overlap with the repair data conductive pattern 350. In other words, the repair data conductive pattern 350 may include a protruding region extending from the region overlapping with the gate conductive pattern 231 toward the second direction DR2 side, and the repair circuit connection pattern 410 may overlap with the protruding region of the gate conductive pattern 231.

[0209] A fourth recessed pattern RC4 can be configured in the overlapping area.

[0210] To illustrate the fourth recessed pattern RC4 in more detail, please refer to further... Figure 10 .

[0211] Figure 10 This is a cross-sectional view of a region configured with a fourth recessed pattern according to an embodiment.

[0212] Further reference Figure 10 The fourth recessed pattern RC4 can be defined by removing at least a portion of the insulating film disposed between the repair data conductive pattern 350 and the repair circuit connection pattern 410. For example, the fourth recessed pattern RC4 can be defined by removing the via layer 105. However, it is not limited to this; the fourth recessed pattern RC4 can also be defined by removing the passivation film 104, which is not the via layer 105, or by removing a portion above the via layer 105 and the passivation film 104.

[0213] Meanwhile, the fourth recessed pattern RC4 is shown as a through hole penetrating the through-hole layer 105 in the thickness direction, but it is not limited to this. The fourth recessed pattern RC4 can also include a groove shape by removing a portion above the through-hole layer 105.

[0214] The repair circuit connection pattern 410 can be configured in the fourth recessed pattern RC4. When the fourth recessed pattern RC4 is configured, the thickness direction (third direction DR3) distance between the repair circuit connection pattern 410 and the repair data conductive pattern 350 can be reduced. As a result, the soldering between the repair circuit connection pattern 410 and the repair data conductive pattern 350 can be made smoother during the repair of the display device as described below.

[0215] Before soldering, in the area where the repair circuit connection pattern 410 and the repair data conductive pattern 350 overlap, the repair circuit connection pattern 410 and the repair data conductive pattern 350 can be electrically insulated by at least one insulating film configured between them.

[0216] Refer again Figures 2 to 8The repair circuit connection pattern 410 can extend from the area where the fourth recessed pattern RC4 is configured towards one side of the first direction DR1 to the other side. The repair circuit connection pattern 410 can extend towards each of the pixels PX configured on one side of the first direction DR1 and the other side of the repair circuit DP. The repair circuit connection pattern 410 can cross and extend across the first to third data lines 131, 132, and 133. The repair circuit connection pattern 410 can overlap with the first to third data lines 131, 132, and 133. In the overlapping area, the repair circuit connection pattern 410 and the first to third data lines 131, 132, and 133 can be insulated from each other through the via layer 105, the passivation film 104, the interlayer insulating film 103, and the buffer layer 101.

[0217] The repair circuit connection pattern 410 may not overlap with the first to third pixel electrodes PXE1, PXE2, and PXE3 in pixel PX, but may overlap with the fourth to sixth data conductive patterns 344, 345, and 346. In other words, the repair circuit connection pattern 410 extends from the area where the recessed pattern RC4 is disposed, bypassing the first and second pixel electrodes PXE1 and PXE2, and extends to the area between the second pixel electrode PXE2 and the third pixel electrode PXE3. The repair circuit connection pattern 410 may bypass the first and second pixel electrodes PXE1 and PXE2 on the second direction DR2 side (upper side), but is not limited to this. In addition, between the second pixel electrode PXE2 and the third pixel electrode PXE3, the repair circuit connection pattern 410 may overlap with the protruding area of ​​each of the fourth to sixth data conductive patterns 344, 345, and 346, but is not limited to this.

[0218] In the area where the repair circuit connection pattern 410 and the fourth to sixth data conductive patterns 344, 345, and 346 overlap, the fifth to seventh recessed patterns RC5, RC6, and RC7 can be configured.

[0219] To illustrate the fifth to seventh recessed patterns RC5, RC6, and RC7 in more detail, please refer to further... Figure 11 .

[0220] Figure 11 This is a cross-sectional view of the region having the fifth to seventh recessed patterns according to one embodiment.

[0221] Further reference Figure 11The fifth to seventh recessed patterns RC5, RC6, and RC7 can be defined by removing at least a portion of the insulating film disposed between each of the fourth to sixth data conductive patterns 344, 345, and 346 and the repair circuit connection pattern 410. For example, the fifth to seventh recessed patterns RC5, RC6, and RC7 can be defined by removing the via layer 105. However, it is not limited to this; the fifth to seventh recessed patterns RC5, RC6, and RC7 can also be defined by removing the passivation film 104, which is not the via layer 105, or by removing a portion above the via layer 105 and the passivation film 104.

[0222] Meanwhile, the fifth to seventh recessed patterns RC5, RC6, and RC7 are shown as through holes penetrating the through-hole layer 105 in the thickness direction, but are not limited thereto. The fifth to seventh recessed patterns RC5, RC6, and RC7 can also include a groove shape by removing a portion above the through-hole layer 105.

[0223] Repair circuit connection patterns 410 can be configured in the fifth to seventh recessed patterns RC5, RC6, and RC7. When the fifth to seventh recessed patterns RC5, RC6, and RC7 are configured, the thickness direction (third direction DR3) distance between the repair circuit connection pattern 410 and the fourth to sixth data conductive patterns 344, 345, and 346 can be reduced. As a result, the soldering between the repair circuit connection pattern 410 and the fourth to sixth data conductive patterns 344, 345, and 346 can be made smoother during the repair of the display device as described below.

[0224] Before soldering, in the areas where the repair circuit connection pattern 410 overlaps with each of the fourth to sixth data conductive patterns 344, 345, 346, each of the repair circuit connection pattern 410 and the fourth to sixth data conductive patterns 344, 345, 346 can be electrically insulated by at least one insulating film disposed between them.

[0225] Refer again Figures 2 to 8 The shapes of the repair circuit connection pattern 410 extending from the fourth recessed pattern RC4 towards one side of the first direction DR1 and the other side can be substantially symmetrical to each other. In other words, a portion of the repair circuit connection pattern 410 extending from the fourth recessed pattern RC4 towards the first direction DR1 and the remaining portion of the repair circuit connection pattern 410 extending towards the other side of the first direction DR2 can be symmetrical to each other in the first direction DR1. That is, on the plane, a portion of the repair circuit connection pattern 410 extending from the fourth recessed pattern RC4 towards the first direction DR1 and the remaining portion of the repair circuit connection pattern 410 extending towards the other side of the first direction DR2 can be symmetrical to each other from the fourth recessed pattern RC4 with reference to the virtual line extending towards the second direction DR2.

[0226] Pixels PX with the repair circuit DP in the middle and adjacent to each other can be arranged symmetrically. For example, two pixels PX with the repair circuit DP in the middle and adjacent to each other in the first direction DR1 can be symmetrical in the first direction DR1 on the plane, with a virtual line extending towards the second direction DR2 as a reference. That is, the semiconductor layer SC and the conductive layers 100, 200, 300, 400 of each of the two pixels PX can be arranged symmetrically to each other. The repair circuit DP and the two pixels PX with it in the middle and adjacent to each other can constitute a minimum repeating unit. That is, the repair circuit DP and the two pixels PX with it in the middle and adjacent to each other can be repeatedly arranged in the first direction DR1 and the second direction DR2 on the plane. However, it is not limited to this.

[0227] By placing the repair circuit DP between adjacent pixels PX, the repair circuit DP can repair the defective pixel PX even if either of the two adjacent pixels PX is defective. Therefore, the repair circuit DP does not need to be placed between pixels PX, and the area where it is placed can be minimized, allowing more pixels PX to be placed in the same area of ​​the display device. This, in turn, enables a higher resolution display device.

[0228] Furthermore, by configuring the repair circuit DP in the display area DA, the nearest neighboring pixel PX can be repaired, and the length of the wiring connecting the repair circuit DP and the pixel PX to be repaired can be minimized. Therefore, RC delay caused by the length of the wiring connecting the repair circuit DP and the pixel PX to be repaired can be suppressed or prevented.

[0229] In the following text, refer to Figures 12 to 17 A repair method for a display device according to one embodiment will be described. Figures 12 to 17 An exemplary method is shown for repairing a defect in the first transistor T1 or storage capacitor CST of the first sub-pixel PXS1 of a pixel PX. However, it is not limited thereto, and the description below can be applied not only to the first sub-pixel PXS1, but also to the second sub-pixel PXS2 and the third sub-pixel PXS3.

[0230] Figure 12 This is an equivalent circuit diagram of pixels and repair circuitry according to an embodiment for illustrating a method of repairing a display device.

[0231] Reference Figure 12When the first transistor T1 or storage capacitor CST of the first sub-pixel PXS1 is defective, the first transistor T1 and the first power line ELVDL can be cut off, and the second transistor T2 and the storage capacitor CST (or the gate electrode of the first transistor T1) can be disconnected. Therefore, the light-emitting element EMD of the first sub-pixel PXS1 is unaffected by the defective first transistor T1 or storage capacitor CST of the first sub-pixel PXS1.

[0232] At this point, the first repair transistor DT1 of the repair circuit DP and the repair capacitor DCST can be electrically connected to the anode electrode of the light-emitting element EMD of the first sub-pixel PXS1. The second repair transistor DT2 of the repair circuit DP can be electrically connected to the first data line DL1.

[0233] The first power supply voltage applied to the first repair transistor DT1 can be transmitted to the light-emitting element EMD of the first sub-pixel PXS through the first repair transistor DT1. The second repair transistor DT2 can receive data signals from the first data line DL1 and transmit them to the gate electrode of the first repair transistor DT1. Therefore, even if at least any one of the first transistor T1 and the storage capacitor CST of the first sub-pixel PXS1 is defective, the light-emitting element EMD of the first sub-pixel PXS1 can still operate smoothly through the first repair transistor DT1, the second repair transistor DT2, the repair capacitor DCST, and the third transistor T3 of the first sub-pixel PXS1 in the repair circuit DP.

[0234] Even if defects occur in the pixel PX, they can be repaired by the repair circuit DP, thereby improving the yield of the display device and reducing process costs.

[0235] Figure 13 This is a layout diagram of pixels and repair circuitry according to an embodiment for illustrating a method of repairing a display device. Figure 14 It is magnification Figure 13 A magnified view of region B.

[0236] Reference Figures 12 to 14 It can be that each of the first semiconductor pattern ACT1 and the first gate conductive pattern 211 of the pixel PX is cut into at least two parts, and the cut parts are separated from each other and electrically disconnected.

[0237] Specifically, the first semiconductor pattern ACT1 can be divided into at least two parts. The first semiconductor pattern ACT1 can be divided into a first region ACT1a that overlaps with the first data conductive pattern 341 and a second region ACT1b that overlaps with the fourth data conductive pattern 344. The first region ACT1a and the second region ACT1b can be separated from each other and electrically disconnected.

[0238] In the portion where the first semiconductor pattern ACT1 is broken into a first region ACT1a and a second region ACT1b, no other components may be disposed on the plane. In this case, when the first semiconductor pattern ACT1 is cut by means of a laser or the like, damage to other components caused by the laser irradiating the first semiconductor pattern ACT1 can be suppressed or prevented.

[0239] The first gate conductive pattern 211 can be divided into at least two parts. The first gate conductive pattern 211 can be divided into a first region 211a that overlaps with the first data conductive pattern 341 and a second region 211b that overlaps with the fourth contact pattern CE4. The first region 211a and the second region 211b can be separated from each other and electrically disconnected.

[0240] In the portion where the first gate conductive pattern 211 is broken into a first region 211a and a second region 211b, no other configurations may be arranged on the plane. In this case, when the first gate conductive pattern 211 is cut by means of a laser or the like, damage to other configurations caused by the laser irradiating the first gate conductive pattern 211 can be suppressed or prevented.

[0241] Thus, the first power line 120 and the second region ACT1b of the first semiconductor pattern ACT1 can be electrically disconnected from each other, and the first data line 131 and the first region 211a of the first gate conductive pattern 211 can be electrically disconnected from each other.

[0242] Alternatively, the first power line 120 can be electrically connected to the first repair transistor DT1, and the first repair transistor DT1 can be electrically connected to the first data conductive pattern 341 through the repair circuit connection pattern 410. Additionally, the first data line 131 can be electrically connected to the second repair transistor DT2 through the third repair contact pattern DCE3.

[0243] For a more detailed explanation, please refer to further... Figures 15 to 17 .

[0244] Figure 15 This is a cross-sectional view of a region with first to third recessed patterns, according to an embodiment of a method for repairing a display device. Figure 16 This is a cross-sectional view of a region with a fourth recessed pattern, according to an embodiment of a method for repairing a display device. Figure 17 This is a cross-sectional view of the region with the fifth to seventh recessed patterns, according to an embodiment of a method for repairing a display device.

[0245] Reference Figures 12 to 17The repair data conductive pattern 350 can be electrically connected to the repair circuit connection pattern 410. Welding can be performed at the location where the fourth recessed pattern RC4 is configured. The welding can be performed by a laser, but is not limited to this. When welding by laser, the area irradiated by the laser can overlap with the location where the fourth recessed pattern RC4 is configured. In other words, in the area where the fourth recessed pattern RC4 is configured, the laser can irradiate the insulating film (e.g., passivation film 104) disposed between the repair data conductive pattern 350 and the repair circuit connection pattern 410. After welding is completed, the repair data conductive pattern 350 and the repair circuit connection pattern 410 can contact each other and can be physically and / or electrically connected. The contact area between the repair data conductive pattern 350 and the repair circuit connection pattern 410 can at least partially overlap with the area where the fourth recessed pattern RC4 is formed.

[0246] For example, after welding is completed, the repair data conductive pattern 350 and the repair circuit connection pattern 410 can expose contact holes of the repair data conductive pattern 350 to contact each other through an insulating film (e.g., passivation film 104) disposed between the repair data conductive pattern 350 and the repair circuit connection pattern 410, but are not limited thereto. Meanwhile, the contact holes can at least partially overlap with the fourth recessed pattern RC4.

[0247] The fourth data conductive pattern 344 can be electrically connected to the repair circuit connection pattern 410. Welding can be performed at the location where the fifth recessed pattern RC5 is configured. The welding can be performed using a laser, but is not limited to this. When welding with a laser, the area irradiated by the laser can overlap with the location where the fifth recessed pattern RC5 is configured. In other words, in the area where the fifth recessed pattern RC5 is configured, the laser can irradiate the insulating film (e.g., passivation film 104) disposed between the fourth data conductive pattern 344 and the repair circuit connection pattern 410. After welding is completed, the fourth data conductive pattern 344 and the repair circuit connection pattern 410 can contact each other and can be physically and / or electrically connected. The area where the fourth data conductive pattern 344 and the repair circuit connection pattern 410 contact each other can at least partially overlap with the area where the fifth recessed pattern RC5 is formed.

[0248] For example, after welding is completed, the fourth data conductive pattern 344 and the repair circuit connection pattern 410 can contact each other by exposing the contact holes of the fourth data conductive pattern 344 through an insulating film (e.g., passivation film 104) disposed between the fourth data conductive pattern 344 and the repair circuit connection pattern 410, but are not limited thereto. Meanwhile, the contact holes can at least partially overlap with the fifth recessed pattern RC5.

[0249] Therefore, by repairing the circuit connection pattern 410, the repair data conductive pattern 350 can be electrically connected to the fourth data conductive pattern 344, and the first repair transistor DT1 and the first pixel electrode PXE1 of the first sub-pixel PXS1 can be electrically connected.

[0250] The third repair contact pattern DCE3 can be electrically connected to the first data line 131. Soldering can be performed at the location where the first recessed pattern RC1 is configured. The soldering can be performed using a laser, but is not limited to this. When soldering with a laser, the area irradiated by the laser can overlap with the location where the first recessed pattern RC1 is configured. In other words, in the area where the first recessed pattern RC1 is configured, the laser can irradiate the insulating film (e.g., buffer layer 101) disposed between the third repair contact pattern DCE3 and the first data line 131. After soldering is completed, the third repair contact pattern DCE3 and the first data line 131 can contact each other and can be physically and / or electrically connected. The area where the third repair contact pattern DCE3 and the first data line 131 contact each other can at least partially overlap with the area where the first recessed pattern RC1 is formed.

[0251] For example, after soldering is completed, the third repair contact pattern DCE3 and the first data line 131 can contact each other by exposing the contact hole of the first data line 131 through an insulating film (e.g., buffer layer 101) disposed between the third repair contact pattern DCE3 and the first data line 131, but are not limited thereto. At the same time, the contact hole can at least partially overlap with the first recessed pattern RC1.

[0252] Therefore, through the third repair contact pattern DCE3, the repair connection pattern 180 can be electrically connected to the first data line 131, and the second repair transistor DT2 and the first data line 131 can be electrically connected.

[0253] The following describes other embodiments. In the embodiments described below, descriptions of structures identical to those already described are omitted or simplified, and the differences will be mainly explained.

[0254] Figure 18 This is an equivalent circuit diagram of pixels and repair circuitry according to another embodiment for illustrating a method of repairing a display device. Figure 19 This is a layout diagram of pixels and repair circuitry according to another embodiment for illustrating a method of repairing a display device. Figure 20 It is magnification Figure 19 A magnified view of region C.

[0255] Reference Figures 18 to 20The repair method of the display device according to this embodiment is a method for repairing a defective second transistor T2 of any one of the sub-pixels PXS1, PXS2, and PXS3. In this respect, it is similar to... Figures 12 to 17 The embodiments differ. Figures 18 to 20 An exemplary method is shown for repairing a defect in the second transistor T2 of the first sub-pixel PXS1 of a pixel PX.

[0256] Specifically, when the second transistor T2 of the first sub-pixel PXS1 of pixel PX is defective, the second transistor T2 and the first data line 131 can be further disconnected. Thus, the light-emitting element EMD of the first sub-pixel PXS1 is unaffected by the defective second transistor T2. However, this is not a limitation; when the second transistor T2 and the first data line 131 are disconnected, the second transistor T2 and the storage capacitor CST (or the gate electrode of the first transistor T1) can also remain connected.

[0257] At this point, the first contact pattern CE1 of pixel PX can be cut into at least two parts, and the cut parts are separated from each other and electrically disconnected. In other words, the first contact pattern CE1 can be cut into at least two parts. The first contact pattern CE1 can be divided into a first region CE1a that overlaps with the fourth semiconductor pattern ACT4 and a second region CE1b that overlaps with the first data line 131. The first region CE1a and the second region CE1b can be separated from each other and electrically disconnected. Thus, the fourth semiconductor pattern ACT4 and the first data line 131 can be electrically disconnected.

[0258] In the portion where the first contact pattern CE1 is broken into a first region CE1a and a second region CE1b, no other components may be disposed on the plane. In this case, when the first contact pattern CE1 is cut by means of a laser or the like, damage to other components caused by the laser irradiating the first contact pattern CE1 can be suppressed or prevented.

[0259] At this point, even if the first transistor T1 or the storage capacitor CST is defective, it can be repaired. Furthermore, in this embodiment, if the second transistor T2 is defective, it can be repaired, further increasing the yield and reducing process costs.

[0260] Figure 21 This is a layout diagram of pixels and repair circuitry for illustrating a method of repairing a display device, according to yet another embodiment.

[0261] Reference Figure 21 According to this embodiment, the repair circuit connection pattern 410_2 is separated into two different parts and electrically disconnected, which is consistent with... Figure 13The embodiments differ.

[0262] Specifically, when the repair circuit DP is electrically connected to the light-emitting element EMD of the first sub-pixel PXS1 of the pixel PX disposed on one side of the first direction DR1 of the repair circuit DP, the repair circuit connection pattern 410_2 may include a first region 410a extending from the portion overlapping with the repair data conductive pattern 350 towards the first direction DR1, and a second region 410b separated from the first region 410a and disposed on the other side of the first direction DR1 of the first region 410a. Alternatively, the first region 410a of the repair circuit connection pattern 410_2 may extend towards the pixel PX disposed on one side of the first direction DR1 of the repair circuit DP, and the second region 410b may extend towards the pixel PX disposed on the other side of the first direction DR1 of the repair circuit DP.

[0263] It is possible that the first region 410a of the repair circuit connection pattern 410_2 is electrically connected to the repair data conductive pattern 350, but the second region 410b of the repair circuit connection pattern 410_2 is electrically disconnected from the repair data conductive pattern 350. The first region 410a and the second region 410b of the repair circuit connection pattern 410_2 can be formed by cutting the integrally formed repair circuit connection pattern 410_2, but are not limited to this.

[0264] At this point, even if the first transistor T1 or the storage capacitor CST is defective, it can be repaired, increasing the yield and reducing process costs. Simultaneously, by cutting the repair circuit connection pattern 410_2, the influence of the repair circuit DP on adjacent but not electrically connected pixels PX can be suppressed or prevented. Furthermore, the reliability of each pixel PX in the display device can be improved.

[0265] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, those skilled in the art will understand that the invention can be implemented in other specific ways without altering the technical concept or essential features of the invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not limiting.

Claims

1. A display device, wherein, include: A pixel includes a first sub-pixel and a second sub-pixel that emit light of different colors from each other, and a first power line electrically connected to the first sub-pixel and the second sub-pixel to apply a first power supply voltage to each of the first sub-pixel and the second sub-pixel; The repair circuit is configured adjacent to the pixel; as well as The first repair circuit connection pattern extends across the pixel and the repair circuit. Each of the first sub-pixel and the second sub-pixel includes a light-emitting element, a first transistor connected to the light-emitting element, and a second transistor connected to the gate electrode of the first transistor. The repair circuit includes a first repair transistor and a second repair transistor connected to the gate electrode of the first repair transistor. The first source / drain electrodes of the first transistors of the first sub-pixel and the second sub-pixel are electrically connected to the first power line, and the second source / drain electrodes of the first transistors of the first sub-pixel and the second sub-pixel overlap with the connection pattern of the first repair circuit. The first source / drain electrode of the first repair transistor is electrically connected to the first power line, and the second source / drain electrode of the first repair transistor overlaps with the connection pattern of the first repair circuit. Wherein, in the region where each of the second source / drain electrodes of the first transistor of the first sub-pixel and the second sub-pixel overlaps with the first repair circuit connection pattern, at least one first insulating film is at least partially disposed between each of the second source / drain electrodes of the first transistor of the first sub-pixel and the second sub-pixel and the first repair circuit connection pattern, thereby electrically insulating each of the second source / drain electrodes of the first transistor of the first sub-pixel and the first repair circuit connection pattern from each other.

2. The display device according to claim 1, wherein, The light-emitting element includes an anode electrode, a light-emitting layer, and a cathode electrode stacked sequentially. The first source / drain electrode and the second source / drain electrode of the first transistor, as well as the first source / drain electrode and the second source / drain electrode of the first repair transistor, constitute a first conductive layer. The first repair circuit connection pattern and the anode electrode of the light-emitting element constitute a second conductive layer that is different from the first conductive layer.

3. The display device according to claim 2, wherein, The at least one first insulating film includes: A via layer is disposed on the first conductive layer. The via layer is disposed between the first conductive layer and the second conductive layer.

4. The display device according to claim 3, wherein, The via layer includes a first recessed pattern and a second recessed pattern defined by removing at least a portion in the thickness direction. The first recessed pattern is disposed in the region where the second source / drain electrode of the first transistor of the first sub-pixel and the second sub-pixel overlaps with the connection pattern of the first repair circuit. The second recessed pattern is disposed in the region where the second source / drain electrode of the first transistor of the repair circuit overlaps with the connection pattern of the first repair circuit.

5. The display device according to claim 4, wherein, At least a portion of the first repair circuit connection pattern is disposed inside at least one of the first recessed pattern and the second recessed pattern.

6. The display device according to claim 2, wherein, The first power line forms a third conductive layer that is different from the first conductive layer and the second conductive layer, and is disposed below the first conductive layer and the second conductive layer.

7. The display device according to claim 6, wherein, The display device further includes: The fourth conductive layer is different from the first, second, and third conductive layers. The fourth conductive layer includes the gate electrodes of the first transistor and the second transistor of the first sub-pixel and the second sub-pixel, and the gate electrodes of the first repair transistor and the second repair transistor.

8. The display device according to claim 1, wherein, The display device further includes: A first data line and a second data line extend adjacent to each other in the same direction; and a second repair circuit connection pattern extends across the first data line and the second data line and overlaps with the first data line and the second data line. The second transistor of the first sub-pixel is electrically connected to the first data line, and the second transistor of the second sub-pixel is electrically connected to the second data line. The second repair transistor is electrically connected to the second repair circuit connection pattern.

9. The display device according to claim 8, wherein, The first data line, the second data line, and the first power line constitute the first conductive layer. The second repair circuit connection pattern, the first source / drain electrode and the second source / drain electrode of the first transistor, and the first source / drain electrode and the second source / drain electrode of the first repair transistor constitute a second conductive layer that is different from the first conductive layer.

10. The display device according to claim 9, wherein, The display device further includes: A second insulating film is disposed between the first conductive layer and the second conductive layer, and includes a first recessed pattern and a second recessed pattern defined by removing at least a portion thereof. The first recessed pattern is disposed in the area where the second repair circuit connection pattern and the first data line overlap, and the second recessed pattern is disposed in the area where the second repair circuit connection pattern and the second data line overlap.

11. The display device according to claim 10, wherein, The second insulating film includes a buffer layer and an interlayer insulating film stacked sequentially.

12. The display device according to claim 1, wherein, The pixels and the repair circuit are provided in multiple forms. Each of the plurality of repair circuits is configured between two adjacent pixels in the plurality of pixels. The two pixels adjacent to the repair circuit each have a shape that is symmetrical to each other.

13. The display device according to claim 12, wherein, The display device further includes: A display area, comprising the displayed image; and a non-display area, disposed around the display area. The plurality of said pixels and the plurality of said repair circuits are configured in the display area.

14. A display device, wherein, include: A pixel includes a first sub-pixel and a second sub-pixel that emit light of different colors from each other, and a first power line electrically connected to at least one of the first sub-pixel and the second sub-pixel. The repair circuit is configured adjacent to the pixel and includes a first repair transistor and a second repair transistor electrically connected to the gate electrode of the first repair transistor. as well as The first repair circuit connection pattern extends across the pixel and the repair circuit. The first sub-pixel includes a first transistor electrically connected to the first light-emitting element and a second transistor electrically connected to the gate electrode of the first transistor. The second sub-pixel includes a second light-emitting element that is different from the first light-emitting element. The first source / drain electrode of the first transistor of the first sub-pixel is electrically connected to the first power line, and the second source / drain electrode of the first transistor of the first sub-pixel overlaps with and is electrically insulated from the connection pattern of the first repair circuit. The first source / drain electrode of the first repair transistor is electrically connected to the first power line, and the second source / drain electrode of the first repair transistor overlaps with the connection pattern of the first repair circuit. The second source / drain electrode of the first repair transistor is electrically connected to the connection pattern of the first repair circuit in the region where it overlaps with the connection pattern of the first repair circuit. In the region where the second source / drain electrode of the first transistor of the first sub-pixel overlaps with the first repair circuit connection pattern, at least one insulating film is at least partially disposed between the second source / drain electrode of the first transistor of the first sub-pixel and the first repair circuit connection pattern, thereby electrically isolating the second source / drain electrode of the first transistor of the first sub-pixel from the first repair circuit connection pattern.

15. The display device according to claim 14, wherein, The light-emitting element includes an anode electrode, a light-emitting layer, and a cathode electrode stacked sequentially. The first source / drain electrode and the second source / drain electrode of the first transistor, as well as the first source / drain electrode and the second source / drain electrode of the first repair transistor, constitute a first conductive layer. The first repair circuit connection pattern and the anode electrode of the light-emitting element constitute a second conductive layer that is different from the first conductive layer.

16. The display device according to claim 14, wherein, The display device further includes: A first data line and a second data line extend adjacent to each other in the same direction; and a second repair circuit connection pattern overlaps with the first data line and the second data line, and is electrically connected to the second repair transistor. The second repair circuit connection pattern is electrically insulated from the first data line, and the second repair circuit connection pattern is electrically connected to the second data line in the area overlapping with the second data line.

17. The display device according to claim 16, wherein, The first data line, the second data line, and the first power line constitute the first conductive layer. The second repair circuit connection pattern, the first source / drain electrode and the second source / drain electrode of the first transistor, the first source / drain electrode and the second source / drain electrode of the first repair transistor, and the first source / drain electrode and the second source / drain electrode of the second repair transistor constitute a second conductive layer different from the first conductive layer.

18. The display device according to claim 14, wherein, By soldering, the first repair circuit connection pattern and the second source / drain electrode of the first repair transistor are electrically connected in the region where the first repair circuit connection pattern and the second source / drain electrode of the first repair transistor overlap.

19. The display device according to claim 14, wherein, The second sub-pixel also includes a first transistor of the second sub-pixel that is electrically connected to the second light-emitting element and electrically disconnected from the first power line.

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