Fin field effect transistor and method of making the same

Abstract

The application provides a fin field effect transistor and a preparation method thereof. A gate dielectric layer of the fin field effect transistor comprises an aluminum oxide layer and a hafnium oxynitride layer covering the aluminum oxide layer. The aluminum oxide layer can form a good interface with a semiconductor substrate, thereby providing a good interface basis for the hafnium oxynitride layer, preventing crystalline epitaxy of the hafnium oxynitride layer, and reducing interface state density between the gate dielectric layer and the semiconductor substrate. The aluminum oxide layer and the hafnium oxynitride layer can cooperate to reduce loss in a carrier movement process, adjust a Fermi level of the gate dielectric layer, thereby reducing leakage current between the gate dielectric layer and the semiconductor substrate, and improving reliability of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a fin field effect transistor and a preparation method thereof. Background Art

[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to the reduction in feature size, the channel length of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) has also been shortened accordingly. Therefore, in order to better adapt to the reduction in feature size, semiconductor processes have gradually begun to transition from planar MOSFET transistors to three-dimensional transistors with higher efficiency, such as fin field-effect transistors (FinFETs). At present, fin field-effect transistors use a high-k gate dielectric layer instead of the traditional silicon dioxide gate dielectric layer, and use metal as the gate electrode to avoid the Fermi level pinning effect and boron penetration effect between high-k materials and traditional gate electrode materials. However, there is a leakage current problem between the gate dielectric layer and the semiconductor substrate of the fin field-effect transistor, which in turn affects the reliability of the device. Summary of the Invention

[0003] An object of the present invention is to provide a fin field effect transistor and a method for manufacturing the same, so as to reduce leakage current between a gate dielectric layer and a semiconductor substrate.

[0004] To achieve the above object, the present invention provides a fin field-effect transistor, comprising:

[0005] Providing a semiconductor substrate, wherein a surface of the semiconductor substrate has a plurality of fins, and shallow trenches are formed between the plurality of fins; and

[0006] A gate dielectric layer is formed, the gate dielectric layer comprising an aluminum oxide layer and a hafnium oxynitride layer, the aluminum oxide layer covers the sidewalls and bottom wall of the shallow trench and extends to cover the fin, and the hafnium oxynitride layer covers the aluminum oxide layer.

[0007] Optionally, in the method for preparing the fin field effect transistor, the method for forming the gate dielectric layer includes:

[0008] forming the aluminum oxide layer by a first atomic layer deposition process;

[0009] forming a hafnium oxide layer by a second atomic layer deposition process, wherein the hafnium oxide layer covers the aluminum oxide layer; and

[0010] The hafnium oxide layer is nitrided by a third atomic layer deposition process or a decoupled plasma process to form the hafnium oxynitride layer.

[0011] Optionally, in the method for preparing the fin field effect transistor, the process gases used in the first atomic layer deposition process are aluminum source gas and oxygen source gas, and the process temperature is 200° C. to 300° C.

[0012] Optionally, in the method for preparing a fin field effect transistor, the second atomic layer deposition process uses a hafnium source gas and an oxygen source gas, and the process temperature is 200° C. to 300° C.

[0013] Optionally, in the preparation method of the fin field effect transistor, the process gas used in the third atomic layer deposition process is nitrogen source gas, and the process temperature is 200°C to 300°C; the process gas used in the decoupling plasma process is nitrogen, and the process temperature is 25°C to 30°C.

[0014] Optionally, in the method for preparing the fin field effect transistor, after forming the gate dielectric layer, the method for preparing the fin field effect transistor further includes: annealing the semiconductor substrate having the gate dielectric layer, the annealing temperature is 800°C to 900°C, and the annealing time is 5s to 10s.

[0015] Optionally, in the method for preparing a fin field effect transistor, the thickness of the aluminum oxide layer is 3 angstroms to 5 angstroms; and the thickness of the hafnium oxynitride layer is 8 angstroms to 10 angstroms.

[0016] Optionally, in the method for preparing the fin field effect transistor, the shallow trench is filled with an isolation layer, a top surface of the isolation layer is lower than a top surface of the fin, and the gate dielectric layer covers the isolation layer.

[0017] Optionally, in the method for preparing a fin field-effect transistor, the material of the isolation layer includes silicon oxide.

[0018] Based on the same inventive concept, the present invention further provides a fin field-effect transistor, comprising:

[0019] A semiconductor substrate having a plurality of fins on its surface and shallow trenches between the plurality of fins; and

[0020] A gate dielectric layer includes an aluminum oxide layer and a hafnium oxynitride layer, wherein the aluminum oxide layer covers the sidewalls and bottom wall of the shallow trench and extends to cover the fin, and the hafnium oxynitride layer covers the aluminum oxide layer.

[0021] In the fin field-effect transistor and its preparation method provided by the present invention, the gate dielectric layer includes an aluminum oxide layer and a hafnium oxynitride layer covering the aluminum oxide layer. The aluminum oxide layer can form a good interface with the semiconductor substrate, provide a good interface foundation for the hafnium oxynitride layer, prevent the crystallization epitaxial growth of the hafnium oxynitride layer, and reduce the interface state density between the gate dielectric layer and the semiconductor substrate. The aluminum oxide layer cooperates with the hafnium oxynitride layer to reduce the loss in the carrier movement process, adjust the Fermi level of the gate dielectric layer, thereby reducing the leakage current between the gate dielectric layer and the semiconductor substrate, and improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 1 is a schematic flow chart of a method for preparing a fin field effect transistor according to an embodiment of the present invention;

[0023] Figures 2 to 4 is a schematic cross-sectional view of a structure formed in a method for preparing a fin field effect transistor according to an embodiment of the present invention;

[0024] The description of the accompanying drawings is as follows:

[0025] 100 - semiconductor substrate; 101 - fin; 102 - shallow trench; 110 - isolation layer; 120 - gate dielectric layer; 121 - aluminum oxide layer; 122 - hafnium oxynitride layer. DETAILED DESCRIPTION

[0026] The following is a further detailed description of the fin field-effect transistor and its fabrication method proposed in the present invention, in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0027] Figure 1 FIG. 1 is a flow chart of a method for preparing a fin field effect transistor according to an embodiment of the present invention. Figure 1 As shown, the present invention provides a method for preparing a fin field effect transistor, comprising:

[0028] Step S1: providing a semiconductor substrate, wherein a surface of the semiconductor substrate has a plurality of fins, and shallow trenches are formed between the plurality of fins; and

[0029] Step S2: forming a gate dielectric layer, the gate dielectric layer comprising an aluminum oxide layer and a hafnium oxynitride layer covering the aluminum oxide layer, the aluminum oxide layer covering the sidewalls and bottom wall of the shallow trench and extending to cover the fin, the hafnium oxynitride layer covering the aluminum oxide layer.

[0030] Figures 2 to 4FIG is a schematic cross-sectional view of a structure formed in a method for preparing a fin field effect transistor according to an embodiment of the present invention. Figures 2 to 4 The method for manufacturing the fin field effect transistor provided in this embodiment is described in more detail.

[0031] First, execute step S1, as Figure 2 As shown, a semiconductor substrate 100 is provided. The surface of the semiconductor substrate 100 has a plurality of fins 101, and shallow trenches 102 are formed between the plurality of fins 101. The material of the semiconductor substrate 100 can be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC), or can be silicon on insulator (SOI) or germanium on insulator (GOI); or can be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 100 is single crystal silicon (Si).

[0032] like Figure 2 As shown, the surface of the semiconductor substrate 100 has multiple fins 101, and there are shallow trenches 102 between the multiple fins 101. The shallow trenches 102 are filled with an isolation layer 110. The top surface of the isolation layer 110 is lower than the top surface of the fins 101, which is used for isolation between the multiple fins 101.

[0033] Specifically, the method for forming the fin 101 includes the following sub-steps S11 to S15:

[0034] Sub-step S11: forming a patterned hard mask layer (not shown) on the semiconductor substrate 100. The hard mask layer may be a nitride film, or an oxide film and a nitride film stacked sequentially on the semiconductor substrate 100.

[0035] Sub-step S12: using the patterned hard mask layer as a mask, etching the semiconductor substrate 100 to form a plurality of shallow trenches 102 in the semiconductor substrate 100, and forming the fins 101 in the semiconductor substrate 100 between the plurality of shallow trenches 102;

[0036] Sub-step S13: Filling the shallow trench 102 with an isolation layer 110. Typically, the isolation layer 110 is made of an oxide, such as silicon oxide. In sub-step S13, a layer of isolation material may be first deposited to cover the entire hard mask layer and the shallow trench 102. CMP (chemical mechanical polishing) is then performed to flatten the surface of the entire device. The isolation material layer and the shallow trench 102 form a shallow trench isolation structure.

[0037] Sub-step S124: removing the patterned hard mask layer. The process of removing the patterned hard mask layer may adopt a wet etching process or a dry etching process, which is well understood by those skilled in the art and will not be described in detail here.

[0038] In sub-step S125, a portion of the thickness of the isolation material layer is removed so that the top surface of the isolation material layer is lower than the top surface of the fin, and the remaining isolation material layer is used to form an isolation layer 110, thereby exposing the fin 101. The process of removing a portion of the thickness of the isolation material layer can be carried out by a wet etching process or a dry etching process, which is understandable to ordinary technicians in this field and will not be elaborated here.

[0039] Next, execute step S2: refer to Figure 3 Combined with Figure 4 As shown, a gate dielectric layer 120 is formed. The gate dielectric layer 120 includes an aluminum oxide layer 121 and a hafnium oxynitride layer 122. The aluminum oxide layer 121 covers the sidewalls and bottom wall of the shallow trench 102 and extends to cover the fin 101. The hafnium oxynitride layer 122 covers the aluminum oxide layer 121. In addition, the gate dielectric layer 120 covers the isolation layer 100. In this embodiment, step S2 includes the following sub-steps S21 to S25:

[0040] Sub-step S21: Figure 3 As shown, the aluminum oxide layer 121 is formed by a first atomic layer deposition process. Specifically, the process of forming the aluminum oxide layer 121 includes: S211: introducing a first precursor gas containing aluminum elements in a pulsed form to wet and clean the surface of the semiconductor substrate 100 to form an aluminum layer; S212, introducing a second precursor gas for generating aluminum oxide in a pulsed form to perform surface treatment on the aluminum layer to form the aluminum oxide layer 121. In addition, an inert gas such as argon or helium can be introduced to clean the surface of the aluminum oxide layer 121 to remove excess first precursor gas, second precursor gas and by-products adsorbed on the surface; S213, cyclically repeating steps S211 and S212 until the thickness of the formed aluminum oxide layer 121 reaches a predetermined value, for example, 3 to 5 angstroms. In this embodiment, the thickness of the aluminum oxide layer 121 can be 5 angstroms. If the thickness of the aluminum oxide layer 121 is too large, it will limit the reduction of the overall thickness of the gate dielectric layer 120. If the thickness is too small, it will affect the uniformity of the film and the resistance of the subsequent hafnium oxynitride layer crystallization.

[0041] In this embodiment, the first precursor gas may be, for example, an aluminum-containing gas such as trimethylaluminum (TMA) or aluminum bromide, i.e., an aluminum source gas. The second precursor gas may be a mixed gas comprising hydrogen peroxide (H2O2) and ozone (O3), i.e., an oxygen source gas. For example, in step S211, TMA is used as the first precursor gas. The TMA in step S211 and the H2O2 and O3 in step S212 are alternately introduced into the reaction chamber, so that the TMA reacts with the H2O2, O3, and other gases to form the aluminum oxide layer 121.

[0042] Furthermore, in steps S211 to S213, the process temperature may be maintained at 200° C. to 300° C., for example, 200° C., 210° C., 230° C., 260° C., 280° C., or 300° C. A preferred process temperature in this embodiment is 300° C., which is conducive to uniform growth of the aluminum oxide layer 121 and improves adhesion between the aluminum oxide layer 121 and the semiconductor substrate 100.

[0043] In this embodiment, due to the presence of a large amount of fixed negative charge and low interface state density at the interface of the aluminum oxide layer 121, the aluminum oxide layer 121 can form a good interface with the semiconductor substrate 100, providing a good interface foundation for the hafnium oxynitride layer 122, reducing the interface state density between the gate dielectric layer 120 and the semiconductor substrate 100, and preventing the epitaxial crystallization of the hafnium oxynitride layer 122. Furthermore, because the aluminum oxide layer 121 is formed by atomic layer deposition, the advantages of the atomic layer deposition process can be utilized to provide good step coverage, providing a good deposition interface for the subsequently formed hafnium oxynitride layer.

[0044] Sub-step S22: Forming a hafnium oxide layer (not shown) through a second atomic layer deposition process, the hafnium oxide layer covering the aluminum oxide layer 121. Specifically, the process of forming the hafnium oxide layer includes: S221, introducing a third precursor gas containing a hafnium element to wet and clean the surface of the aluminum oxide layer 121 to form the hafnium layer; S222, introducing a fourth precursor gas for generating hafnium oxide to perform surface treatment on the hafnium layer to form the hafnium oxide layer; S223, cyclically repeating steps S221 and S223 until the thickness of the formed hafnium oxide layer reaches a predetermined value, for example, 8 to 10 angstroms.

[0045] In this embodiment, the third precursor gas may be, for example, hafnium tetrachloride (HfCl 4 ), ie, the hafnium source gas. The fourth precursor gas may be a mixed gas comprising hydrogen peroxide (H 2 O 2 ) and ozone (O 3 ), ie, the oxygen source gas.

[0046] Furthermore, in steps S221 to S223 , the process temperature may be maintained at 200° C. to 300° C., for example, 200° C., 210° C., 230° C., 260° C., 280° C., or 300° C. The preferred process temperature in this embodiment is 300° C., which is conducive to uniform growth of the hafnium oxide layer and improves adhesion between the hafnium oxide layer and the aluminum oxide layer 121 .

[0047] Sub-step S23: Figure 4 As shown, the hafnium oxide layer is nitrided by a third atomic layer deposition process or a decoupled plasma process to form the hafnium oxynitride layer 122. The thickness of the hafnium oxynitride layer 122 can be, for example, 8 angstroms to 10 angstroms. In this embodiment, the hafnium oxide layer is nitrided by a third atomic layer deposition process, which can take advantage of the advantages of the atomic layer deposition process to provide better step coverage.

[0048] Specifically, such as Figure 4 As shown, the process of nitriding the hafnium oxide layer through the third atomic layer deposition process includes: introducing a fifth precursor gas for generating hafnium oxynitride, and performing surface treatment on the hafnium oxide layer to form the hafnium oxynitride layer 122. The fifth precursor gas can be, for example, ammonia (NH3), i.e., a nitrogen source gas. By introducing the ammonia gas into the reaction chamber, the ammonia reacts with the hafnium oxide layer, thereby forming the hafnium oxynitride layer 122. In the third atomic layer deposition process, the process temperature can be 200°C to 300°C.

[0049] In this embodiment, the aluminum oxide layer 121 cooperates with the hafnium oxynitride layer 122 to form the gate dielectric layer 120, which can reduce the loss in the carrier movement process, adjust the Fermi level of the gate dielectric layer 120, thereby reducing the leakage current between the gate dielectric layer 120 and the semiconductor substrate 100, and improving the reliability of the device.

[0050] In another embodiment, the hafnium oxide layer is nitrided by a decoupled plasma process to form the hafnium oxynitride layer 122. Specifically, the process of nitriding the hafnium oxide layer by a decoupled plasma process includes: performing a nitrogen doping process on the hafnium oxide layer by a decoupled plasma machine to nitridate the hafnium oxide layer. The process gas may be nitrogen, for example. The nitrogen enters the hafnium oxide layer after being plasma-formed, thereby repairing oxygen vacancy defects in the hafnium oxide layer and forming the hafnium oxynitride layer 122, thereby reducing leakage current and improving device reliability. The process temperature of the decoupled plasma process may be 25°C to 30°C.

[0051] Specifically, in the process of nitriding the hafnium oxide layer by a decoupled plasma process, the nitrogen ion energy of the nitrogen plasma can be reduced by using a radio frequency signal with a low duty cycle, and the smaller the duty cycle of the radio frequency signal, the smaller the nitrogen ion energy. For example, the nitrogen ion energy can be reduced by reducing the power of the radio frequency signal, and the power range can be 1500W to 1600W. Furthermore, the duty cycle can range from 10% to 15%. In this way, the nitrogen element doped in the hafnium oxide layer has a spatial distribution structure away from the interface of the aluminum oxide layer. Even if the nitrogen element is integrated and distributed on the surface of the hafnium oxide layer, on the one hand, it can prevent metal atoms from diffusing into the interior thereof (for example, preventing metal atoms of the subsequently formed metal gate from diffusing into the interior thereof), and on the other hand, it can improve the temperature bias stability of the device, thereby improving the reliability of the device.

[0052] In this embodiment, after forming the gate dielectric layer 120 , the method for preparing the fin field effect transistor further includes: annealing the semiconductor substrate 100 having the gate dielectric layer 120 , the annealing temperature being 800° C. to 900° C., and the annealing time being 5s to 10s.

[0053] In this embodiment, the annealing treatment is used to repair the gate dielectric layer 120, thereby reducing oxygen vacancies and charge defects in the gate dielectric layer 120, thereby improving the quality and density of the gate dielectric layer 120, and correspondingly improving the electrical performance and reliability performance of the formed fin field effect transistor.

[0054] The gas used in the annealing process may be, for example, ammonia or nitrogen. In this embodiment, the annealing process is performed using a low-temperature furnace tube annealing process. The annealing temperature of the low-temperature furnace tube annealing process is relatively low, which is beneficial for reducing the impact on the uniformity of the annealing effect. The annealing temperature may be 800°C to 900°C.

[0055] In other embodiments, the annealing process may also be a spike annealing process, a laser annealing process, or a flash annealing process.

[0056] Continue to refer Figure 4As shown, the present invention also provides a fin field effect transistor, comprising: a semiconductor substrate 100, wherein the surface of the semiconductor substrate 100 has a plurality of fins 101, and shallow trenches are formed between the plurality of fins 101; and a gate dielectric layer 120, wherein the gate dielectric layer 120 comprises an aluminum oxide layer 121 and a hafnium oxynitride layer 122, wherein the aluminum oxide layer 121 covers the sidewalls and bottom walls of the shallow trenches and extends to cover the fins 101, and the hafnium oxide layer covers the aluminum oxide layer 121. Since the gate dielectric layer 120 includes an aluminum oxide layer 121 and a hafnium oxynitride layer 122 covering the aluminum oxide layer 121, the aluminum oxide layer 121 can form a good interface with the semiconductor substrate 100, providing a good interface foundation for the hafnium oxynitride layer 122, preventing the epitaxial crystallization of the hafnium oxynitride layer and reducing the interface state density between the gate dielectric layer 120 and the semiconductor substrate 100. The aluminum oxide layer 121 cooperates with the hafnium oxynitride layer 122 to reduce losses in the carrier movement process, adjust the Fermi level of the gate dielectric layer 120, thereby reducing leakage current between the gate dielectric layer 120 and the semiconductor substrate 100 and improving device reliability.

[0057] In this embodiment, the shallow trench is filled with an isolation layer 110 . The top surface of the isolation layer 110 is lower than the top surface of the fin 101 . The isolation layer 110 may be made of silicon oxide and is used for isolation between the multiple fins 120 .

[0058] In summary, in the fin field effect transistor and its preparation method provided in the embodiment of the present invention, the gate dielectric layer includes an aluminum oxide layer and a hafnium oxynitride layer covering the aluminum oxide layer. The aluminum oxide layer can form a good interface with the semiconductor substrate, provide a good interface foundation for the hafnium oxynitride layer, prevent the crystallization epitaxial growth of the hafnium oxynitride layer, and reduce the interface state density between the gate dielectric layer and the semiconductor substrate. The aluminum oxide layer cooperates with the hafnium oxynitride layer to reduce the loss in the carrier movement process, adjust the Fermi level of the gate dielectric layer, thereby reducing the leakage current between the gate dielectric layer and the semiconductor substrate, and improving the reliability of the device.

[0059] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for preparing a fin field effect transistor, characterized in that: include: Providing a semiconductor substrate, wherein a surface of the semiconductor substrate has a plurality of fins, and shallow trenches are formed between the plurality of fins; as well as, forming a gate dielectric layer, the gate dielectric layer comprising an aluminum oxide layer and a hafnium oxynitride layer, the aluminum oxide layer covering the sidewalls and bottom wall of the shallow trench and extending to cover the fin, and the hafnium oxynitride layer covering the aluminum oxide layer; The method of forming the gate dielectric layer includes: forming the aluminum oxide layer by a first atomic layer deposition process; forming a hafnium oxide layer by a second atomic layer deposition process, wherein the hafnium oxide layer covers the aluminum oxide layer; and The hafnium oxide layer is nitrided by a third atomic layer deposition process to form the hafnium oxynitride layer.

2. The method for preparing a fin field effect transistor according to claim 1, wherein: The process gases used in the first atomic layer deposition process are aluminum source gas and oxygen source gas, and the process temperature is 200°C~300°C.

3. The method for preparing a fin field effect transistor according to claim 1, wherein: The second atomic layer deposition process uses hafnium source gas and oxygen source gas, and the process temperature is 200° C. to 300° C.

4. The method for preparing a fin field effect transistor according to claim 1, wherein: The process gas used in the third atomic layer deposition process is nitrogen source gas, and the process temperature is 200°C~300°C.

5. The method for preparing a fin field effect transistor according to claim 1, wherein: After forming the gate dielectric layer, the method for preparing the fin field effect transistor further includes: performing annealing on the semiconductor substrate having the gate dielectric layer, wherein the annealing temperature is 800° C. to 900° C. and the annealing time is 5s to 10s.

6. The method for preparing a fin field effect transistor according to claim 1, wherein: The thickness of the aluminum oxide layer is 3 angstroms to 5 angstroms; the thickness of the hafnium oxynitride layer is 8 angstroms to 10 angstroms.

7. The method for preparing a fin field effect transistor according to claim 1, wherein: The shallow trench is filled with an isolation layer, a top surface of the isolation layer is lower than a top surface of the fin, and the gate dielectric layer covers the isolation layer.

8. The method for preparing a fin field effect transistor according to claim 7, wherein: The isolation layer is made of silicon oxide.

9. A fin field effect transistor manufactured by the method for manufacturing a fin field effect transistor according to any one of claims 1 to 8, characterized in that: include: A semiconductor substrate having a plurality of fins on a surface thereof and shallow trenches between the plurality of fins; as well as, A gate dielectric layer includes an aluminum oxide layer and a hafnium oxynitride layer, wherein the aluminum oxide layer covers the sidewalls and bottom wall of the shallow trench and extends to cover the fin, and the hafnium oxynitride layer covers the aluminum oxide layer.

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