Chip separation supported by a backside trench and an adhesive in the backside trench

Abstract

A method of singulating an electronic die (100) from a wafer (102) includes forming at least one trench (104) in a backside (106) of the wafer (102) around at least a portion of the electronic die to be singulated, forming a backside metallization structure (108) covering at least a portion of the backside (106) and at least a portion of the at least one trench (104), attaching an adhesive layer (110) of a tape (112) to at least a portion of the backside metallization structure (108), and singulating the electronic die (100) by removing material from a frontside (114) of the wafer (102) along a singulation path (116) including a portion of the at least one trench (104) such that, during singulation, the adhesive layer (110) fills at least a portion of the at least one trench (104) at the backside (106) and fills above a height level of the backside metallization structure (108).

Description

Technical Field

[0001] This invention relates to a method for separating an electronic chip from a wafer and to an electronic chip. Background Technology

[0002] A package can be represented as an encapsulated electronic chip having electrical connection structures extending from an encapsulating material and mounted to, for example, a printed circuit board. Prior to packaging, a semiconductor wafer is individually diced into multiple electronic chips. After the wafer is individually diced into individual electronic chips, the electronic chips from the wafer can then be picked up for further processing.

[0003] Individualization can be achieved by dicing the wafer from the front side. Especially in the presence of a back-side metallization structure, subsequent pickup of the individualized diced electronic chips may require undesirably high pickup forces. This can make particularly thin electronic chips susceptible to damage and may undesirably prolong the pickup time required to sequentially pick up electronic chips from the separated wafer. Furthermore, pickup capability is often a limiting factor relating to the minimum thickness and / or maximum size of the electronic chip to be manipulated. Summary of the Invention

[0004] The electronic chip on the chip may require a relatively small picking force to manipulate.

[0005] According to an exemplary embodiment, a method for separating an electronic chip from a wafer is provided, wherein the method includes: forming at least one trench in the back side of the wafer surrounding at least a portion of the electronic chip to be separated; forming a back-side metallization structure covering at least a portion of the back side and at least a portion of the at least one trench; attaching an adhesive layer of a strip to at least a portion of the back-side metallization structure; and separating the electronic chip by removing material from the front side of the wafer along a separation path including a portion of the at least one trench, such that during separation, the adhesive layer fills at least a portion of the at least one trench on the back side and fills above the height level of the back-side metallization structure.

[0006] According to another exemplary embodiment, an electronic chip is provided, the electronic chip comprising: a semiconductor body, an active region at the front side of the semiconductor body, a back-side metallization structure at the back side of the semiconductor body, a peripheral notch at a peripheral corner of the semiconductor body located between the back side and the sidewall of the semiconductor body, and a dopant selectively located in a region of the semiconductor body adjacent to the peripheral notch.

[0007] According to an exemplary embodiment, an electronic chip can be separated from a wafer with a small pick-up force that allows for individualization after dicing. This can be accomplished by slotting the back side of the wafer prior to dicing, which can then be performed after the formation of the back-side metallization structure. Preferably, but not necessarily, the trench formation can then be completed by selectively doping the trench regions of the wafer and then etching the doped regions at a higher etch rate than the etch rate of the undoped regions. Still prior to dicing, an adhesive layer of temporary or dicing tape can be attached to the slotted back-side metallization structure on the slotted wafer. Using this method, due to the previous trench formation, subsequent dicing from the opposite front side, for example using a dicing blade or by laser ablation, may result in the edges of the structured back-side metallization structure of the obtained electronic chip having an upwardly curved configuration. This can suppress the formation of downward-protruding burrs adjacent to the separation path (e.g., dicing lines) (especially when performing individualization using dicing blades) or recasting (especially when performing individualization by laser ablation), and can avoid undesirable pick-up forces that increase the creeping effect between the burrs or recasting and the strip. The aforementioned creeping effect can be so strong that it determines the necessary pick-up force, thus the creeping effect may be a limiting factor in allowing electronic chips to become increasingly thinner. Advantageously, the adhesive layer of the strip can fill at least a portion of the trench and fill it to a degree extending beyond the height level of the back metallization structure in the trench region. Preferably, during the formation of the separation path, at least a portion of the trench is filled with the adhesive of the adhesive layer of the strip above a baseline level—the baseline level can be defined as the horizontal height corresponding to the interface between the back metallization structure outside the trench and the wafer. Thus, the adhesive supports the back metallization structure to prevent cracking and breakage. Therefore, defect-free separated electronic chips can be picked up from the adhesive strip with a relatively small pick-up force for subsequent processing, such as in assembly. Descriptively speaking, the trench-based upward bending of the back-side metallization structure adjacent to the separation path, along with the mechanical integrity ensured by the back-side metallization structure and the wafer material adjacent to the separation path, facilitates the easy and intact lifting of individual electronic chips from the adhesive layer of the strip. Exemplary embodiments can reliably protect particularly thin electronic chips from damage and can significantly reduce the pick-up time for sequentially picking up electronic chips from separated wafers. Utilizing the manufacturing architecture according to exemplary embodiments, the pick-up capability in terms of minimum thickness and / or maximum size of the electronic chips to be manipulated can be increased.

[0008] As a unique aspect of the described manufacturing architecture involving trench formation, an electronic chip according to an exemplary embodiment may have a peripheral notch extending along the peripheral corner of the electronic chip on its back side. Furthermore, dopant residues may be present in the semiconductor material adjacent to the peripheral notch. The correspondingly configured electronic chip can be picked up with a small pickup force and is properly protected from undesirable damage during manufacturing, even in the case of extremely thin chips.

[0009] Description of further exemplary embodiments

[0010] Below, further exemplary embodiments of the method and the electronic chip will be explained.

[0011] In the context of this application, the term "wafer" may specifically refer to a semiconductor substrate that has been processed to form multiple integrated circuit elements in the active region of the wafer and can be individualized into multiple separate electronic chips. For example, a wafer may be disk-shaped and may include a matrix arrangement of electronic chips in rows and columns. A wafer may have a circular geometry or a polygonal geometry (e.g., a rectangular geometry or a triangular geometry).

[0012] In the context of this application, the term "electronic chip" can specifically refer to a bare die, i.e., an unpackaged (e.g., unmolded) chip made of processed semiconductors, such as a diced semiconductor wafer. However, a semiconductor chip can also be a packaged (e.g., molded or laminated) bare die. One or more integrated circuit elements (e.g., MEMS, diodes, transistors, etc.) can be formed within the semiconductor chip. Such a semiconductor chip may be equipped with metallization structures, particularly with one or more pads, on the front side (corresponding to the active region) and / or the back side.

[0013] In the context of this application, the term "separation" may specifically refer to the process of dividing multiple separate electronic chips from a monolithic wafer into multiple segments of the previous wafer. Such separation or individualization may be accomplished, in particular, by sawing or by laser cutting.

[0014] In the context of this application, the term "trench" may specifically refer to a notch, elongated recess, or indentation formed in the body of a wafer, particularly a semiconductor body. For example, the trench or notch may be closed circumferentially around or along the periphery of an electronic chip to be separated from the wafer. For example, the trench may have a rectangular shape in the circumferential direction. In the direction of extension into the semiconductor body of the wafer, the cross-section of the trench may preferably have a concave, rounded shape.

[0015] In the context of this application, the term "front side" may specifically refer to the main surface of a wafer or electronic chip, on which at least one integrated circuit element (e.g., a transistor or diode) may be monolithically integrated. Therefore, the front side may correspond to the main surface of a wafer or electronic chip having an active region.

[0016] In the context of this application, the term "back side" may specifically refer to the main surface of a wafer or electronic chip that is opposite to or away from its front side. For example, the back side of a wafer or electronic chip may not have monolithically integrated circuit elements.

[0017] In the context of this application, the term "separation path" may specifically refer to the trajectory along which the material of the wafer is removed to separate individual electronic chips from the wafer composite. For example, a separation path may be a cutting path along which a cutting blade or knife (or alternatively a laser beam) moves and removes material from the wafer during chip separation.

[0018] In the context of this application, the term "active region" may specifically refer to a surface region of the semiconductor body of a wafer or electronic chip, in which at least one monolithically integrated circuit element is formed. In particular, such an active region may be formed on the front side of the surface region of the wafer or electronic chip.

[0019] In the context of this application, the term "peripheral notch at a peripheral corner" can specifically refer to an indentation or recess extending into the semiconductor material of an electronic chip and along a closed periphery. More specifically, the notch can extend into a corner of an electronic chip, for example, substantially cubic, located between the bottom main surface and the sidewalls, thus forming a stepped geometry with two outer corners and one inner corner in between. Each of the aforementioned corners can be defined by a sharp edge or by a rounded edge. It is also possible that the peripheral notch at least partially lining a curved portion of the back-side metallized structure.

[0020] In the context of this application, the term "dopant" can specifically refer to the traces of an impurity element introduced into the semiconductor body of a wafer or electronic chip and locally altering the properties of the semiconductor body, particularly its etchability. When implanted into a crystalline material (particularly a semiconductor such as silicon or germanium), dopant atoms are incorporated into the crystal lattice. However, dopant can also be introduced into amorphous or polycrystalline materials. When the semiconductor body is a group IV material (e.g., silicon), the dopant atoms can particularly be group III materials (e.g., boron) or group V materials (e.g., antimony). Dopant atoms may also include both group III and group V materials. In another embodiment, the dopant atoms can form a reverse dopant (i.e., can be of the anti-dopant type) compared to the semiconductor substrate.

[0021] In one embodiment, the method includes forming two spaced trenches around at least a portion of the electronic chip in the back side of the wafer. Advantageously, a sub-portion of each of the two trenches can form part of a separation path. More specifically, separation of the electronic chip from the wafer composite can be accomplished by cutting through a semiconductor material that partially includes the trenches between them. Therefore, a tilted or stepped geometry of the wafer and / or back-side metallization structure material can be achieved adjacent to the separation path, which can facilitate easy, low-force pickup of the separated electronic chip.

[0022] Specifically, when the separation path for separating electronic chips includes portions of two trenches, these trenches can be shared between different electronic chips to be separated from the wafer. For example, the electronic chips can be arranged in rows and columns in a matrix-like manner within a disk-shaped wafer. In this case, individualizing multiple electronic components can include cutting along the rows and columns by removing the substrate corresponding to the trench portions between the trenches. For example, different trenches can be arranged vertically along the rows and columns of the wafer for separating the electronic chips between them.

[0023] In one embodiment, the method includes forming two spaced-apart trenches that are parallel to each other and / or around a common center. For example, both trenches may be circumferentially closed, with the smaller trench extending within the boundary of the larger trench. In other words, the smaller trench may be a closed-loop trench extending entirely within another closed-loop trench constituting the larger trench. This allows a cutting blade or laser beam to cut along a separate path that extends through the entire wafer and along the space between the two trenches.

[0024] In one embodiment, the method includes separating an electronic chip along a separation path comprising a region between two spaced-apart trenches. By removing material between the spaced-apart trenches, the shape of the lateral edges of the separated electronic chip can be partially defined by trench geometry. Therefore, the geometry at the lateral edges can be at least partially defined by trench geometry.

[0025] In one embodiment, the method includes forming the at least one trench that is closed circumferentially along the entire periphery of the electronic chip to be separated. Therefore, the separated electronic chip can be lifted with a small pick-up force along its entire periphery, since the pick-up force that reduces the influence of the trench can be effective around the entire periphery. Alternatively, the at least one trench may extend only along a portion of the periphery of the trench, such that a portion of the periphery of the electronic chip facilitates a low pick-up force while allowing the separation process to be performed in a particularly fast manner.

[0026] In one embodiment, the method includes forming at least one trench with a depth less than or equal to the thickness of the adhesive layer. When ensuring that the depth of the trench does not exceed the thickness of the adhesive layer, it can facilitate the adhesive layer to largely fill, particularly completely fill, the trench. In other words, a trench with such a small depth can be (at least almost) completely filled with the adhesive layer to fully support all areas during cutting.

[0027] In one embodiment, the method includes forming at least one trench with a depth not exceeding 10 μm, particularly in the range of 3 μm to 10 μm. The 10 μm dimension can be a suitable thickness for the adhesive layer of the wafer and electronic chip strip, allowing for sufficiently low pick-up forces. Trenches with depths in the range of 3 μm to 10 μm can be appropriately filled with the adhesive material of the adjacent adhesive layer, and can be fabricated in a rapid manner and in a way that facilitates low-force pick-up. Furthermore, trench depths not exceeding 10 μm are also suitable for the separation of ultra-thin electronic chips with a thickness of 60 μm or less, where the limitation of pick-up forces is a major advantage given their limited mechanical reliability.

[0028] In one embodiment, the method includes forming at least one trench with a width smaller than the width of the separation path. Specifically, the at least one trench may be formed with a width not exceeding 70% or even 50% of the width of the separation path. Sufficient support should be maintained along the separation path (along which the sawing process may take place), and the volume of the trench should not be excessive.

[0029] In one embodiment, the method includes separating electronic chips by utilizing one of the groups of mechanical blade cutting and laser processing. Mechanically cutting a wafer into individual electronic chips can produce burrs of undesirable back-side metallization near the cut line. Correspondingly, cutting a wafer into individual electronic chips by laser processing can produce undesirable recasting of the back-side metallization near the cut line. In the case of mechanical cutting involving blades, the metal material may deform or bend downwards during separation. In laser cutting, the material of the back-side metallization can be melted or otherwise rearranged to form a downwardly extending recasting. Such burrs or recasting can cause gripping between the back-side metallization and the strip, potentially increasing pick-up force undesirably. However, forming grooves at the lateral ends of the separation path and removing wafer material along the separation path during individual dicing can strongly suppress this undesirable gripping phenomenon.

[0030] In one embodiment, the method includes separation by guiding a mechanical blade through the entire wafer, through the entire adhesive layer, and (preferably only partially) into the foil beneath the adhesive layer of the strip. By advancing the mechanical cutting blade beyond the wafer, through the entire adhesive layer, and to the foil of the strip, complete individualization separation is ensured, and human artifacts adjacent to the separation path of the electronic chip are prevented, thereby significantly reducing pick-up force.

[0031] In one embodiment, the method includes separating the electronic chip in such a manner that the adhesive layer fills the entire trench during separation. By ensuring that the entire trench is filled with the adhesive during individual dicing, the entire back-side metallization structure and the semiconductor body material can be reliably protected from breakage and burr formation or recasting. Therefore, the pick-up force of the individual diced electronic chip can be significantly reduced by efficiently minimizing the adhesion effect of burrs and the adhesive.

[0032] In one embodiment, the method includes forming at least one trench by covering the back side of a wafer with a patterned mask, doping the wafer through the patterned mask, and etching the wafer after removing the patterned mask. According to such a preferred embodiment, selective doping of a trench-defining portion on the back side of the semiconductor body of the wafer using a structured mask (e.g., a photolithographically processed mask) allows for precise definition of the doped surface region of the semiconductor body. After mask removal, wet etching (e.g., using HNA, i.e., an etching solution composed of hydrofluoric acid, nitric acid, and acetic acid) enables trench formation because the doped semiconductor material is more efficient to etch than the undoped semiconductor material. Preferably, an etching medium that acts in a manner that amplifies doping differences can be used. For example, HNA (where a certain proportion of acetic acid produces an enhancing effect according to the doping concentration) can be used for this purpose. The described process allows trenches to be formed with high precision and very low effort.

[0033] In another embodiment, the method includes forming the at least one trench by covering the back side of the wafer with a patterned mask and etching the wafer through the patterned mask. The method also allows trench formation where a doping process can be omitted. However, the overall effort required for dopant-based trench formation described above may be lower.

[0034] In one embodiment, the method includes picking up the separated electronic chips from the tape after separation. When a wafer is separated into multiple electronic chips, multiple separated electronic chips can be picked up sequentially from the adhesive tape. This indicates that the picking process contributes significantly to the overall effort in terms of time consumption. By reducing the picking time, the exemplary embodiment can significantly reduce the overall effort of the individualization and picking processes.

[0035] In one embodiment, picking up the separated electronic chip involves lifting the electronic chip from the strip by applying a lifting force to the back side of the electronic chip using at least one pin. Such a pin or needle can penetrate the strip (including its adhesive layer), thereby allowing the application of an upwardly oriented lifting force. Particularly in the presence of very thin electronic chips with a thickness not exceeding 60 μm, lifting the electronic chip can also cause such chips to bend or even vibrate, which can complicate and time-consuming the picking process. Advantageously, reducing the picking force through the trench-based individual segmentation concept of the exemplary embodiment can reduce or even mitigate such conventional disadvantages.

[0036] In one embodiment, picking up the separated electronic chip includes gripping the lifted electronic chip at the front side of the electronic chip (particularly during or after lifting the electronic chip via at least one pin described above). During and / or after lifting the separated electronic chip from the back side via one or more pins described above, the lifted electronic chip can be removed from the remainder of the wafer by applying vacuum suction to the respective electronic chip via a nozzle or the like at the front side of the electronic chip. Through such a vacuum nozzle, the electronic chip can be manipulated or transported to a destination, such as an assembly location.

[0037] In one embodiment, the electronic chip has a thickness of less than 100 μm, particularly less than 60 μm. Modern chip technology, such as in power semiconductor applications, increasingly focuses on reducing chip thickness. While this offers significant advantages in terms of packaging, compactness, and performance, extremely thick electronic chips present a handling challenge. This is particularly true for tasks involving the picking up of such extremely thin electronic chips. However, based on the described concept of trench formation on the back side and then separation from the front side, the picking force can be significantly reduced, allowing even very thin electronic chips to be manipulated in a time-efficient manner without the risk of damage.

[0038] In one embodiment, the electronic chip is configured to undergo vertical current flow between the front and back sides during operation. Specifically, current can flow from pads on the lower main surface of the electronic component through the semiconductor material of the electronic component to another pad on the upper main surface of the electronic component. For example, the electronic chip undergoing vertical current flow can be configured as a field-effect transistor chip, wherein source and gate pads are arranged on one main surface, while drain pads are arranged on the opposite main surface of the electronic chip.

[0039] Electronic chips with vertical current flow during operation may require both front-side and back-side metallization structures. However, equipping a wafer with a back-side metallization structure can present challenges in terms of burr formation or recasting during individual dicing. However, as described above, due to individual dicing along one or two trenches with a back-side metallization structure, exemplary embodiments can address such challenges by triggering an upward bending of the chip edge on its underside.

[0040] However, other exemplary embodiments can also be applied to electronic chips where no vertical current flows. For such electronic chips, a back-side metallization structure can be formed, for example, to meet the requirements of die attachment adhesion, for cooling purposes, etc.

[0041] In one embodiment, the peripheral notch is rounded on the back side. This rounding is key to the etching process that creates trenches with a smooth surface profile.

[0042] In one embodiment, the peripheral notch is defined by a continuously curved (e.g., substantially S-shaped) surface portion of the semiconductor body. This geometry is also created by trenches formed through etching.

[0043] In one embodiment, the concentration of the dopant is at least 10. 17 One atom per cm 3 Especially at least 10 18 One atom per cm 3 Specifically, the dopant concentration can be at least 10 times, particularly at least 100 times, and preferably at least 1000 times, the intrinsic carrier concentration in the semiconductor body. Correspondingly, the concentration at least a portion of the dopant concentration along the periphery of the notch on the back side of the semiconductor body is greater than the concentration in the central portion of the back side of the semiconductor body (particularly at least 10 times, more particularly at least 100 times, and preferably at least 1000 times). The greater the difference between the dopant concentration for locally confined dopant implantation for trench formation and the intrinsic non-specific carrier concentration in the semiconductor body, the higher the precision of trench formation in terms of size, location, and shape. In the case of reverse doping of dopant atoms compared to the semiconductor substrate (i.e., reverse doping using dopant atoms of an anti-doping type compared to the semiconductor substrate), other (particularly smaller) dopant concentrations besides the mentioned concentrations may be suitable.

[0044] In one embodiment, the electronic chip is a power semiconductor chip. Such a power semiconductor chip may have one or more integrated integrated circuit elements therein, such as transistors (e.g., field-effect transistors such as metal-oxide-semiconductor field-effect transistors and / or bipolar transistors such as insulated-gate bipolar transistors) and / or diodes. An exemplary application that can be provided by such integrated circuit elements is for switching purposes. For example, such another integrated circuit element of a power semiconductor device may be integrated in a half-bridge or full-bridge. An exemplary application is automotive applications.

[0045] The one or more electronic chips (particularly semiconductor chips) may include at least one of the groups consisting of diodes and transistors, more particularly insulated-gate bipolar transistors. For example, the one or more electronic chips may be used as semiconductor chips in power applications, such as in the automotive field. In one embodiment, at least one semiconductor chip may include a logic IC or a semiconductor chip for RF power applications. In one embodiment, the semiconductor chip may be used as one or more sensors or actuators in a microelectromechanical system (MEMS), such as a pressure sensor or accelerometer, a microphone, a speaker, etc.

[0046] As a substrate or wafer for use in semiconductor chips, a semiconductor substrate, i.e., a silicon substrate, can be used. Alternatively, silicon oxide or another insulating substrate can be provided. Germanium substrates or III-V semiconductor materials can also be implemented. For example, exemplary embodiments can be implemented using GaN or SiC technology.

[0047] Furthermore, exemplary embodiments may utilize standard semiconductor processing techniques such as suitable etching techniques (including isotropic and anisotropic etching techniques, particularly plasma etching, dry etching, and wet etching), patterning techniques (which may involve photomasks), and deposition techniques (e.g., chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sputtering, etc.).

[0048] The above and other objects, features and advantages of the invention will become apparent from the following description taken in conjunction with the accompanying drawings and the appended claims, in which like parts or elements are indicated by like reference numerals. Attached Figure Description

[0049] The accompanying drawings, which are included to provide a further understanding of exemplary embodiments of the invention and form part of the specification, illustrate exemplary embodiments of the invention.

[0050] In the diagram:

[0051] Figures 1 to 5 Different structures obtained during the execution of a method for separating and picking up electronic chips from a wafer, according to an exemplary embodiment, are shown.

[0052] Figures 6 to 11 Different structures obtained during the execution of a method for separating and picking up electronic chips from a wafer are shown according to an exemplary embodiment and another method described for comparative purposes.

[0053] Figure 12 This is a graph showing experimental results of the relationship between pin distance and lifting force according to an exemplary embodiment and in a conventional method.

[0054] Figure 13 A cross-sectional view of an electronic chip manufactured according to an exemplary embodiment is shown.

[0055] Figures 14 to 16 Different structures obtained during the execution of a method for separating and picking up electronic chips from a wafer, according to an exemplary embodiment, are shown.

[0056] Figure 17 A top view of an electronic chip manufactured according to an exemplary embodiment is shown. Detailed Implementation

[0057] The illustrations in the image are schematic and not to scale.

[0058] Before describing the exemplary embodiments in more detail with reference to the accompanying drawings, some general considerations will be summarized based on those exemplary embodiments that have been developed.

[0059] Thin power devices can have back-side metal, which can cause burrs to form on the back side of the wafer during mechanical dicing or recasting during ablation laser dicing. Burrs or recasting significantly affect the adhesion to the tape and the necessary pick-up force.

[0060] It may be desirable to reduce or even eliminate such burrs or recasting phenomena that affect the adhesion of the bare film.

[0061] According to an exemplary embodiment, by forming trenches under the back-side metallization structure of the wafer prior to individual dicing along a separation path from the front side, the pick-up force required to pick up separated electronic chips from the wafer on the adhesion tape can be significantly reduced, wherein the separation path includes a portion of the trench at its edge or preferably a portion of two opposing trenches. This allows for the pick-up of even very thin dies with low force, a simple, and fast pick-up process. Exemplary embodiments can be particularly advantageously applied to processing electronic chips for power devices with low on-resistance (RDSON) values. Furthermore, this method enables a faster pick-up process. This is highly beneficial because picking up electronic chips from an individualized diced wafer is a continuous process, thus having a significant impact on the overall effort required for chip processing. In addition, exemplary embodiments can allow for fewer die cracks during pick-up.

[0062] According to a preferred embodiment, the formation of one or more trenches can be performed as follows: First, modification of wafer backside stress relief can be accomplished by local doping at one or more locations on the semiconductor body of the wafer, at which trench formation and subsequent individualization will then be performed. Advantageously, pick-up behavior can be facilitated by local wafer backside doping. More specifically, an exemplary embodiment can apply patterned implantation on the wafer backside in such a way that subsequent wet etching processes alleviate stress and form shallow grooves on the wafer backside. Advantageously, pick-up force can be reduced by decreasing the adhesion effect of burrs on adhesives and strips. More specifically, burrs or recasting of the backside metallization structure can be suppressed prior to individualization by forming trenches in the semiconductor body under the backside metallization structure and by partially or preferably completely filling the trenches with adhesive material of an adhesive layer attached to a temporary strip of the backside metallization structure. Descriptively speaking, this can reduce the undesirable creeping effect of adhesive strips on burrs or recasting of the backside metallization structure. Advantageously, edge adhesion of separated electronic devices or chips can be suppressed by a slight upward bending of the back-side metallization structure adjacent to the trench.

[0063] In a preferred embodiment, each electronic chip to be separated may be surrounded by two trenches, each trench corresponding to a corresponding edge of the cutting blade or cutting laser beam. Advantageously, the width of each trench may be less than the width of the cut or separation path. In embodiments, the trench depth may not exceed 10 μm, as the trenches are preferably completely filled with a tape compound that can have a typical thickness of approximately 10 μm. Simultaneously, the trench depth should preferably be at least 1 μm to achieve a sufficiently strong effect on the upward bending of the free edges of the back-side metallized structure in order to reduce pick-up forces. By following the design rules described above, all areas can be fully supported during cutting. A trench depth of no more than 10 μm may be advantageous when the electronic chip is implemented as an ultrathin die with a thickness of less than 60 μm, making pick-up most critical at this point.

[0064] In terms of trench formation, implantation-based patterning can be performed using an etch solution that is sensitive to dopant concentration and whose etch rate increases with increasing implantation dose. It is possible to use the same dopant type as the substrate (both n-type or both p-type) as well as the opposite dopant type (one n-type and another p-type).

[0065] Alternatively, trenches can also be formed using a selective etching process that has a higher etching rate in undoped semiconductor materials compared to doped semiconductor materials. The logic for trench formation can be reversed compared to the embodiments described above.

[0066] In an embodiment, a process for relieving back-side stress on the wafer through localized doping can be performed, the process including grinding the back side of the wafer. Subsequently, back-side photolithography can be performed. This is followed by a back-side implantation process (e.g., doping with boron or arsenic) on the surface portion of the doped wafer. The resist can then be removed by stripping. Shallow pits or trenches can then be created at the implanted areas due to the locally higher etching rate. Next, back-side metal deposition (e.g., gold-tin or silver-based) can be performed. A strip with an adhesive layer can then be mounted on the back-side metallized structure, such that the adhesive is preferably fully embedded in the pits or trenches. The glass carrier, which may have previously supported the wafer on the front side, can then be removed. The wafer can then be diced (e.g., mechanically or by laser processing). The separated electronic chip or die can then be lifted from the back-side strip using one or more ejector pins or needles. Thus, the electronic chip can be completely released from the strip.

[0067] According to an exemplary embodiment, the process flow for back-side metal deposition on a wafer can be configured in a manner that reduces the pick-up force required for pick-up compared to conventional methods. Burrs that may be generated during mechanical dicing, or recasting formed during ablation laser dicing, can significantly determine the adhesion force of the electronic chip to the strip, thus determining the necessary pick-up force. However, reducing the pick-up force can be highly advantageous because it allows for the pick-up of even thinner dies through a simpler pick-up process. Therefore, a low-force pick-up process can be particularly beneficial for reducing the RDSON value of power devices. A faster pick-up process, as implemented by the exemplary embodiment, can be beneficial because pick-up is a serial process and therefore contributes significantly to the effort invested during chip individualization and processing. Furthermore, the reduced pick-up force can decrease the risk of die breakage during pick-up. These advantages can be achieved by forming trenches in the semiconductor body located beneath the back-side metallization structure and adjacent to the separation path between adjacent electronic chips.

[0068] Specifically, such trenches can be created by a patterned implantation process on the back side of the wafer, allowing subsequent wet etching stress reduction to selectively form shallow grooves in the dopant implantation regions on the back side of the wafer. These grooves can preferably be located near the dicing channels. Different embodiments may include different dopants (particularly group III or V materials, such as boron or arsenic). In different embodiments, different layouts of the grooved pits, different dicing methods, etc., can be implemented.

[0069] Exemplary embodiments can reduce the risk of crack formation during pick-up and / or enable pick-up of thinner dies (particularly with improved performance) and / or faster pick-up processes. Regions with increased doping levels can be created at chip back corners or chip back edges.

[0070] The inventors have surprisingly discovered that the lateral chip edges provide a significant contribution to the adhesion force, exceeding the pick-up force required to lift and separate the electronic chip from the tape or dicing foil. Studies have shown that this is particularly applicable to very thin electronic chips with a thickness of less than 100 μm, especially less than 60 μm. Picking up such ultrathin electronic chips is a particular challenge because the pick-up force can also exert mechanical stress on the electronic chip, making it susceptible to damage during the pick-up process. This challenge can become even more critical due to the tendency for burrs to form at the chip edges (in the case of mechanical cutting) or recasting (in the case of laser cutting), potentially increasing the adhesion force of the electronic chip to the adhesive tape and thus increasing the required pick-up force due to mechanical interlocking or creeping effects between the tape and the back-side metallization structure. Advantageously, an exemplary embodiment can reduce chip adhesion force, particularly at the chip edges, thereby enabling the pick-up of even very thin electronic chips with moderate pick-up force. This can be achieved by forming one or more trenches on the back side of the wafer, the trenches having a depth preferably not exceeding the thickness of the adhesive layer of the tape on which the wafer is adhered. Surprisingly, it has been found that trench locations should be (preferably fully) mechanically supported during individual chip splitting, as the effects of excessive adhesion at the chip edges may be amplified in other ways. Advantageously, this support of the trench locations can be achieved by filling the trenches vertically horizontally, fully or at least to the base level above the upper side of the back metallization structure, with an adhesive material. This supports the back metallization structure during individual chip splitting and ensures that the free ends of the back metallization structure of the separated electronic chips protrude upwards rather than downwards at the critical chip edges.

[0071] Figures 1 to 5 Different structures obtained during the execution of a method for separating and picking up an electronic chip 100 from a wafer 102 are shown according to an exemplary embodiment.

[0072] refer to Figure 1 The diagram shows a cross-sectional view of the semiconductor body 122 of the silicon wafer 102, such as a bulk substrate in the form of a silicon body. A carrier 150, implemented herein as a glass carrier, is arranged on the front side 114 of the wafer 102. An active region 124 is formed in the surface portion of the wafer 102 located on the front side 114, in which one or more integrated circuit elements can be monolithically integrated.

[0073] according to Figure 1 And as schematically indicated by reference numeral 151 in the accompanying drawings, wafer 102 is thinned from the back side 106, for example, by grinding. Through this grinding process, the thickness of wafer 102 can be reduced to, for example, 50 μm to 60 μm. Thereafter, further thinning processes can be performed on the back side 106, for example, by removing an additional 20 μm of wafer 102 through wet etching.

[0074] like Figure 2 As shown, the back side 106 of wafer 102 may be covered with a layer of photoresist. Subsequently, the photoresist layer can be patterned to form a patterned mask 118. Through patterning, specific surface portions of the back side 106 of wafer 102 can be exposed, while the remaining surfaces on the back side 106 of wafer 102 remain covered by the photoresist material of the patterned mask 118. Subsequently, the exposed surface portions of wafer 102 on the back side 106 can be doped through the patterned mask 118, such that defined and locally confined regions of dopant 128 can be formed in the surface portions of wafer 102 located on the back side 106.

[0075] Therefore, dopant implantation (e.g., dopant 128, implemented as boron, arsenic, or antimony) can be performed at the back side 106 after photolithography. The patterned mask 118 can then be removed, for example, by resist stripping. Descriptively, the implantation profile of the patterned mask 118 defines the shape of the pits or trenches 104 that will later be formed at the defined locations of the dopant 128. For example, a quad-mode implantation process can allow for the formation of shallow, smooth trench profiles. Traces of the implantation or dopant 128 remain in the processed wafer 102 and the electronic chip 100 to be manufactured.

[0076] Despite Figure 2 Not shown, but after removing the patterned mask 118, the process can continue to further etch the wafer 102 from the back side 106 of the wafer 102. Thus, trenches 104, 130 can be formed in the back side 106 of the wafer 102 at the locations of the dopant 128 (see [reference]). Figure 3 Therefore, a selective wet etching process with a higher etching rate in the doped semiconductor material of wafer 102 (i.e., in the region of dopant 128) can be performed compared to the undoped semiconductor material of wafer 102. Although in Figure 2 Not shown in the cross-sectional view, but trenches 104, 130 can form circumferentially closed recesses in the bottom surface or back side 106 of wafer 102 and can surround the corresponding portion of wafer 102 corresponding to the electronic chip 100 to be separated from the wafer composite. Advantageously, and still referring to Figure 2 And refer to other sources Figure 3The method may include forming two spaced-apart trenches 104, 130 in the back side 106 of wafer 102 around an electronic chip 100 to be individualized. For example, each of the trenches 104, 130 on the back side 106 of wafer 102 may be a closed (e.g., rectangular) recess, wherein the smaller diameter trench 104 may be completely disposed within the boundary of the larger diameter trench 130. Thus, each of the trenches 104, 130 may be formed circumferentially closed around the entire electronic chip 100 to be separated. More specifically, the two spaced-apart trenches 104, 130 may consist of a plurality of connected trench segments, each pair of corresponding trench segments of trenches 104, 130 extending parallel to each other. Furthermore, both trenches 104, 130 may be formed around a common center 153.

[0077] The trenches 104, 130, ... can also extend as straight intersecting lines along the rows and columns between the different electronic chips 100 of the wafer 102 to be separated. The separation of the electronic chips 100 can then be performed by cutting along the trenches 104, 130, ... in two perpendicular directions.

[0078] In an alternative embodiment (not shown), trenches 104, 140 can be formed without forming dopant 128 in the exposed surface portion of wafer 102 on the back side 106, and the trenches can be formed by selective etching of the semiconductor material of wafer 102 through openings in patterned mask 118 prior to removal of patterned mask 118. However, the previously described embodiments involving the formation of regions of dopant 128 may involve less overall effort due to the faster etching process used to define trenches 104, 130.

[0079] In order to obtain Figure 3 In the structure shown, to alleviate stress and form trenches 104, 130 at these locations of the dopant 128, the exposed back side 106 can undergo the aforementioned etching process, such as a wet etching process. This etching process allows for the removal of more semiconductor material from the back side 106 of the wafer 102. During the etching process, because the etching rate of the doped semiconductor material is higher than that of the undoped semiconductor material of the wafer 102, trenches 104, 130 in the form of shallow pits are formed only at the implantation regions of the dopant 128. For example, etching of the undoped semiconductor material can remove 5 μm from the wafer 102, while the same etching process using doped semiconductor material in the regions of the dopant 128 can remove 10 μm from the wafer 102.

[0080] Subsequently, a back-side metallization structure 108 (e.g., made of AuSn) is formed throughout the entire back side 106 and the surface portions of trenches 104 and 130. For example, the thickness of the back-side metallization structure 108 can range from 1 μm to 5 μm. The back-side metallization structure 108 can provide reliable electrical contact and contribute to efficient heat removal. The back-side metallization structure 108 can be formed as a conformal layer with substantially uniform thickness. Therefore, the back-side metallization structure 108 can cover the entire back side 106 and trenches 104 and 130.

[0081] from Figure 3 As can be seen from the magnified view 152, each trench 104, 130 can be formed with a depth "d" of, for example, 5 μm. Furthermore, the depth "d" can be less than or equal to the depth subsequently attached according to... Figure 3 The thickness “D” of the adhesive layer 110 on the bottom side of the structure with 112, see [reference]. Figure 4 The width "w" of each trench 104, 130 can be less than the width "W" of the separation path 116, that is, less than according to Figure 4 The width of the dicing lines that divide the wafer 102 into multiple electronic chips 100. For example, the width "w" of each trench 104, 130 can be 10 μm.

[0082] In order to obtain Figure 4 In the structure shown, the strip 112 is adhesively mounted on the back metallized structure 108 on the back side 106. Subsequently, the carrier 150 is removed from the front side 114, and the wafer 102 is separated by cutting (e.g., mechanically or using laser cutting) along the separation path 116 into individual electronic chips 100.

[0083] from Figure 4 As can be seen in magnified view 154, the adhesive layer 110 of the strip 112 can be attached to the back-side metallization structure 108. More specifically, the strip 112 can consist of a foil 136 (e.g., a plastic foil) and an adhesive layer 110 applied to the foil 136 facing the top side of the wafer 102. During the separation of the electronic chip 100, the adhesive layer 110 can advantageously extend into the trenches 104, 130, as shown below. Figure 9 A more detailed description.

[0084] After attaching the strip 110 to the back side 106 and exposing the front side 114 by removing the optional carrier 150, the electronic chip 100 is separated from the wafer 102 by removing material from the front side 114 of the wafer 102 along a vertically and circumferentially closed separation path 116. In the vertical direction, the separation path 116 extends completely through the wafer 102 and also includes portions of the trenches 104, 130. The relationship between the trenches 104, 130 in the wafer 102, the back side metallization structure 108 on the wafer 102, the adhesive layer 110 of the strip 112, and the separation path 116 can be adjusted such that the adhesive layer 110 preferably completely fills the trenches 104, 130 during separation. Advantageously, the adhesive layer 110 should, during separation, fill at least partially in the trenches 104, 130 on the back side 106 above the upper baseline level 155 of the back side metallization structure 108 (see below). Figure 9 and Figure 10 (Described in more detail). With this configuration, the adhesive layer 110 supports the back-side metallization structure 108 to prevent cracking during the separation process. Furthermore, as a result of the trenches 104, 130, the upwardly curved portion of the back-side metallization structure 108 in the interface region between the bottom and sidewalls of the separated electronic chip 100 reduces the pick-up force required to retrieve the electronic chip 100 from the tape 112. Therefore, the electronic chip 100 can be retrieved from the tape 112 without the risk of damaging the tiny electronic chip 100 during manipulation.

[0085] To completely separate each electronic chip 100 from the wafer composite, a separation path 116 also extends circumferentially around the sidewalls of the separated electronic chip 100. Furthermore, the separation of the respective electronic chip 100 occurs along the separation path 116, which includes the region between two spaced-apart trenches 104, 130. Specifically, a portion of the material of the wafer 102 of the back-side metallized structure 108 and the strip 112 is removed between the trenches 104, 130, including the material above the corresponding sub-section of each trench 130, 104.

[0086] according to Figure 4 Each separated electronic chip 100 can have a very small thickness "L", for example, 40 μm. Even for electronic chips 100 with such a small thickness, separation (as already described) and pickup (as described below) processes can be performed. Electronic chips 100 with such a small thickness "L" can also be configured to withstand vertical current flow between the front side 114 and the back side 106 during operation of electronic chip 100. For example, electronic chip 100 can be a power semiconductor chip with a monolithic integrated field-effect transistor.

[0087] Preferably, during the dicing process, the back side 106 of the wafer 102, covered with the back-side metallization structure 108, is fully supported by the dicing tape adhesive of the adhesive layer 110 to prevent back-side breakage and to avoid dicing residue between the back side 106 of the electronic chip 100 and the tape 112. The adhesive layer thickness “D” can be, for example, about 10 μm, to perfectly match the described boundary conditions. The adhesive layer 110 should preferably partially or completely fill the pits or trenches 104, 130 during separation. Preferably, the trench height or depth “d” does not exceed the adhesive layer thickness “D” to facilitate significant filling of the trenches 104, 130 with adhesive during separation.

[0088] Furthermore, using two small grooves 104, 130 (located at the edges of the cutting channel, i.e., at the left and right ends of the separation path 116) may be more easily filled by the adhesive compound surrounded by the adhesive layer 110 than a very wide and very deep back groove that spans the entire cutting channel or separation path 116.

[0089] Figure 5 It is shown in accordance with Figure 4 The separation process describes how the separated electronic chip 100 is picked up from the belt 112. During the pickup of the separated electronic chip 100, the electronic chip 100 is lifted from the belt 112 by applying a vertical lifting force to the disengagement pin 120 or needle on the back side 106 of the electronic chip 100. Due to this lifting force, the electronic chip 100 moves upward and separates from the belt 112. Advantageously, the back metallization structure 108 of the individual segmented electronic chip 100 can also make the upwardly curved or inclined edge portion forming the circumferential groove 126 facilitate the low-force detachment of the electronic chip 100 from the belt 112. Due to the described manufacturing process involving the grooves 104, 130 and the manufacturing process of filling them with an adhesive during separation, the formation of undesirable burrs at the lateral ends of the back metallization structure 108 (which can typically interlock with the material of the belt 112 to increase the pickup force) can be reliably prevented. The reduced pickup force also reliably protects the tiny electronic chip 100 from mechanical damage during pickup and manipulation.

[0090] Although not shown in the figure, the pick-up process can also be supported from the top side by using a vacuum nozzle (not shown) to adsorb the raised electronic chip 100 on the front side 114 of the electronic chip 100. While held by the vacuum nozzle, the separated electronic chip 100 can be transported elsewhere, for example, for assembly purposes.

[0091] In summary, according to Figure 5The process shown includes: lifting the die-type electronic chip 100 from the bottom side using a detachment pin 120; forming trenches 104, 130 due to additional implantation using dopant 128, thereby releasing the edge clamping; and completely releasing the electronic chip 100 from the strip 112. Through the advantageous measures described, the edge of the microelectronic chip 100 is released from the strip 112.

[0092] For the purpose of comparison, Figure 4 Area 200 and Figure 5 Region 202 illustrates a scenario where trenches 104 and 130 were not formed and no additional injection was performed prior to the separation of the electronic components. See also... Figure 4 In the magnified view 206, the downwardly extending burrs 204 of the back-side metallization structure 208 on the electronic chip 212 show a strong mechanical interlock or gripping with the band 210, resulting in undesirable high pick-up forces. Due to the excessive forces acting on the tiny electronic chip 212 during pick-up, the electronic chip 212 is prone to breakage.

[0093] Figures 6 to 11 Different structures obtained during the process of separating and picking up electronic chip 100 from wafer 102 according to an exemplary embodiment and other methods described for comparative purposes are shown. Figures 6 to 11 In each of these, a manufacturing architecture according to an exemplary embodiment is shown on the left-hand side. This manufacturing process is similar to that referenced above. Figures 1 to 4 Similar to the description. For comparative purposes, reference numeral 220 is used to show the case where no trenches are formed in wafer 214.

[0094] Figure 6 It shows the relationship with Figure 1 Similar thinning on the back side of the wafer. For example... Figure 6 As shown, the chip 102 has a front metallization structure 198 on the front side 114.

[0095] refer to Figure 7 A resist layer is attached to the back side 106 and patterned to form a patterned mask 118 on the left side. (Still referencing...) Figure 7 On the left-hand side, dopant 128 is implanted into the exposed surface portions of wafer 102 that are not covered by the patterned mask 118. Subsequently, the photoresist that forms the patterned mask 118 is removed. Therefore, processes including back-side lithography, back-side implantation (e.g., using boron dopant), and resist stripping can be performed.

[0096] In order to obtain Figure 8The structure shown on the left-hand side performs a stress-relief wet etching process on the back side 106, while shallow pits or trenches 104, 130 are selectively formed in the implantation region due to the higher etching rate in the region corresponding to the dopant 128 compared to the undoped semiconductor material of wafer 102. Subsequently, a back-side metallization structure 108 is formed by metal deposition (e.g., made of AuSn).

[0097] On the right-hand side, indicated by reference numeral 220, a conformal back-side metallization structure 208 is formed.

[0098] refer to Figure 9 On the left, the electronic chip 100 is separated from the wafer 102 by mechanical cutting using a mechanical blade 134 (or knife). More specifically, the electronic chip 100 is separated from the wafer 102 by guiding the mechanical blade 134 through the entire wafer 102, through the entire adhesive layer 110 of the tape 112, and partially into the foil 136 of the tape 112 located below the adhesive layer 110. Complete separation of the electronic chip 100 is ensured by advancing it into the foil 136 of the tape 112.

[0099] Preferably, during the formation of the separation path 116 that separates the respective electronic chip 100 from the wafer 102, at least a portion of each of the trenches 104, 130 is filled with adhesive of the adhesive layer 110 of the tape 112 above a baseline level 155, which can be defined as the horizontal height corresponding to the interface between the back-side metallization structure 108 outside the trenches 104, 130 and the wafer 102. Advantageously, the separation of the electronic chip 100 is performed such that the adhesive layer 110 fills the entire trenches 104, 130 during separation. Therefore, according to Figure 9 The tape 112 is mounted on the back side 106 to completely fill the pits or trenches 104, 130 with the adhesive material (e.g., adhesive compound) of the adhesive layer 110. The support carrier 150 can then be removed. Further, the wafer 102 is then individualized by cutting (e.g., mechanically or laser-cut) into individual electronic chips 100 along the separation path 116.

[0100] exist Figure 9 The corresponding process is performed on the right-hand side, comparing with reference numeral 220 in the attached figure. However, grooves 104 and 130 do not exist.

[0101] like Figure 10 As shown, the mechanical blade 134 can then be removed.

[0102] refer to Figure 10 and Figure 11On the left side, during the pick-up process, the individualized die-type electronic chip 100 can be lifted using the separation pin 120. Advantageously, edge clamping does not occur due to the upwardly curved lateral ends of the back metallization structure 108 of the corresponding chip 100. Complete release of the electronic chip 100 from the tape 112 can be achieved with low pick-up force. Since the adhesive material of the adhesive layer 110 of the tape 112 also fills the trenches 104, 130 above the baseline level 155 of the back metallization structure 108 (see also reference numeral 182) during individualization, the adhesive supports the back metallization structure 108 to prevent cracking, thereby ensuring the mechanical integrity of the separated electronic chip 100.

[0103] like Figure 10 and Figure 11 As shown on the right-hand side and referring to reference numeral 220, without additional dopant implantation 128 and without the formation of trenches 104, 130, the chip edge would be more difficult to release from the strip 210. The downward (rather than upward) curved burrs 204 of the back-side metallization structure 208 keep the chip edge firmly adhered to the strip 210, thereby creating an undesirable high pick-up force with a high risk of damaging the microelectronic chip 212.

[0104] Refer again Figure 11 On the left-hand side, the picking process is smooth and requires little force, as shown in the reference above. Figure 5 As stated above.

[0105] Refer again Figure 11 On the right side, without additional injection, electronic chip 212 will have difficulty being released from band 210.

[0106] Figure 12 Graph 184 shows experimental results relating pin distance to lifting force according to an exemplary embodiment and a conventional method. More specifically, pin or needle height (in micrometers) is plotted along the horizontal axis 186. Pickup force (in cN) is plotted along the vertical axis 188. Descriptively speaking, pushing to the right along the horizontal axis 186 corresponds to the rise of the disengaged pin or needle, which increases the force. First curve 190 relates to the conventional case with edge clamping. Second curve 192 relates to an exemplary embodiment where edge clamping of the disengaged electronic component 100 is not performed during pickup. Graph 184 was obtained by performing a pickup force measurement.

[0107] Comparing curves 190 and 192, curve 192 shows a smoother and gentler separation of the electronic chip edge from the strip. At position 194, the electronic chip 100 separates from the strip 112. As indicated by reference numeral 196, the pickup force of an exemplary embodiment is significantly less than the pickup force in the conventional method compared to curve 190. In the conventional method according to curve 190, the electronic chip separates from the strip in a discontinuous manner under high mechanical load, which may trigger undesirable oscillations or even breakage of the electronic chip. In contrast, this exemplary embodiment allows the electronic chip to be picked up from the strip with less force and in a more continuous manner.

[0108] Figure 13 A cross-sectional view of an electronic chip 100 manufactured according to an exemplary embodiment is shown. For example, the electronic chip 100 may be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) chip, an IGBT (Insulated Gate Bipolar Transistor) chip, and may have a monolithically integrated diode. During operation, the electronic chip 100 may be subjected to vertical current flow, such as… Figure 13 The figure is schematically indicated by reference numeral 180. The thickness L of the electronic chip 100 can be very small, for example, less than 60 μm.

[0109] The illustrated electronic chip 100 is configured as a semiconductor power chip and includes a semiconductor body 122, such as a piece of silicon. An active region 124 at the front side 114 of the semiconductor body 122 is processed using integrated circuit technology, such that components, such as field-effect transistors, are monolithically integrated into the active region 124 on the front side 114. Furthermore, a front-side metallization structure 198 is formed on the active region 124. Moreover, a back-side metallization structure 108 is formed on the back side 106 of the semiconductor body 122, opposite to the front side 114. When the electronic chip 100 experiences a vertical current flow between the front side 114 and the back side 106 during operation, the current flows between the front-side metallization structure 198 and the back-side metallization structure 108 along a direction according to reference numeral 180.

[0110] As a reference Figures 1 to 11 The manufacturing of one of the described embodiments is based on Figure 13 A unique feature of the manufacturing method of the electronic chip 100 is that a peripheral notch 126 is formed at a peripheral corner 138 of the semiconductor body 122 located between the back side 106 (i.e., the bottom main surface of the electronic chip 100) and the sidewall 123. The peripheral notch 126 corresponds to a portion of the front trenches 104, 130 formed to reduce the pick-up force of the electronic chip 102 from the wafer composite after individual dicing, as described above. Furthermore, a dopant 128 (e.g., implanted boron atoms) is selectively present in the region of the semiconductor body 122 adjacent to the peripheral notch 126.

[0111] Due to the selective etching process performed to create the corresponding trenches 104, 130, the peripheral notch 126 can be rounded at the back side 106. Furthermore, the peripheral notch 126 can be defined by a continuously curved surface portion of the semiconductor body 122, which is also a result of the previous creation of the corresponding trenches 104, 130. For example, the concentration of the dopant 128 is at least 10. 17 One atom per cm 3 Furthermore, the dopant concentration can be at least 1000 times that of natural impurities in the semiconductor body 122. Specifically, the dopant concentration along the entire periphery of the notch 126 at the back side 106 of the semiconductor body 122 can be significantly greater than the dopant concentration in the central portion of the back side 106 of the semiconductor body 122. The presence of dopant 128 is due to the fact that the corresponding trenches 104, 130 have been selectively etched in the semiconductor body 122 at an etch rate significantly increased compared to undoped semiconductor material.

[0112] Figures 14 to 16 Different structures obtained during the execution of a method for separating and picking up an electronic chip 100 from a wafer 102 are shown according to an exemplary embodiment.

[0113] refer to Figure 14 The figure shows a cross-section through the edge of a cut channel on the back side of the chip. More specifically, reference numeral 197 shows dopant 128 implanted via a four-mode implantation process. This angled implantation of dopant 128 yields the doping profile shown. Figure 14 The cutting channel is indicated by reference numeral 195 in the attached figure.

[0114] Figure 15 An etch profile 175 obtained by wet etching the back side 106 of the semiconductor body 122 is shown. Thus, the final back side geometry after wet etching is shown. For example, when using HNA as the wet etchant, this geometry can be obtained because the etching rate in doped silicon is higher than that in undoped silicon.

[0115] Figure 16 The altered geometry is shown when the semiconductor body 122 is cut using a cutting blade 134 in a cutting channel. As indicated by reference numeral 191, a certain implantation dose or dopant 128 is retained at the peripheral notch 126 in the electronic chip 100 to be manufactured. Referring to reference numeral 189, the characteristic shape of the wet edge surface is shown.

[0116] Figure 17 A top view of the bottom side of an electronic chip 100 manufactured according to an exemplary embodiment is shown.

[0117] like Figure 17As shown, the dopant concentration along the entire perimeter of the notch 126 at the back side 106 of the semiconductor body 122 is greater than the dopant concentration in the central portion of the back side 106 of the semiconductor body 122. More specifically, the dimension "H" along which the dopant 128 extends into the semiconductor body 122 at each corner of the electronic chip 100 is greater than the dimension "h" along which the dopant 128 extends into the semiconductor body 122 at each edge of the electronic chip 100. As shown, the dopant 128 is only present in the peripheral region of the semiconductor body 122 adjacent to the peripheral notch 126. In particular, the dopant 128 extends deeper (i.e., the dimension "H") into the interior of the semiconductor body 122 at the corner 125 than at the edge 127 of the semiconductor body 122 (corresponding to the dimension "h", where h < H) at the back side 106. This is Figure 17 the result of the implantation geometry shown by reference numeral 185 in. Thus, in a four-mode implantation process, the corners are rounded due to the higher implantation dose at the chip corners.

[0118] It should be noted that the term "comprising" does not exclude other elements or features, and the singular form "a" does not exclude a plurality. Elements described in connection with different embodiments can also be combined. It should also be noted that reference numerals should not be construed as limiting the scope of the claims. In addition, the scope of the present application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope.

Claims

1. A method for separating an electronic chip (100) from a wafer (102), wherein, The method includes: • Two spaced trenches (104, 130) are formed in the back side (106) of the wafer (102) around at least a portion of the electronic chip (100) to be separated. • A back-side metallization structure (108) is formed covering at least a portion of the back side (106) and at least a portion of the two spaced-apart trenches (104, 130). • Attach the adhesive layer (110) of the strip (112) to at least a portion of the back-side metallized structure (108); and • The electronic chip (100) is separated by removing material from the front side (114) of the wafer (102) along a separation path (116) that includes a portion of each of the two spaced trenches (104, 130), such that: during separation, the adhesive layer (110) fills at least a portion of the two spaced trenches (104, 130) on the back side (106) and fills above the height level of the back metallization structure (108) to support the back metallization structure along the separation path during separation of the electronic chip.

2. The method according to claim 1, wherein, The method includes forming two spaced-apart trenches (104, 130) that are parallel to each other and / or around a common center.

3. The method according to claim 1 or 2, wherein, The method includes separating the electronic chip (100) along a separation path (116) extending between the two spaced-apart trenches (104, 130).

4. The method according to claim 1 or 2, wherein, The method includes forming two spaced-apart trenches (104, 130) that are circumferentially closed around the entire electronic chip (100) to be separated.

5. The method according to claim 1 or 2, wherein, The method includes forming the two spaced trenches (104, 130) having a depth (d) less than or equal to the thickness (D) of the adhesive layer (110).

6. The method according to claim 1 or 2, wherein, The method includes forming the two spaced trenches (104, 130) having a depth (d) of no more than 10 μm.

7. The method according to claim 6, wherein, The two spaced trenches (104, 130) are formed with a depth (d) in the range of 3 μm to 10 μm.

8. The method according to any one of claims 1 to 2 and 7, wherein, The method includes forming each of the two spaced-apart trenches (104, 130) having a width (W) smaller than that of the separation path (116).

9. The method according to any one of claims 1 to 2 and 7, wherein, The method includes separating the electronic chip (100) by one of the groups consisting of cutting with a mechanical blade (134) and laser processing.

10. The method according to claim 9, wherein, The method includes separating the electronic chip (100) by guiding the mechanical blade (134) through the entire wafer (102), through the entire adhesive layer (110), and into the foil (136) of the strip (112) located below the adhesive layer (110).

11. The method according to any one of claims 1 to 2, 7, and 10, wherein, The method includes separating the electronic chip (100) in such a way that the adhesive layer (110) completely fills the two spaced trenches (104, 130) during separation.

12. The method according to any one of claims 1 to 2, 7, and 10, wherein, The method includes forming the two spaced trenches (104, 130) by covering the back side (106) of the wafer (102) with a patterned mask (118), by doping the wafer (102) through the patterned mask (118), and by etching the wafer (102) after removing the patterned mask (118).

13. The method according to any one of claims 1 to 2, 7, and 10, wherein, The method includes forming the two spaced trenches (104, 130) by covering the back side (106) of the wafer (102) with a patterned mask (118) and by etching the wafer (102) through the patterned mask (118).

14. The method according to any one of claims 1 to 2, 7, and 10, wherein, The method includes picking up the separated electronic chip (100) from the strip (112) after the separation.

15. The method according to claim 14, wherein, Picking up the separated electronic chip (100) includes lifting the electronic chip (100) from the belt (112) by applying a lifting force to the back side (106) of the electronic chip (100).

16. The method of claim 14, wherein, Picking up the separated electronic chip (100) includes: adsorbing the raised electronic chip (100) at the front side (114) of the electronic chip (100).

17. The method according to claim 15, wherein, Picking up the separated electronic chip (100) includes: adsorbing the raised electronic chip (100) at the front side (114) of the electronic chip (100).

18. The method according to any one of claims 1 to 2, 7, 10, 16 to 17, wherein, The electronic chip (100) has a thickness (L) of less than 100 μm.

19. The method according to claim 18, wherein, The electronic chip (100) has a thickness (L) of less than 60 μm.

20. The method according to any one of claims 1 to 2, 7, 10, 16 to 17, and 19, wherein, The electronic chip (100) is configured to withstand vertical current flow between the front side (114) and the back side (106) during operation.

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