Electrostatic discharge (ESD) protection circuit

Abstract

The application provides an ESD protection circuit and a multi-power integrated circuit, and relates to the technical field of integrated circuits. The ESD protection circuit comprises a first port and a second port, the first port is coupled with a contact pad, and the second port is coupled with a power supply; a plurality of parallel ESD devices, each of which comprises a first sub-port and a second sub-port; all the first sub-ports are coupled with the first port; all the second sub-ports are coupled with the second port; each of the ESD devices comprises a resistor and an OTS element, and the resistor and the OTS element are connected in series; and the ESD protection circuit provides ESD protection for the contact pad. The ESD protection circuit and the multi-power integrated circuit provided by the application have the advantages of reducing the area of the ESD protection circuit and reducing the cost.

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of integrated circuits, and more particularly, to ESD protection circuits and multi-power integrated circuits. BACKGROUND

[0002] Electrostatic discharge (ESD) poses a great challenge to the reliability of integrated circuits. Figure 1 An integrated circuit 00 is disclosed to protect a protected circuit 20 from ESD. A contact pad 10 is coupled to the protected circuit 20. Since the contact pad 10 can cause ESD, an ESD protection circuit 100 is needed between the contact pad 10 and a power source (e.g., ground GND) 0. The ESD protection circuit 100 is coupled to the contact pad 10 through a first port 140 and to the power source 0 through a second port 150.

[0003] In integrated circuits, conventional ESD protection circuits 100 include diodes (e.g., Zener diodes) and SCRs (silicon controlled rectifiers, or thyristors), which are compatible with the protected circuit 20 in process and do not require extra process steps. However, diodes and SCRs have limited conduction capability, with a maximum on-current density of 10 4 -10 5 A / cm 2 During an ESD event, the ESD protection circuit 100 of a single contact pad 10 needs to sink at least 1 A of ESD current (I ESD ). To sink such a large I ESD , the conventional ESD protection circuit 100 requires a silicon area of 1,000-10,000 square microns. This poses two problems: 1) the large ESD area results in extra chip area (e.g., a large SoC, CPU, or FPGA chip contains hundreds of contact pads, and all their ESD protection circuits occupy up to ~20% of the chip area); and 2) the large ESD area results in large parasitic capacitance, which is not friendly to high-speed integrated circuits.

[0004] Ovonic threshold switch (OTS) elements can be used as ESD protection circuits. Figure 2 An ESD protection circuit 100 based on OTS elements is disclosed. It contains an upper electrode 110, a lower electrode 120, and an OTS film 130 between the upper electrode 110 and the lower electrode 120. The OTS film 130 contains OTS material with a thickness of T and a size of D*. Figure 1The lower electrode 120 is coupled to the contact pad 10, and the lower electrode 120 is coupled to the second port 150. Figure 1 (Coupled with power supply 0).

[0005] Figure 3 This indicates the electrical (IV) characteristics of an OTS element, which has an OFF (high impedance) state and an ON (low impedance) state: during forward scan (1->2), when the applied voltage V is greater than the threshold voltage V0. th When the OTS element switches from the OFF state to the ON state, the conduction current (I) increases. ON ) flows through; during reverse scanning (3->4), when the applied voltage V is less than the holding voltage V hold (or current I is less than holding current I) hold When the ON state is reached, the OTS element transitions from the ON state to the OFF state. The conduction current density (J / L) of the OTS element... ON J is defined as: ON =I ON / A OTS , where A OTS S represents the area of ​​the OTS element; its selectivity is defined as: S = I ON / I OFF , among which, I OFF For V = V th Leakage current at / 2. Figure 4 (Table 1) Comparison of performance parameters of various OTS materials. OTS materials generally contain chalcogen elements, such as Te, Se, S (in which case the OTS material is a sulfide) and O (in which case the OTS material is an oxide), etc. ON It can reach or exceed 1MA / cm 2 The selectivity can reach or exceed 10 5 Therefore, ESD protection circuits using OTS components can reduce the ESD area by 10-100 times. Furthermore, since OTS components do not occupy silicon area, this will further reduce the chip area.

[0006] US Patent 7,764,477 B2 (inventors: Tang et al., granted July 27, 2010, abbreviated as 447 patent) discloses an ESD protection circuit based on OTS components. It contains a few (e.g., four, see 447 patent) components. Figure 1 OTS components, which are not connected in parallel, each OTS component needs to discharge almost all of its I. ESD Patent 447 failed to recognize that the ON state of an OTS element exhibits a nonlinear area effect, i.e., I... ON It is not directly proportional to the device area (see this specification). Figure 5(and its explanation). Large-area OTS components are difficult to discharge I. ESD An ESD event will cause the OTS component to fail.

[0007] For high power supply voltage (power supply voltage V) S Greater than V th V S >V th ESD protection for OTS components can be achieved by connecting several OTS components in series. For example, when V... S =1.8V, can 3V th =0.6V OTS elements connected in series. US Patent 10,388,561B2 (inventor: Hong, grant date: August 20, 2019, abbreviated as 561 patent) discloses an ESD protection circuit based on series-connected OTS elements, which adopts a vertical series connection: three series-connected OTS elements 121, 122, 123 are stacked in a direction perpendicular to the chip and are located on different surfaces (in 561 patent). Figure 4 Because these three OTS components 121, 122, and 123 need to be manufactured in three separate process steps, this results in increased process costs.

[0008] Neither Patent 447 nor Patent 561 takes into account that actual integrated circuits typically use multiple power supplies (such as 3.3V, 1.8V, and 1.2V), and these integrated circuits are called multi-power supply integrated circuits. In multi-power supply integrated circuits, existing technologies use different ESD protection circuits for different power supply voltages, which increases manufacturing costs. Summary of the Invention

[0009] The main objective of this invention is to reduce the area of ​​ESD protection circuits.

[0010] Another objective of this invention is to reduce the increase in chip area caused by ESD protection.

[0011] Another objective of this invention is to reduce the additional parasitic capacitance introduced by ESD protection.

[0012] Another objective of this invention is to prevent ESD protection circuits from thermal breakdown.

[0013] Another objective of this invention is to reduce the nonlinear area effect of the ON state of the OTS element.

[0014] Another objective of this invention is to reduce the manufacturing cost of high power supply voltage ESD protection circuits.

[0015] Another objective of this invention is to provide ESD protection for multi-power integrated circuits.

[0016] Another objective of this invention is to reduce the cost of ESD protection for multi-power integrated circuits.

[0017] OTS elements exhibit a non-linear area effect in the ON state. As shown in Figure 5 , two OTS elements with different areas A1(30 nm x 30 nm) and A2(100 nm x 100 nm) have a current I OFF proportional to A OTS in the OFF state; but in the ON state, I on is not proportional to A OTS . This is because in the OFF state, the OTS element is area conduction; but in the ON state, the OTS element is local conduction, not area conduction. When switching from the OFF state to the ON state, not all OTS material on the entire surface of the OTS element (meaning the entire contact surface of the OTS film with the upper electrode or the lower electrode) is converted to a low resistance state, but only the OTS material near one (or a few) points is converted to a low resistance state. These points are conductive filaments, i.e. conductive filaments. Therefore, if the ESD protection circuit contains only one (or a few) independent OTS elements with a large area (with a size of ten microns or more), although each OTS element has a large area on the surface, in fact, during an ESD event, only a few conductive filaments can be formed in each OTS element or even no conductive filaments can be formed (the number of conductive filaments is not proportional to A OTS , and each conductive filament needs to conduct a large I ESD , which will cause the OTS material near the conductive filament to be thermally run away.

[0018] In order to avoid thermal runaway, the ESD protection circuit preferably contains a large number of small-area (with a size of ten nanometers to microns) OTS elements in parallel. During an ESD event, I ESD is dispersed into each OTS element. Since the current flowing through each OTS element is small, thermal runaway does not occur. Considering that the threshold voltage V th of the OTS element has a certain distribution, as shown in Figure 6 , the average value of V th of all OTS elements is V th,0 , and the mean square deviation is V delta (for example, V delta ~ 0.1 V). During an ESD event, in order to activate all OTS elements (i.e. to ensure that each OTS element is turned on), it is necessary to connect each OTS element in series with a resistance, so that the resistance generates a voltage drop V delta greater than V R during an ESD event. Specifically, VR = kV delta where k > 1, and k is preferably greater than 2. Thus, even in the worst case, the voltage experienced by each OTS element will be greater than its V th , so that all OTS elements are activated and conduct ESD current. Since each OTS element is assigned a small portion of the ESD current, the OTS material will not be thermally damaged.

[0019] Accordingly, the present application provides a parallel ESD protection circuit, comprising a first port coupled to a contact pad, and a second port coupled to a power supply; a plurality of parallel ESD devices, each of the ESD devices comprising a first sub-port and a second sub-port; all of the first sub-ports coupled to the first port; all of the second sub-ports coupled to the second port; each of the ESD devices comprising a resistor and an OTS element, the resistor and the OTS element connected in series; the ESD protection circuit providing ESD protection for the contact pad.

[0020] In designing the ESD protection circuit, to increase the number of ESD devices, the size D of the OTS element 300i is typically less than 10 microns, and preferably less than 1 micron, such as 0.2 microns or 60 nanometers. During an ESD event, a voltage drop V delta > V R (V R > V delta , and preferably V R > 2V delta . As an example, an OTS element with a size D of 60 nanometers can conduct 5 mA of current, and to generate a voltage drop of V R > 2V delta = 0.2V, the series resistor 200i preferably has a resistance greater than 40 Ohms. Typically, the series resistor 200i preferably has a resistance greater than 10 Ohms. In addition, to save chip area, the series resistor 200i is preferably formed in a resistive via 210. The resistive via 210 typically has a resistivity greater than 10 micro-Ohm*cm (1E-7 Ohm*m), and preferably greater than 100 micro-Ohm*cm (1E-6 Ohm*m). In a preferred embodiment, the resistive via 210 has a resistivity greater than 1000 micro-Ohm*cm (1E-5 Ohm*m).

[0021] For ESD protection circuits with high supply voltages (V S > V th ), a plurality of OTS elements can be connected in series. For example, when V S = 1.8V, three OTS elements with Vth 561 patent uses vertical series connection, and different series OTS elements are made in different process steps, which needs several additional processes and increases the process cost. In order to overcome the above difficulties, the ESD protection circuit preferably uses horizontal series connection: all series OTS elements are located on the same plane and are manufactured at the same time, and the OTS elements are connected in series through interconnection lines and via holes.

[0022] Correspondingly, the present application provides a series type ESD protection circuit, which comprises a first port and a second port, the first port is coupled with a contact pad, and the second port is coupled with a power supply; a first ESD device and a second ESD device connected in series, the first ESD device comprises a first sub-port and a second sub-port, and the second ESD device comprises a third sub-port and a fourth sub-port; the first port is coupled with the first sub-port, the second sub-port is coupled with the third sub-port, and the fourth sub-port is coupled with the second port; the first ESD device comprises a first OTS element, and the second ESD device comprises a second OTS element, and the first and second OTS elements are located on the same plane; the ESD protection circuit provides ESD protection for the contact pad.

[0023] The series type ESD protection circuit is particularly suitable for multi-power supply integrated circuits. Correspondingly, the present application provides a multi-power supply integrated circuit with at least two power supply voltages, which comprises a first ESD protection circuit for providing ESD protection for a first power supply voltage and comprising m ESD devices connected in series; a second ESD protection circuit for providing ESD protection for a second power supply voltage and comprising n ESD devices connected in series; m and n are both positive integers greater than 1 but different in value; at least one ESD device in the first ESD protection circuit has the same structure as at least one ESD device in the second ESD protection circuit.

[0024] In practical applications, in order to achieve the purposes of avoiding thermal breakdown and providing ESD protection for high-voltage power supply at the same time, it is necessary to combine the parallel type and series type ESD protection circuits. Correspondingly, the present application provides a series-parallel type ESD protection circuit, which comprises a first ESD group, the first ESD group comprises a plurality of ESD devices connected in series; a second ESD group, the second ESD group comprises a plurality of ESD devices connected in series; the first and second ESD groups are connected in parallel; each of the ESD devices comprises an OTS element.

[0025] In addition, the present application also provides a series-parallel type ESD protection circuit, which comprises a third ESD group, the third ESD group comprises a plurality of ESD devices connected in parallel; a fourth ESD group, the fourth ESD group comprises a plurality of ESD devices connected in parallel; the third and fourth ESD groups are connected in series; each of the ESD devices comprises an OTS element. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 An integrated circuit with ESD protection circuit.

[0027] Figure 2 A cross-sectional view of an ESD protection circuit based on OTS device (prior art).

[0028] Figure 3 Electrical (I-V) characteristics of a typical OTS device.

[0029] Figure 4 Performance parameters of various OTS materials (Table 1).

[0030] Figure 5 Electrical characteristics of OTS devices with two different areas (30 nm x 30 nm and 100 nm x 100 nm).

[0031] Figure 6 Cumulative distribution function of V th of all OTS devices on a wafer.

[0032] Figure 7A A circuit diagram of a parallel-type ESD protection circuit. Figure 7B A circuit diagram of its ESD device.

[0033] Figures 8A-8C Cross-sectional views of three parallel-type ESD protection circuits of the first kind.

[0034] Figures 9A-9B Cross-sectional views of two parallel-type ESD protection circuits of the second kind.

[0035] Figure 10 A circuit diagram of a series-type ESD protection circuit.

[0036] Figures 11A-11B Cross-sectional views of two series-type ESD protection circuits.

[0037] Figure 12 A circuit diagram of a multi-power integrated circuit.

[0038] Figure 13 A circuit diagram of a series-type ESD protection circuit used in a multi-power integrated circuit.

[0039] Figure 14 Cross-sectional views of the series-type ESD protection circuit in Figure 13

[0040] Figure 15 ​This is a circuit diagram of a series-parallel ESD protection circuit.

[0041] Figure 16 This is a circuit diagram of a parallel-series ESD protection circuit.

[0042] Note that these figures are schematic diagrams only and are not drawn to scale. For clarity and convenience, some dimensions and structures in the figures may have been enlarged or reduced. In different embodiments, the same symbols generally represent corresponding or similar structures. " / " indicates an "and" or "or" relationship.

[0043] The ESD protection circuit 100 in this invention can be integrated into the protected integrated circuit chip or used as a separate component (i.e., separate from the protected integrated circuit chip). Figures 8A-9B The substrate 0X is shown in the figure. If the ESD protection circuit 100 is integrated into the chip, then substrate 0X is the chip substrate; if the ESD protection circuit 100 is a discrete component, then substrate 0X is the substrate of the ESD protection circuit 100 itself. For simplicity, the substrate is not shown in other figures. In this specification, the positional relationship between "above" and "below" is relative to the substrate. Detailed Implementation

[0044] This invention proposes a parallel ESD protection circuit. The OTS element exhibits a nonlinear area effect when in the ON state. For example... Figure 5 As shown, two OTS devices with different areas, A1 (30nm × 30nm) and A2 (100nm × 100nm), have I in the OFF state. OFF With A OTS It is directly proportional; however, in the ON state, I on With A OTS However, this is not directly proportional. This is because in the OFF state, the OTS element is area conduction; while in the ON state, the OTS element is local conduction (or point conduction), not area conduction. When transitioning from the OFF state to the ON state, not all the OTS material on the entire surface of the OTS element (referring to the entire contact surface between the OTS film and the upper or lower electrode) transitions to a low-resistance state, but only the OTS material near one (or a few) points transitions to a low-resistance state. These points are conductive filaments. Therefore, if the ESD protection circuit contains only one (or a few) independent, large-area (tens of micrometers or larger) OTS element, although each OTS element appears to have a large area, in reality, during an ESD event, only a few conductive filaments can be formed in each OTS element, or even none can be formed (the number of conductive filaments is related to A). OTS(Not directly proportional), then each conductive filament needs to conduct a very large I. ESD This can cause thermal runaway of the OTS material near the conductive filament.

[0045] To avoid thermal breakdown, ESD protection circuits should ideally contain a large number of parallel, small-area (tens of nanometers to micrometers) OTS components. During an ESD event, I... ESD The current is distributed across individual OTS components. Since the current flowing through each OTS component is small, thermal breakdown will not occur. This is considering the threshold voltage V of the OTS component. th It has a certain distribution. For example... Figure 6 As shown, all OTS components V th The average value is V th,0 The mean squared error is V delta (For example, V) delta ~0.1V). During an ESD event, to activate all OTS components (i.e., ensure each OTS component is conducting), it is necessary to connect each OTS component in series with a resistor, so that this resistor generates a voltage greater than V during the ESD event. delta voltage drop V R Specifically, V R =kV delta Where k>1, and k is preferably greater than 2. Therefore, even in the worst-case scenario, the voltage across each OTS element will be greater than its V. th This activates all OTS elements and conducts ESD current. Because the ESD current allocated to each OTS element is small, the OTS material will not be thermally broken down.

[0046] When designing ESD protection circuits, to increase the number of ESD devices, the size D of the OTS element 300i is generally less than 10 micrometers, and preferably less than 1 micrometer, such as 0.2 micrometers or 60 nanometers. During an ESD event, a voltage greater than V needs to be generated across the series resistor 200i. delta voltage drop V R (V R >V delta V is the best R >2V delta As an example, an OTS device with a size D of 60 nanometers can conduct a current of 5mA in order to generate V. R >2V deltaThe voltage drop across the series resistor 200i is preferably greater than 0.2V. In general, the series resistor 200i has a resistance greater than 10 Ohm. In addition, to save chip area, the series resistor 200i is preferably formed in a resistive via 210. The resistive via 210 has a resistivity greater than 10 micro-Ohm*cm (1E-7 Ohm*m) and preferably greater than 100 micro-Ohm*cm (1E-6 Ohm*m). In a preferred embodiment, the resistive via 210 has a resistivity greater than 1000 micro-Ohm*cm (1E-5 Ohm*m).

[0047] Figure 7A and Figure 7B Fig. 1 shows a parallel type ESD protection circuit 100 and its ESD device 100i. The ESD protection circuit 100 is coupled to a contact pad 10 and a power supply 0, and contains a plurality of parallel ESD devices 100a, 100b,... 100i,... 100z. Figure 7A ) Each ESD device 100i contains a first sub-port 140i and a second sub-port 150i. Figure 7B ) The first sub-ports 140a, 140b,... 140i,... 140z of the ESD devices 100a, 100b,... 100i,... 100z are coupled to a first port 140 of the ESD protection circuit 100, and the second sub-ports 150a, 150b,... 150i,... 150z are coupled to a second port 150 of the ESD protection circuit 100. Figure 7A ) To activate all the OTS elements and prevent thermal breakdown during an ESD event, the ESD device 100i contains a resistor 200i and an OTS element 300i. Figure 7B ) The resistor 200i is connected in series with the OTS element 300i. Thus, the resistor 200i is also called a series resistor 200i. During an ESD event, the voltage drop across each ESD device 100i is the same, and the same current flows through the series resistor 200i and the OTS element 300i in each ESD device 100i. A voltage drop (V delta ) greater than the mean square deviation (V R ) is generated across the series resistor 200i.

[0048] Figures 8A-8C Fig. 2 shows three parallel type ESD protection circuits 100 of the first type, which correspond to Figure 7A and Figure 7BIn the first-class ESD protection circuit 100, the series resistor 200i is located above the OTS element 300i. The OTS element 300i includes an upper electrode 310, a lower electrode 320, and an OTS thin film 330 between the upper electrode 310 and the lower electrode 320. The size of the OTS element 300i is D. To avoid nonlinear area effects in the ON state, it is best to use a small-area OTS element 300i. Specifically, D is less than 10 micrometers, preferably less than 1 micrometer, for example, 0.2 micrometers or 60 nanometers. In other words, D is in the tens of nanometers to the micrometers range.

[0049] An interlayer dielectric 180 is present between the upper electrode 310 and the contact pad 10. Multiple resistive vias 210 are formed within the interlayer dielectric 180, and a series resistor 200i is formed within each resistive via 210, filled with a conductive material. The resistive via 210 has a dimension of d and a height of t. This is to generate a sufficiently large voltage drop (V) in the resistive via 210 during an ESD event. R >V delta V is the best R >2V delta The resistance channel 210 needs to be filled with a conductive (high-resistivity) material with a high resistivity, generally greater than 10 micro-Ohm*cm (i.e., 1E-7 Ohm*m), and preferably greater than 100 micro-Ohm*cm (i.e., 1E-6 Ohm*m). As an example, high-resistivity materials can be titanium nitride (TiN, with a resistivity of 150 micro-Ohm*cm). To further increase the resistivity, small amounts of oxygen and / or nitrogen can be injected into the metallic material.

[0050] exist Figure 8A In this embodiment, the OTS film 330 is also etched after the step of etching the upper electrode 310, and this etching step stops at the upper surface of the lower electrode 320. Figure 8B In this embodiment, the etching step of the upper electrode 310 stops at the upper surface of the OTS thin film 330. Figure 8C In this embodiment, the OTS element 330i does not have a separate upper electrode 310; the resistor channel hole 210 is in direct contact with the OTS film 330, forming the OTS element 300i. In this case, the size D of the OTS element 300i is equal to the diameter d of the resistor channel hole 210.

[0051] Figures 9A-9B This illustrates two types of parallel ESD protection circuits 100 of the second type. In this second-type ESD protection circuit 100, a series resistor 200i is located below the OTS element 300i. Specifically, the series resistor 200i is formed in a resistor channel hole 210, which is then planarized, and the OTS element 300i is formed on top of it. Figure 9AIn one embodiment, the OTS material 330 is formed directly on the resistor channel hole 210. Figure 9B In one embodiment, the complete OTS element 300i (including the upper electrode 310, the lower electrode 320, and the OTS thin film 330) is formed on the resistor channel hole 210.

[0052] For high power supply voltage (V) S >V th The ESD protection circuit of a device can connect several OTS components in series. For example, when V... S =1.8V, can 3V th =0.6V OTS elements are connected in series. Patent 561 uses vertical series connection, with different series-connected OTS elements manufactured in different process steps, which requires several additional processes and increases process costs. To overcome the above difficulties, this invention proposes a series-connected ESD protection circuit 100, which uses horizontal series connection: the ESD protection circuit 100 contains multiple series-connected ESD devices 100A, 100B, 100C..., and these ESD devices 100A, 100B, 100C... contain OTS elements 300A, 300B, 300C..., all of which are located on the same plane 500 and manufactured simultaneously.

[0053] like Figure 10 As shown, contact pad 10 is connected to the first port 140 of ESD protection circuit 100; the first sub-port 140A of ESD device 100A is connected to the first port 140 of ESD protection circuit 100; the second sub-port 150A of ESD device 100A is connected to the first sub-port 140B of ESD device 100B; the second sub-port 150B of ESD device 100B is connected to the first sub-port 140C of ESD device 100C; the second sub-port 150C of ESD device 100C is connected to the second port 150 of ESD protection circuit 100; and the second port 150 of ESD protection circuit 100 is connected to power supply 0. During an ESD event, all these ESD devices 100A, 100B, 100C… flow with the same current.

[0054] The specific structure of the series-type ESD protection circuit 100 is as follows: Figure 11A and Figure 11B As shown. In Figure 11AIn this design, ESD devices 100A, 100B, and 100C are all located on the same plane 500 and fabricated simultaneously. These ESD devices 100A, 100B, and 100C contain OTS elements 300A, 300B, and 300C. Each OTS element (e.g., 300A) contains an upper electrode 310, an OTS film 330, and a lower electrode 320. The OTS films 330 in different OTS elements have the same thickness and are formed in the same process step. Each ESD device (e.g., 100A) may also contain a series resistor (e.g., 200A), each series resistor being formed in a resistor via 210. Adjacent ESD devices 100A and 100B are connected in lateral series via via 220 and interconnects 230. Here, via 220 may contain a high-resistivity material (similar to resistor via 210) or a low-resistivity material (similar to conventional vias).

[0055] Because it contains a standard channel hole 220, Figure 11A The ESD protection circuit 100 in the circuit has a large area. To further reduce its area, Figure 11B The embodiments described herein avoid using conventional vias 220 as much as possible. In this embodiment, ESD device 100A is directly connected to the lower electrode 320B of ESD device 100B via its lower electrode 320A. Thus, the lower electrode 320A of ESD device 100A and the lower electrode 320B of ESD device 100B form a shared electrode (lateral interconnect) 320. Similarly, the interconnect 230B of ESD device 100B and the interconnect 230C of ESD device 100C are also directly connected, forming a shared interconnect (lateral interconnect). Note that in Figure 11A In the embodiments described, the current direction is consistent in all ESD devices 100A, 100B, and 100C; Figure 11B In the embodiments, the current direction is opposite in ESD devices 100A and 100B.

[0056] Series-type ESD protection circuits are particularly suitable for multi-power integrated circuits (00M). For example... Figure 12 As shown, the multi-power supply integrated circuit 00M has multiple V... S Among them, with V S =1.8V related first signal is coupled to contact pad 10 and protected by first ESD protection circuit 100; with V S A second signal related to 1.2V is coupled to contact pad 10' and protected by the second ESD protection circuit 100'. For different V values... S V S The existing technology for ESD protection circuits typically uses OTS films of varying thicknesses, which requires multiple OTS film processing steps, resulting in high processing costs.

[0057] Lateral cascading helps reduce the ESD protection cost of multi-power integrated circuits (00M). For multi-power integrated circuits (00M), different numbers of laterally cascaded OTS components can be used to achieve protection against different voltage levels. S ESD protection. For example... Figure 13 As shown, for V S =1.8V, can be achieved by using 3 horizontally connected series, V th =0.6V ESD devices 100A, 100B, and 100C are used to provide ESD protection; for V S =1.2V, two transversely connected V th ESD protection is provided by 0.6V ESD devices 100A' and 100B'. These ESD devices 100A, 100B, 100C; 100A' and 100B' all have the same structure.

[0058] The specific structure of the ESD protection circuit is as follows: Figure 14 As shown. ESD devices 100A, 100B, and 100C in ESD protection circuit 100 and 100A' and 100B' in ESD protection circuit 100' are all located on the same plane 500 and fabricated simultaneously. These ESD devices contain OTS elements 300A, 300B, 300C, and 300A' and 300B', with the OTS films 330 of different OTS elements having the same thickness, and they are formed in the same process step. Each ESD device (e.g., 100A) preferably also contains a series resistor (e.g., 200A). Adjacent ESD devices (e.g., 100A and 100B) are connected in lateral series via vias 220 and interconnects 230. In other optimized embodiments, at least one ESD device (e.g., 100A) in ESD protection circuit 100 has the same structure as at least one ESD device (e.g., 100A') in ESD protection circuit 100'.

[0059] In practical applications, in order to simultaneously prevent thermal breakdown and provide ESD protection for high-voltage power supplies, it is necessary to use parallel-connected ( Figures 7A-9B ) and series type ( Figures 10-14 The ESD protection circuits are combined. Accordingly, this invention proposes a series-parallel ESD protection circuit and a parallel-series ESD protection circuit. Figure 15 This represents a series-parallel ESD protection circuit 100, which includes a first ESD group 100a* and a second ESD group 100b* connected in parallel: the first ESD group 100a* contains multiple ESD devices 100aA, 100aB, and 100aC connected in series; the second ESD group 100b* contains multiple ESD devices 100bA, 100bB, and 100bC connected in series. Figure 16A series-parallel ESD protection circuit 100 is shown, which includes a third ESD group 100A* and a fourth ESD group 100B* connected in series. The third ESD group 100A* includes a plurality of ESD devices 100aA, 100bA... 100iA... 100zA connected in parallel. The fourth ESD group 100B* includes a plurality of ESD devices 100aB, 100bB... 100iB... 100zB connected in parallel. In Figure 15 and Figure 16 Each of the ESD devices includes an OTS element 300i and preferably a series resistor 200i.

[0060] In summary, to overcome the ON-state nonlinear area effect of OTS devices and to avoid thermal breakdown, a parallel ESD protection circuit includes a plurality of small area OTS devices connected in parallel. To activate each OTS device during an ESD event, the OTS device is preferably connected in series with a resistor. To reduce the manufacturing cost of high voltage ESD protection circuits, the series ESD is preferably connected in lateral series. The series-parallel ESD protection circuit is suitable for multi-voltage integrated circuits.

[0061] It should be understood that the forms and details of the application can be modified in various ways without departing from the spirit or scope of the application. Therefore, except as specified in the appended claims, the application is not to be limited by any of the details of the application.

Claims

1. An ESD protection circuit (100), characterized in that, include: A first port (140) and a second port (150), the first port (140) being coupled to a contact pad (10) and the second port (150) being coupled to a power supply (0); Multiple ESD devices connected in parallel, each of the ESD devices (100i) having a first sub-port (140i) and a second sub-port (150i); all the first sub-ports (140i) are coupled to the first port (140); all the second sub-ports (150i) are coupled to the second port (150); Each of the ESD devices (100i) includes a resistor (200i) and an OTS element (300i), wherein the resistor (200i) and the OTS element (300i) are connected in series; The ESD protection circuit (100) provides ESD protection for the contact pad (10).

2. The ESD protection circuit (100) according to claim 1, characterized in that, The threshold voltage of all the OTS elements (300i) in the plurality of ESD devices has a mean square deviation; During an ESD event, the voltage drop across each of the ESD devices (100i) is the same, and the resistor (200i) in each of the ESD devices (100i) and the OTS element (300i) carry the same current, and a voltage drop greater than the mean square error is generated across the resistor (200i).

3. The ESD protection circuit (100) according to claim 1, characterized in that, The resistor (200i) is formed in a resistor channel hole (210); or, The resistance value of the resistor (200i) is greater than 10 Ohms; or, The size of the OTS element (300i) is less than 10 micrometers.

4. An ESD protection circuit (100), characterized in that, include: A first port (140) and a second port (150), the first port (140) being coupled to a contact pad (10) and the second port (150) being coupled to a power supply (0); A first ESD device (100A) and a second ESD device (100B) are connected in series. The first ESD device (100A) has a first sub-port (140A) and a second sub-port (150A), and the second ESD device (100B) has a third sub-port (140B) and a fourth sub-port (150B). The first port (140A) is coupled to the first sub-port (140A), the second sub-port (150A) is coupled to the third sub-port (140B), and the fourth sub-port (150B) is coupled to the second port (150A). The first ESD device (100A) contains a first OTS element (300A), and the second ESD device (100B) contains a second OTS element (300B). The first OTS element (300A) and the second OTS element (300B) are both located on the same plane (500). Adjacent ESD devices are connected in series laterally, and the ESD protection circuit (100) provides ESD protection for the contact pad (10).

5. The ESD protection circuit (100) according to claim 4, characterized in that, During an ESD event, the first ESD device (100A) and the second ESD device (100B) carry the same current.

6. The ESD protection circuit (100) according to claim 4, characterized in that, The first OTS element (300A) and the second OTS element (300B) are adjacent to each other on the plane (500) and share a lateral interconnect.

7. An ESD protection circuit (100), characterized in that, include: The first ESD group (100a*) contains multiple ESD devices connected in series. The second ESD group (100b*) contains multiple ESD devices connected in series. The first ESD group (100a*) and the second ESD group (100b*) are connected in parallel; Each of the ESD devices contains an OTS element.

8. An ESD protection circuit (100), characterized in that, include: The third ESD group (100A*) contains multiple ESD devices connected in parallel; The fourth ESD group (100B*) contains multiple ESD devices connected in parallel. The third ESD group (100A*) and the fourth ESD group (100B*) are connected in series; Each of the ESD devices contains an OTS element.

9. The ESD protection circuit (100) according to any one of claims 1-8, characterized in that, The OTS element contains at least one chalcogenide element.

10. A multi-power integrated circuit (00M) having at least two power supply voltages, characterized in that, include: The first power supply voltage (V) S A first ESD protection circuit (100) provides ESD protection and contains m ESD devices connected in series; a second power supply voltage (V) S `) provides ESD protection and contains n ESD devices connected in series, a second ESD protection circuit (100`); m and n are both positive integers greater than 1 but with different values; at least one ESD device (100A) in the first ESD protection circuit (100) and at least one ESD device (100A`) in the second ESD protection circuit (100`) have the same structure; at least one of the first ESD protection circuit and the second ESD protection circuit is an ESD protection circuit as described in any one of claims 1 to 9.

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