A layer-number-dependent ferroelectric tunnel junction multi-value memory cell and a method for manufacturing the same

Abstract

The application discloses a layer-number-dependent ferroelectric tunnel junction multi-value storage unit and a preparation method thereof. The unit comprises a support substrate, a back gate electrode, a back gate dielectric layer, a source electrode, a van der waals ferroelectric tunnel layer, a drain electrode, a top gate dielectric layer and a top gate electrode which are stacked from bottom to top. The van der waals ferroelectric tunnel layer is prepared from a van der waals ferroelectric material. The source electrode and the drain electrode are connected to the upper and lower ends of the van der waals ferroelectric tunnel layer respectively and form clean atomic-level van der waals interface contact. The ferroelectric tunnel junction multi-value storage unit provided by the application realizes multi-value erasing and writing of a single storage unit by layer-number sliding control of an interface barrier through a ferroelectric tunnel junction with a van der waals sliding ferroelectric material as a tunnel layer.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of microelectronic devices, and particularly relates to a layer number dependent ferroelectric tunnel junction multi-value storage unit and a preparation method thereof. BACKGROUND

[0002] In the big data era, in the face of massive data writing and reading, the traditional flash memory is increasingly difficult to meet the demand. Ferroelectric materials are applied to the storage field because of their inherent advantages such as fast erasing and writing speed, ultra-low power consumption, multiple cycles, and non-volatile polarization state. At present, ferroelectric storage devices with destructive reading, non-destructive ferroelectric field effect transistors and non-destructive ferroelectric tunnel junctions have been developed based on ferroelectric materials. Among them, the ferroelectric tunnel junction not only has the advantages of fast reading and writing speed, ultra-low power consumption, long service life and non-volatility of the ferroelectric access device, but also has the advantages of small size, simple structure and non-destructive reading. However, the only two polarization states of the traditional ferroelectric material make the ferroelectric tunnel junction only have two states of '1' or '0'. This also leads to that, in order to further improve the storage density of data, the only means is to microsize the device unit, and it is impossible to realize multi-value erasing and writing in a single ferroelectric tunnel junction storage unit. SUMMARY

[0003] The purpose of the application is to provide a layer number dependent ferroelectric tunnel junction multi-value storage unit and a preparation method thereof, which can realize multi-value erasing and writing of a single storage unit by using a van der Waals slip ferroelectric material as a tunnel layer of the ferroelectric tunnel junction.

[0004] To achieve the above purpose, the application provides a layer number dependent ferroelectric tunnel junction multi-value storage unit, which comprises a support substrate, a back gate electrode, a back gate dielectric layer, a source electrode, a van der Waals ferroelectric tunnel layer, a drain electrode, a top gate dielectric layer and a top gate electrode which are stacked from bottom to top. The van der Waals ferroelectric tunnel layer is prepared from a van der Waals ferroelectric material. The source electrode and the drain electrode are respectively connected to the upper and lower ends of the van der Waals ferroelectric tunnel layer and form an atomic level van der Waals interface contact.

[0005] Further, the support substrate is a rigid or flexible substrate material, the back gate electrode and the top gate electrode are metal electrodes, heavily doped semiconductors, two-dimensional metal or semimetal materials, and when the back gate electrode and the top gate electrode are metal electrodes, they are Au, Ti, Cr, Ni or Pd.

[0006] The material of the back gate dielectric layer is SiO2, Al2O3 or h-BN, and the source electrode and the drain electrode are metal electrodes, graphene electrodes, two-dimensional metal or semimetal material electrodes, and when the source electrode and the drain electrode are metal electrodes, they are Ti, Cr, Au, Pt or Pd.

[0007] The material of the top gate dielectric layer is h-BN or Al2O3.

[0008] Further, the van der Waals ferroelectric material is a layered compound with asymmetric structure, which is prepared by mechanical exfoliation or chemical vapor deposition.

[0009] Further, the number of layers of the van der Waals ferroelectric tunneling layer is not less than 2, and the thickness of the van der Waals ferroelectric tunneling layer is not less than 1 nm.

[0010] Further, the thickness of the top gate dielectric layer is 5-15 nm.

[0011] The application further provides a preparation method of the above-mentioned number-of-layer-dependent ferroelectric tunneling junction multi-value storage unit, comprising the following steps:

[0012] (1) preparing a metal electrode on a substrate, wherein the metal electrode comprises a back gate electrode, a source electrode, a drain electrode and a top gate electrode;

[0013] (2) sequentially stacking the back gate electrode, the back gate dielectric layer, the source electrode, the van der Waals ferroelectric tunneling layer, the drain electrode, the top gate dielectric layer and the top gate electrode;

[0014] (3) finally using silver glue and gold wire to lead out the source electrode, the drain electrode, the back gate electrode and the top gate electrode, and completing the preparation.

[0015] Further, the back gate electrode, the source electrode, the drain electrode and the top gate electrode can be prepared by PC dry transfer film or thermal evaporation plating film, the van der Waals ferroelectric tunneling layer can be prepared by PC dry transfer film or prepared by chemical vapor deposition, and the back gate dielectric layer and the top gate dielectric layer can be prepared by PC dry transfer film or atomic layer deposition method.

[0016] Further, the preparation method of the PC dry transfer film comprises the following steps: dissolving polycarbonate in an organic solvent to obtain a solution with a polycarbonate concentration of 5-15 wt%, dropping the solution on the surface of a glass substrate and drying the film at 20-60 DEG C, and then placing the film on a polydimethylsiloxane supported by a transparent glass sheet to obtain a PC transfer film for dry transfer.

[0017] Further, the thermal evaporation plating film specifically comprises the following steps:

[0018] photographing a pattern on a substrate, then using a thermal evaporation plating film equipment to deposit a 40-60 nm thick metal film on the substrate, and then immersing the substrate in an organic solution for 20-40 min to obtain a patterned metal electrode.

[0019] In summary, the application has the following advantages:

[0020] 1. This invention uses van der Waals slip ferroelectric material as the tunneling layer. It utilizes the weak interlayer interaction of the material to cause a half-cell displacement under the action of an electric field, which causes a change in the polarization of the material. For two layers of van der Waals material, there are only two polarization states. However, when the number of material layers is greater than two, different polarization states exist after each layer of material undergoes relative slip, which reflects the multi-valued characteristics in electrical terms. Therefore, when using multilayer van der Waals material as the tunneling layer, multi-valued storage can be realized in a single tunneling junction.

[0021] 2. The present invention is based on the fabrication of a multi-valued memory cell with a layer-dependent ferroelectric tunnel junction. Thanks to the weak interaction between layers, as the number of layers increases, the polarization between adjacent layers can accumulate or cancel each other out. At this time, the polarization state of the interface can control the macroscopic polarization of the material. The device exhibits that it can perform multi-valued erasure and writing under the action of an electric field.

[0022] 3. The ferroelectric tunnel junction prepared by the dry transfer method of this invention has an atomically clean interface, which ensures that the intrinsic ferroelectric properties of the material will not be affected by the interface effect and generate a depolarization field. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of the present invention;

[0024] Figure 2 and Figure 3 The relationship between current and electric field in a ferroelectric tunnel junction of 4 layers of 3R-MoS2;

[0025] Figure 4 and Figure 5 The relationship between current and electric field in a ferroelectric tunnel junction of 3R-MoS2 layers;

[0026] Figure 6 and Figure 7 The relationship between current and electric field in a ferroelectric tunnel junction of two layers of 3R-MoS2;

[0027] Among them, 1. Supporting substrate; 2. Back gate electrode; 3. Back gate dielectric layer; 4. Source electrode; 5. Van der Waals ferroelectric tunneling layer; 6. Drain electrode; 7. Top gate dielectric layer; 8. Top gate electrode. Detailed Implementation

[0028] In the embodiments of the present invention, the back gate electrode, source electrode, drain electrode, and top gate electrode can all be prepared by PC dry transfer film, or by thermal evaporation coating equipment, or by preparing a film structure by thermal evaporation coating equipment and then transferring it sequentially by PC dry transfer film to prepare a layer-dependent ferroelectric tunnel junction multi-value memory cell.

[0029] The van der Waals ferroelectric tunnel layer in the embodiment of the application can be prepared by a PC dry transfer film or by chemical vapor deposition.

[0030] The back gate electrode, the source electrode, the drain electrode and the top gate electrode in the embodiment of the application all need to be prepared into patterned metal electrodes by photolithography.

[0031] The principles and characteristics of the application are described below in conjunction with the embodiments, and the examples are only used to explain the application and are not used to limit the scope of the application. If the specific conditions are not indicated in the embodiments, the conventional conditions or the conditions recommended by the manufacturers are used. If the manufacturers of the reagents or instruments are not indicated, the conventional products that can be purchased on the market are used.

[0032] Embodiment 1

[0033] The embodiment provides a preparation method of a layer number dependent ferroelectric tunnel junction multi-value storage unit, comprising the following steps:

[0034] 1) Preparation of the medium layer h-BN, the graphene electrode and the ferroelectric material: Si / SiO2 is selected as a support substrate, a few-layer h-BN sample is obtained from a h-BN crystal by mechanical exfoliation, a single-layer or few-layer graphene sample is obtained from a graphite layered crystal, and a 4-layer sample with a thickness of 3 nm is obtained from a 3R-MoS2 crystal, suitable samples are found under the assistance of a microscope, and position marks are made.

[0035] 2) Preparation of a PC dry transfer film: first, a 10wt% PC solution is prepared, then 5mL of the solution is dropped on a cleaned glass substrate, and then the glass substrate is placed on a heating plate with a temperature of 50℃ for 10min to obtain a PC film; then a 3mm*3mm PC film is cut by a blade and is attached to a PDMS substrate with the same size at one end of a transparent glass sheet, so that the PC dry transfer film is obtained.

[0036] 3) Dry transfer of the ferroelectric tunnel junction: first, the sample stage is heated to 90℃, under the assistance of a microscope and a three-micro-displacement platform, one corner of the PC dry transfer film is slowly and uniformly attached to the graphene on the SiO2 substrate, and after cooling to room temperature, the PC film lifts the graphene, and then the operation is repeated several times; the h-BN used as the medium layer, the graphene source electrode, the tunnel layer and the graphene drain electrode are lifted in turn with the graphene (i.e. the back gate electrode) as the target area, and finally the preparation of the ferroelectric tunnel junction is realized.

[0037] 4) Preparation of the metal lead electrode: first, the sample is placed in an organic solvent, and after being taken out, the PC film is removed by blowing dry nitrogen; then an electron beam lithography machine is used to in-situ exposure and development to prepare a lead electrode photolithography pattern; then a hot evaporation film coating device is used to evaporate and coat the metal lead electrode on the graphene source electrode and the graphene drain electrode. Ti(5nm) / Au(50nm) metal thin film was prepared by the rate of 0.1 A / s; then the sample was immersed in acetone solution to lift off to obtain the patterned metal lead electrode; finally, the source electrode, the drain electrode, the back gate electrode and the top gate electrode were prepared by using silver glue and gold wire, and the preparation was completed.

[0038] The back gate electrode, the source electrode, the drain electrode and the top gate electrode in this embodiment are graphene electrodes.

[0039] The back gate electrode, the source electrode, the drain electrode and the top gate electrode in this embodiment are prepared by thermal evaporation and film plating, and then stacked in sequence by PC dry transfer film to prepare a layer-dependent ferroelectric tunnel junction multi-value storage unit.

[0040] Embodiment 2

[0041] The embodiment provides a preparation method of a layer-dependent ferroelectric tunnel junction multi-value storage unit, including the following steps:

[0042] 1) Au electrode was prepared on the SiO2 substrate: first, a strip-shaped mask pattern with an interval of 5 μm and a width of 10 μm was photoetched on a heavily doped Si / SiO2 substrate, and then a 50 nm thick Au thin film was deposited on the substrate by using a thermal evaporation film plating device at a rate of 0.1 A / s, and then the substrate was immersed in acetone solution for 30 min to lift off to obtain a patterned Au electrode (the source electrode, the drain electrode, the back gate electrode and the top gate electrode are all Au electrodes).

[0043] 2) Preparation of PC dry transfer film: first, a 10wt% PC solution was prepared, then 5 mL of the solution was dropped on a clean glass substrate, and then the substrate was placed on a heating plate at a temperature of 50℃ for 10 min to obtain a PC film; then a 3mm×3mm PC film was cut by a blade and adhered to a PDMS substrate of the same size on one end of a transparent glass sheet, thereby obtaining a PC dry transfer film.

[0044] 3) PC dry transfer of Au electrode: under the assistance of a microscope and a three-dimensional displacement platform, the sample stage was first heated to 50℃, and then the corner of the PC dry transfer film was slowly and uniformly attached to the Au electrode on the SiO2 substrate, and after the heating stage was cooled to room temperature, the glass sheet was slowly lifted to realize the dry transfer of the metal electrode to the PC film.

[0045] ​4) Preparation of metal source-drain electrode: First, 3-layer 2.6 nm thick sample material is obtained from 3R-MoS2crystal material by mechanical dissociation, and is placed on a SiO2target substrate containing heavily doped Si, then the SiO2substrate is heated to 60°C using a sample stage, the metal electrode on the PC transfer film and the 3R-MoS2sample are aligned under a microscope, and then the glass sheet is slowly and uniformly pressed down; after the PC film is in full contact with the SiO2substrate, wait for 2 min, and then slowly and uniformly lift the glass sheet; since the metal electrode falls on the SiO2substrate together with the PC film, the device sample with the PC film on the surface is finally obtained.

[0046] 5) Preparation of Al2O3top gate dielectric layer: First, the sample is placed in an organic solvent, and after the PC is dissolved, it is taken out and blown dry with nitrogen; then, using Al(CH3)3and H2O as precursors, an atomic layer deposition equipment is used to deposit a 10 nm thick Al2O3encapsulation protection film on the surface of the 3R-MoS2, and the deposition temperature is 175°C; finally, the source-drain electrode, back gate electrode and top gate electrode are led out using silver glue and gold wire, and the preparation is completed.

[0047] The source-drain electrode, back gate electrode and top gate electrode in this embodiment are all Au electrodes, and the van der Waals ferroelectric tunneling layer in this embodiment is 3 layers (2.6 nm).

[0048] Example 3

[0049] The embodiment provides a preparation method of a layer number dependent ferroelectric tunnel junction multi-value storage unit, including the following steps:

[0050] 1) Preparation of a metal Pt electrode on a SiO2substrate: a monolayer film is self-assembled on a Si / SiO2substrate, a hard metal mask containing an electrode pattern with a 7 μm interval width is placed on the substrate, and then a 50 nm thick Pt film is deposited on the substrate at a rate of 0.1 A / s using a thermal evaporation film deposition equipment, and the metal mask is removed to obtain a patterned Pt electrode.

[0051] 2) Preparation of a PC dry transfer film: first, a 10 wt% PC solution is prepared, then 5 mL of the solution is dropped on a cleaned glass substrate, and then the glass substrate is placed on a heating plate at a temperature of 50°C for 10 min to obtain a PC film; then a 3 mm x 3 mm PC film is cut by a blade and adhered to a PDMS substrate of the same size on one end of a transparent glass sheet, thereby obtaining a PC dry transfer film.

[0052] ​3) Dry transfer of Pt electrode to PC: With the aid of a microscope and a three-dimensional displacement platform, the sample stage is first heated to 50°C, and then a corner of the PC dry transfer film is slowly and evenly attached to the Pt electrode on the SiO2 substrate. After the heating stage cools to room temperature, the glass slide is slowly lifted to realize the dry transfer of the metal electrode to the PC film.

[0053] 4) Fabrication of metal source and drain electrodes: Two 1.4 nm thick 3R-MoS2 crystalline films were grown on the surface of a Si / SiO2 substrate using chemical vapor deposition. Under the aid of a microscope, the metal electrode and the 3R-MoS2 (as a van der Waals ferroelectric tunneling layer) sample on the PC transfer film were aligned. The SiO2 substrate was heated to 180 °C using a sample stage and then slowly and uniformly pressed down. After the PC film was in complete contact with the SiO2 substrate, it was waited for 2 minutes and then the glass slide was slowly and uniformly lifted. Since the metal Pt electrode fell onto the SiO2 substrate along with the PVA film, a device sample with a PC film on its surface was finally obtained.

[0054] 5) Preparation of Al2O3 encapsulation layer. First, the sample was placed in an organic solvent and then dried with nitrogen gas. Then, using an atomic layer deposition (ALD) device, a 10 nm thick Al2O3 encapsulation protective film was deposited on the 3R-MoS2 surface using Al(CH3)3 and H2O as precursors at a deposition temperature of 175 °C. Finally, the source / drain electrodes, top gate electrode, and back gate electrode were led out using silver paste and gold wires to complete the preparation.

[0055] In this embodiment, the van der Waals ferroelectric tunneling layer consists of two layers (1.4 nm).

[0056] Test case

[0057] The relationship between the electric field and current of the 3R-MoS2 layer-dependent ferroelectric tunnel junction prepared in Example 1 at source-drain electrode inputs was measured, as follows: Figure 2 As shown, the multiple jump points appearing on the electrical transport curve under the action of an electric field indicate that when the four-layer 3R-MoS2 ferroelectric material acts as a tunneling layer, there are three interfaces with multiple polarization states. Figure 3 The pulse voltage test also shows that multiple different polarization states appear under the influence of the electric field.

[0058] The relationship between the electric field and current of the 3R-MoS2 layer-dependent ferroelectric tunneling junction prepared in Example 2 at source-drain electrode inputs was measured, as follows: Figure 4 As shown, the two jump points on the electrical transport curve under the action of an electric field indicate that when the three-layered 3R-MoS2 ferroelectric material acts as a tunneling layer, there are two interfaces and only three polarization states. Figure 5 The pulse voltage test also showed that three different polarization states appeared under the influence of the electric field.

[0059] The relationship between the electric field and the current of the 3R-MoS2 layer number dependent ferroelectric tunnel junction prepared in Example 3 at the source-drain electrode input is shown in FIG. 6. As shown in FIG. 6, only one jump point appears on the electric transport curve under the action of the electric field, indicating that there is only one interface existing polarization state when the 2-layer 3R-MoS2 ferroelectric material is used as a tunnel layer, and the polarization state is from the bottom to the top of the tunnel layer. Figure 6 It can also be seen from the test of the pulse voltage that there are only two polarization states under the action of the electric field. Figure 7

[0060] Although the specific embodiments of the present application are described in detail, it should not be understood as limiting the protection scope of the patent. Various modifications and variations made by those skilled in the art within the scope described in the claims are still within the protection scope of the patent.​

Claims

1. A layer-dependent ferroelectric tunnel junction multi-value storage cell, characterized in that, The device comprises a support substrate, a back gate electrode, a back gate dielectric layer, a source electrode, a van der Waals ferroelectric tunneling layer, a drain electrode, a top gate dielectric layer and a top gate electrode stacked from bottom to top, the van der Waals ferroelectric tunneling layer is prepared from a van der Waals ferroelectric material, and the source electrode and the drain electrode are connected to the upper and lower ends of the van der Waals ferroelectric tunneling layer respectively and form an atomic-level van der Waals interface contact. The van der Waals ferroelectric material is a layered compound with an asymmetric structure and is prepared by mechanical exfoliation or chemical vapor deposition; the number of layers of the van der Waals ferroelectric tunneling layer is not less than 2, and the total thickness of the van der Waals ferroelectric tunneling layer is not less than 1 nm; the thickness of the top gate dielectric layer is 5-15 nm.

2. The layer count dependent ferroelectric tunnel junction multi-level storage cell of claim 1, wherein, The support substrate is a rigid or flexible substrate material, the back gate electrode and the top gate electrode are metal electrodes, heavily doped semiconductors, two-dimensional metal or semimetal materials, the material of the back gate dielectric layer is SiO2, Al2O3 or h-BN, the source electrode and the drain electrode are metal electrodes, graphene electrodes, two-dimensional metal or semimetal material electrodes, and the material of the top gate dielectric layer is h-BN or Al2O3.

3. The method of making a layer count dependent ferroelectric tunnel junction multi-level memory cell as claimed in any one of claims 1-2, wherein, The device comprises the following steps: (1) preparing a metal electrode on a substrate, the metal electrode comprising a back gate electrode, a source electrode, a drain electrode and a top gate electrode; The metal electrode is prepared by PC dry transfer film or thermal evaporation plating film, the van der Waals ferroelectric tunneling layer is prepared by PC dry transfer film or chemical vapor deposition, and the back gate dielectric layer and the top gate dielectric layer are prepared by PC dry transfer film or atomic layer deposition method; (2) stacking the back gate electrode, the back gate dielectric layer, the source electrode, the van der Waals ferroelectric tunneling layer, the drain electrode, the top gate dielectric layer and the top gate electrode in sequence; (3) using silver glue and gold wire to lead out the source electrode, the drain electrode, the back gate electrode and the top gate electrode, and completing the preparation.

4. The method of making a layer-number-dependent ferroelectric tunnel junction multi-level memory cell as claimed in claim 3, wherein, The preparation method of the PC dry transfer film comprises the following steps: dissolving polycarbonate in an organic solvent to obtain a solution with a polycarbonate concentration of 5-15 wt%, dropping the solution on the surface of a glass substrate and drying the film at 20-60°C, and then placing the film on a polydimethylsiloxane supported by a transparent glass sheet to obtain a PC transfer film for dry transfer.

5. The method of making a layer-number-dependent ferroelectric tunnel junction multi-level memory cell as claimed in claim 3, wherein, The thermal evaporation plating film specifically comprises the following steps: photolithography on a substrate, then depositing a 40-60 nm thick metal film on the substrate using a thermal evaporation plating film equipment, and then immersing the substrate in an organic solution for 20-40 min and peeling off to obtain a patterned metal electrode.

Images