Display Panel

Abstract

The present application discloses a display panel, which includes a display area. The display panel includes a signal transmission layer and a display function layer. The signal transmission layer is located in the display area. The signal transmission layer includes a gate drive circuit. The display function layer includes a pixel drive circuit layer and a light-emitting function layer. The pixel drive circuit layer is arranged above the signal transmission layer. The light-emitting function layer is arranged on a side of the pixel drive circuit layer away from the signal transmission layer. In an embodiment of the present application, a signal transmission layer for transmitting signals to the display function layer is arranged below the display function layer, and the signal transmission layer corresponds to the display area, so that the signal transmission layer does not occupy the space of the non-display area, and the proportion of the display area of ​​the display surface of the display panel is increased, thereby realizing a narrow frame or a frameless design and improving the user experience.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] With the continuous upgrading of electronic products, large-screen electronic products are becoming more and more popular among users. At present, electronic products on the market always have large or small borders around them. The development trend of electronic products requires that their borders should be made narrower and narrower to achieve a borderless effect. Full-screen electronic products have become one of the most popular technologies nowadays due to their ultra-high screen-to-body ratio and excellent user experience. However, in the actual production process, it is difficult to meet the borderless requirements, resulting in a small proportion of the screen display area on the front of the fuselage, affecting the user experience. Summary of the invention

[0003] An embodiment of the present application provides a display panel for increasing the proportion of a display area of ​​a front body of the display panel.

[0004] An embodiment of the present application provides a display panel, the display panel comprising:

[0005] A signal transmission layer, located in the display area, the signal transmission layer includes a gate driving circuit;

[0006] The display function layer includes a pixel driving circuit layer and a light emitting function layer. The pixel driving circuit layer is arranged on the signal transmission layer, and the light emitting function layer is arranged on a side of the pixel driving circuit layer away from the signal transmission layer.

[0007] Optionally, in some embodiments provided in the present application, the display panel further includes a first signal connection line, the first signal connection line is located in the display area, and the first signal connection line is used to connect the pixel driving circuit layer and the signal transmission layer.

[0008] Optionally, in some embodiments provided in the present application, the first signal connection line includes a first signal connection segment, a second signal connection segment, and a third signal connection segment that are connected; the display panel includes a first via, a second via, and a third via, the first signal connection segment is arranged in the first via, the second signal connection segment is arranged in the second via, and the third signal connection segment is arranged in the third via.

[0009] Optionally, in some embodiments provided in the present application, the signal transmission layer further includes a plurality of first power lines, a plurality of second power lines, a plurality of reset signal lines, an array test pad and a plurality of fan-out lines; wherein

[0010] The first signal connection section is connected to the gate driving circuit, the first power line, the second power line, the reset signal line, the array test pad or the fan-out line, and the third signal connection section is connected to the pixel driving circuit layer.

[0011] Optionally, in some embodiments provided in the present application, the display panel further includes a second signal connection line, the second signal connection line is located in the display area, and the second signal connection line is used to connect the pixel driving circuit layer and the signal transmission layer.

[0012] Optionally, in some embodiments provided in the present application, the second signal connection line includes a fourth signal connection segment, a fifth signal connection segment and a sixth signal connection segment connected to each other; the display panel includes a fourth via, a fifth via and a sixth via, the fourth signal connection segment is arranged in the fourth via, the fifth signal connection segment is arranged in the fifth via, and the sixth signal connection segment is arranged in the sixth via.

[0013] Optionally, in some embodiments provided in the present application, the signal transmission layer further includes a plurality of first power lines, a plurality of second power lines, a plurality of reset signal lines, an array test pad and a plurality of fan-out lines; wherein

[0014] The fourth signal connection segment is connected to the gate driving circuit, the first power line, the second power line, the reset signal line, the array test pad or the fan-out line, and the sixth signal connection segment is connected to the pixel driving circuit layer.

[0015] Optionally, in some embodiments provided in the present application, the display panel further includes a first connection terminal and a second connection terminal; the gate driving circuit includes a first thin film transistor, the first thin film transistor includes a first active layer, a first gate, a second gate, a first source electrode and a first drain electrode, and the signal transmission layer further includes:

[0016] a substrate, wherein the first active layer is disposed on the substrate;

[0017] A first gate insulating layer is disposed on the substrate, the first gate is disposed on the substrate, and the first connecting terminal and the first gate are in the same layer and made of the same material;

[0018] a second gate insulating layer, disposed on the first gate insulating layer, the second gate insulating layer covering the first gate and the first connecting terminal, the second gate and the second connecting terminal being disposed on the second gate insulating layer, the second gate and the second connecting terminal being in the same layer and made of the same material;

[0019] a first interlayer insulating layer, disposed on the second gate insulating layer, and covering the second gate and the second connecting terminal; a first via hole penetrating the first interlayer insulating layer and the second gate insulating layer; a first signal connecting segment connected to the first connecting terminal through the first via hole; a fourth via hole penetrating the first interlayer insulating layer; a fourth signal connecting segment connected to the second connecting terminal through the fourth via hole; and a first source and a first drain connected to the first active layer through a first contact hole and a second contact hole, respectively;

[0020] The second interlayer insulating layer is arranged on the first interlayer insulating layer, the second via penetrates the second interlayer insulating layer, the second signal connection segment is connected to the first signal connection segment through the second via, the fifth via penetrates the second interlayer insulating layer, and the fifth signal connection segment is connected to the fourth signal connection segment through the fifth via.

[0021] Optionally, in some embodiments provided in the present application, the display panel further includes a third connection terminal and a fourth connection terminal; and the pixel driving circuit layer includes:

[0022] A base layer, disposed on the second interlayer insulating layer;

[0023] A second active layer is disposed on the base layer;

[0024] an insulating layer, disposed on a side of the second active layer away from the base layer, the sixth via hole penetrating the insulating layer and the base layer, and the sixth signal connection segment being connected to the fifth signal connection segment through the sixth via hole;

[0025] A third gate is arranged on a side of the insulating layer away from the second active layer, the third connecting terminal is connected to the sixth signal connecting segment and is in the same layer and made of the same material as the third gate;

[0026] an interlayer dielectric layer, arranged on a side of the third gate away from the insulating layer, the third via hole penetrating the interlayer dielectric layer, the insulating layer and the base layer, and the third signal connection segment being connected to the second signal connection segment through the third via hole;

[0027] a second source and a second drain, wherein the second source and the second drain are arranged on the interlayer dielectric layer and are connected to the second active layer through a third contact hole and a fourth contact hole respectively, the fourth connecting terminal and the second source are of the same layer and material, and the fourth connecting terminal is connected to the third signal connecting segment;

[0028] A planarization layer is disposed on the interlayer dielectric layer.

[0029] Optionally, in some embodiments provided in the present application, the signal transmission layer also includes a light-shielding layer, which is disposed on the second interlayer insulating layer, the light-shielding layer is connected to the first drain through a via, and the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the second active layer on the substrate.

[0030] Optionally, in some embodiments provided in the present application, the display panel also includes a seventh via hole, and the seventh via hole penetrates part of the insulating layer of the signal transmission layer; the signal transmission layer also includes a connecting wire and a connecting pad, and the connecting pad is arranged on a side of the substrate away from the first interlayer insulating layer, and the connecting wire is arranged in the seventh via hole, one end of the connecting wire is connected to the connecting pad, and the other end of the connecting wire is connected to the pixel driving circuit layer.

[0031] Optionally, in some embodiments provided in the present application, the display panel further includes a driving chip, the driving chip is disposed on a side of the substrate away from the first interlayer insulating layer, and the driving chip is connected to the connecting pad.

[0032] Optionally, in some embodiments provided in the present application, the pixel driving circuit layer includes a pixel driving circuit, and the pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor and an organic light emitting diode; the first transistor, the second transistor, wherein the first transistor is a driving thin film transistor.

[0033] An embodiment of the present application provides a display panel, which includes a display area. The display panel includes a signal transmission layer and a display function layer. Among them, the signal transmission layer is located in the display area. The signal transmission layer includes a gate drive circuit. The display function layer includes a pixel drive circuit layer and a light-emitting function layer. The pixel drive circuit layer is arranged on the signal transmission layer. The light-emitting function layer is arranged on the side of the pixel drive circuit layer away from the signal transmission layer. In the embodiment of the present application, a signal transmission layer for transmitting signals to the display function layer is arranged below the display function layer, and the signal transmission layer corresponds to the display area. That is to say, in the embodiment of the present application, a metal wiring for providing signals to the pixel drive circuit in the display area is arranged in the display area. Therefore, the signal transmission layer does not occupy the space of the non-display area, and the proportion of the display area of ​​the display surface of the display panel is increased, thereby realizing a narrow frame or a frameless design and improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 A schematic diagram of a structure of a display panel provided in an embodiment of the present application;

[0036] Figure 2 A schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of the structure of the signal transmission layer provided in an embodiment of the present application;

[0038] Figure 4 A schematic diagram of the structure of a display function layer provided in an embodiment of the present application;

[0039] Figure 5 A circuit diagram of a pixel driving circuit of a pixel driving circuit layer provided in an embodiment of the present application.

[0040] Figure 6 A schematic diagram of a method for manufacturing a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. Please refer to the drawings in the accompanying drawings, in which the same component symbols represent the same components. The following description is based on the specific embodiments of the present application shown, which should not be construed as limiting other specific embodiments of the present application that are not described in detail herein. The word "embodiment" used in this specification means an example, an example or an illustration.

[0042] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0043] The embodiments of the present application provide a display panel. The following are detailed descriptions. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0044] An embodiment of the present application provides a display panel, which includes a display area. The display panel includes a signal transmission layer and a display function layer. Among them, the signal transmission layer is located in the display area. The signal transmission layer includes a gate drive circuit. The display function layer includes a pixel drive circuit layer and a light-emitting function layer. The pixel drive circuit layer is arranged on the signal transmission layer. The light-emitting function layer is arranged on a side of the pixel drive circuit layer away from the signal transmission layer. In an embodiment of the present application, a signal transmission layer for transmitting signals to the display function layer is arranged below the display function layer, and the signal transmission layer corresponds to the display area, so that the signal transmission layer does not occupy the space of the non-display area, and the proportion of the display area of ​​the display surface of the display panel is increased, thereby realizing a narrow frame or a frameless design and improving the user experience.

[0045] The display panel provided by the present application is described in detail below through specific embodiments.

[0046] In the known technology, the border area of ​​the display panel is provided with a gate driving circuit and metal wiring, etc. The gate driving circuit and the metal wiring occupy a large proportion of the front screen of the display panel, so that the display area of ​​the display panel screen is relatively small, and a truly narrow border design cannot be achieved.

[0047] The embodiments of the present application provide a display panel for increasing the proportion of a display area of ​​a display surface of the display panel, thereby achieving a narrow frame or a frameless design and improving user experience.

[0048] Please combine Figure 1 and Figure 2, Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 2 A schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application. The display panel 100 includes a display area AA. The display panel 100 includes a signal transmission layer 10, a display function layer 20 and a first signal connection line 40. Among them, the signal transmission layer 10 is located in the display area AA. The signal transmission layer 10 includes a gate drive circuit 102. The display function layer 20 includes a pixel drive circuit layer 20a and a light-emitting function layer 20b, the pixel drive circuit layer 20a is arranged above the signal transmission layer 10, and the light-emitting function layer 20b is arranged on a side of the pixel drive circuit layer 20a away from the signal transmission layer 10. The first signal connection line 40 is used to connect the signal transmission layer 10 and the pixel drive circuit layer 20a.

[0049] In the embodiment of the present application, the signal transmission layer 10 for transmitting signals to the display function layer 20 is arranged below the display function layer 20, so that the signal transmission layer 10 is located in the display area AA. Therefore, the signal transmission layer does not occupy the space of the non-display area, thereby increasing the proportion of the display area AA of the display panel 100, thereby realizing a narrow bezel or bezel-free design, improving the taste of the display panel 100, and thus improving the user experience.

[0050] The first signal connection line 40 is located in the display area AA.

[0051] In some embodiments, the display panel 100 further includes a second signal connection line 50 , which is located in the display area and is used to connect the pixel driving circuit layer 20 a and the signal transmission layer 10 .

[0052] Specifically, the first signal connection line 40 includes a first signal connection section 401, a second signal connection section 402 and a third signal connection section 403. The second signal connection line 50 includes a fourth signal connection section 501, a fifth signal connection section 502 and a sixth signal connection section 503 which are connected.

[0053] The display panel 100 includes a first via hole h1, a second via hole h2, a third via hole h3, a fourth via hole h4, a fifth via hole h5, and a sixth via hole h6. The first signal connection section 401 is disposed in the first via hole h1, the second signal connection section 402 is disposed in the second via hole h2, and the third signal connection section 403 is disposed in the third via hole h3. The fourth signal connection section 501 is disposed in the fourth via hole h4, the fifth signal connection section 502 is disposed in the fifth via hole h5, and the sixth signal connection section 503 is disposed in the sixth via hole h6.

[0054] The display panel 100 further includes a first connection terminal a1, a second connection terminal a2, a third connection terminal a3 and a fourth connection terminal a4, wherein the first connection terminal a1 is connected to the first signal connection section 401, the fourth connection terminal a4 is connected to the third signal connection section 403, the second connection terminal a2 is connected to the fourth signal connection section 501, and the third connection terminal a3 is connected to the sixth signal connection section 503.

[0055] The signal transmission layer 10 further includes a plurality of first power supply lines 110, a plurality of second power supply lines 111, a plurality of reset signal lines 113, an array test pad 114 and a plurality of fan-out lines 115. Among them, the first signal connection section 401 is connected to the gate drive circuit 102, the first power supply line 110, the second power supply line 111, the reset signal line 113, the array test pad 114 or the fan-out line 115. The third signal connection section 403 is connected to the pixel drive circuit layer 20a. Specifically, the output ends of the gate drive circuit 102, the first power supply line 110, the second power supply line 111, the reset signal line 113, the array test pad 114 or the fan-out line 115 are connected to the first connection terminal a1, so that the corresponding signal is transmitted through the first signal connection line 40, and the fourth connection terminal a4 is connected to the transistor or metal line corresponding to the pixel drive circuit layer 20a, thereby realizing signal transmission.

[0056] In some embodiments, the fourth signal connection section 501 is connected to the gate drive circuit 102, the first power supply line 110, the second power supply line 111, the reset signal line 113, the array test pad 114 or the fan-out line 115. The sixth signal connection section 503 is connected to the pixel drive circuit layer 20a. Specifically, the output ends of the gate drive circuit 102, the first power supply line 110, the second power supply line 111, the reset signal line 113, the array test pad 114 or the fan-out line 115 are connected to the second connection terminal a2, so that the corresponding signal is transmitted through the second signal connection line 50, and the third connection terminal a3 is connected to the transistor or metal line corresponding to the pixel drive circuit layer 20a, thereby realizing signal transmission.

[0057] In an embodiment of the present application, the first power line 110, the second power line 111, the reset signal line 113, the array test pad 114 and the plurality of fan-shaped lines 115 are all arranged below the display function layer 20, and all correspond to the display area AA. At this time, there is no need to set a non-display area for placing metal lines, thereby realizing a borderless design of the display panel 100, realizing a true full screen, and greatly improving the user experience.

[0058] It should be noted that, in the embodiment of the present application, the fan-out wiring 115 may be a metal wiring used to lead out the data line of the pixel driving circuit layer, but is not limited thereto.

[0059] For details, please refer to Figure 3 , Figure 3 A schematic diagram of a structure of a signal transmission layer provided in an embodiment of the present application. The gate drive circuit 102 includes a first thin film transistor structure 102a. The first thin film transistor structure 102a includes a first active layer 1021, a first gate 1022, a second gate 1023, a first source 1024 and a first drain 1025. The signal transmission layer 10 also includes a substrate 101, a first gate insulating layer 103, a second gate insulating layer 104, a first interlayer insulating layer 105 and a second interlayer insulating layer 106.

[0060] The first gate insulating layer 103 is disposed on the substrate 101. The first gate 1022 is disposed on the substrate 101, and the first connection terminal a1 and the first gate 1022 are in the same layer and made of the same material.

[0061] The second gate insulating layer 104 is disposed on the first gate insulating layer 103. The second gate insulating layer 104 covers the first gate 1022 and the first connection terminal a1. The second gate 1023 and the second connection terminal a2 are disposed on the second gate insulating layer 104, and the second gate 1023 and the second connection terminal a2 are in the same layer and made of the same material.

[0062] The first interlayer insulating layer 105 is disposed on the second gate insulating layer 104, and the first interlayer insulating layer 105 covers the second gate 1023 and the second connection terminal a2. The first via hole h1 penetrates the first interlayer insulating layer 105 and the second gate insulating layer 104, and the first signal connection section 401 is connected to the first connection terminal a1 through the first via hole h1. The fourth via hole h4 penetrates the first interlayer insulating layer 105, and the fourth signal connection section 501 is connected to the second connection terminal a2 through the fourth via hole h4.

[0063] The first source electrode 1024 and the first drain electrode 1025 are connected to the first active layer 1021 through the first contact hole cnt1 and the second contact hole cnt2, respectively.

[0064] The second interlayer insulating layer 106 is disposed on the first interlayer insulating layer 105, and the second via h2 penetrates the second interlayer insulating layer 106. The second signal connection segment 402 is connected to the first signal connection segment 401 through the second via h2. The fifth via h5 penetrates the second interlayer insulating layer 106, and the fifth signal connection segment is connected to the fourth signal connection segment through the fifth via.

[0065] It should be noted that in the embodiment of the present application, the thin film transistor of the gate driving circuit 102 can be a bottom-gate thin film transistor, a top-gate thin film transistor or a dual-gate thin film transistor. The present application uses the gate driving circuit 102 as a dual-gate thin film transistor as an example for explanation, but is not limited to this.

[0066] In some embodiments, the first active layer 1021 is a low temperature polysilicon active layer. Low temperature polysilicon (LTPS) technology is another new technology in the field of flat panel displays, and is the next generation technology after amorphous silicon (a-Si). Low temperature polysilicon display panels have the advantages of faster electron mobility, smaller thin film circuit area, higher resolution, lower power consumption, and higher stability.

[0067] Please combine Figure 2 and Figure 4 , Figure 4 A schematic diagram of a structure of a display function layer provided in an embodiment of the present application. The pixel driving circuit layer 20a includes a base layer 201, a second active layer 202, a third gate 204, an insulating layer 203, a third gate 204, an interlayer dielectric layer 205, a second source 206, a second drain 207 and a planarization layer 208.

[0068] The base layer 201 is disposed on a side of the second interlayer insulating layer 106 away from the first interlayer insulating layer 105. The second active layer 202 is disposed on a side of the base layer 201 away from the second interlayer insulating layer 106, and the orthographic projection of the second active layer 202 on the substrate 101 is located within the orthographic projections of the light shielding layer 108 and the substrate 101.

[0069] The insulating layer 203 is disposed on a side of the second active layer 202 away from the base layer 201. The sixth via hole h6 penetrates the insulating layer 203 and the base layer 201, and the sixth signal connection segment 503 is connected to the fifth signal connection segment 502 through the sixth via hole h6.

[0070] The third gate 204 is disposed on a side of the insulating layer 203 away from the second active layer 202. The third connection terminal a3 is connected to the sixth signal connection section 503 and is in the same layer and made of the same material as the third gate 204.

[0071] The interlayer dielectric layer 205 is disposed on a side of the third gate 204 away from the insulating layer 203. The third via h3 penetrates the interlayer dielectric layer 205, the insulating layer 203 and the base layer 201, and the third signal connection segment 403 is connected to the second signal connection segment 402 through the third via h3.

[0072] The pixel driving circuit layer 20 a has a third contact hole cnt3 and a fourth contact hole cnt4 . The third contact hole cnt3 and the fourth contact hole cnt4 penetrate the interlayer dielectric layer 205 .

[0073] The second source 206 and the second drain 207 are disposed on the interlayer dielectric layer 205 and connected to the second active layer 202 through the third contact hole cnt3 and the fourth contact hole cnt4 respectively. The fourth connection terminal a4 and the second source 206 are of the same layer and material, and the fourth connection terminal a4 is connected to the third signal connection section 403.

[0074] The planarization layer 208 is disposed on the interlayer dielectric layer 205 and covers the second source 206 and the second drain 207 .

[0075] In the embodiment of the present application, different film layers are punched respectively, so that corresponding connection signal segments are formed in different vias while forming the metal layer, and a plurality of signal connection segments are connected to form a signal connection line. That is, the first signal connection line 40 and the second signal connection line 50 of the embodiment of the present application are formed in the process of forming the metal line required for the display panel 100, and no additional process is required, thereby reducing the production cost of the display panel 100.

[0076] In some embodiments, the second active layer 202 is a metal oxide active layer, wherein the material of the second active layer 202 can be selected from indium gallium zinc oxide.

[0077] Metal oxide semiconductors have the characteristics of high mobility, high on-state current, better switching characteristics and better uniformity. They can be used in applications that require fast response and large current, such as high-frequency, high-resolution, large-size displays and organic light-emitting displays.

[0078] The light-emitting functional layer 20b includes an anode 210, a pixel definition layer 209, a light-emitting layer 211 and a cathode 212. The anode 210 is connected to the second drain 207 through a via. The pixel definition layer 209 has an opening, and the opening of the pixel definition layer 209 exposes the surface of the anode 210. The light-emitting layer 211 is arranged in the opening of the pixel definition layer 209. The cathode 212 is arranged on a side of the light-emitting layer 211 away from the anode 210.

[0079] In some embodiments, the signal transmission layer 10 further includes a light shielding layer 108. The light shielding layer 108 is disposed on a side of the second interlayer insulating layer 106 away from the first interlayer insulating layer 105, and the light shielding layer 108 is connected to the first drain electrode 1025 through a via. The orthographic projection of the light shielding layer 108 on the substrate 101 covers the orthographic projection of the second active layer 202 on the substrate 101. In the embodiment of the present application, by disposing the light shielding layer 108 connected to the first drain electrode 1025, the light shielding layer 108 can be used to reduce the electromagnetic interference of the signal transmission layer 10 to the display function layer 20, and can block the external light incident from one side of the substrate 101, thereby improving the stability of the display panel 100.

[0080] In some embodiments, the display panel 100 further includes a seventh via hole h7, and the seventh via hole h7 penetrates a portion of the insulating layer of the signal transmission layer 10. The signal transmission layer 10 further includes a connecting wire 107 and a connecting pad 109, and the connecting pad 109 is disposed on a side of the substrate 101 away from the first interlayer insulating layer 105. The connecting wire 107 is disposed in the seventh via hole h7, one end of the connecting wire h7 is connected to the connecting pad 109, and the other end of the connecting wire 107 is connected to the pixel driving circuit layer 20a.

[0081] In some embodiments, the seventh via hole h7 penetrates the first interlayer insulating layer 106 , the second gate insulating layer 104 , the first gate insulating layer 103 , and the substrate 101 .

[0082] In some embodiments, the connection trace 107 is used to connect the data line on the pixel driving circuit layer 20 a to the connection pad 109 , but is not limited thereto.

[0083] The display panel 100 further includes a driving chip 30. The driving chip 30 is disposed on a side of the connection pad 109 away from the substrate 101. The driving chip 30 is used to drive the display panel 100 to emit light.

[0084] In an embodiment of the present application, the driver chip 30 is bound to a side of the signal transmission layer 10 away from the display function layer 20, that is, the driver chip 30 is bound to the back side. Compared with the prior art arrangement of binding the driver chip to the back side of the display panel by bending, the frame of the display panel 100 is further reduced, and the proportion of the display area AA of the display surface of the display panel 100 is increased.

[0085] It should be noted that, in some embodiments, the connection pads 109 include chip connection pads and test connection pads. The embodiment of the present application does not limit the arrangement of the connection pads and the test connection pads.

[0086] Please continue reading Figure 1 , the gate drive circuit 102 corresponds to the outer edge of the display area AA. The first power supply line 110 is arranged on the outside of the gate drive circuit 102. The second power supply line 111 is arranged on the side close to the connection pad 109. The reset signal line 113 is arranged on the inner side of the gate drive circuit 102. The array test pad 114 is arranged on the side of the second power supply line 111 away from the connection pad 109. The fan-shaped line 115 is arranged between the second power supply line 111 and the connection pad 109, and is used to connect the second power supply line 111 and the connection pad 109.

[0087] In some embodiments, the substrate 101 includes an inorganic layer 1011, a first flexible substrate layer, a first barrier layer 1013, and a second barrier layer 1014 stacked in sequence. The first active layer 1021 is disposed on the second barrier layer 1014. The connection pad 109 is disposed on one side of the inorganic layer 1011 away from the first flexible substrate layer 1012.

[0088] In some embodiments, the material of the first flexible substrate layer 1012 may include at least one of PI (polyimide), PET (polyethylene phthalate), PEN (polyethylene naphthalate), PC (polycarbonate), PES (polyethersulfone), PAR (aromatic fluorotoluene containing polyarylate), or PCO (polycyclic olefin). The inorganic layer 1011, the first barrier layer 1013, and the second barrier layer 1014 are composed of a stack structure of one or two or more of silicon-containing nitride, silicon-containing oxide, or silicon-containing oxynitride.

[0089] In some embodiments, the pixel driving circuit layer 20 a includes a pixel driving circuit, and the pixel driving circuit may include a 3T1C pixel driving circuit, a 4T2C pixel driving circuit, a 5T2C pixel driving circuit, or a 6T1C pixel driving circuit.

[0090] Please refer to Figure 5 , Figure 5 A circuit diagram of a pixel driving circuit of a pixel driving circuit layer provided in an embodiment of the present application. The pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, a second capacitor C2, and an organic light emitting diode OLED. Each transistor is a P-type thin film transistor. The first transistor T1 is a driving thin film transistor, the gate of the first transistor T1 is electrically connected to one end of the first capacitor (C1) via the first node (A), and the source of the first transistor T1 is connected to the positive voltage of the second power supply line 111. The drain of the first transistor T1 is electrically connected to the anode of the organic light emitting diode OLED. The gate of the second transistor T2 is connected to the nth scan signal SCAN(n) corresponding to the row where the pixel driving circuit is located, the source of the second transistor T2 is connected to the data signal data, and the drain of the second transistor T2 is electrically connected to the other end of the first capacitor C1 via the second node B. The gate of the third transistor T3 is connected to the n+1th scan signal SCAN(n+1) corresponding to the next row of the pixel driving circuit, the source of the third transistor T3 is electrically connected to the second node B, and the drain is connected to the reference voltage Vref. The gate of the fourth transistor T4 is connected to the nth scan signal SCAN(n) corresponding to the row of the pixel driving circuit, the source of the fourth transistor T4 is electrically connected to the first node A, and the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode OLED.

[0091] One end of the first capacitor C1 is electrically connected to the first node A, and the other end is electrically connected to the second node B. One end of the second capacitor C2 is electrically connected to the first node A, and the other end is electrically connected to the second power line 111. The anode of the organic light emitting diode OLED is electrically connected to the drain of the first transistor T1 and the drain of the fourth transistor T4, and the cathode is electrically connected to the first power line 110.

[0092] A pixel driving circuit provided by the present invention adopts a 4T2C structure. Compared with the existing pixel driving circuit, it only needs to set a scanning signal to control the corresponding thin film transistor, which not only plays a compensation role, but also reduces the number of control signals, simplifies the circuit structure and reduces the cost.

[0093] Accordingly, the present application also provides a method for manufacturing a display panel, please refer to Figure 6 The method for manufacturing a display panel comprises the following steps:

[0094] Step B001, providing a signal transmission layer, where the signal transmission layer is located in a display area of ​​the display panel.

[0095] The step of providing a signal transmission layer includes providing a flexible substrate and then arranging a connection pad 109 on the flexible substrate.

[0096] Next, the inorganic layer 1011 and the first flexible substrate layer 1012 are sequentially disposed on the flexible substrate 1015 .

[0097] Subsequently, the gate driving circuit 102 is disposed on the first flexible substrate layer 1012 to form a signal transmission layer.

[0098] In some embodiments, the signal transmission layer further includes a plurality of first power lines, a plurality of second power lines, a plurality of reset signal lines, an array test pad, and a plurality of fan-out lines.

[0099] Step B002, a display function layer is arranged on the signal transmission layer, wherein the display function layer includes a pixel driving circuit layer and a light emitting function layer. The pixel driving circuit layer is arranged on the signal transmission layer. The light emitting function layer is arranged on a side of the pixel driving circuit layer away from the signal transmission layer.

[0100] Step B003, the flexible substrate 1015 is peeled off by laser peeling, mechanical peeling, dissolving peeling or other methods to expose the connection pads.

[0101] Step B003, binding the driving chip to the connecting pad, thereby completing the production of the display panel.

[0102] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A display panel, characterized in that: The display panel includes a display area, and the display panel includes: A signal transmission layer, located in the display area, the signal transmission layer includes a substrate, a gate driving circuit and a second interlayer insulating layer; the gate driving circuit includes a first thin film transistor structure arranged on the substrate, the first thin film transistor structure includes a first drain electrode, and the second interlayer insulating layer covers the first drain electrode; A display function layer, the display function layer comprising a pixel driving circuit layer and a light emitting function layer, the pixel driving circuit layer being arranged above the signal transmission layer, the light emitting function layer being arranged on a side of the pixel driving circuit layer away from the signal transmission layer; the pixel driving circuit layer comprising a second active layer; The signal transmission layer also includes a light-shielding layer arranged between the first thin-film transistor structure and the pixel driving circuit layer, the light-shielding layer is arranged on the second interlayer insulating layer, the light-shielding layer is connected to the first drain through a via, and the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the second active layer on the substrate.

2. The display panel according to claim 1, characterized in that: The display panel further includes a first signal connection line, the first signal connection line is located in the display area, and the first signal connection line is used to connect the pixel driving circuit layer and the signal transmission layer.

3. The display panel according to claim 2, characterized in that: The first signal connection line includes a first signal connection segment, a second signal connection segment and a third signal connection segment that are connected; the display panel includes a first via hole, a second via hole and a third via hole, the first signal connection segment is arranged in the first via hole, the second signal connection segment is arranged in the second via hole, and the third signal connection segment is arranged in the third via hole.

4. The display panel according to claim 3, characterized in that: The signal transmission layer also includes a plurality of first power supply lines, a plurality of second power supply lines, a plurality of reset signal lines, an array test pad and a plurality of fan-out lines; wherein The first signal connection section is connected to the gate driving circuit, the first power line, the second power line, the reset signal line, the array test pad or the fan-out line, and the third signal connection section is connected to the pixel driving circuit layer.

5. The display panel according to claim 3, characterized in that: The display panel further includes a second signal connection line, the second signal connection line is located in the display area, and the second signal connection line is used to connect the pixel driving circuit layer and the signal transmission layer.

6. The display panel according to claim 5, characterized in that: The second signal connection line includes a fourth signal connection segment, a fifth signal connection segment and a sixth signal connection segment connected to each other; the display panel includes a fourth via hole, a fifth via hole and a sixth via hole, the fourth signal connection segment is arranged in the fourth via hole, the fifth signal connection segment is arranged in the fifth via hole, and the sixth signal connection segment is arranged in the sixth via hole.

7. The display panel according to claim 6, characterized in that: The signal transmission layer also includes a plurality of first power supply lines, a plurality of second power supply lines, a plurality of reset signal lines, an array test pad and a plurality of fan-out lines; wherein The fourth signal connection segment is connected to the gate driving circuit, the first power line, the second power line, the reset signal line, the array test pad or the fan-out line, and the sixth signal connection segment is connected to the pixel driving circuit layer.

8. The display panel according to claim 6, characterized in that: The display panel further includes a first connection terminal and a second connection terminal; the first thin film transistor further includes a first active layer, a first gate, a second gate and a first source electrode; the signal transmission layer includes: the substrate, the first active layer being disposed on the substrate; A first gate insulating layer is disposed on the substrate, the first gate is disposed on the substrate, and the first connecting terminal and the first gate are in the same layer and made of the same material; a second gate insulating layer, disposed on the first gate insulating layer, the second gate insulating layer covering the first gate and the first connecting terminal, the second gate and the second connecting terminal being disposed on the second gate insulating layer, the second gate and the second connecting terminal being in the same layer and made of the same material; a first interlayer insulating layer, disposed on the second gate insulating layer, and covering the second gate and the second connecting terminal; a first via hole penetrating the first interlayer insulating layer and the second gate insulating layer; a first signal connecting segment connected to the first connecting terminal through the first via hole; a fourth via hole penetrating the first interlayer insulating layer; a fourth signal connecting segment connected to the second connecting terminal through the fourth via hole; and a first source and a first drain connected to the first active layer through a first contact hole and a second contact hole, respectively; The second interlayer insulating layer is arranged on the first interlayer insulating layer, the second via penetrates the second interlayer insulating layer, the second signal connection segment is connected to the first signal connection segment through the second via, the fifth via penetrates the second interlayer insulating layer, and the fifth signal connection segment is connected to the fourth signal connection segment through the fifth via.

9. The display panel according to claim 8, characterized in that: The display panel further includes a third connection terminal and a fourth connection terminal; the pixel driving circuit layer includes: A base layer, disposed on the second interlayer insulating layer; The second active layer is disposed on the base layer; an insulating layer, disposed on a side of the second active layer away from the base layer, the sixth via hole penetrating the insulating layer and the base layer, and the sixth signal connection segment being connected to the fifth signal connection segment through the sixth via hole; A third gate is arranged on a side of the insulating layer away from the second active layer, the third connecting terminal is connected to the sixth signal connecting segment and is in the same layer and made of the same material as the third gate; an interlayer dielectric layer, arranged on a side of the third gate away from the insulating layer, the third via hole penetrating the interlayer dielectric layer, the insulating layer and the base layer, and the third signal connection segment being connected to the second signal connection segment through the third via hole; a second source and a second drain, wherein the second source and the second drain are arranged on the interlayer dielectric layer and are connected to the second active layer through a third contact hole and a fourth contact hole respectively, the fourth connecting terminal and the second source are of the same layer and material, and the fourth connecting terminal is connected to the third signal connecting segment; A planarization layer is disposed on the interlayer dielectric layer.

10. The display panel according to claim 8, characterized in that: The display panel also includes a seventh via hole, which penetrates part of the insulating layer of the signal transmission layer; the signal transmission layer also includes a connecting wire and a connecting pad, the connecting pad is arranged on a side of the substrate away from the first interlayer insulating layer, the connecting wire is arranged in the seventh via hole, one end of the connecting wire is connected to the connecting pad, and the other end of the connecting wire is connected to the pixel driving circuit layer.

11. The display panel according to claim 10, characterized in that: The display panel further includes a driving chip, and the driving chip is arranged on a side of the connecting pad away from the substrate.

12. The display panel according to claim 1, characterized in that: The pixel driving circuit layer includes a pixel driving circuit, and the pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor and an organic light emitting diode; the first transistor and the second transistor, wherein the first transistor is a driving thin film transistor.

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