Display Panel and its Manufacturing Method

Abstract

This application discloses a display panel and its manufacturing method, comprising a first display surface and a second display surface disposed opposite to each other; wherein the display panel includes a plurality of storage capacitors, and in a second direction perpendicular to a first direction pointing from the first display surface to the second display surface, the storage capacitors include a first electrode plate and a second electrode plate disposed opposite to each other and spaced apart. This structure reduces the metal area of ​​the capacitors and improves the light transmittance of the device.

Description

Technical Field

[0001] This invention relates to the field of transparent displays, and in particular to display panels and methods for manufacturing the same. Background Technology

[0002] With the rise of AR, people's demand for the integration of virtual content and the real world is increasing. Transparent displays, due to their unique ability to integrate displayed content with the real world, are gradually appearing in people's daily lives and may become a new trend in the display industry. Currently, panel manufacturers are advancing the research and development of products such as transparent car window displays; LG and Xiaomi have both produced transparent display TVs.

[0003] AMOLED (Active Matrix Organic Light Emitting Diode) panels, with their self-emissive, thin, and flexible characteristics, are more suitable for the fabrication of transparent displays. However, transparent display devices require relatively low pixel density (ppi), currently less than 100. Transparent displays require high light transmittance of the screen, and the limitations on increasing transmittance are not only the module materials and OLED cathode metal materials, but also the influence of the metal structure in the array circuit.

[0004] Therefore, by reducing the metal area in the array backplane through a special structure, the light transmittance of the screen can be effectively improved. Summary of the Invention

[0005] The main technical problem addressed by this application is to provide a display panel and its manufacturing method to reduce the area of ​​the capacitor metal and improve the light transmittance of the device.

[0006] To address the aforementioned issues, this application provides a display panel comprising a first display surface and a second display surface disposed opposite to each other; wherein the display panel includes a plurality of storage capacitors, and in a second direction perpendicular to a first direction pointing from the first display surface to the second display surface, the storage capacitors include a first electrode plate and a second electrode plate disposed opposite to each other and spaced apart.

[0007] The first electrode plate includes a first electrode portion and a second electrode portion connected to each other, with an included angle between the first electrode portion and the second electrode portion. The second electrode plate includes a third electrode portion and a fourth electrode portion connected to each other, with an included angle between the third electrode portion and the fourth electrode portion. Along the second direction, the first electrode portion and the third electrode portion within the same storage capacitor are arranged parallel to each other and spaced apart. The first electrode portion and the third electrode portion are disposed on the same layer, and the second electrode portion and the fourth electrode portion are spaced apart.

[0008] The distance between the second electrode portion and the fourth electrode portion within the same storage capacitor gradually decreases along the first direction.

[0009] The second electrode portion is perpendicularly connected to the first electrode portion, the third electrode portion is perpendicularly connected to the fourth electrode portion, and the second electrode portion and the fourth electrode portion are parallel and spaced apart.

[0010] In the first direction, the display panel includes an array substrate, the array substrate including a plurality of film layers stacked together; wherein at least a portion of the plurality of film layers has a first groove at a position corresponding to the first electrode plate, and at least a portion of the plurality of film layers has a second groove at a position corresponding to the second electrode plate, the first electrode plate fills at least a portion of the first groove, and the second electrode plate fills at least a portion of the second groove.

[0011] The plurality of film layers include a spacer film layer located between adjacent first grooves and second grooves;

[0012] Wherein, the second electrode portion fills at least a portion of the first groove, and the first electrode portion is located on the surface of the spacer film layer; the fourth electrode portion fills at least a portion of the second groove, and the third electrode portion is located on the surface of the spacer film layer.

[0013] Wherein, the second electrode portion fills part of the first groove, and a first gap is formed between the side of the second electrode portion away from the fourth electrode portion and the sidewall of the first groove; and / or, the fourth electrode portion fills part of the second groove, and a second gap is formed between the side of the fourth electrode portion away from the second electrode portion and the sidewall of the second groove.

[0014] In the first direction, the plurality of film layers include a substrate layer, a buffer layer, a gate insulating layer, a first metal layer, an interlayer insulating layer, and a second metal layer stacked together; wherein the material of the storage capacitor is the same as the material of the first metal layer, and one end of the first groove and the second groove penetrates the gate insulating layer in the first direction; or, the material of the storage capacitor is the same as the material of the second metal layer, and one end of the first groove and the second groove penetrates the interlayer insulating layer in the first direction; preferably, in the first direction, the other end of the first groove and the second groove extends into the substrate layer; preferably, the side of the substrate layer opposite to the second metal layer is a first display surface, and the side of the second metal layer opposite to the substrate layer is a second display surface; in the first direction, the first groove and / or the second groove is an inverted trapezoidal groove.

[0015] To address the aforementioned problems, this application provides a method for manufacturing a display panel, comprising: providing a substrate; forming a plurality of storage capacitors on the substrate; wherein the substrate includes a first display surface and a second display surface disposed opposite to each other; and in a second direction perpendicular to a first direction pointing from the first display surface to the second display surface, the storage capacitor includes a first electrode plate and a second electrode plate disposed opposite to each other.

[0016] The step of forming multiple storage capacitors on the substrate includes: sequentially stacking a substrate layer, a buffer layer, a gate insulating layer, a first metal layer, an interlayer insulating layer, and a second metal layer on the substrate; forming a first groove and a second groove on the gate insulating layer, and fabricating the storage capacitors on the first groove, the second groove, and the surface of the gate insulating layer, such that the material of the storage capacitors is the same as the material of the first metal layer; or, forming a first groove and a second groove on the interlayer insulating layer, and fabricating the storage capacitors on the first groove, the second groove, and the surface of the interlayer insulating layer, such that the material of the storage capacitors is the same as the material of the second metal layer.

[0017] The beneficial effect of this application is that by changing the first electrode plate and the second electrode plate of the storage capacitor from being spaced apart in the first direction to being spaced apart in the second direction, the storage capacitor is transformed from a horizontal structure to a vertical structure, which reduces the metal surface area projected by the storage capacitor in the vertical direction and improves the light transmittance of the storage capacitor device. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a display panel according to an embodiment of this application;

[0020] Figure 2a This is a top view of one embodiment of the storage capacitor of this application;

[0021] Figure 2b This is a schematic cross-sectional view of an embodiment of the storage capacitor of this application;

[0022] Figure 3 This is a schematic diagram of the structure of a specific embodiment of the display panel of this application;

[0023] Figure 4This is a schematic flowchart of an embodiment of the method for manufacturing the display panel of this application;

[0024] Figure 5 This is a flowchart illustrating the first embodiment of a method for manufacturing a display panel according to this application.

[0025] Figure 6 This is a flowchart illustrating a second embodiment of the method for manufacturing a display panel according to this application.

[0026] Figure 7 This is a flowchart illustrating a second embodiment of the method for manufacturing a display panel according to this application. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated above. “Multiple” generally includes at least two, but does not exclude the inclusion of at least one.

[0029] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0030] It should be understood that the terms "comprising," "including," or any other variations used herein are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0031] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0032] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0033] This application provides a display panel; please refer to the details. Figure 1 , Figure 1 This is a schematic diagram of the structure of a display panel according to an embodiment of this application. Figure 1 As shown, the display panel includes a first display surface 101 and a second display surface 102 arranged opposite to each other.

[0034] The display panel includes multiple storage capacitors 11, each of which includes a first electrode plate 111 and a second electrode plate 112 that are arranged opposite to and spaced apart from each other.

[0035] The direction from the first display surface 101 to the second display surface 102 is defined as the first direction, and the second direction is perpendicular to the first direction. The second direction can be to the left or to the right; specifically, the second direction is parallel to either the first display surface 101 or the second display surface 102. The first electrode plate 111 and the second electrode plate 112 are positioned opposite each other and spaced apart along the second direction.

[0036] By arranging the first electrode plate 111 and the second electrode plate 112 opposite to each other in the second direction, i.e., in a direction perpendicular to the first display surface 101 and the second display surface 102, a vertical capacitor structure is formed. Compared to conventional capacitors arranged parallel to the display surface, this vertical capacitor structure can greatly reduce the projected area of ​​the storage capacitor 11 in the first direction, i.e., reduce the area in the light projection direction, thereby improving the light transmittance of the display panel. Specifically, the display panel is a transparent display panel.

[0037] The spacing and projected area of ​​the first electrode plate 111 and the second electrode plate 112 in the second direction are closely related to the capacitance of the storage capacitor 11. The spacing and projected area of ​​the first electrode plate 111 and the second electrode plate 112 in the second direction can be designed according to the capacitance of the storage capacitor 11.

[0038] Specifically, please refer to Figure 2a and Figure 2b , Figure 2a This is a top view schematic diagram of an embodiment of the storage capacitor of this application. Figure 2b This is a schematic cross-sectional view of an embodiment of the storage capacitor of this application. Figure 2a and Figure 2b As shown, in one specific embodiment, the first electrode plate 111 includes a first electrode portion 1101 and a second electrode portion 1102, with an included angle between the first electrode portion 1101 and the second electrode portion 1102. The second electrode plate 112 includes a third electrode portion 1201 and a fourth electrode portion 1202, with an included angle between the third electrode portion 1201 and the fourth electrode portion 1202.

[0039] The angle between the first electrode portion 1101 and the second electrode portion 1102 may be the same as or different from the angle between the third electrode portion 1201 and the fourth electrode portion 1202. No limitation is made here.

[0040] In the second direction, the first electrode portion 1101 and the third electrode portion 1201 within the same storage capacitor 11 are arranged parallel to each other and spaced apart, the first electrode portion 1101 and the third electrode portion 1201 are disposed on the same layer, and the second electrode portion 1102 and the fourth electrode portion 1202 are arranged parallel to each other and spaced apart.

[0041] In this embodiment, the included angle between the first electrode portion 1101 and the second electrode portion 1102, and the included angle between the third electrode portion 1201 and the fourth electrode portion 1202, can be a right angle, an acute angle, or an obtuse angle.

[0042] In one specific embodiment, the distance between the second electrode portion 1102 and the fourth electrode portion 1202 within the same storage capacitor 11 gradually decreases in a first direction. The included angle between the first electrode portion 1101 and the second electrode portion 1102, and the included angle between the third electrode portion 1201 and the fourth electrode portion 1202, are obtuse angles.

[0043] In another specific embodiment, the first electrode portion 1101 and the second electrode portion 1102 of the storage capacitor 11 are vertically connected, and the third electrode portion 1201 and the fourth electrode portion 1202 are vertically connected, such that the second electrode portion 1102 and the fourth electrode portion 1202 are parallel and spaced apart. In this case, the spacing and projected area of ​​the first electrode plate 111 and the second electrode plate 112 in the second direction satisfy C = εS / d with respect to the capacitance of the storage capacitor 11. Furthermore, the angles between the first electrode portion 1101 and the second electrode portion 1102, and the angles between the third electrode portion 1201 and the fourth electrode portion 1202, are right angles. The projected area S is the product of the height H and length L of the first electrode plate 111 or the second electrode plate 112.

[0044] In this embodiment, in the first direction, the display panel includes an array substrate 10, which includes a plurality of stacked film layers. At least a portion of the film layers have a first groove 201 corresponding to a first electrode 111, and at least a portion of the film layers have a second groove 202 corresponding to a second electrode plate 112. The first electrode plate 111 fills at least a portion of the first groove 201, and the second electrode plate 112 fills at least a portion of the second groove 202. Specifically, as follows... Figure 2a and 2b As shown, the first electrode plate 111 fills a portion of the first groove 201, and the second electrode plate 112 fills a portion of the second groove 202. In other embodiments, the first electrode plate 111 completely fills the first groove 201, and the second electrode plate 112 completely fills the second groove 202. In other fully filled embodiments, the capacitance of the storage capacitor 11 is the same as that of the partially filled embodiments.

[0045] The plurality of film layers include a spacer film layer 203 located between adjacent first grooves 201 and second grooves 202, a second electrode portion 1102 filling at least a portion of the first groove 201, and a first electrode portion 1101 located on the surface of the spacer film layer 203. A fourth electrode portion 1202 filling at least a portion of the second groove 202, and a third electrode portion 1201 located on the surface of the spacer film layer 203.

[0046] Specifically, the first electrode portion 1101 and the third electrode portion 1201 are respectively used to connect different electrode voltages to form a storage capacitor 11.

[0047] In this embodiment, the second electrode portion 1102 fills the first groove 201, and a first gap D1 is formed between the side of the second electrode portion 1102 away from the fourth electrode portion 1202 and the sidewall of the first groove 201. The fourth electrode portion 1202 fills part of the second groove 202, and a second gap D2 is formed between the side of the fourth electrode portion 1202 away from the second electrode portion 1102 and the sidewall of the second groove 202. The first gap D1 and the second gap D2 may be the same or different. The first gap D1 and the second gap D2 gradually increase along the first direction, forming an inverted trapezoid. The first gap D1 and the second gap D2 of the groove are used to fill other film layers.

[0048] For further information, please refer to the following: Figure 3 , Figure 3 This is a schematic diagram of the structure of a specific embodiment of the display panel of this application. Figure 3 As shown, in the first direction, the plurality of film layers include a substrate layer 31, a buffer layer 32, a gate insulating layer 33, a first metal layer G, an interlayer insulating layer 34, and a second metal layer S / D stacked together. The second metal layer S / D is spaced apart to form the source S and drain D of the thin-film transistor.

[0049] The substrate layer 31 includes a first substrate layer PI-1, a second substrate layer BL-1, a third substrate layer PI-2, and a fourth substrate layer BL-2. The number of substrate layers is not limited here and can be set according to actual conditions. The substrate layer 31 is disposed on a glass substrate Class.

[0050] The second metal layer S / D is further provided with a first passivation layer 35 and a second passivation layer 36. Specifically, the number of passivation layers can be set according to actual needs and is not limited here. Grooves are drilled on the passivation layer, and pixel anodes 301 are formed in the grooves and on the surface of the passivation layer. A pixel defining layer 37 is formed on the surface of the pixel anode 301. The substrate layer 31, buffer layer 32, gate insulating layer 33, first metal layer G, interlayer insulating layer 34 and second metal layer S / D mentioned above are all basic film layers of the array substrate, and their functions are also basic, so they will not be described in detail here.

[0051] In this embodiment, the material of the storage capacitor 11 is the same as the material of the first metal layer G. In the first direction, the first groove and the second groove ( Figure 1 One end of the first and second grooves (not shown) penetrates at least through the gate insulating layer 33. In a preferred embodiment, the other ends of the first and second grooves extend into the buffer layer 32. In another preferred embodiment, the other ends of the first and second grooves penetrate through the buffer layer 32 and extend into the substrate layer 31. The specific penetration layer is determined by the height requirements of the electrode plates of the storage capacitor 11.

[0052] In another embodiment, the material of the storage capacitor 11 may be the same as that of the second metal layer S / D. In the first direction, one end of the first groove and the second groove penetrates at least the interlayer insulating layer 34. In a preferred embodiment, the other end of the first groove and the second groove penetrates the gate insulating layer 33, the buffer layer 32, and a portion of the substrate layer 31. The specific penetration layer is determined by the height requirement of the electrode plate of the storage capacitor 11, and the height of the electrode plate of the storage capacitor 11 is related to the capacitance of the storage capacitor 11.

[0053] It should be noted that the first metal layer G and the second metal layer S / D can be made of the same material. In this embodiment, the fact that the material of the storage capacitor 11 is the same as the material of the first metal layer G means that the storage capacitor 11 is formed when the first metal layer G is formed, that is, the first electrode portion 1101 and the third electrode portion 1201 of the storage capacitor 11 are disposed in the same layer as the first metal layer G. The fact that the material of the storage capacitor 11 can also be the same as the material of the second metal layer S / D means that the first electrode portion 1101 and the third electrode portion 1201 of the storage capacitor 11 are disposed in the same layer as the second metal layer S / D.

[0054] In another embodiment, the interlayer insulating layer 34 further includes a first interlayer insulating layer and a second interlayer insulating layer, and the first electrode portion 1101 and the third electrode portion 1201 of the storage capacitor 11 may also be disposed between the first interlayer insulating layer and the second interlayer insulating layer.

[0055] The beneficial effect of this embodiment is that by changing the spacing between the first electrode plate and the second electrode plate of the storage capacitor from the original spacing in the first direction to the spacing in the second direction, the storage capacitor is transformed from the original horizontal structure to a vertical structure, which reduces the metal surface area projected by the storage capacitor in the vertical direction and improves the light transmittance of the storage capacitor device.

[0056] This application also provides a method for manufacturing a display panel; please refer to the details below. Figure 4 , Figure 4 This is a schematic flowchart illustrating one embodiment of the method for manufacturing the display panel according to this application. Figure 4 As shown, it includes:

[0057] Step S31: Provide a substrate.

[0058] The substrate includes a first display surface and a second display surface disposed opposite to each other. For details, please refer to [link / reference]. Figure 1 As shown, the direction from the first display surface 101 to the second display surface 102 is the first direction, and the direction perpendicular to the first direction from the first display surface 101 to the second display surface 102 is the second direction.

[0059] In this embodiment, the substrate refers to an array substrate.

[0060] Step S32: Form multiple storage capacitors on the substrate.

[0061] The storage capacitor 11 includes a first electrode plate 111 and a second electrode plate 112 arranged opposite to each other, wherein the first electrode plate 111 and the second electrode plate 112 are arranged opposite to each other in a second direction, that is, forming a vertical capacitor structure.

[0062] For details on the formation process, please refer to the following specific implementation methods. Figure 5 , Figure 5 This is a flowchart illustrating a first embodiment of the method for manufacturing the display panel according to this application. For further details on the specific implementation method, please refer to [link to relevant documentation]. Figure 3 The structure within. For example... Figure 5 As shown, it specifically includes:

[0063] Step S41: Provide a substrate.

[0064] Step S42: Fabricate a buffer layer on the surface of the substrate.

[0065] Step S43: Fabricate a gate insulating layer on the surface of the buffer layer.

[0066] Prior to this step, a partial active layer is fabricated at the location corresponding to the thin-film transistor. Figure 3 (not shown in the image), wherein the active layer is positioned away from the storage capacitor to facilitate the subsequent formation of a thin-film transistor.

[0067] Step S44: Open the first groove and the second groove at the preset position of the gate insulating layer.

[0068] The first and second grooves are respectively provided with a first electrode plate 111 and a second electrode portion 112, which are not shown in the figure. The first and second grooves sequentially penetrate the gate insulating layer 33 and at least a portion of the buffer layer 32. The depth of the first and second grooves is designed according to the capacitance of the storage capacitor 11.

[0069] Step S45: Fabricate storage capacitors on the surface of the first groove, the second groove, and the gate insulating layer.

[0070] The storage capacitor 11 includes a first electrode plate 111 and a second electrode plate 112, which are spaced apart in the horizontal direction.

[0071] This step specifically includes: fabricating a first metal layer G on the surface of the first and second recesses and the gate insulating layer 33; and using a photolithography + etching process to pattern the first metal layer G to form the first electrode plate 111 and the second electrode plate 112 of the storage capacitor 11. The second electrode portion of the first electrode plate 111 is disposed within the first recess, and the first electrode portion is disposed on the surface of the gate insulating layer 33. The fourth electrode portion of the second electrode plate 112 is disposed within the second recess, and the third electrode portion is disposed on the surface of the gate insulating layer 33. The first and third electrode portions are disposed on the same layer and spaced apart, respectively connected to different electrodes.

[0072] This step also includes simultaneously fabricating a first metal layer G for the thin-film transistor, such that the material of the storage capacitor 11 is the same as that of the first metal layer G. The first metal layer G forms the gate of the thin-film transistor.

[0073] In one embodiment, the second electrode portion fills a portion of the first groove, and the fourth electrode portion fills a portion of the second groove.

[0074] This step also includes etching away the remaining first metal layers except for the first metal layer of the storage capacitor and the first metal layer of the thin-film transistor.

[0075] Following this step, the process further includes sequentially covering the surfaces of the first electrode plate 111 and the second electrode plate 112 of the storage capacitor 11 with an interlayer insulating layer 34, a first passivation layer 35, and a second passivation layer 36, which are not limited here. After fabricating the interlayer insulating layer, the process further includes fabricating a corresponding second metal layer at the thin-film transistor, so that the second metal layer forms the source and drain of the thin-film transistor, respectively.

[0076] This application also provides another method for manufacturing a display panel. Figure 6 This is a schematic flowchart illustrating a second embodiment of the method for manufacturing the display panel according to this application. Its structure can be referred to... Figure 3 .like Figure 6 As shown, it includes:

[0077] Step S51: Provide a substrate.

[0078] Step S52: Fabricate a buffer layer on the surface of the substrate.

[0079] Step S53: Fabricate a gate insulating layer on the surface of the buffer layer.

[0080] Prior to this step, an active layer is fabricated at the location of the corresponding thin-film transistor. The active layer is positioned away from the storage capacitor to facilitate the subsequent formation of the thin-film transistor.

[0081] Step S54: Fabricate a first metal layer and an interlayer insulating layer on the surface of the gate insulating layer.

[0082] The first metal layer G is positioned away from the storage capacitor 11, and the first metal layer G covers part of the surface of the gate insulating layer 33 to form the gate layer of the thin film transistor.

[0083] The interlayer insulating layer 34 covers the entire surface of the gate insulating layer 33 and the first metal layer G.

[0084] Step S55: Create a first groove and a second groove on the interlayer insulation layer.

[0085] The first and second grooves sequentially penetrate the interlayer insulating layer 34, the gate insulating layer 33, and at least a portion of the buffer layer 32. The depth of the first and second grooves is designed based on the capacitance of the storage capacitor.

[0086] Step S56: Fabricate storage capacitors on the surfaces of the first groove, the second groove, and the interlayer insulating layer.

[0087] The storage capacitor 11 includes a first electrode plate 111 and a second electrode plate 112, which are spaced apart.

[0088] This step specifically includes: fabricating a second metal layer on the surface of the first and second grooves and the interlayer insulating layer 34; and using a photolithography + etching process to pattern the second metal layer to form the first electrode plate 111 and the second electrode plate 112 of the storage capacitor 11. The second electrode portion of the first electrode plate 111 is disposed within the first groove, and the first electrode portion is disposed on the surface of the interlayer insulating layer. The fourth electrode portion of the second electrode plate 112 is disposed within the second groove, and the third electrode portion is disposed on the surface of the interlayer insulating layer. The first and third electrode portions are disposed on the same layer and spaced apart, respectively connected to different electrodes.

[0089] This step also includes fabricating a second metal layer at the location of the thin-film transistor to form the source and drain of the thin-film transistor.

[0090] This step also includes etching away the second metal layer in areas other than the storage capacitor and the thin-film crystal layer.

[0091] Following this step, the process also includes: forming a first passivation layer 35, a second passivation layer 36, and a pixel electrode layer 37 on the surfaces of the first electrode plate 111 and the second electrode plate 112 of the storage capacitor 11, etc., which are not limited here.

[0092] This application also provides another method for manufacturing a display panel. Figure 7 This is a schematic flowchart illustrating a second embodiment of the method for manufacturing the display panel according to this application. Its structure can be referred to... Figure 3 .like Figure 7 As shown, it includes:

[0093] Step S61: Provide a substrate.

[0094] Step S62: Fabricate a buffer layer on the surface of the substrate.

[0095] Step S63: Fabricate a gate insulating layer on the surface of the buffer layer.

[0096] Prior to this step, an active layer is fabricated at the location of the corresponding thin-film transistor. The active layer is positioned away from the storage capacitor to facilitate the subsequent formation of the thin-film transistor.

[0097] Step S64: Fabricate a first metal layer and a first interlayer insulating layer on the surface of the gate insulating layer.

[0098] The first metal layer is positioned away from the storage capacitor and covers a portion of the surface of the gate insulating layer to form the gate layer of the thin-film transistor.

[0099] First interlayer insulation layer ( Figure 3(Not specifically shown) It covers the entire surface of the gate insulating layer 33 and the first metal layer G. The first interlayer insulating layer refers to a portion of the interlayer insulating layer 34.

[0100] Step S65: Create a first groove and a second groove on the first interlayer insulation layer.

[0101] The first and second grooves sequentially penetrate the first interlayer insulating layer, the gate insulating layer 33, and at least a portion of the buffer layer 32. The depth of the first and second grooves is designed based on the capacitance of the storage capacitor.

[0102] Step S66: Fabricate storage capacitors on the surfaces of the first groove, the second groove, and the first interlayer insulating layer.

[0103] The storage capacitor 11 includes a first electrode plate 111 and a second electrode plate 112, which are spaced apart.

[0104] This step is followed by the fabrication of a second interlayer insulation layer on the surface of the first interlayer insulation layer to form interlayer insulation layer 34.

[0105] This step specifically includes: fabricating a metal layer on the surface of the first groove, the second groove, and the first interlayer insulating layer; and using a photolithography + etching process to pattern the metal layer to form the first electrode plate 111 and the second electrode plate 112 of the storage capacitor 11. The second electrode portion of the first electrode plate 111 is disposed within the first groove, and the first electrode portion is disposed on the surface of the first interlayer insulating layer. The fourth electrode portion of the second electrode plate 112 is disposed within the second groove, and the third electrode portion is disposed on the surface of the first interlayer insulating layer. The first electrode portion and the third electrode portion are disposed on the same layer and spaced apart, respectively connected to different electrodes.

[0106] This step also includes fabricating a second metal layer at the location of the thin-film transistor to form the source (S) and drain (D) of the thin-film transistor.

[0107] This step also includes etching away the metal layer in areas other than the storage capacitor and the thin-film crystal layer.

[0108] Step S67: Create a second interlayer insulating layer on the surface of the storage capacitor.

[0109] Specifically, a second interlayer insulating layer is formed on the surface of the first electrode plate and the second electrode plate of the storage capacitor, and a second interlayer insulating layer is formed in the first groove and the second groove.

[0110] This step also includes fabricating a first passivation layer 35, a second passivation layer 36, and a pixel electrode layer 301 on the surface of the second interlayer insulating layer, which is not limited here.

[0111] The materials of the first interlayer insulation layer and the second interlayer insulation layer can be the same or different, and no limitation is made here.

[0112] The beneficial effect of this embodiment is that by changing the spacing between the first and second electrode plates of the storage capacitor from the original spacing in the first direction to a spacing in the second direction, the metal surface area projected by the storage capacitor in the vertical direction is reduced, thereby improving the light transmittance of the storage capacitor. Furthermore, the height of the first and second electrode plates of the storage capacitor can be achieved through different film layer structures. They can be formed in the gate insulating layer, in the interlayer insulating layer, in the middle layer of the interlayer insulating layer, or between the first and second passivation layers. In other words, the electrode plates of the storage capacitor can be made of different metal layers, and the appropriate film layer can be selected based on the capacitance requirements of the storage capacitor.

[0113] The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display panel, characterized by, The display panel comprises a first display surface and a second display surface arranged opposite to each other; The display panel comprises a plurality of storage capacitors; in a second direction perpendicular to a first direction in which the first display surface points to the second display surface, the storage capacitors comprise a first electrode plate and a second electrode plate arranged opposite to each other; The first electrode plate comprises a first electrode part and a second electrode part connected to each other, and the first electrode part and the second electrode part form an included angle; the second electrode plate comprises a third electrode part and a fourth electrode part connected to each other, and the third electrode part and the fourth electrode part form an included angle; The first electrode part and the third electrode part of the same storage capacitor are arranged on the same layer of a first metal layer; or, the first electrode part and the third electrode part of the same storage capacitor are arranged on the same layer of a second metal layer; the first metal layer forms a gate layer of a thin film transistor, and the second metal layer is arranged in a spaced manner to form a source and a drain of the thin film transistor.

2. The display panel of claim 1, wherein In the second direction, the first electrode part and the third electrode part in the same storage capacitor are arranged in parallel and in a spaced manner, the first electrode part and the third electrode part are arranged on the same layer, and the second electrode part and the fourth electrode part are arranged in a spaced manner.

3. The display panel of claim 2, wherein The distance between the second electrode part and the fourth electrode part in the same storage capacitor gradually decreases in the first direction.

4. The display panel of claim 2, wherein, The second electrode part and the first electrode part are connected perpendicularly, the third electrode part and the fourth electrode part are connected perpendicularly, and the second electrode part and the fourth electrode part are arranged in parallel.

5. The display panel of any one of claims 2-4, wherein In the first direction, the display panel comprises an array substrate comprising a plurality of film layers arranged in a stacked manner; At least some of the film layers in the plurality of film layers are provided with a first recess at a position corresponding to the first electrode plate, at least some of the film layers in the plurality of film layers are provided with a second recess at a position corresponding to the second electrode plate, the first electrode plate fills at least part of the first recess, and the second electrode plate fills at least part of the second recess.

6. The display panel of claim 5, wherein The plurality of film layers comprises an interval film layer between adjacent first recesses and second recesses; The second electrode part fills at least part of the first recess, and the first electrode part is located on the surface of the interval film layer; the fourth electrode part fills at least part of the second recess, and the third electrode part is located on the surface of the interval film layer.

7. The display panel of claim 6, wherein The second electrode part fills part of the first recess, and a first interval is formed between the side wall of the first recess and the side of the second electrode part away from the fourth electrode part; and / or, The fourth electrode part fills part of the second groove, and a second interval is formed between the side wall of the second groove and the side of the fourth electrode part away from the second electrode part.

8. The display panel of claim 5, wherein, In the first direction, the plurality of film layers include a substrate layer, a buffer layer, a gate insulating layer, a first metal layer, an interlayer insulating layer, and a second metal layer which are stacked. The material of the storage capacitor is the same as that of the first metal layer, and one end of the first groove and the second groove penetrates the gate insulating layer in the first direction. Alternatively, the material of the storage capacitor is the same as that of the second metal layer, and one end of the first groove and the second groove penetrates the interlayer insulating layer in the first direction. In the first direction, the other end of the first groove and the second groove extends into the substrate layer. The side of the substrate layer away from the second metal layer is a first display surface, and the side of the second metal layer away from the substrate layer is a second display surface. In the first direction, the first groove and / or the second groove is a reverse trapezoidal groove.

9. A method for manufacturing a display panel, characterized by, Comprising: providing a substrate; forming a plurality of storage capacitors on the substrate; wherein the substrate comprises a first display surface and a second display surface arranged opposite to each other; in a second direction perpendicular to a first direction in which the first display surface points to the second display surface, the storage capacitor comprises a first electrode plate and a second electrode plate arranged opposite to each other; wherein the first electrode plate comprises a first electrode part and a second electrode part connected to each other, and the second electrode part and the second electrode part have an included angle therebetween, and the second electrode plate comprises a third electrode part and a fourth electrode part connected to each other, and the third electrode part and the fourth electrode part have an included angle therebetween; the first electrode part and the third electrode part of the same storage capacitor are arranged in the same layer as a first metal layer; or, the first electrode part and the third electrode part of the same storage capacitor are arranged in the same layer as a second metal layer; wherein the first metal layer forms a gate layer of a thin film transistor, and the second metal layer is arranged in an interval to form a source and a drain of a thin film transistor.

10. The method of manufacturing a display panel according to claim 9, wherein, The step of forming a plurality of storage capacitors on the substrate comprises: sequentially stacking a substrate layer, a buffer layer, a gate insulating layer, a first metal layer, an interlayer insulating layer, and a second metal layer on the substrate; opening a first groove and a second groove in the gate insulating layer respectively, and manufacturing the storage capacitor on the surface of the first groove, the second groove, and the gate insulating layer, so that the material of the storage capacitor is the same as that of the first metal layer; or, opening a first groove and a second groove in the interlayer insulating layer respectively, and manufacturing the storage capacitor on the surface of the first groove, the second groove, and the interlayer insulating layer, so that the material of the storage capacitor is the same as that of the second metal layer.

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