A TVS device and a manufacturing method thereof

Abstract

The application discloses a TVS device and a manufacturing method thereof. The TVS device comprises an N-type substrate, an N-type buried layer arranged on one side of the N-type substrate, and an N-epitaxial layer arranged on a side of the N-type buried layer away from the N-type substrate. The N-epitaxial layer is provided with a P well and at least one N-type deep well. The N-type deep well penetrates the N-epitaxial layer. The surface of the P well away from the N-type substrate is flush with the surface of the N-epitaxial layer away from the N-type substrate. The depth of the P well is less than the thickness of the N-epitaxial layer. The N-type deep well and the P well are both provided with an N+ region. The N+ region is flush with the surface of the N-type deep well and the P well away from the N-type substrate. The depth of the N+ region is less than the depth of the P well. The embodiment of the application realizes the manufacturing of a TVS diode and a PIN tube in the same device, does not need to occupy the wiring space of a circuit, and can reduce the capacitance of the TVS device and improve the clamping characteristic.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a TVS device and a manufacturing method thereof. BACKGROUND

[0002] According to Moore's Law, the number of transistors on an integrated circuit doubles approximately every eighteen months. And the constant miniaturization of transistors can make ICs have more complex functions in the same layout. As CMOS processes are miniaturized with manufacturing precision, the gate dielectric layer (SiO2) needs to be made thinner and thinner, which makes the anti-static ability of ICs weaker and weaker. In this case, if appropriate protection is not done, the ICs will be easily damaged. Therefore, protection devices represented by TVS (Transient Voltage Suppressor) are widely used in various I / O interfaces. In the normal state, the TVS diode is in an open circuit state and will not interfere with the normal work of the back-end IC, but when static electricity or surges are generated in the peripheral circuit, the TVS diode will break down at a picosecond level, instantaneously releasing the current and clamping the voltage of the back-end IC in a safe voltage range.

[0003] In actual application process, the capacitance characteristic and clamping characteristic of the TVS diode are two key indicators for examining the performance of the device. Taking HDMI (High-Definition Multimedia Interface) as an example, the transmission rate of high-speed interface is getting faster and faster, even up to 3GHz, which requires the capacitance of the TVS diode to be less than 0.3pf. Only such ultra-low capacitance can protect the signals on each signal line of the interface from being lost. In addition, the clamping characteristic of the TVS diode will directly affect the voltage borne by the corresponding port of the back-end IC when it is disturbed externally. If the clamping characteristic of the TVS diode is poor, the situation that the back-end IC is still damaged after the TVS diode is not damaged when encountering external interference may occur.

[0004] The traditional implementation method of the low-capacitance TVS diode will parallelly connect an ultra-low-capacitance TVS diode to each signal end, and the TVS diode needs to be connected in series with an ultra-low-capacitance PIN diode to realize a capacitance as low as 0.3pF, so the cost of this protection scheme is high, and a large amount of space of circuit layout is occupied. The clamping characteristic of the TVS diode is mainly affected by the bulk resistance of the TVS diode. The traditional implementation method of the TVS diode mostly adopts the method of manufacturing a positive electrode and a negative electrode on the front surface and the back surface of a wafer respectively. Although this method is simple in process, it is greatly affected by the thickness of the wafer, and the clamping voltage is usually high. SUMMARY

[0005] The application provides a TVS device and a manufacturing method thereof, which can realize manufacturing of a TVS diode and a PIN tube in the same device, occupy no wiring space of a circuit, reduce the capacitance of the TVS device, and improve the clamping characteristic.

[0006] According to an aspect of the application, a TVS device is provided, which comprises:

[0007] an N-type substrate;

[0008] an N-type buried layer arranged on one side of the N-type substrate;

[0009] an N-epitaxial layer arranged on the side of the N-type buried layer away from the N-type substrate; the N-epitaxial layer is provided with a P well and at least one N-type deep well, the N-type deep well penetrates the N-epitaxial layer, the surface of the P well away from the N-type substrate is flush with the surface of the N-epitaxial layer away from the N-type substrate, and the depth of the P well is less than the thickness of the N-epitaxial layer;

[0010] N+ regions are arranged in the N-type deep well and the P well, the N+ regions are flush with the surfaces of the N-type deep well and the P well away from the N-type substrate, and the depth of the N+ regions is less than the depth of the P well.

[0011] Optionally, the TVS device further comprises:

[0012] an oxide layer and a metal layer, the oxide layer is arranged on the side of the N-epitaxial layer away from the N-type substrate; the oxide layer covers the N-epitaxial layer, the N-type deep well, the P well and the N+ regions, and the oxide layer is provided with a first through hole and a second through hole, the first through hole exposes at least part of the N+ regions in the N-type deep well, and the second through hole exposes at least part of the N+ regions in the P well;

[0013] the metal layer is arranged on the side of the oxide layer away from the N-type substrate, the metal layer comprises a first metal block and a second metal block, and the first metal block and the second metal block are insulated from each other;

[0014] the first metal block is in contact with the N+ regions in the N-type deep well through the first through hole, and the second metal block is in contact with the N+ regions in the P well through the second through hole.

[0015] Optionally, the N-epitaxial layer is provided with one P well and two N-type deep wells, and the two N-type deep wells are located on the two sides of the P well.

[0016] Optionally, the N-epitaxial layer is provided with a first deep groove and a second deep groove;

[0017] The first deep trench is arranged between the P well and the N-type deep well, and the first deep trench surrounds the P well, and the second deep trench surrounds the P well and the at least one N-type deep well;

[0018] The first deep trench and the second deep trench both penetrate the N-epitaxial layer, the N-type buried layer and part of the N-type substrate;

[0019] The first deep trench and the second deep trench are filled with silicon dioxide.

[0020] Optionally, the depth of the first deep trench and the second deep trench is greater than or equal to 15 um.

[0021] Optionally, the thickness of the N-type substrate is 100-200 um, and the depth of the N+ region is 2-3 um.

[0022] The thickness of the N-epitaxial layer is 5-10 um, and the resistivity is 1000-3000 Ohm·cm.

[0023] The thickness of the oxide layer is 0.8-1.5 um, and the thickness of the metal layer is 2-6 um.

[0024] Optionally, the doping material of the N-type buried layer includes As, the doping material of the P well includes B, the doping material of the N-type deep well includes P, and the doping material of the N+ region includes P.

[0025] The material of the metal layer includes AlSiCu.

[0026] According to another aspect of the present application, a manufacturing method of a TVS device is provided, comprising:

[0027] Providing an N-type substrate;

[0028] Performing N-type buried layer general injection on one side of the N-type substrate to form an N-type buried layer;

[0029] Forming an N-epitaxial layer on the side of the N-type buried layer away from the N-type substrate;

[0030] Forming a P well and at least one N-type deep well in the N-epitaxial layer, the N-type deep well penetrating the N-epitaxial layer, the surface of the P well away from the N-type substrate being flush with the surface of the N-epitaxial layer away from the N-type substrate, and the depth of the P well being less than the thickness of the N-epitaxial layer;

[0031] Forming an N+ region in the N-type deep well and the P well, the N+ region being flush with the surface of the N-type deep well and the P well away from the N-type substrate, and the depth of the N+ region being less than the depth of the P well.

[0032] Optionally, after setting the N+ region in the N-type deep well and the P-well, the method further includes:

[0033] A first deep trench and a second deep trench are formed in the N-epitaxial layer; wherein the first deep trench is disposed between the P-well and the N-type deep well, and the first deep trench surrounds the P-well, and the second deep trench surrounds the P-well and the at least one N-type deep well; both the first deep trench and the second deep trench penetrate the N-epitaxial layer, the N-type buried layer and a portion of the N-type substrate;

[0034] The first and second deep trenches are filled with silicon dioxide.

[0035] Optionally, after filling the first and second deep trenches with silicon dioxide, the method further includes:

[0036] An oxide layer is formed on the side of the N-epitaxial layer away from the N-type substrate; the oxide layer covers the N-epitaxial layer, the N-type deep well, the P-well, and the N+ region, and the oxide layer is provided with a first via and a second via, the first via exposing at least a portion of the N+ region in the N-type deep well, and the second via exposing at least a portion of the N+ region in the P-well;

[0037] A metal layer is formed on the side of the oxide layer away from the N-type substrate. The metal layer includes a first metal block and a second metal block. The first metal block and the second metal block are insulated from each other. The first metal block is in contact with the N+ region in the N-type deep well through the first via, and the second metal block is in contact with the N+ region in the P-well through the second via.

[0038] Thinning of the N-type substrate.

[0039] This invention integrates the structure of a TVS diode and a PIN switch into a single die, reducing the overall capacitance of the device. Furthermore, the PIN switch does not require additional wiring space in the circuit. The combination of buried layer and deep well processes allows the positive and negative electrodes to be located on the front side of the chip, overcoming the drawback of having to bring the negative electrode out from the back of the chip. This reduces the device's bulk resistance, thereby lowering the clamping voltage and improving clamping characteristics.

[0040] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiments description. Obviously, the drawings in the following description only show some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without any creative effort.

[0042] Figure 1 is a schematic diagram of a TVS device provided by an embodiment of the present application;

[0043] Figure 2 is a flow chart of a manufacturing method of a TVS device provided by an embodiment of the present application;

[0044] Figure 3 is a flow chart of a manufacturing method of a TVS device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the technical personnel in the art better understand the present application scheme, the following will combine the drawings in the embodiments of the present application, and the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort should be within the scope of protection of the present application.

[0046] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to include those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0047] The embodiments of the present application provide a TVS device, Figure 1 is a schematic diagram of a TVS device provided by an embodiment of the present application, referring to Figure 1 The TVS device comprises:

[0048] N-type substrate 10;

[0049] N-type buried layer 20 arranged on one side of the N-type substrate 10;

[0050] An N-epitaxial layer 30 is arranged on the side of the N-type buried layer 20 away from the N-type substrate 10; the N-epitaxial layer 30 is provided with a P well 40 and at least one N-type deep well 50, the N-type deep well 50 penetrates the N-epitaxial layer 30, the surface of the P well 40 away from the N-type substrate 10 is flush with the surface of the N-epitaxial layer 30 away from the N-type substrate 10, and the depth of the P well is less than the thickness of the N-epitaxial layer;

[0051] N+ regions 60 are arranged in the N-type deep well 50 and the P well 40, the N+ regions 60 are flush with the surface of the N-type deep well 50 and the P well 40 away from the N-type substrate 10, and the depth of the N+ regions 60 is less than the depth of the P well 40.

[0052] Specifically, the N-type substrate 10 can be a <100> crystal direction N-type substrate wafer, and the resistivity can be 10-30 Ohm·cm. N-type buried layer implantation can be performed on the N-type substrate 10, the implanted element is As, the concentration is about 1E15-5E15 per square centimeter, the energy is 70 KeV, the N-type buried layer 20 is formed, and the N-type buried layer is referred to as BN. The N-epitaxial layer 30 can be a super-high resistance epitaxial N-. N-type deep well diffusion can be performed on the specified area of the N-epitaxial layer 30 to form the N-type deep well 50, the N-type deep well 50 needs to be expanded through the thickness of the N-epitaxial layer 30 and connected with the N-type buried layer 20, so that the N-type deep well 50 and the N-type buried layer 20 jointly constitute an N-type current channel, and the N-type deep well 50 is referred to as DN. P well implantation can be performed on the specified area of the N-epitaxial layer 30, the implanted element is B, the concentration is about 1E15-5E15 per square centimeter, the energy is 70 KeV, the P well 40 is formed, and the P well 40 is referred to as PW. N+ ion implantation is performed in the P well 40 and the N-type deep well 50, the implanted element is P, the concentration is about 1E15-5E15 per square centimeter, the energy is 70 KeV, the N+ region 60 is formed, and the N+ region 60 is referred to as SN. The furnace tube can be advanced to advance the SN and the PW to the specified depth.

[0053] The PN junction of the SN (N+ region 60) and the PW (P well 40) is the PN junction of the TVS diode, which determines the breakdown voltage of the TVS diode. The PW (P well 40), the N-epitaxial layer 30, and the BN (N-type buried layer 20) form the structure of a PIN switch tube, and the capacitance of the switch tube is about 0.3 pF, which plays a role in reducing the capacitance in the entire device structure. The N+ region 60 in the N-type deep well 50 is used to connect the first electrode of the device, and the N+ region 60 in the P well 40 is used to connect the second electrode of the device.

[0054] The embodiment of the application designs the structure of the TVS diode and the PIN switch tube in one die, reduces the capacitance of the whole device, sets the PIN switch tube without occupying the wiring space of the circuit, and through the combination of the buried layer and the deep well process, sets the positive and negative electrodes of the device on the front surface of the chip, overcomes the disadvantage that the negative electrode must be led out from the back surface of the chip, reduces the bulk resistance of the device, thereby reduces the clamping voltage of the device and improves the clamping characteristic. In addition, the N-epitaxial layer adopts the super-high resistance epitaxy, which can further reduce the capacitance of the device.

[0055] Optionally, referring to Figure 1 , the TVS device further comprises:

[0056] The oxide layer 70 and the metal layer 80, the oxide layer 70 is arranged on the side of the N-epitaxial layer 30 away from the N-type substrate 10; the oxide layer 40 covers the N-epitaxial layer 30, the N-type deep well 50, the P well 40 and the N+ region 60, and the oxide layer 70 is provided with a first through hole 71 and a second through hole 72, the first through hole 71 exposes at least part of the N+ region 60 in the N-type deep well 50, and the second through hole 72 exposes at least part of the N+ region 60 in the P well 40;

[0057] The metal layer 80 is arranged on the side of the oxide layer 70 away from the N-type substrate 10, and the metal layer 80 comprises a first metal block 81 and a second metal block 82, and the first metal block 81 and the second metal block 82 are insulated from each other;

[0058] The first metal block 81 is in contact with the N+ region 60 in the N-type deep well 50 through the first through hole 71, and the second metal block 82 is in contact with the N+ region 60 in the P well 40 through the second through hole 72.

[0059] Specifically, the oxide layer 70 plays an insulating and protective role, the first metal block 81 and the second metal block 82 are respectively the first electrode and the second electrode of the device, and the N-type buried layer 20 and the N-type deep well 50 are arranged in the embodiment, so that the negative electrode of the device can be led out from the same side as the positive electrode, the bulk resistance of the device is reduced, thereby the clamping voltage of the device is reduced and the clamping characteristic is improved.

[0060] In addition, SN is a shallow N+ region, the SN (N+ region 60) generally has a shallow junction depth of 2-3 um and a high doping concentration, the SN (N+ region 60) in the DN (N-type deep well 50) plays a role of connecting the DN (N-type deep well 50) and the first metal block 81 in series, and reduces the contact resistance of the metal directly contacting the DN (N-type deep well 50).

[0061] Optionally, referring to Figure 1 , the N-epitaxial layer 30 is provided with one P well 40 and two N-type deep wells 50, and the two N-type deep wells 50 are located on the two sides of the P well 40.

[0062] Specifically, two N-type deep wells 50 can realize that a single TVS device protects two high-speed ports, and improves the integration of the device.

[0063] Optionally, the N-epitaxial layer 30 is provided with a first deep trench 91 and a second deep trench 92.

[0064] The first deep trench 91 is arranged between the P-well 40 and the N-type deep well 50, and the first deep trench 91 surrounds the P-well 40, and the second deep trench 92 surrounds the P-well 40 and at least one N-type deep well 50; the first deep trench 91 and the second deep trench 92 both penetrate the N-epitaxial layer 30, the N-type buried layer 20 and part of the N-type substrate 10; the first deep trench 91 and the second deep trench 92 are filled with silicon dioxide.

[0065] Specifically, the first deep trench 91 and the second deep trench 92 play a role in device isolation and reduce leakage. The first deep trench 91 and the second deep trench 92 can be formed by dry etching.

[0066] Optionally, the depth of the first deep trench 91 and the second deep trench 92 is greater than or equal to 15 um.

[0067] In this way, the first deep trench 91 and the second deep trench 92 can penetrate the N-epitaxial layer 30, the N-type buried layer 20 and part of the N-type substrate 10, and better play a role in device isolation.

[0068] Optionally, the thickness of the N-type substrate 10 is 100-200 um; the thickness of the N-epitaxial layer 30 is 5-10 um, and the resistivity of the N-epitaxial layer 30 is 1000-3000 Ohm·cm; the thickness of the oxide layer 70 is 0.8-1.5 um, and the thickness of the metal layer 80 is 2-6 um.

[0069] Specifically, the thickness of the N-type substrate 10 is 100-200 um, which can adapt to most packaging thicknesses. For example, the thickness of the N-type substrate 10 can be 150 um. The thickness of the N-epitaxial layer 30 is 5-10 um, and the resistivity is 1000-3000 Ohm·cm, so that the device has smaller capacitance. The thickness of the oxide layer 70 is 0.8-1.5 um, which on the one hand reduces the process difficulty, and on the other hand can better play a role in insulation protection. For example, the thickness of the oxide layer 70 can be 1.2 um. The thickness of the metal layer 80 is 2-6 um, which on the one hand reduces the process difficulty, and on the other hand can better transmit signals and reduce resistance. For example, the thickness of the metal layer can be 4 um.

[0070] Optionally, the doping material of the N-type buried layer 20 includes As, the doping material of the P-well 40 includes B, the doping material of the N-type deep well 50 includes P, and the doping material of the N+ region 60 includes P; the material of the metal layer 80 includes AlSiCu.

[0071] The application also provides a manufacturing method of the TVS device, Figure 2 is a flow chart of the manufacturing method of the TVS device provided by the application, referring to Figure 2 The method comprises the following steps.

[0072] S110, providing an N-type substrate.

[0073] S120, performing N-type buried layer general injection on one side of the N-type substrate to form an N-type buried layer.

[0074] S130, forming an N-epitaxial layer on the side of the N-type buried layer away from the N-type substrate.

[0075] S140, forming a P well and at least one N-type deep well in the N-epitaxial layer, the N-type deep well penetrating the N-epitaxial layer, the P well being flush with the surface of the N-epitaxial layer away from the N-type substrate, and the depth of the P well being less than the thickness of the N-epitaxial layer.

[0076] Specifically, the N-type deep well is mainly formed by Pocl3 phosphorus diffusion, Pocl3 is decomposed into PCl5 and P2O5 at high temperature, P2O5 reacts with silicon at high temperature to generate silicon dioxide and P atoms, and the P atoms form the N-type deep well during the high-temperature propulsion process.

[0077] S150, setting an N+ region in the N-type deep well and the P well, the N+ region being flush with the surface of the N-type deep well and the P well away from the N-type substrate, and the depth of the N+ region being less than the depth of the P well.

[0078] The application designs the structures of the TVS diode and the PIN switch tube in one die, reduces the capacitance of the whole device, sets the PIN switch tube without occupying the wiring space of the circuit, and arranges the positive and negative electrodes of the device on the front surface of the chip through the combination of the buried layer and the deep well process, so that the disadvantages of the negative electrode being necessarily led out from the back surface of the chip are overcome, the bulk resistance of the device is reduced, the clamping voltage of the device is reduced, and the clamping characteristics are improved. In addition, the N-epitaxial layer adopts the super-high resistance epitaxy, and the capacitance of the device can be further reduced.

[0079] Optionally, after the N+ region is set in the N-type deep well and the P well, the method further comprises the following steps.

[0080] forming a first deep trench and a second deep trench in the N-epitaxial layer; wherein the first deep trench is arranged between the P well and the N-type deep well, and the first deep trench surrounds the P well, the second deep trench surrounds the P well and the at least one N-type deep well, and the first deep trench and the second deep trench both penetrate the N-epitaxial layer, the N-type buried layer and part of the N-type substrate;

[0081] filling the first deep trench and the second deep trench with silicon dioxide.

[0082] Figure 3 is a flow chart of a method for manufacturing a TVS device provided by an embodiment of the present application, which comprises:

[0083] S110, providing an N-type substrate.

[0084] S120, performing N-type buried layer general injection on one side of the N-type substrate to form an N-type buried layer.

[0085] S130, forming an N-epitaxial layer on the side of the N-type buried layer away from the N-type substrate.

[0086] S140, forming a P-well and at least one N-type deep well in the N-epitaxial layer, the N-type deep well penetrating the N-epitaxial layer, the surface of the P-well away from the N-type substrate being flush with the surface of the N-epitaxial layer away from the N-type substrate, and the depth of the P-well being less than the thickness of the N-epitaxial layer.

[0087] S150, setting an N+ region in the N-type deep well and the P-well, the N+ region being flush with the surface of the N-type deep well and the P-well away from the N-type substrate, and the depth of the N+ region being less than the depth of the P-well.

[0088] S160, forming a first deep trench and a second deep trench in the N-epitaxial layer; wherein the first deep trench is arranged between the P-well and the N-type deep well, and the first deep trench is arranged around the P-well, the second deep trench is arranged around the P-well and the at least one N-type deep well; the first deep trench and the second deep trench both penetrate the N-epitaxial layer, the N-type buried layer and part of the N-type substrate.

[0089] S170, filling silicon dioxide in the first deep trench and the second deep trench.

[0090] S180, forming an oxide layer on the side of the N-epitaxial layer away from the N-type substrate; the oxide layer covers the N-epitaxial layer, the N-type deep well, the P-well and the N+ region, and the oxide layer is provided with a first through hole and a second through hole, the first through hole exposing at least part of the N+ region in the N-type deep well, and the second through hole exposing at least part of the N+ region in the P-well.

[0091] S190, forming a metal layer on the side of the oxide layer away from the N-type substrate, the metal layer comprising a first metal block and a second metal block, the first metal block and the second metal block being insulated from each other, the first metal block being in contact with the N+ region in the N-type deep well through the first through hole, and the second metal block being in contact with the N+ region in the P-well through the second through hole.

[0092] S200, thinning the N-type substrate.

[0093] The method for manufacturing a TVS device and the TVS device provided by the embodiment of the present application belong to the same inventive concept and have corresponding beneficial effects, and the TVS device provided by any embodiment of the present application is described in detail.

[0094] It should be understood that the various forms of flow shown above can be used to reorder, add, or remove steps. For example, the steps recited in the present application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0095] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A TVS device, characterized by, Comprise: N-type substrate; N-type buried layer disposed on one side of the N-type substrate; N-epitaxial layer disposed on the side of the N-type buried layer away from the N-type substrate; the N-epitaxial layer is provided with a P well and at least one N-type deep well, the N-type deep well penetrates the N-epitaxial layer, the surface of the P well away from the N-type substrate is flush with the surface of the N-epitaxial layer away from the N-type substrate, and the depth of the P well is less than the thickness of the N-epitaxial layer; The N+ region is flush with the surface of the N-type deep well and the P well away from the N-type substrate, and the depth of the N+ region is less than the depth of the P well; The N-epitaxial layer is provided with a first deep trench and a second deep trench; The first deep trench is disposed between the P well and the N-type deep well, and the first deep trench is disposed around the P well, and the second deep trench is disposed around the P well and the at least one N-type deep well; The first deep trench and the second deep trench both penetrate the N-epitaxial layer, the N-type buried layer and part of the N-type substrate; The first deep trench and the second deep trench are filled with silicon dioxide; The PN of the N+ region and the P well is the PN junction of the TVS diode, and the P well, the N-epitaxial layer and the N-type buried layer form a PIN switch tube structure.

2. The TVS device of claim 1, wherein, Also include: An oxide layer and a metal layer, the oxide layer is disposed on the side of the N-epitaxial layer away from the N-type substrate; the oxide layer covers the N-epitaxial layer, the N-type deep well, the P well and the N+ region, and the oxide layer is provided with a first through hole and a second through hole, the first through hole exposes at least part of the N+ region in the N-type deep well, and the second through hole exposes at least part of the N+ region in the P well; The metal layer is disposed on the side of the oxide layer away from the N-type substrate, and the metal layer comprises a first metal block and a second metal block, and the first metal block and the second metal block are insulated from each other; The first metal block contacts the N+ region in the N-type deep well through the first through hole, and the second metal block contacts the N+ region in the P well through the second through hole.

3. The TVS device according to claim 1, wherein: The N-epitaxial layer is provided with one P well and two N-type deep wells, and the two N-type deep wells are located on both sides of the P well.

4. The TVS device according to claim 1, wherein: The depth of the first deep trench and the second deep trench is greater than or equal to 15 μm.

5. The TVS device according to claim 2, wherein: The thickness of the N-type substrate is 100-200 μm; the depth of the N+ region is 2-3 μm; The thickness of the N-epitaxial layer is 5-10 μm, and the resistivity is 1000-3000 Ohm·cm; The thickness of the oxide layer is 0.8-1.5 μm, and the thickness of the metal layer is 2-6 μm.

6. The TVS device according to claim 2, wherein: The doping material of the N-type buried layer comprises As, the doping material of the P well comprises B, the doping material of the N-type deep well comprises P, and the doping material of the N+ region comprises P; The material of the metal layer comprises AlSiCu.

7. A method of fabricating a TVS device, comprising: Comprise: An N-type substrate is provided; An N-type buried layer is formed on one side of the N-type substrate; An N-epitaxial layer is formed on the side of the N-type buried layer away from the N-type substrate; A P-well and at least one N-type deep well are formed in the N-epitaxial layer, the N-type deep well penetrates the N-epitaxial layer, the surface of the P-well away from the N-type substrate is flush with the surface of the N-epitaxial layer away from the N-type substrate, and the depth of the P-well is less than the thickness of the N-epitaxial layer; N+ regions are arranged in the N-type deep well and the P-well, the N+ regions are flush with the surface of the N-type deep well and the P-well away from the N-type substrate, and the depth of the N+ regions is less than the depth of the P-well; After the N+ regions are arranged in the N-type deep well and the P-well, further comprising: A first deep trench and a second deep trench are formed in the N-epitaxial layer; wherein the first deep trench is arranged between the P-well and the N-type deep well, and the first deep trench surrounds the P-well, the second deep trench surrounds the P-well and the at least one N-type deep well; the first deep trench and the second deep trench both penetrate the N-epitaxial layer, the N-type buried layer and part of the N-type substrate; Silicon dioxide is filled in the first deep trench and the second deep trench; The PN of the N+ regions and the P-well is the PN junction of the TVS diode, and the P-well, the N-epitaxial layer and the N-type buried layer form a PIN switch tube structure.

8. The method of claim 7, wherein, After the silicon dioxide is filled in the first deep trench and the second deep trench, further comprising: An oxide layer is formed on the side of the N-epitaxial layer away from the N-type substrate; the oxide layer covers the N-epitaxial layer, the N-type deep well, the P-well and the N+ regions, and the oxide layer is provided with a first through hole and a second through hole, the first through hole exposes at least part of the N+ regions in the N-type deep well, and the second through hole exposes at least part of the N+ regions in the P-well; A metal layer is formed on the side of the oxide layer away from the N-type substrate, the metal layer comprises a first metal block and a second metal block, the first metal block and the second metal block are insulated from each other, the first metal block contacts the N+ regions in the N-type deep well through the first through hole, and the second metal block contacts the N+ regions in the P-well through the second through hole; The N-type substrate is thinned.

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