A segmented ramp compensation circuit for a buck DCDC

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a segmented slope compensation circuit for a step-down DCDC, which comprises a slope compensation capacitor control circuit and a slope compensation circuit; the slope compensation capacitor control circuit is connected with the slope compensation circuit to form the segmented slope compensation circuit, wherein the slope compensation capacitor control circuit is used for controlling the capacitor size of the segmented slope compensation circuit, and the slope compensation circuit compensates a current signal according to the capacitor size; the application divides the slope compensation capacitor into four intervals, and the slope compensation amplitude gradually increases in the process of gradually increasing the duty cycle, so that the load capacity under the full duty cycle in the large-current DCDC can be improved, and the problem of slow speed caused by over-compensation under the low duty cycle can be inhibited.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a segmented slope compensation circuit for a buck DC-DC converter. Background Technology

[0002] A switching power supply is a type of power supply that maintains a stable output voltage, typically composed of a pulse width modulation (PWM) control IC and MOSFETs. With the development and innovation of power electronics technology, switching power supply technology is also constantly evolving. Currently, switching power supplies can be categorized based on the relationship between input and output voltage into buck converters, boost converters, and buck-boost converters. Buck converters can only perform buck conversion, while boost converters can only perform boost conversion. In the power switching field, due to the slow response speed of voltage-model DC-DC converters and the faster response speed of current-model DC-DC converters, the application of current-model DC-DC converters is becoming increasingly widespread. However, current-model DC-DC converters exhibit sub-slope oscillations when applied to power switching, reducing the stability of the power circuit loop. Therefore, slope compensation circuits are needed in power switching circuits. Traditional slope compensation circuits, due to their fixed compensation amplitude, can only compensate for a single current model scenario. For low duty cycle models, overcompensation can occur, reducing the loop response speed and load-carrying capacity. Summary of the Invention

[0003] To address the problems existing in the prior art, this invention proposes a segmented slope compensation circuit for a step-down DC-DC converter. The circuit includes a slope compensation capacitor control circuit and a slope compensation circuit. The slope compensation capacitor control circuit is connected to the slope compensation circuit to form a segmented slope compensation circuit. The slope compensation capacitor control circuit is used to control the capacitance of the segmented slope compensation circuit, and the slope compensation circuit compensates the current signal according to the capacitance value.

[0004] The slope compensation capacitor control circuit includes three comparators, seven NMOS transistors, and four capacitors. The positive terminals of comparators A1, A2, and A3 are all connected to FB, and their negative terminals are connected to the reference voltage input terminals VREF1, VREF2, and VREF3, respectively. The output terminal of comparator A1 is connected to the gate of MN6, the output terminal of comparator A2 is connected to the gate of MN4, and the output terminal of comparator A3 is connected to the gate of NM2. The source of MN1 is grounded, its gate is connected to the input terminal of the reference clock signal CLK, and its drain is connected to the drains of MN2, MN4, and MN6, as well as the positive terminal of capacitor C4. The source of MN2 is connected to the drain of MN3 and the positive terminal of capacitor C1, respectively; the gate of MN3 is connected to the input terminal of the clock signal CLK, and its source is grounded; the negative terminal of capacitor C1 is grounded; the source of MN4 is connected to the drain of MN5 and the positive terminal of capacitor C2, respectively; the gate of MN5 is connected to the input terminal of the clock signal CLK, and its source is grounded; the negative terminal of capacitor C2 is grounded; the source of MN6 is connected to the drain of MN7 and the positive terminal of capacitor C3, respectively; the gate of MN7 is connected to the input terminal of the clock signal CLK, and its source is grounded; the negative terminals of capacitors C3 and C4 are grounded, forming a slope compensation capacitor control circuit.

[0005] Preferably, the slope compensation circuit includes: four current sources, six PMOS transistors, nine PMOS transistors, and one resistor; the positive terminals of current source I1, current source IEA, current source I4, the sources of MP1, MP2, MP3, and MP4 are all connected to the power supply VDD; the negative terminal of current source I1 is connected to the gate of MP5; the gate of MP1 is connected to the drain of MP1, the gate of MP2, the gate of MP3, and the gate of MP4, respectively; the drain of MP1 is connected to the positive terminal of current source I2; the negative terminal of current source I2 is grounded; the gate of MP2 is connected to the positive terminal of MP1. After the gate is connected, it is connected to the positive terminal of current source I2, the gate of MP3, and the gate of MP4. The drain of MP2 is connected to the drain of MN8, the gate of MN8, and the gate of MN9, respectively. The drain of MP3 is connected to the drain of MN9. The drain of MP4 is connected to the source of MP5, the drain of MN12, and one end of resistor R1, respectively. The negative terminals of current sources IEA and I4 are connected to the signal output terminal TO and the drain of MN16, respectively. The source of MN8 is connected to the gate of MN10, the drain of MN10, and the gate of MN11, and the gate is connected to the drain of MN8 and the gate of MN9, respectively. Gate connections; the source of MN9 is connected to the drain of MP5, the drain of MN11, and the gate of MN12 respectively; the source of MN10 is grounded, and its gate is connected to the gate of MN11; the source of MN11 is grounded, and its drain is connected to the source of MN9, the drain of MP5, and the gate of MN12; the source of MP5 is connected to the drain of MP4, the drain of MN12, and one end of R1 respectively, and its drain is connected to the source of MN9, the drain of MN11, and the gate of MN12 respectively; the source of MN12 is grounded, and its drain is connected to the drain of MP4, the source of MP5, and one end of resistor R1; the other end of resistor R1 is connected to... The source of MP6, the drain of MN15, the gate of MN15, and the gate of MN16 are connected separately. The gate of MP6 is grounded, and its drain is connected to the drain of MN13. The gate of MN13 is connected to the input of the reference clock signal CLK, and its source is connected to the gate and drain of MN14 respectively. The gate of MN14 is connected to the drain of MN14, and the source of MN14 is grounded. The gate of MN15 is connected to the gate of MN16, and the source of MN15 is grounded. The source of MN16 is grounded, and its drain is connected to the signal output terminal and the negative terminals of current source IEA and current source I4 respectively, forming a slope compensation circuit.

[0006] Furthermore, the connection between the slope compensation circuit and the slope compensation capacitor control circuit includes: the drains of MN1, MN2, MN4, and MN6 of the slope compensation capacitor control circuit, as well as the positive terminal of the capacitor, are all connected to the negative terminal of the current source I4 and the gate of MP5 of the slope compensation circuit.

[0007] Preferably, the negative terminals of comparators A1, A2, and A3 are reference level input terminals VREF1, VREF2, and VREF3, respectively; the input voltages of the reference level input terminals VREF1, VREF2, and VREF3 are 0.2V, 0.4V, and 0.6V, respectively.

[0008] Preferably, the frequency division ratio of the signal input to the input terminal of the reference clock signal CLK in the segmented slope compensation circuit is 2:4:8.

[0009] Preferably, the process of controlling the capacitance value in the slope compensation capacitor control circuit includes: the voltage at the FB voltage input terminal is controllable; when the voltage input at the FB voltage input terminal is 0 to X1V, MN2, MN4, and MN6 are cut off, and the capacitance of the slope compensation capacitor control circuit is C4; when the voltage input at the FB voltage input terminal is X1 to X2V, MN2 and MN4 are cut off, and the capacitance of the slope compensation capacitor control circuit is C3+C4; when the voltage input at the FB voltage input terminal is X2 to X3V, MN2 is cut off, and the capacitance of the slope compensation capacitor control circuit is C2+C3+C4; when the voltage input at the FB voltage input terminal is above X3V, the capacitance of the slope compensation capacitor control circuit is C1+C2+C3+C4.

[0010] The beneficial effects of this invention are:

[0011] The segmented slope compensation circuit of this invention divides the slope compensation capacitor into four sections. As the duty cycle gradually increases, the slope compensation amplitude gradually increases, thereby improving the load-carrying capacity under full duty cycle in high-current DC-DC converters and suppressing the slowdown problem caused by overcompensation under low duty cycle. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the segmented slope compensation circuit for a step-down DC-DC converter according to the present invention.

[0013] Where: 101 represents the slope compensation capacitor control circuit, and 102 represents the slope compensation circuit. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] This invention discloses a segmented slope compensation circuit for a step-down DC-DC converter. By employing a novel architecture, it first outputs segmented switching signals based on the feedback voltage level. As the feedback voltage gradually increases, the slope compensation amplitude gradually increases, thus achieving full duty cycle slope compensation while reducing the slope compensation current. For high-current DC-DC converters, this method effectively solves the challenge of achieving the correct slope compensation amplitude and has a wide range of applications.

[0016] A segmented slope compensation circuit for buck DC-DC converters, such as Figure 1 As shown, the circuit includes: a slope compensation capacitor control circuit 101 and a slope compensation circuit 102; the slope compensation capacitor control circuit 101 and the slope compensation circuit 102 are connected to form a segmented slope compensation circuit, wherein the slope compensation capacitor control circuit 101 is used to control the capacitance of the segmented slope compensation circuit, and the slope compensation circuit 102 compensates the current signal according to the capacitance.

[0017] The slope compensation capacitor control circuit 101 includes three comparators, seven NMOS transistors, and four capacitors. Comparator A1's positive terminal is connected to FB, its negative terminal to the reference voltage VREF1, and its output terminal to the gate of MN6. Comparator A2's positive terminal is connected to FB, its negative terminal to the reference voltage VREF2, and its output terminal to the gate of MN4. Comparator A3's positive terminal is connected to FB, its negative terminal to the reference voltage VREF3, and its output terminal to the gate of MN2. MN1's source is grounded, its gate is connected to the reference clock CLK, and its drain is connected to the negative terminal of current source I1, the drains of MN2, MN4, and MN6, the positive terminal of C4, and the gate of MP5. MN2's source is connected to the drain of MN3 and the positive terminal of C1, its gate is connected to the output of comparator A3, and its drain is connected to the negative terminal of current source I1, the drains of MN1, MN4, and MN6, the positive terminal of C4, and the gate of MP5. MN3's source is grounded, its gate is connected to the reference clock CLK, and its drain is connected to the source of MN2 and the positive terminal of C1. The source of MN2 and the drain of MN3 are connected together, with the negative terminal grounded; the source of MN4 is connected to the drain of MN5 and the positive terminal of C2, the gate is connected to the output of comparator A2, and the drain is connected to the negative terminal of current source I1, the drains of MN1, MN2, and MN6, the positive terminal of C4, and the gate of MP5; the source of MN5 is grounded, the gate is connected to the reference clock CLK, and the drain is connected to the source of MN4 and the positive terminal of C2; the positive terminal of C2 is connected to the source of MN4 and the drain of MN5, with the negative terminal grounded; the source of MN6 is connected to the drain of MN7 and... The positive terminal of C3 is connected, the gate is connected to the output terminal of comparator A1, the drain is connected to the negative terminal of current source I1 and the drains of MN1, MN2, and MN4, the positive terminal of C4 and the gate of MP5 are connected; the source of MN7 is grounded, the gate is connected to the reference clock CLK, the drain is connected to the source of MN6 and the positive terminal of C3; the positive terminal of C3 is connected to the source of MN6 and the drain of MN7, and the negative terminal is grounded; the positive terminal of C4 is connected to the negative terminal of current source I1 and the drains of MN1, MN2, MN4, and MN6 and the gate of MP5, and the negative terminal is grounded.

[0018] The slope compensation circuit 102 includes: four current sources, six PMOS transistors, nine PMOS transistors, and one resistor; the positive terminal of current source I1 is connected to the power supply VDD, and the negative terminal is connected to the drains of MN1, MN2, MN4, and MN6, the rectifier C4, and the gate of MP5; the source of MP1 is connected to the power supply VDD, and its gate is connected to the drain of MP1; the positive terminal of current source I2 is connected to the gates of MP2, MP3, and MP4, and its drain is connected to the positive terminal of current source I2 and the gates of MP1, MP2, MP3, and MP4; the positive terminal of current source I2 is connected to the gates of MP1, MP2, MP3, and MP4, and the drain of MP1, and its negative terminal is grounded; the source of MP2 is connected to the power supply VDD, and its gate is connected to the drain of MP1; the positive terminal of current source I2 is connected to the gates of MP1, MP3, and MP4, and the drain of MP1. MP4's gate is connected to the drain of MN8 and the gates of MN8 and MN9; MP3's source is connected to power supply VDD, its gate is connected to the drain of MP1 and the positive terminal of current source I2, and the gates of MP1, MP2, and MP4 are connected; its drain is connected to the drain of MN9; MP4's source is connected to power supply VDD, its gate is connected to the drain of MP1 and the positive terminal of current source I2, and the gates of MP1, MP2, and MP3 are connected; its drain is connected to the source of MP5 and the drain of MN12 and the positive terminal of R1; MN8's source is connected to the gates of MN10 and MN11 and the drain of MN10; its gate is connected to the drain of MP2, the drain of MN8 and the gate of MN9; its drain is connected to the drain of MP2 and the gates of MN8 and MN9; MN9's source is connected to the drains of MP5 and MN11 and... MN12 gate connection, gate to MN8 gate and MP2, MN8 drain connection, drain to MP3 drain connection; MN10 source ground, gate to MN11 gate and MN8 source and MN10 drain connection, drain to MN10, MN11 gate and MN8 source connection; MN11 source ground, gate to MN10 gate and MN10 drain and MN8 source connection, drain to MN9 source and MP5 drain and MN12 gate connection; MP5 source to MP4, MN12 drain and R1 positive terminal connection, gate to MN1, MN2, MN4, MN6 drain and current source I1 negative terminal connection, drain to MN9 source and MN11 drain and MN12 gate connection; MN12 The source is grounded, the gate of MP5, the drain of MN11 and the source of MN9 are connected, and the drain of MP4 and the source of MP5 are connected to the positive terminal of R1; the positive terminal of R1 is connected to the drain of MP4 and MN12 and the source of MP5, and the negative terminal is connected to the source of MP6 and the gates of MN15 and MN16 and the drain of MN15; the source of MP6 is connected to the negative terminal of R1 and the gates of MN15 and MN16 and the drain of MN15, the gate is grounded, and the drain is connected to the drain of MN13; the source of MN13 is connected to the gate and drain of MN14, the gate is connected to the reference clock CLK, and the drain is connected to the drain of MP6; the source of MN14 is grounded, the gate is connected to the source of MN13 and the drain of MN14, and the drain is connected to the source of MN13 and the gate of MN14;The source of MN15 is grounded, its gate is connected to the gate of MN16, the negative terminal of R1, the source of MP6, and the drain of MN15. The drain of MN16 is connected to the gates of MN15 and MN16, the negative terminal of R1, and the source of MP6. The source of MN16 is grounded, its gate is connected to the gate of MN15, the negative terminal of R1, the source of MP6, and the drain of MN15. The drain of MN16 is connected to the negative terminal of current source IEA, the negative terminal of current source I4, and the output. The positive terminal of current source IEA is connected to power supply VDD, and its negative terminal is connected to the negative terminal of current source I4, the drain of MN16, and the output. The positive terminal of current source I4 is connected to power supply VDD, and its negative terminal is connected to the negative terminal of current source IEA, the drain of MN16, and the output.

[0019] The negative terminals of comparators A1, A2, and A3 serve as reference level inputs VREF1, VREF2, and VREF3, respectively. The input voltages of VREF1, VREF2, and VREF3 are 0.2V, 0.4V, and 0.6V, respectively. The corresponding reference clock CLK has a division ratio of 2:4:8. As FB gradually increases, the outputs of comparators A1, A2, and A3 sequentially go high, and the ramp current gradually increases, ensuring that the change in ramp compensation current remains constant within one cycle. The final ramp compensation current is generated by MN16. This ramp compensation current is then subtracted from the current signal IEA, which is converted from the output voltage of the error amplifier, to obtain the final ramp-compensated signal, used to implement the PWM comparison function.

[0020] The process of controlling the capacitor size in the slope compensation capacitor control circuit includes: the voltage at the FB voltage input terminal is controllable. When the voltage input at the FB voltage input terminal is 0V~0.2V, MN2, MN4, and MN6 are cut off, and the capacitor of the slope compensation capacitor control circuit is C4; when the voltage input at the FB voltage input terminal is 0.2V~0.4V, MN2 and MN4 are cut off, and the capacitor of the slope compensation capacitor control circuit is C3+C4; when the voltage input at the FB voltage input terminal is 0.4V~0.6V, MN2 is cut off, and the capacitor of the slope compensation capacitor control circuit is C2+C3+C4; when the voltage input at the FB voltage input terminal is above 0.6V, the capacitor of the slope compensation capacitor control circuit is C1+C2+C3+C4.

[0021] The CLK signal is a narrow pulse signal. When the CLK signal is high, NMOS transistors MN1, MN3, MN5, and MN7 are turned on, quickly pulling the voltage at the positive terminal of C4 low. When the CLK signal is low, NMOS transistors MN1, MN3, MN5, and MN7 are turned off, and current source I1 slowly charges the capacitor. This generates a cycle-by-cycle ramp voltage signal at the positive terminal of C4, the magnitude of which is:

[0022]

[0023] Where I1 is the charging current, C is the capacitance value of the segmented slope compensation circuit at this time, and T is the low-level time of the clock CLK.

[0024] When the voltage at the positive terminal of C4 is high, MP5 is turned off, due to (W / L) MP2 / (W / L) MP3 =2, (W / L) MN10 / (W / L) MN11 =1, so the drain of MP5 is low at this time, and MN11 operates in the linear region. When the voltage at the positive terminal of C4 is low, MP5 is turned on, the drain voltage of MP5 is high, and MN11 operates in the saturation region. At this time, the voltage at the positive terminal of R1 is the voltage at the positive terminal of C4 plus a fixed level. The voltage across C4 is:

[0025]

[0026] Where V1 represents the ramp voltage signal, V GSMP5 I1 represents the gate-source voltage of the MP5 transistor, C is the charging current, T is the capacitance value of the segmented slope compensation circuit at this time, and T is the low-level time of the clock CLK. DMP5 This represents the leakage current of the MP5 transistor, in μ. p C represents hole mobility. ox The capacitance per unit area of ​​the gate oxide layer is given by V, where W represents the gate width of the MP5 transistor, L represents the gate length of the MP5 transistor, and V represents the gate oxide capacitance per unit area. THMP5 This indicates the threshold voltage of the MP5 transistor.

[0027] The voltage at the positive terminal of resistor R1 is converted into a current signal, which is then mirrored by transistor MN16 to obtain the ramp current. This ramp current is then subtracted from the current signal output by the error amplifier to obtain the final output signal. The final output ramp current value is:

[0028]

[0029] Among them, I slope This represents the ramp current value (W / L). MN16 This indicates the width-to-length ratio (W / L) of the MN16 tube. MN15 R1 represents the aspect ratio of the MN15 transistor, and I represents the resistance value. DMP5 This represents the leakage current of the MP5 transistor, in μ. p C represents hole mobility. ox The capacitance per unit area of ​​the gate oxide layer is given by V, where W represents the gate width of the MP5 transistor, L represents the gate length of the MP5 transistor, and V represents the gate oxide capacitance per unit area. THMP5 I represents the threshold voltage of the MP5 transistor. DMN15 This represents the drain current of transistor MN5, μ. n V represents electron mobility. THMN15This indicates the threshold voltage of the MN15 transistor.

[0030] This invention can improve the application range by adjusting the mirror ratio of MN16 and MN15 to meet the slope compensation values ​​of different loads and different inductance DC-DC converters.

[0031] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A segmented slope compensation circuit for a step-down DC-DC converter, characterized in that, include: The slope compensation capacitor control circuit and the slope compensation circuit are connected to form a segmented slope compensation circuit. The slope compensation capacitor control circuit is used to control the capacitance of the segmented slope compensation circuit, and the slope compensation circuit compensates the current signal according to the capacitance. The ramp compensation capacitor control circuit includes three comparators, seven NMOS transistors, and four capacitors. The positive terminals of comparators A1, A2, and A3 are all connected to FB, and their negative terminals are connected to the reference voltage input terminals VREF1, VREF2, and VREF3, respectively. The output terminal of comparator A1 is connected to the gate of MN6, the output terminal of comparator A2 is connected to the gate of MN4, and the output terminal of comparator A3 is connected to the gate of NM2. The source of MN1 is grounded, its gate is connected to the input terminal of the reference clock signal CLK, and its drain is connected to the drains of MN2, MN4, and MN6, as well as the positive terminal of capacitor C4. The source of MN2 is connected to the drain of MN3 and the positive terminal of capacitor C1, respectively; the gate of MN3 is connected to the input terminal of the reference clock signal CLK, and its source is grounded; the negative terminal of capacitor C1 is grounded; the source of MN4 is connected to the drain of MN5 and the positive terminal of capacitor C2, respectively; the gate of MN5 is connected to the input terminal of the reference clock signal CLK, and its source is grounded; the negative terminal of capacitor C2 is grounded; the source of MN6 is connected to the drain of MN7 and the positive terminal of capacitor C3, respectively; the gate of MN7 is connected to the input terminal of the reference clock signal CLK, and its source is grounded; the negative terminals of capacitors C3 and C4 are grounded, forming a slope compensation capacitor control circuit; The slope compensation circuit includes: four current sources, six PMOS transistors, nine PMOS transistors, and one resistor; the positive terminals of current sources I1, IEA, and I4, as well as the sources of MP1, MP2, MP3, and MP4, are all connected to the power supply VDD; the negative terminal of current source I1 is connected to the gate of MP5; the gate of MP1 is connected to the drain of MP1, the gate of MP2, the gate of MP3, and the gate of MP4, respectively, and the drain of MP1 is connected to the positive terminal of current source I2; the negative terminal of current source I2 is grounded; the gate of MP2 is connected to the gate of MP1. After connection, connect to the positive terminal of current source I2, the gate of MP3, and the gate of MP4. Connect the drain of MP2 to the drain of MN8, the gate of MN8, and the gate of MN9. Connect the drain of MP3 to the drain of MN9. Connect the drain of MP4 to the source of MP5, the drain of MN12, and one end of resistor R1. Connect the negative terminals of current source IEA and current source I4 to the signal output terminal TO and the drain of MN16, respectively. Connect the source of MN8 to the gate of MN10, the drain of MN10, and the gate of MN11. Connect the gates of MN8 and MN9, respectively. Connections: The source of MN9 is connected to the drain of MP5, the drain of MN11, and the gate of MN12, respectively; the source of MN10 is grounded, and its gate is connected to the gate of MN11; the source of MN11 is grounded, and its drain is connected to the source of MN9, the drain of MP5, and the gate of MN12, respectively; the source of MP5 is connected to the drain of MP4, the drain of MN12, and one end of R1, and its drain is connected to the source of MN9, the drain of MN11, and the gate of MN12, respectively; the source of MN12 is grounded, and its drain is connected to the drain of MP4, the source of MP5, and one end of resistor R1; the other end of resistor R1 is connected to... The source of MP6, the drain of MN15, the gate of MN15, and the gate of MN16 are connected; the gate of MP6 is grounded, and its drain is connected to the drain of MN13; the gate of MN13 is connected to the input of the reference clock signal CLK, and its source is connected to the gate and drain of MN14 respectively; the gate of MN14 is connected to the drain of MN14, and the source of MN14 is grounded; the gate of MN15 is connected to the gate of MN16, and the source of MN15 is grounded; the source of MN16 is grounded, and its drain is connected to the signal output terminal and the negative terminals of current source IEA and current source I4 respectively, forming a slope compensation circuit.

2. The segmented slope compensation circuit for a step-down DC-DC converter according to claim 1, characterized in that, The connection between the slope compensation circuit and the slope compensation capacitor control circuit includes: the drains of MN1, MN2, MN4, and MN6 of the slope compensation capacitor control circuit, as well as the positive terminal of capacitor C4, are all connected to the negative terminal of current source I1 and the gate of MP5 of the slope compensation circuit.

3. A segmented slope compensation circuit for a step-down DC-DC converter according to claim 1, characterized in that, The negative terminals of comparators A1, A2, and A3 are the reference level input terminals VREF1, VREF2, and VREF3, respectively; the input voltages of the reference level input terminals VREF1, VREF2, and VREF3 are 0.2V, 0.4V, and 0.6V, respectively.

4. A segmented slope compensation circuit for a step-down DC-DC converter according to claim 1, characterized in that, In the segmented slope compensation circuit, the frequency division ratio of the input signal to the reference clock signal CLK is 2:4:

8.

5. A segmented slope compensation circuit for a step-down DC-DC converter according to claim 1, characterized in that, The process of controlling the capacitor size in the slope compensation capacitor control circuit includes: the voltage at the FB voltage input terminal is controllable. When the voltage input at the FB voltage input terminal is 0V~0.2V, MN2, MN4, and MN6 are cut off, and the capacitor of the slope compensation capacitor control circuit is C4; when the voltage input at the FB voltage input terminal is 0.2V~0.4V, MN2 and MN4 are cut off, and the capacitor of the slope compensation capacitor control circuit is C3+C4; when the voltage input at the FB voltage input terminal is 0.4V~0.6V, MN2 is cut off, and the capacitor of the slope compensation capacitor control circuit is C2+C3+C4; when the voltage input at the FB voltage input terminal is above 0.6V, the capacitor of the slope compensation capacitor control circuit is C1+C2+C3+C4.

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