A silicon-based radio frequency single pole four throw switch

Abstract

The application provides a silicon-based radio frequency single-pole four-throw switch which is composed of resistors, inductors, MOS tubes, transmission lines and direct-current isolation capacitors and includes four branches, one of which is connected with one end of a direct-current isolation capacitor C1 through a port P1, the other end of the direct-current isolation capacitor C1 is connected with a source electrode of a MOS tube M1 and one end of an inductor L1, a gate electrode of the MOS tube M1 is installed with a resistor R17 and then connected with a control voltage VC1, a substrate of the MOS tube M1 is installed with a resistor R1 and then connected with the ground, a drain electrode of the MOS tube M1 is connected with a source electrode of a MOS tube M2, a gate electrode of the MOS tube M2 is installed with a resistor R18 and then connected with the control voltage VC1, a substrate of the MOS tube M2 is installed with a resistor R2 and then connected with the ground, a drain electrode of the MOS tube M2 is connected with a source electrode of a MOS tube M3, a gate electrode of the MOS tube M3 is installed with a resistor R19 and then connected with the control voltage VC1, and a substrate of the MOS tube M3 is installed with a resistor R3 and then connected with the ground. The application realizes high isolation, high power capacity and high return loss of the switch through transmission line impedance conversion mode, stacking mode, source-drain bias mode, alternating current floating body mode and LC resonance mode.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic devices, and particularly relates to a silicon-based radio frequency single-pole four-throw switch. BACKGROUND

[0002] Beamforming array technology can change the shape of spatial beams in real time according to a precoding matrix, realize directional communication for different users, and is an effective technology for improving communication signal-to-noise ratio, and has great development prospects. The Butler matrix network can output fixed power and phase difference at each output port, and is widely used in passive beamforming systems. With the evolution of wireless communication frequency to millimeter wave and higher frequency bands, the indicators of the signal selection circuit have a crucial influence on the comprehensive performance of the system.

[0003] Since the 1980s, commercial wireless communication has rapidly developed from a simple voice system to a mobile broadband multimedia system. The alternation of wireless communication technology has brought far-reaching influence on our daily life and social activities. Due to the promotion of mobile applications, data traffic and connected devices continue to increase. The fifth generation mobile communication technology has significantly different system performance indicators compared with the previous generation, including gigabit-level data rate per second, extremely high traffic density, millisecond-level low latency, and ultra-dense connection. From the perspective of electromagnetic wave resources, the available spectrum resources below 6GHz are very limited, and there are a large number of unused spectrum resources in the millimeter wave frequency band. The millimeter wave frequency band is 30GHz-300GHz, and its short wavelength characteristics result in weak propagation ability, i.e. large path loss, poor diffraction and transmission ability, which actually reduces the SINR of the wireless system. Therefore, for the millimeter wave communication system, designing a suitable beamforming scheme to concentrate the beam to the desired direction so as to improve the working distance has become the focus of attention. The Butler matrix network is a classic beamforming circuit and is widely used in millimeter wave array systems.

[0004] Switching circuit is a key module of low-cost Butler matrix beamforming system, and has an important influence on the performance of the whole system. Figure 1For the typical application of the switching circuit in the Butler matrix beamforming system, the switch allows the signal to pass through a specific input port of the Butler matrix network, thereby determining the pointing of the system signal. Because the Butler matrix needs to perform phase shift processing on the signal, it is necessary to prevent signal interference caused by signal leakage from other ports, so there is a high requirement for the port isolation of the switching circuit. At the same time, the other unselected ports act as isolated ends of the coupler, which need to be matched with the coupler to maintain the isolation of the coupler and prevent multiple internal reflections. Therefore, the selected port of the switch needs to be matched with the input port, and the closed port needs to be matched with the coupler port. In the Butler matrix beamforming system, the upper stage of the switching circuit is usually a power amplifier, so it needs to bear a large power, and therefore there is a high requirement for the power capacity of the switch. Therefore, it is of great practical significance to study how to design a switching circuit with high power capacity, high return loss and high isolation.

[0005] A common traditional radio frequency SP4T switch is a series-parallel structure, as shown in Figure 2 The circuit is mainly composed of MOS tubes. By controlling the gate voltage of MOS tubes M1 and M2, the signal selection function can be realized. For the selected branch, the M1 gate is connected to the high level, which is equivalent to a small resistance, and the M2 gate is connected to the low level, which is equivalent to a large resistance, so the signal flows from P1 to P2. For the closed branch, the M1 gate is connected to the low level, which is equivalent to a large resistance, and the M2 gate is connected to the high level, which is equivalent to a small resistance, so only a small part of the signal will pass through M1, and the leaked signal will be introduced into the ground through M2, and will not flow into the next stage circuit, thereby improving the isolation.

[0006] The traditional series-parallel SP4T switch mentioned above can realize signal path selection, but there are many problems, and the corresponding disadvantages are as follows:

[0007] (1) The isolation of the traditional series-parallel SP4T switch is not high enough. When the MOS tube is closed, it is usually considered as an open circuit, i.e. the impedance is infinite, and the signal will not pass through the closed MOS tube. However, at the radio frequency band, the MOS tube cannot be simply considered as an open circuit when it is closed, and there is a parasitic capacitance between its gate and drain and source. Therefore, its impedance is limited, and a certain amount of signal will pass through the closed MOS tube to the port that should be isolated, i.e. the isolation is not high enough. Therefore, the traditional series-parallel SP4T switch cannot block the leakage signal, and the leaked signal will usually cause serious deterioration of the overall performance of the circuit, and for the Butler matrix beamforming system, it will cause multiple internal reflections and reduce the beam pointing performance.

[0008] (2) The power capacity of the traditional series-parallel SP4T switch is not enough. From Figure 2It can be seen that for the gating branch, M1 is connected to high level, M2 is connected to low level, and the signal of P1 port should flow into P2 port and cannot flow into the ground. However, when the signal swing of P2 port is too large, due to the influence of parasitic capacitance, the gate voltage of M2 appears, and the amplitude is positively correlated with the signal voltage swing of P2 port. When the gate voltage of M2 is greater than the threshold voltage of M2, M2 changes from the off state to the on state, and the signal of P2 port will flow into the ground in large quantity, which worsens the insertion loss of the switch. Therefore, the traditional series-parallel SP4T switch cannot process large voltage swing signals, and its power capacity is usually small.

[0009] (3) The return loss of the traditional series-parallel SP4T switch is not high. By Figure 2 It can be seen that for the gating branch, M1 is connected to high level, M2 is connected to low level, and the signal of P1 port should flow into P2 port and cannot flow into the ground. However, when the signal swing of P2 port is too large, due to the influence of parasitic capacitance, the gate voltage of M2 appears, and the amplitude is positively correlated with the signal voltage swing of P2 port. When the gate voltage of M2 is greater than the threshold voltage of M2, M2 changes from the off state to the on state, and the signal of P2 port will flow into the ground in large quantity, which worsens the insertion loss of the switch. Therefore, the traditional series-parallel SP4T switch cannot process large voltage swing signals, and its power capacity is usually small. SUMMARY

[0010] The purpose of the present application is to solve the defects of the prior art, and to provide a silicon-based radio frequency single-pole four-throw switch, which realizes high isolation, high power capacity and high return loss through transmission line impedance transformation, stacking, source-drain bias, AC floating body and LC resonance.

[0011] The SPT4 switch of the present application uses transmission line impedance transformation technology, stacking technology, source-drain bias and AC floating body technology, and LC resonance technology on the structure of the traditional series-parallel SP4T switch, suppresses the leakage of signals from the off branch and the parallel branch, and makes the switch have the advantages of high power capacity and high isolation. At the same time, by selecting the size of the transmission line and the MOS tube connected in series with the ground, the impedance matching performance of the off branch and the port is improved, and the return loss of the switch is improved.

[0012] The present application adopts the following technical scheme:

[0013] A silicon-based radio frequency single-pole four-throw switch is composed of resistors, inductors, MOS tubes, transmission lines and DC blocking capacitors.

[0014] The fourth branch is that the port P1 connects one end of the blocking capacitor C4, the other end of the blocking capacitor C4 connects the source electrode of the MOS transistor M1-4, the gate electrode of the MOS transistor M1-4 is installed with a resistor R27 and then connected with the control voltage VC3, the substrate of the MOS transistor M1-4 is installed with a resistor R13 and then connected with the ground, the drain electrode of the MOS transistor M1-4 connects the source electrode of the MOS transistor M2-4, the gate electrode of the MOS transistor M2-4 is installed with a resistor R28 and then connected with the control voltage VC3, the substrate of the MOS transistor M2-4 is installed with a resistor R14 and then connected with the ground, the drain electrode of the MOS transistor M2-4 connects the source electrode of the MOS transistor M3-4, the gate electrode of the MOS transistor M3-4 is installed with a resistor R29 and then connected with the control voltage VC3, the substrate of the MOS transistor M3-4 is installed with a resistor R15 and then connected with the ground, the drain electrode of the MOS transistor M3-4 connects the other end of the inductor L4, one end of the blocking capacitor C5, the other end of the blocking capacitor C5 connects the port P4, one end of the transmission line TL3, the other end of the transmission line TL3 connects the other end of the inductor L5, the source electrode of the MOS transistor M4-4, the gate electrode of the MOS transistor M4-4 is installed with a resistor R30 and then connected with the control voltage VC3, the substrate of the MOS transistor M4-4 is installed with a resistor R16 and then connected with the ground, the drain electrode of the MOS transistor M4-4 connects the other end of the inductor L5, and VC3 is a low level.

[0015] The second branch is that the port P1 connects one end of the blocking capacitor C3, the other end of the blocking capacitor C3 connects the source electrode of the MOS transistor M1-1, the gate electrode of the MOS transistor M1-1 is installed with a resistor R21 and then connected with the control voltage VC2, the substrate of the MOS transistor M1-1 is installed with a resistor R5 and then connected with the ground, the drain electrode of the MOS transistor M1-1 connects the source electrode of the MOS transistor M2-1, the gate electrode of the MOS transistor M2-1 is installed with a resistor R22 and then connected with the control voltage VC2, the substrate of the MOS transistor M2-1 is installed with a resistor R6 and then connected with the ground, the drain electrode of the MOS transistor M2-1 connects the source electrode of the MOS transistor M3-1, the gate electrode of the MOS transistor M3-1 is installed with a resistor R23 and then connected with the control voltage VC2, the substrate of the MOS transistor M3-1 is installed with a resistor R7 and then connected with the ground, the drain electrode of the MOS transistor M3-1 connects the other end of the inductor L3 and one end of the blocking capacitor C4, the other end of the blocking capacitor C4 connects the port P3 and one end of the transmission line TL2, the other end of the transmission line TL2 connects the inductor L4, the source electrode of the MOS transistor M4-1, the gate electrode of the MOS transistor M4-1 is installed with a resistor R24 and then connected with the control voltage VC2, the substrate of the MOS transistor M4-1 is installed with a resistor R8 and then connected with the ground, the drain electrode of the MOS transistor M4-1 connects the other end of the inductor L4, and VC2 is a low level.

[0016] The third branch is that port P1 is connected with one end of DC blocking capacitor C5, the other end of DC blocking capacitor C5 is connected with one end of inductor L5 and the source of MOS tube M1-2, the gate of MOS tube M1-2 is installed with a resistor R25 and then connected with control voltage VC2, the substrate of MOS tube M1-2 is installed with a resistor R9 and then connected with the ground, the drain of MOS tube M1-2 is connected with the source of MOS tube M2-2, the gate of MOS tube M2-2 is installed with a resistor R26 and then connected with control voltage VC2, the substrate of MOS tube M2-2 is installed with a resistor R10 and then connected with the ground, the drain of MOS tube M2-2 is connected with the source of MOS tube M3-2, the gate of MOS tube M3-2 is installed with a resistor R27 and then connected with control voltage VC2, the substrate of MOS tube M3-2 is installed with a resistor R11 and then connected with the ground, the drain of MOS tube M3-2 is connected with the other end of inductor L5 and one end of DC blocking capacitor C6, the other end of DC blocking capacitor C6 is connected with port P4 and one end of transmission line TL3, the other end of transmission line TL3 is connected with one end of inductor L6 and the source of MOS tube M4-2, the gate of MOS tube M4-2 is installed with a resistor R28 and then connected with control voltage VC2, the substrate of MOS tube M4-2 is installed with a resistor R12 and then connected with the ground, the drain of MOS tube M4-2 is connected with the other end of inductor L6.

[0017] The fourth branch is that port P1 is connected with one end of DC blocking capacitor C7, the other end of DC blocking capacitor C7 is connected with one end of inductor L7 and the source of MOS tube M1-3, the gate of MOS tube M1-3 is installed with a resistor R29 and then connected with control voltage VC2, the substrate of MOS tube M1-3 is installed with a resistor R13 and then connected with the ground, the drain is connected with the source of MOS tube M2-3, the gate of MOS tube M2-3 is installed with a resistor R30 and then connected with control voltage VC2, the substrate of MOS tube M2-3 is installed with a resistor R14 and then connected with the ground, the drain of MOS tube M2-3 is connected with the source of MOS tube M3-3, the gate of MOS tube M3-3 is installed with a resistor R31 and then connected with control voltage VC2, the substrate of MOS tube M2-3 is installed with a resistor R15 and then connected with the ground, the drain of MOS tube M3-3 is connected with the other end of inductor L7 and one end of DC blocking capacitor C8, the other end of DC blocking capacitor C8 is connected with port P5 and one end of transmission line TL4, the other end of transmission line TL4 is connected with one end of inductor L8 and the source of MOS tube M4-3, the gate of MOS tube M4-3 is installed with a resistor R32 and then connected with control voltage VC3, the substrate of MOS tube M3-3 is installed with a resistor R16 and then connected with the ground, the drain of MOS tube M4-3 is connected with the other end of inductor L8.

[0018] The resistance of resistors R1-R32 is greater than or equal to 10 kΩ.

[0019] The beneficial effects of the present application are as follows:

[0020] 1. The SP4T switch of the present application uses transmission line impedance transformation technology in parallel branches, a MOS tube with small on-resistance is connected at one end of the quarter wavelength transmission line, by controlling the gate voltage of the MOS tube, the combination of the transmission line and the MOS tube can be switched between high resistance state and low resistance state, the high resistance state can improve the power capacity of the selected branch, and the low resistance is adjusted as the port impedance, which can improve the return loss of the closed branch.

[0021] 2. The SP4T switch of the present application uses stacking technology in series branches, so that the voltage of the radio frequency signal is uniformly distributed in the three MOS tubes, avoiding the single MOS tube from bearing too high voltage swing and causing the working state to change, and inhibiting the signal from leaking from the closed branch, thereby achieving the purposes of improving power capacity and isolation, and reducing insertion loss.

[0022] 3. The SP4T switch of the present application uses source-drain biasing technology in series branches, a large resistance is connected in series between the source and the drain of the MOS tube of the closed branch, and then connected to a high level, so that the drain and source nodes are reversely biased with respect to the gate, so that the MOS tube can bear a larger voltage swing, thereby further improving the power capacity and isolation, and reducing the insertion loss. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 SP4T switch diagram for Butler matrix beamforming system;

[0024] Figure 2 Conventional series-parallel SP4T switch schematic diagram;

[0025] Figure 3 Structural diagram of the present application;

[0026] Figure 4 Power capacity diagram of the SP4T switch of the present application;

[0027] Figure 5 Return loss diagram of the SP4T switch of the present application;

[0028] Figure 6 Isolation diagram of the SP4T switch of the present application;

[0029] Figure 7 SP4T power capacity test condition schematic diagram;

[0030] Figure 8 SP4T parameter test condition schematic diagram. DETAILED DESCRIPTION

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention are described clearly and completely below. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0032] Terminology Explanation:

[0033] MOS transistor: Metal-Oxide-Semiconductor Field-Effect Transistor

[0034] SINR: Signal-to-Interference-and-Noise Ratio

[0035] SP4T: Single-pole four-throw switch

[0036] VC: Control Voltage

[0037] TL: Transmission Line

[0038] This invention utilizes the traditional series-parallel SP4T switch structure.

[0039] like Figure 3 As shown, a silicon-based radio frequency single-pole four-throw switch of the present invention mainly consists of a large resistor (about 10 kiloohms), an inductor, a MOSFET, a transmission line, and a DC blocking capacitor.

[0040] The circuit includes four branches. One branch connects port P1 to one end of DC blocking capacitor C1. The other end of DC blocking capacitor C1 is connected to the source of MOSFET M1 and one end of inductor L1. A resistor R17 is mounted on the gate of MOSFET M1 and connected to the control voltage VC1. A resistor R1 is mounted on the substrate of MOSFET M1 and grounded. The drain of MOSFET M1 is connected to the source of MOSFET M2. A resistor R18 is mounted on the gate of MOSFET M2 and connected to the control voltage VC1. A resistor R2 is mounted on the substrate of MOSFET M2 and grounded. The drain of MOSFET M2 is connected to the source of MOSFET M3. A resistor R19 is installed on the gate of MOSFET M3 and then connected to the control voltage VC1. A resistor R3 is installed on the substrate of MOSFET M3 and then grounded. The drain of MOSFET M3 is connected to the other end of inductor L1. One end of DC blocking capacitor C2 is connected to the other end of DC blocking capacitor C2. The other end of DC blocking capacitor C2 is connected to port P2 and one end of transmission line TL1. The other end of transmission line TL1 is connected to one end of inductor L2 and the source of MOSFET M4. A resistor R20 is installed on the gate of MOSFET M4 and then connected to the control voltage VC1. A resistor R4 is installed on the substrate of MOSFET M4 and then grounded. The drain of MOSFET M4 is connected to the other end of inductor L2. VC1 is at a high level.

[0041] The second branch is that the port P1 connects one end of the blocking capacitor C3, the other end of the blocking capacitor C3 connects one end of the inductor L3 and the source of the MOS transistor M1-1, the gate of the MOS transistor M1-1 is installed with a resistor R21 and then connected to the control voltage VC2, the substrate of the MOS transistor M1-1 is installed with a resistor R5 and then connected to the ground, the drain of the MOS transistor M1-1 connects the source of the MOS transistor M2-1, the gate of the MOS transistor M2-1 is installed with a resistor R22 and then connected to the control voltage VC2, the substrate of the MOS transistor M2-1 is installed with a resistor R6 and then connected to the ground, the drain of the MOS transistor M2-1 connects the source of the MOS transistor M3-1, the gate of the MOS transistor M3-1 is installed with a resistor R23 and then connected to the control voltage VC2, the substrate of the MOS transistor M3-1 is installed with a resistor R7 and then connected to the ground, the drain of the MOS transistor M3-1 connects the other end of the inductor L3 and one end of the blocking capacitor C4, the other end of the blocking capacitor C4 connects the port P3 and one end of the transmission line TL2, the other end of the transmission line TL2 connects one end of the inductor L4, the source of the MOS transistor M4-1, the gate of the MOS transistor M4-1 is installed with a resistor R24 and then connected to the control voltage VC2, the substrate of the MOS transistor M4-1 is installed with a resistor R8 and then connected to the ground, the drain of the MOS transistor M4-1 connects the other end of the inductor L4, and VC2 is at a low level.

[0042] The third branch is that the port P1 connects one end of the blocking capacitor C5, the other end of the blocking capacitor C5 connects one end of the inductor L5 and the source of the MOS transistor M1-2, the gate of the MOS transistor M1-2 is installed with a resistor R25 and then connected to the control voltage VC2, the substrate of the MOS transistor M1-2 is installed with a resistor R9 and then connected to the ground, the drain of the MOS transistor M1-2 connects the source of the MOS transistor M2-2, the gate of the MOS transistor M2-2 is installed with a resistor R26 and then connected to the control voltage VC2, the substrate of the MOS transistor M2-2 is installed with a resistor R10 and then connected to the ground, the drain of the MOS transistor M2-2 connects the source of the MOS transistor M3-2, the gate of the MOS transistor M3-2 is installed with a resistor R27 and then connected to the control voltage VC2,

[0043] the substrate of the MOS transistor M3-2 is installed with a resistor R11 and then connected to the ground, the drain of the MOS transistor M3-2 connects the other end of the inductor L5 and one end of the blocking capacitor C6, the other end of the blocking capacitor C6 connects the port P4 and one end of the transmission line TL3, the other end of the transmission line TL3 connects one end of the inductor L6, the source of the MOS transistor M4-2, the gate of the MOS transistor M4-2 is installed with a resistor R28 and then connected to the control voltage VC2, the substrate of the MOS transistor M4-2 is installed with a resistor R12 and then connected to the ground, and the drain of the MOS transistor M4-2 connects the other end of the inductor L6.

[0044] The fourth branch is that port P1 is connected to one end of the DC blocking capacitor C7, the other end of the DC blocking capacitor C7 is connected to one end of the inductor L7 and the source of the MOS transistor M1-3, a resistor R29 is connected to the gate of the MOS transistor M1-3 and then the control voltage VC2 is connected, a resistor R13 is connected to the substrate of the MOS transistor M1-3 and then the ground is connected, the drain of the MOS transistor is connected to the source of the MOS transistor M2-3, a resistor R30 is connected to the gate of the MOS transistor M2-3 and then the control voltage VC2 is connected, a resistor R14 is connected to the substrate of the MOS transistor M2-3 and then the ground is connected, the drain of the MOS transistor M2-3 is connected to the source of the MOS transistor M3-3, a resistor R31 is connected to the gate of the MOS transistor M3-3 and then the control voltage VC2 is connected, a resistor R15 is connected to the substrate of the MOS transistor M2-3 and then the ground is connected, the drain of the MOS transistor M3-3 is connected to the other end of the inductor L7 and one end of the DC blocking capacitor C8, the other end of the DC blocking capacitor C8 is connected to the port P5 and one end of the transmission line TL4, the other end of the transmission line TL4 is connected to one end of the inductor L8 and the source of the MOS transistor M4-3, a resistor R32 is connected to the gate of the MOS transistor M4-3 and then the control voltage VC3 is connected, a resistor R16 is connected to the substrate of the MOS transistor M3-3 and then the ground is connected, and the drain of the MOS transistor M4-3 is connected to the other end of the inductor L8.

[0045] The resistance of the resistors R1-R32 is greater than or equal to 10 kilo-ohms.

[0046] Because there is a parasitic capacitance between the gate and the substrate of the MOS transistor and between the source and the drain, the radio frequency signal will leak through the parasitic capacitance, which will deteriorate the insertion loss of the switch. The AC floating body technology means that a large resistor is connected to the substrate and the gate of the MOS transistor, which will block the path through which the radio frequency signal may leak, so that the AC signal will not leak to the ground or the power supply of the gate through the parasitic capacitance, thereby reducing the insertion loss of the switch. In addition, when the gate of the MOS transistor is connected to a low level, it can be equivalent to a large resistor and the parallel parasitic capacitance between the source and the drain. As the frequency increases, the effect of this capacitance becomes more obvious, causing signal leakage and deteriorating the insertion loss. The LC resonance technology means that an inductor is connected in parallel with the MOS transistor, so that the LC resonates at the target frequency and eliminates the influence of the MOS parasitic capacitance, thereby reducing the insertion loss of the switch.

[0047] For the gating branch, the control voltage Vc1 is high, MOS transistor M1, MOS transistor M2, MOS transistor M3 and MOS transistor M4 are equivalent to small resistors, the signal flows from port P1 to port P2, and the parallel branch is composed of the transmission line TL1 and MOS transistor M4 in series, which can be equivalent to a quarter wavelength transmission line with one end short-circuited, so the impedance of the parallel branch viewed from port P2 is very high, and therefore the signal cannot flow into the ground from the parallel branch. Because the gate control voltage of MOS transistor M4 is high, the working state of MOS transistor M4 will not change due to the large voltage swing of port P2, and the parallel branch composed of TL1 and MOS transistor M4 can withstand a very high voltage, thereby improving the power capacity of the switch circuit. For the off branch, when a single transistor processes a large power radio frequency signal, the swing of the large power signal can cause the parasitic PN junction inside the transistor in the off state to re-conduct or break down, causing the leakage of the radio frequency signal power, thereby deteriorating the insertion loss of the switch and reducing the power capacity. In order to realize high power capacity, three MOS transistors are used to share the voltage swing, so as to avoid the change of the working state of a single MOS transistor due to the bearing of too large voltage swing, thereby improving the linearity. In order to further improve the power bearing capacity of the off branch, the direct current level of the drain and source nodes is raised to high, and the gate is connected to low through a large resistor, so that the drain and source nodes are reversely biased with respect to the gate, thereby preventing the large signal from generating a large voltage swing at the gate of MOS transistor M1, MOS transistor M2 and MOS transistor M3 and changing the working state of the MOS transistor.

[0048] Therefore, the SP4T switch of the present application uses the stacking technology, the transmission line technology and the source biasing technology, so that the switch can bear a very high voltage, and therefore the power capacity is greatly improved, as shown in Figure 4 The test conditions and contents are shown in the following Figure 7 A power source is connected to port P1, one end of the power source is connected to the SP4T, and the other end of the SP4T is connected to a power meter through the gating branch. Figure 4 The abscissa represents the input power of the power source, and the ordinate represents the power measured by the power meter minus the input power of the power source, that is, the loss power of the SP4T. From Figure 4 It can be seen that when the input power is less than 24.8dBm, the loss of the SP4T is basically maintained at 2.2dB; when the input power is greater than 24.8dBm, the loss of the SP4T begins to increase greatly, and the 1dB compression point is 30.1dBm.

[0049] For the remaining three branches closed, the control voltage VC2 is low, MOS M1-1 (MOS M1-2, MOS M1-3), MOS M2-1 (MOS M2-2, MOS M2-3), MOS M3-1 (MOS M3-2, MOS 3-3) are equivalent to a large resistance, the signal will not from port P1 into port P3, port P4, port P5. Parallel branch TL2 (TL3, TL4) and MOS M4-1 (MOS 4-2, MOS 4-3) in series, can be equivalent to an open-ended quarter wavelength transmission line, so from the port P3, port P4, port P5 to the parallel branch impedance is low. By selecting the appropriate TL size, the low impedance formed by the MOS tube in series can be the impedance of port P3, port P4, port P5, so as to optimize the port matching of the closed branch and improve the return loss, as shown in Figure 5 Test conditions and contents: as shown in the following Figure 8 P1, P2, P3, P4, P5 port is connected to an impedance load, such as 50 ohms, by selecting the size of the parallel branch TL and MOS tube, so that the low resistance formed by the MOS tube in series is also 50 ohms. The reflection coefficient of P3, P4, P5 port is measured, and the return loss of P3, P4, P5 port is obtained. From Figure 5 It can be seen that in the target frequency band, the port return loss of SP4T closed branch is less than-34dB.

[0050] In addition, the parallel branch also provides a path for the signal leaked from port P1 via MOS M1-1 (MOS M1-2, MOS M1-3), MOS M2-1 (MOS M2-2, MOS M2-3), MOS M3-1 (MOS M3-2, MOS 3-3) to flow into the ground, which improves the isolation of the switch, as shown in Figure 6 Test conditions and contents: as shown in the following Figure 8 P1, P2, P3, P4, P5 port is connected to an impedance load, such as 50 ohms, by selecting the size of the parallel branch TL and MOS tube, so that the low resistance formed by the MOS tube in series is also 50 ohms (because the return loss and isolation are expressed by S parameters, so the test conditions of the two are the same). From Figure 6 It can be seen that in the target frequency band, the isolation of SP4T closed branch is less than-29.5dB.

[0051] It should be pointed out finally that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit the same; and although the present application has been described in detail with reference to the foregoing embodiments, it should be appreciated by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of operating a silicon-based radio frequency single pole four throw switch, characterized by: The silicon-based radio frequency single-pole four-throw switch structure is composed of a resistor, an inductor, a MOS tube, a transmission line and a DC blocking capacitor; The fourth branch is that the port P1 is connected with one end of a DC blocking capacitor C3, the other end of the DC blocking capacitor C3 is connected with one end of an inductor L3 and a source electrode of a MOS tube M1-1, a gate electrode of the MOS tube M1-1 is provided with a resistor R21 and is connected with a control voltage VC2, a substrate of the MOS tube M1-1 is provided with a resistor R5 and is connected with the ground, a drain electrode of the MOS tube M1-1 is connected with a source electrode of a MOS tube M2-1, a gate electrode of the MOS tube M2-1 is provided with a resistor R22 and is connected with the control voltage VC2, a substrate of the MOS tube M2-1 is provided with a resistor R6 and is connected with the ground, a drain electrode of the MOS tube M2-1 is connected with a source electrode of a MOS tube M3-1, a gate electrode of the MOS tube M3-1 is provided with a resistor R23 and is connected with the control voltage VC2, a substrate of the MOS tube M3-1 is provided with a resistor R7 and is connected with the ground, a drain electrode of the MOS tube M3-1 is connected with the other end of the inductor L3 and one end of a DC blocking capacitor C4, the other end of the DC blocking capacitor C4 is connected with a port P3 and one end of a transmission line TL2, the other end of the transmission line TL2 is connected with one end of an inductor L4 and a source electrode of a MOS tube M4-1, a gate electrode of the MOS tube M4-1 is provided with a resistor R24 and is connected with the control voltage VC2, a substrate of the MOS tube M4-1 is provided with a resistor R8 and is connected with the ground, and a drain electrode of the MOS tube M4-1 is connected with the other end of the inductor L4, wherein the control voltage VC2 is a low level. The fourth branch is that the port P1 is connected with one end of a DC blocking capacitor C3, the other end of the DC blocking capacitor C3 is connected with one end of an inductor L3 and a source electrode of a MOS tube M1-1, a gate electrode of the MOS tube M1-1 is provided with a resistor R21 and is connected with a control voltage VC2, a substrate of the MOS tube M1-1 is provided with a resistor R5 and is connected with the ground, a drain electrode of the MOS tube M1-1 is connected with a source electrode of a MOS tube M2-1, a gate electrode of the MOS tube M2-1 is provided with a resistor R22 and is connected with the control voltage VC2, a substrate of the MOS tube M2-1 is provided with a resistor R6 and is connected with the ground, a drain electrode of the MOS tube M2-1 is connected with a source electrode of a MOS tube M3-1, a gate electrode of the MOS tube M3-1 is provided with a resistor R23 and is connected with the control voltage VC2, a substrate of the MOS tube M3-1 is provided with a resistor R7 and is connected with the ground, a drain electrode of the MOS tube M3-1 is connected with the other end of the inductor L3 and one end of a DC blocking capacitor C4, the other end of the DC blocking capacitor C4 is connected with a port P3 and one end of a transmission line TL2, the other end of the transmission line TL2 is connected with one end of an inductor L4 and a source electrode of a MOS tube M4-1, a gate electrode of the MOS tube M4-1 is provided with a resistor R24 and is connected with the control voltage VC2, a substrate of the MOS tube M4-1 is provided with a resistor R8 and is connected with the ground, and a drain electrode of the MOS tube M4-1 is connected with the other end of the inductor L4, wherein the control voltage VC2 is a low level. The third branch is that port P1 is connected with one end of DC blocking capacitor C5, the other end of DC blocking capacitor C5 is connected with one end of inductor L5 and the source of MOS transistor M1-2, the gate of MOS transistor M1-2 is installed with a resistor R25 and then connected with control voltage VC2, the substrate of MOS transistor M1-2 is installed with resistor R9 and then connected with ground, the drain of MOS transistor M1-2 is connected with the source of MOS transistor M2-2, the gate of MOS transistor M2-2 is installed with a resistor R26 and then connected with control voltage VC2, the substrate of MOS transistor M2-2 is installed with resistor R10 and then connected with ground, the drain of MOS transistor M2-2 is connected with the source of MOS transistor M3-2, the gate of MOS transistor M3-2 is installed with a resistor R27 and then connected with control voltage VC2, the substrate of MOS transistor M3-2 is installed with resistor R11 and then connected with ground, the drain of MOS transistor M3-2 is connected with the other end of inductor L5 and one end of DC blocking capacitor C6, the other end of DC blocking capacitor C6 is connected with port P4 and one end of transmission line TL3, the other end of transmission line TL3 is connected with one end of inductor L6 and the source of MOS transistor M4-2, the gate of MOS transistor M4-2 is installed with a resistor R28 and then connected with control voltage VC2, the substrate of MOS transistor M4-2 is installed with resistor R12 and then connected with ground, the drain of MOS transistor M4-2 is connected with the other end of inductor L6; The fourth branch is that port P1 is connected with one end of DC blocking capacitor C7, the other end of DC blocking capacitor C7 is connected with one end of inductor L7 and the source of MOS transistor M1-3, the gate of MOS transistor M1-3 is installed with a resistor R29 and then connected with control voltage VC2, the substrate of MOS transistor M1-3 is installed with resistor R13 and then connected with ground, the drain of MOS transistor is connected with the source of MOS transistor M2-3, the gate of MOS transistor M2-3 is installed with a resistor R30 and then connected with control voltage VC2, the substrate of MOS transistor M2-3 is installed with resistor R14 and then connected with ground, the drain of MOS transistor M2-3 is connected with the source of MOS transistor M3-3, the gate of MOS transistor M3-3 is installed with a resistor R31 and then connected with control voltage VC2, the substrate of MOS transistor M2-3 is installed with resistor R15 and then connected with ground, the drain of MOS transistor M3-3 is connected with the other end of inductor L7 and one end of DC blocking capacitor C8, the other end of DC blocking capacitor C8 is connected with port P5 and one end of transmission line TL4, the other end of transmission line TL4 is connected with one end of inductor L8 and the source of MOS transistor M4-3, the gate of MOS transistor M4-3 is installed with a resistor R32 and then connected with control voltage VC2, the substrate of MOS transistor M4-3 is installed with resistor R16 and then connected with ground, the drain of MOS transistor M4-3 is connected with the other end of inductor L8; The working method is that For the gating branch, the control voltage VC1 is high, MOS M1, MOS M2, MOS M3, MOS M4 are equivalent to small resistance, the signal flows from port P1 to port P2, and the parallel branch is composed of transmission line TL1 and MOS M4 in series, which is equivalent to a quarter wavelength transmission line with one end short-circuited, the impedance of the parallel branch from port P2 is very high, and the signal will not flow into the ground from the parallel branch, the gate control voltage of MOS M4 is high, and its working state will not change due to the large voltage swing of port P2, the parallel branch composed of TL1 and MOS M4 can withstand very high voltage, thereby improving the power capacity of the switch circuit, for the off branch, when a single transistor handles a larger power radio frequency signal, the swing of the high-power signal will cause the internal parasitic PN junction of the transistor in the off state to re-conduct or break down, causing the leakage of radio frequency signal power, thereby deteriorating the insertion loss of the switch and reducing the power capacity, in order to realize high power capacity, three MOS transistors are used to share the voltage swing, avoiding the change of the working state of a single MOS transistor due to bearing too large voltage swing, thereby improving the linearity, in order to further improve the power bearing capacity of the off branch, the DC level of the drain and source node is raised to high level, and the gate is connected to low level through a large resistance, so that the drain and source node is reversely biased with respect to the gate, preventing large signal from generating large voltage swing at the gate of MOS M1, MOS M2, MOS M3 and changing the working state of the MOS transistor; For the remaining three branches, the control voltage VC2 is low, MOS M1-1, MOS M1-2, MOS M1-3, MOS M2-1, MOS M2-2, MOS M2-3, MOS M3-1, MOS M3-2, MOS M3-3 are equivalent to large resistance, the signal will not flow from port P1 to port P3, port P4, port P5, the parallel branch is composed of TL2, TL3, TL4 and MOS M4-1, MOS M4-2, MOS M4-3 in series, which is equivalent to a quarter wavelength transmission line with one end open-circuited, the impedance of the parallel branch from port P3, port P4, port P5 is low, by selecting appropriate TL size, the low impedance formed by TL and MOS transistor in series is the impedance of port P3, port P4, port P5, thereby optimizing the port matching of the off branch and improving the return loss.

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