level shifter
By designing a level converter with cross-coupled pairs and pull-down pairs, and utilizing P-channel metal-oxide-semiconductor field-effect transistors and control circuits, the problem of insufficient reliability of voltage converters in semiconductor manufacturing is solved, achieving high reliability and stable voltage conversion effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MEDIATEK INC
- Filing Date
- 2022-02-15
- Publication Date
- 2026-06-26
AI Technical Summary
In semiconductor manufacturing, as voltages shrink, power supply systems need to provide overdrive designs to transmit different voltage levels. Existing level converters are not reliable enough to meet high reliability requirements.
The level converter design employs cross-coupled pairs and pull-down pairs, utilizing P-channel metal-oxide-semiconductor field-effect transistors to achieve voltage conversion. Control signals are generated through control circuits and inverters to ensure stable operation of the voltage conversion between high and low levels.
This achieves stable operation of voltage conversion between high and low levels, avoids the influence of transistor threshold voltage, and improves the reliability of the level converter and the stability of the output signal duty cycle.
Smart Images
Figure CN115208378B_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention generally relate to voltage conversion technology, and more specifically, to a level shifter. Background Technology
[0002] As semiconductor manufacturing processes advance (e.g., shrinking to 5nm, 4nm, 3nm or below), the maximum applied voltage is suppressed (e.g., reduced to 1.2V, significantly lower than the 1.8V applied to 7nm products). If both 7nm and more advanced (e.g., 5nm / 4nm / 3nm or below) chips are present on the same printed circuit board (PCB), the power system must provide an overdriving design, for example, passing two different voltage levels, VDDQ and 2VDDQ (e.g., 2VDDQ is 2.5V or 3.3V), to two different power pins, VDIO0 and VDIO1. Therefore, a level shifter is required in this scenario. Moreover, a highly reliable level shifter is needed. Summary of the Invention
[0003] In view of this, one of the objectives of the present invention is to provide a level converter with high reliability.
[0004] The following summary is illustrative only and is not intended to be limiting in any way. That is, it provides an overview to introduce the concepts, key points, benefits, and advantages of the novel and non-obvious techniques described herein. Selected embodiments are further described in the detailed description below. Therefore, the following summary is neither intended to identify the essential features of the claimed subject matter nor to define the scope of the claimed subject matter.
[0005] In a first aspect, the present invention provides a level converter, wherein the level converter includes a cross-coupled pair and a pull-down pair. The cross-coupled pair couples a first power supply terminal to a first output terminal and a second output terminal of the level converter; the pull-down pair includes a first transistor and a second transistor, the first transistor and the second transistor being controlled by an input signal of the level converter. The first transistor is coupled between the second output terminal and a second power supply terminal, the second transistor is coupled between the first output terminal and the second power supply terminal, and a first voltage level coupled to the first power supply terminal is greater than a second voltage level coupled to the second power supply terminal, the second voltage level being greater than a ground level.
[0006] In some embodiments, the first voltage level coupled to the first power supply terminal is an overdrive voltage; and the second voltage level is equal to the power supply voltage level of the preceding stage circuit that supplies the input signal to the level converter.
[0007] In some embodiments, the level shifter further includes: a first control circuit that receives the input signal and generates a first control signal to be coupled to the gate of the first transistor; an inverter that receives the input signal and generates an inverted input signal; and a second control circuit that receives the inverted input signal and generates a second control signal to be coupled to the gate of the second transistor.
[0008] In some embodiments, the first transistor is a P-channel metal-oxide-semiconductor field-effect transistor, with its source coupled to the second output terminal and its drain coupled to the second power supply terminal; and the second transistor is a P-channel metal-oxide-semiconductor field-effect transistor, with its source coupled to the first output terminal and its drain coupled to the second power supply terminal.
[0009] In some embodiments, the cross-coupled pair includes a third transistor and a fourth transistor; the third transistor is a P-channel metal-oxide-semiconductor field-effect transistor, with its source coupled to the first power supply terminal, its drain coupled to the second output terminal, and its gate coupled to the first output terminal; and the fourth transistor is a P-channel metal-oxide-semiconductor field-effect transistor, with its source coupled to the first power supply terminal, its drain coupled to the first output terminal, and its gate coupled to the second output terminal.
[0010] In some embodiments, the first voltage level coupled to the first power supply terminal is an overdrive voltage; the first control signal generated by the first control circuit operates between the ground level and the overdrive voltage; and the second control signal generated by the second control circuit operates between the ground level and the overdrive voltage.
[0011] In some embodiments, the first control circuit pulls the first control signal high when the input signal is low and pulls the first control signal low when the input signal is high; and the second control circuit pulls the second control signal low when the inverted input signal is high and pulls the second control signal high when the inverted input signal is low.
[0012] In some embodiments, when the input signal is low, the first control circuit couples the gate of the first transistor to the second output terminal; when the input signal is high, the first control circuit grounds the gate of the first transistor; when the inverting input signal is high, the second control circuit grounds the gate of the second transistor; and when the inverting input signal is low, the second control circuit couples the gate of the second transistor to the first output terminal.
[0013] In some embodiments, the first control circuit includes a fifth transistor, a sixth transistor, and a seventh transistor; the fifth transistor is an N-channel metal-oxide-semiconductor field-effect transistor, whose gate receives the input signal and whose source is grounded; the sixth transistor is an N-channel metal-oxide-semiconductor field-effect transistor, whose source is coupled to the drain of the fifth transistor and whose drain is coupled to the gate of the first transistor; and the seventh transistor is a P-channel metal-oxide-semiconductor field-effect transistor, whose source is coupled to the second output terminal and whose drain is coupled to the gate of the first transistor.
[0014] In some embodiments, the gate of the sixth transistor is biased at a third voltage level, which is greater than the ground level and lower than the overdrive voltage; and the gate of the seventh transistor is biased at a fourth voltage level, which is greater than the ground level and lower than the overdrive voltage.
[0015] In some embodiments, the second control circuit includes an eighth transistor, a ninth transistor, and a tenth transistor; the eighth transistor is an N-channel metal-oxide-semiconductor field-effect transistor, whose gate receives the inverted input signal and whose source is grounded; the ninth transistor is an N-channel metal-oxide-semiconductor field-effect transistor, whose source is coupled to the drain of the eighth transistor and whose drain is coupled to the gate of the second transistor; and the tenth transistor is a P-channel metal-oxide-semiconductor field-effect transistor, whose source is coupled to the first output terminal and whose drain is coupled to the gate of the second transistor.
[0016] In some embodiments, the gate of the ninth transistor is biased at a third voltage level that is greater than the ground level and lower than the overdrive voltage; and the gate of the tenth transistor is biased at a fourth voltage level that is greater than the ground level and lower than the overdrive voltage.
[0017] In some embodiments, the second voltage level is equal to the third voltage level and also equal to the fourth voltage level.
[0018] In some embodiments, the second voltage level is also equal to the fifth voltage level of the power supply that provides the input signal to the preceding stage circuit of the level converter.
[0019] The present invention is provided by way of example and is not intended to limit the invention. These and other objects of the invention will be readily understood by those skilled in the art upon reading the following detailed description of the preferred embodiments illustrated in the accompanying drawings. A detailed description will be given in the following embodiments with reference to the accompanying drawings. Attached Figure Description
[0020] The accompanying drawings (in which the same numerals denote the same components) illustrate embodiments of the present invention. The included drawings are used to provide a further understanding of embodiments of the present disclosure, and are incorporated in and constitute a part of the present disclosure. The drawings illustrate implementations of embodiments of the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure. It is understood that the drawings are not necessarily drawn to scale, as some components may be shown out of proportion to actual dimensions in order to clearly illustrate the concepts of the embodiments of the present disclosure.
[0021] Figure 1 An exemplary embodiment of the present invention illustrates a level converter 100, which includes a cross-coupled pair 102, a pull-down pair 104, a first control circuit 106, an inverter Inv, and a second control circuit 108.
[0022] Figure 2 This is a detailed schematic diagram of the first control circuit 106 and the second control circuit 108 shown in an embodiment of the present invention.
[0023] Figure 3 It is an input and output (I / O) buffer 300 according to an exemplary embodiment of the present invention, which is coupled to pad 302.
[0024] In the following detailed description, numerous specific details are set forth for illustrative purposes so that those skilled in the art can more thoroughly understand the embodiments of the invention. However, it will be apparent that one or more embodiments may be practiced without these specific details, and different embodiments may be combined as needed, and should not be limited to the embodiments illustrated in the accompanying drawings. Detailed Implementation
[0025] The following description illustrates preferred embodiments of the present invention and is intended only to exemplify the technical features of the invention, not to limit the scope of the invention. Throughout this specification and claims, certain terms are used to refer to specific elements. Those skilled in the art should understand that manufacturers may use different names for the same element. Therefore, this specification and claims do not distinguish elements by differences in name, but rather by differences in function. The terms "element," "system," and "device" used in this invention can refer to computer-related entities, where the computer can be hardware, software, or a combination of hardware and software. The terms "comprising" and "including" as used in the following description and claims are open-ended terms and should be interpreted as "comprising, but not limited to...". Furthermore, the term "coupled" refers to an indirect or direct electrical connection. Therefore, if a device is described as coupled to another device, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.
[0026] Unless otherwise indicated, the corresponding numbers and symbols in the various figures generally refer to the corresponding parts. The figures are drawn to clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.
[0027] The terms "basically" or "roughly" as used in this document mean that, within an acceptable range, a person skilled in the art can solve the technical problem to be solved and basically achieve the desired technical effect. For example, "roughly equal to" means a method that a person skilled in the art can accept with a certain margin of error from "exactly equal to" without affecting the correctness of the result.
[0028] Figure 1 A level shifter 100 according to an exemplary embodiment of the present invention is shown, which includes a cross-coupled pair 102 (e.g., a cross-coupled transistor pair, such as M3 and M4, also referred to as a cross-coupled pull-up transistor pair), a pull-down pair 104 (e.g., a pull-down transistor pair, such as M1 and M2), a first control circuit 106, an inverter Inv, and a second control circuit 108.
[0029] Cross-coupler 102 couples a first power supply terminal (power line PW1 as shown in the figure) to a first output terminal OUT and a second output terminal OUTB of level converter 100. Pull-down pair 104 includes a first transistor M1 and a second transistor M2, which are controlled by the input signal IN of level converter 100; in other words, level converter 100 controls the first transistor M1 and the second transistor M2 based on the input signal IN of level converter 100. The first transistor M1 is coupled between the second output terminal OUTB and the second power supply terminal (power line PW2 as shown in the figure), and the second transistor M2 is coupled between the first output terminal OUT and the second power supply terminal PW2. A first voltage level (e.g., 2VDDQ) coupled to the first power supply terminal PW1 is greater than a second voltage level (e.g., approximately VDDQ) coupled to the second power supply terminal PW2, and the second voltage level (approximately VDDQ) is greater than the ground level (0 volts). In this example, the first voltage level coupled to the first power supply terminal PW1 (e.g., 2VDDQ, which can be understood as approximately twice VDDQ) is an overdrive voltage. That is, the first voltage level is greater than the threshold voltage at which the driving transistor in the circuit turns on, and is not necessarily 2VDDQ; 2VDDQ is an example voltage for ease of illustration. In another exemplary embodiment, the second voltage level is equal to the voltage level (e.g., VDDQ) of the power source that provides the input signal IN to the level converter 100 in the preceding stage circuit. Alternatively, the second voltage level may be equal to the voltage level (e.g., VDDQ) of the power source in the preceding stage circuit, which provides the input signal IN (as shown, the input signal IN is a control signal that switches between 0 and the second voltage level (e.g., VDDQ)) to the level converter 100.
[0030] like Figure 1 As shown, the shifted output signal (e.g., the signal at the first output terminal OUT) obtained from the input signal IN operates between a second voltage level (≈VDDQ) and a first voltage level (2VDDQ). Unaffected by the transistor threshold voltage Vt, the output duty cycle is not dependent on the manufacturing process.
[0031] exist Figure 1In the example, the first transistor M1 is a p-channel metal-oxide-semiconductor field-effect transistor (PMOS), with its source coupled to the second output terminal OUTB and its drain coupled to the second power supply terminal PW2. The second transistor M2 is a PMOS, with its source coupled to the first output terminal OUT and its drain coupled to the second power supply terminal PW2. The cross-coupled pair 102 includes a third transistor M3 and a fourth transistor M4. The third transistor M3 is a PMOS, with its source coupled to the first power supply terminal PW1, its drain coupled to the second output terminal OUTB, and its gate coupled to the first output terminal OUT. The fourth transistor M4 is a PMOS, with its source coupled to the first power supply terminal PW1, its drain coupled to the first output terminal OUT, and its gate coupled to the second output terminal OUTB.
[0032] The first control circuit 106 receives the input signal IN and generates a first control signal CS1, wherein the first control signal CS1 is coupled to the gate of the first transistor M1. The inverter Inv receives the input signal IN and generates an inverted input signal INB. The second control circuit 108 receives the inverted input signal INB and generates a second control signal CS2, wherein the second control signal CS2 is coupled to the gate of the second transistor M2. Both the first control signal CS1 generated by the first control circuit 106 and the second control signal CS2 generated by the second control circuit 108 operate between ground level (0 volts) and overdrive voltage (2VDDQ). The first control circuit 106 pulls up the first control signal CS1 when the input signal IN is low (e.g., 0 volts) and pulls down the first control signal CS1 when the input signal IN is high (e.g., VDDQ). The second control circuit 108 pulls the second control signal CS2 low when the inverting input signal INB is high (e.g., VDDQ), and pulls the second control signal CS2 high when the inverting input signal INB is low (e.g., 0 volts).
[0033] Figure 2 A schematic diagram of a first control circuit 106 and a second control circuit 108 is shown according to an exemplary embodiment of the present invention. When the input signal IN is low, the first control circuit 106 couples the gate of the first transistor M1 to the second output terminal OUTB; when the input signal IN is high, the first control circuit 106 grounds the gate of the first transistor M1; when the inverting input signal is high, the second control circuit 108 grounds the gate of the second transistor M2; and when the inverting input signal is low, the second control circuit 108 couples the gate of the second transistor M2 to the first output terminal OUT.
[0034] exist Figure 2 In the first control circuit 106, there are a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. Figure 2 In the example, the fifth transistor M5 is an n-channel metal-oxide-semiconductor field-effect transistor (NMOS) whose gate receives the input signal IN and whose source is grounded (0 volts). The sixth transistor M6 is an NMOS whose source is coupled to the drain of the fifth transistor M5, and whose drain is coupled to the gate of the first transistor M1. The seventh transistor M7 is a PMOS whose source is coupled to the second output terminal OUTB and whose drain is coupled to the gate of the first transistor M1. The gate of the sixth transistor M6 is biased at a third voltage level (e.g., the third voltage level ≈ VDDQ), which is greater than the ground level / voltage (0 volts) and lower than the overdrive level / voltage (e.g., the overdrive voltage is 2VDDQ). The gate of the seventh transistor M7 is biased at a fourth voltage level (e.g., the fourth voltage level ≈ VDDQ), which is greater than the ground level (0 volts) and lower than the overdrive level / voltage (e.g., the overdrive voltage is 2VDDQ).
[0035] exist Figure 2 In this circuit, the second control circuit 108 includes an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The eighth transistor M8 is an NMOS transistor, whose gate receives the inverted input signal INB, and whose source is grounded (0 volts). The ninth transistor M9 is an NMOS transistor, with its source coupled to the drain of the eighth transistor M8, and its drain coupled to the gate of the second transistor M2. The tenth transistor M10 is a PMOS transistor, with its source coupled to the first output terminal OUT, and its drain coupled to the gate of the second transistor M2. The gate of the ninth transistor M9 is biased at a third voltage level (e.g., approximately VDDQ), which is greater than ground (0 volts) and lower than the overdrive level (e.g., 2VDDQ). The gate of the tenth transistor M10 is biased at a fourth voltage level (e.g., approximately VDDQ), which is greater than ground (0 volts) and lower than the overdrive level (e.g., 2VDDQ).
[0036] The voltage level applied to the second power supply terminal PW2 and the voltage levels applied to the gates of the sixth transistor M6, seventh transistor M7, ninth transistor M9, and tenth transistor M10 may be different. In one exemplary embodiment, the voltage level applied to the second power supply terminal PW2 is equal to the voltage level applied to the gates of the sixth transistor M6, seventh transistor M7, ninth transistor M9, and tenth transistor M10. In another example embodiment, the second power supply terminal PW2 and the gates of the sixth transistor M6, seventh transistor M7, ninth transistor M9, and tenth transistor M10 are all biased to voltage level VDDQ (i.e., the second, third, and fourth voltage levels are all VDDQ). In one example, voltage level VDDQ is provided by a power supply coupled to the preceding stage circuitry that provides the input signal IN to the level shifter.
[0037] In some exemplary embodiments, more PMOS transistors may be coupled between the gate of the first transistor M1 and the second output terminal OUTB, and / or more PMOS transistors may be coupled between the gate of the second transistor M2 and the first output terminal OUT, and / or more NMOS transistors may be coupled to ground of the gate of the first transistor M1, and / or multiple NMOS transistors may be coupled to ground of the gate of the second transistor M2.
[0038] Figure 3 An input / output (I / O) buffer 300 coupled to pads 302 is shown according to an exemplary embodiment of the present invention. The I / O buffer 300 includes a pull-up string (such as a pull-up transistor string) 304, a pull-down string (such as a pull-down transistor string) 306, a driver circuit 308, and a level shifter 310. The power supply voltage of the driver circuit 308 is a second voltage level VDDQ. The power supply voltage of the pull-up string 304 and the pull-down string 306 is a first voltage level 2VDDQ, which is an overdrive voltage. The level shifter 310 is designed according to the foregoing example. In response to a high-to-low transition at input port I of the driver circuit 308, the output of the driver circuit transitions from 0 volts to VDDQ. Through the level shifter 310, the output signal of the driver circuit 308 is converted to operate between VDDQ and 2VDDQ, which is the appropriate voltage range for operating the pull-up string 304. The level shifter 310 is unaffected by changes in the transistor threshold voltage Vt.
[0039] The use of ordinal terms such as “first,” “second,” and “third” in the claims to modify claim elements does not in itself indicate any priority, precedence, or order of one claim element relative to another claim element, or the chronological order of the execution of method actions. Rather, it is merely used as a marker to distinguish one claim element with the same name from another element with the same name.
[0040] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various variations and similar structures (as will be apparent to those skilled in the art), such as combinations or substitutions of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such variations and similar structures.
Claims
1. A level converter, characterized in that, The level shifter includes: A cross-coupled pair is used to couple the first power supply terminal to the first output terminal and the second output terminal of the level converter. The pull-down pair includes a first transistor and a second transistor, which are controlled by the input signal of the level shifter; A first control circuit receives the input signal and generates a first control signal to be coupled to the gate of the first transistor; An inverter receives the input signal and generates an inverted input signal; and, The second control circuit receives the inverted input signal and generates a second control signal to be coupled to the gate of the second transistor. in: The first transistor is coupled between the second output terminal and the second power supply terminal, the second transistor is coupled between the first output terminal and the second power supply terminal, and the first voltage level coupled to the first power supply terminal is greater than the second voltage level coupled to the second power supply terminal, and the second voltage level is greater than the ground level. Wherein, the first transistor is a P-channel metal-oxide-semiconductor field-effect transistor, with its source coupled to the second output terminal and its drain coupled to the second power supply terminal; and the second transistor is a P-channel metal-oxide-semiconductor field-effect transistor, with its source coupled to the first output terminal and its drain coupled to the second power supply terminal. Wherein, at least one of the first control circuit and the second control circuit includes two N-channel metal-oxide-semiconductor field-effect transistors and one P-channel metal-oxide-semiconductor field-effect transistor. When the first control circuit includes two N-channel metal-oxide-semiconductor field-effect transistors and one P-channel metal-oxide-semiconductor field-effect transistor, the first control circuit includes a fifth transistor, a sixth transistor, and a seventh transistor. The fifth transistor is an N-channel metal-oxide-semiconductor field-effect transistor, whose gate receives the input signal and whose source is grounded. The sixth transistor is an N-channel metal-oxide-semiconductor field-effect transistor, with its source coupled to the drain of the fifth transistor, and its drain coupled to the gate of the first transistor; and, The seventh transistor is a P-channel metal-oxide-semiconductor field-effect transistor, with its source coupled to the second output terminal and its drain coupled to the gate of the first transistor. When the second control circuit includes two N-channel metal-oxide-semiconductor field-effect transistors and one P-channel metal-oxide-semiconductor field-effect transistor, the second control circuit includes an eighth transistor, a ninth transistor, and a tenth transistor. The eighth transistor is an N-channel metal-oxide-semiconductor field-effect transistor, whose gate receives the inverted input signal and whose source is grounded. The ninth transistor is an N-channel metal-oxide-semiconductor field-effect transistor, its source is coupled to the drain of the eighth transistor, and the drain of the ninth transistor is coupled to the gate of the second transistor; and, The tenth transistor is a P-channel metal-oxide-semiconductor field-effect transistor, with its source coupled to the first output terminal and its drain coupled to the gate of the second transistor.
2. The level converter as described in claim 1, characterized in that, The first voltage level coupled to the first power supply terminal is an overdrive voltage; and, The second voltage level is equal to the power supply voltage level of the preceding stage circuit that supplies the input signal to the level converter.
3. The level converter as described in claim 1, characterized in that, The cross-coupled pair includes a third transistor and a fourth transistor; The third transistor is a P-channel metal-oxide-semiconductor field-effect transistor, with its source coupled to the first power supply terminal, its drain coupled to the second output terminal, and its gate coupled to the first output terminal. as well as, The fourth transistor is a P-channel metal-oxide-semiconductor field-effect transistor, with its source coupled to the first power supply terminal, its drain coupled to the first output terminal, and its gate coupled to the second output terminal.
4. The level converter as described in claim 3, characterized in that, The first voltage level coupled to the first power supply terminal is an overdrive voltage; The first control signal generated by the first control circuit operates between the ground level and the overdrive voltage; and The second control signal generated by the second control circuit operates between the ground level and the overdrive voltage.
5. The level converter as described in claim 4, characterized in that, The first control circuit pulls the first control signal high when the input signal is low and pulls the first control signal low when the input signal is high; and The second control circuit pulls the second control signal low when the inverting input signal is high and pulls the second control signal high when the inverting input signal is low.
6. The level converter as described in claim 4, characterized in that, When the input signal is low, the first control circuit couples the gate of the first transistor to the second output terminal; When the input signal is high, the first control circuit grounds the gate of the first transistor; When the inverting input signal is high, the second control circuit grounds the gate of the second transistor; and, When the inverting input signal is low, the second control circuit couples the gate of the second transistor to the first output terminal.
7. The level converter as described in claim 2, characterized in that, The gate of the sixth transistor is biased at a third voltage level, which is greater than the ground level and lower than the overdrive voltage; and, The gate of the seventh transistor is biased at a fourth voltage level, which is greater than the ground level and lower than the overdrive voltage.
8. The level converter as described in claim 2, characterized in that, The gate of the ninth transistor is biased at a third voltage level that is greater than the ground level and lower than the overdrive voltage; and, The gate of the tenth transistor is biased at a fourth voltage level that is greater than the ground level and lower than the overdrive voltage.
9. The level converter as described in claim 7 or 8, characterized in that, The second voltage level is equal to the third voltage level and also equal to the fourth voltage level.
10. The level converter as claimed in claim 9, characterized in that, The second voltage level is also equal to the fifth voltage level of the power supply that provides the input signal to the preceding stage circuit of the level converter.