Fractional Divider

Abstract

The invention discloses a fractional frequency divider, which includes: a frequency division coefficient decoding module splits a received real-time frequency division coefficient into two parts, an integer frequency division ratio FN and a fractional frequency division ratio FD, and maps the frequency division ratio FN+FD to: FN+(x+y*FD1), FD=x+y*FD1; an SDM modulator module performs integral quantization processing on the mapped FD1, outputs a number of sequences K0 containing only 1 or 1, and the average of the sum of each number in K0 is FD1; a modulation and coding module receives the FN+x output by the frequency division coefficient decoding module and the sequence K0 output by the SDM modulator module for modulation and coding to form a frequency division ratio K2, and K2 is a sequence composed of (FN+x)+y and (FN+x)-y; a multi-mode frequency divider module receives the sequence K2 and divides the input clock. The fractional frequency divider of the invention is a fully digital design, which reduces aperture jitter, does not involve module integrated circuits, greatly reduces the chip footprint, and is more conducive to the high integration of the chip.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more particularly to a fractional frequency divider for reducing aperture jitter. Background Art

[0002] A common digital-analog hybrid IP core, whose function is to provide a stable and accurate clock signal for other modules. The principle is to compare the frequency and phase of the reference clock and the feedback clock through a frequency detection and phase detection module, and control the charge pump module to charge or discharge the internal capacitor. During the charging or discharging process, the plate voltage of the capacitor changes, thereby changing the input voltage of the voltage-controlled oscillation module. Because the output frequency of the voltage-controlled oscillation module is in direct proportion to the input voltage, the output clock frequency changes with the input voltage. On the one hand, the output clock is used as the input clock of the secondary circuit, and on the other hand, it is divided by a fractional frequency division module as the feedback clock of the input frequency detection and phase detection module; in this feedback process, the frequency of the feedback clock tends to be the same as that of the reference clock, the circuit enters a stable state, and the output clock is also stable. However, this circuit can provide a relatively stable clock frequency and its jitter is also small, but because it needs to use the device unit of the analog circuit, the area and power consumption are large.

[0003] Another solution is to use a fully digital fractional divider with a Sigma-Delta Mash structure, which has the function of accurately dividing the existing clock and pushing the noise brought by the division to high frequency, ensuring that the average frequency of the clock used in the subsequent circuit will not have large fluctuations within a period of time. The main principle is that the input division ratio is first accumulated in an integration module, and after accumulating to a certain threshold, the value in the integrator is quantized, and then sent to a high-pass filter after quantization. The integral value minus the value of the quantization bit is sent to the next level integrator. This is repeated three or four times to form a third-order Sigma-Delta Mash structure or a fourth-order Sigma-Delta Mash structure. Then the value of each level of quantization bit is added after passing through a high-pass filter, and its arithmetic sum is sent to the multi-mode divider module as the division ratio output. Finally, the multi-mode divider module divides the input clock to obtain the output clock. Although this all-digital Sigma-DeltaMash structured all-digital fractional frequency divider has a small area and low power consumption, the aperture jitter of the output clock is large and is not suitable for some applications that require high clock stability.

[0004] Therefore, it is necessary to provide an improved fractional frequency divider for reducing aperture jitter to overcome the above-mentioned defects. Summary of the invention

[0005] The object of the present invention is to provide a fractional frequency divider. The fractional frequency divider of the present invention is a fully digital design, which reduces aperture jitter, does not involve module integrated circuits, greatly reduces the chip occupied area, and is more conducive to the high integration of the chip.

[0006] To achieve the above object, the present invention provides a fractional frequency divider with the aperture jitter set to 1, which includes:

[0007] A frequency division coefficient decoding module, which splits the received real-time frequency division coefficient into two parts, an integer frequency division ratio FN and a fractional frequency division ratio FD, and 0 < FD < 1, and maps the frequency division ratio FN + FD into: FN+(x + y*FD1), FD = x + y*FD1, -1 < FD1 < 1, where both x and y are constants and are decimals less than 1;

[0008] An SDM modulator module, which performs integral quantization processing on the mapped FD1 and outputs a sequence K0 containing only 1 or -1, and the average value of the sum of each number in the sequence K0 is FD1;

[0009] A modulation coding module, which receives FN + x output by the frequency division coefficient decoding module and the sequence K0 output by the SDM modulator module for modulation coding to form a frequency division ratio K2, and K2 is a sequence composed of (FN + x)+y and (FN + x)-y;

[0010] A multi-mode frequency divider module, which receives the sequence K2 and divides the input clock according to the value of the K2 sequence.

[0011] Preferably, the fractional frequency divider further includes an amplitude control module, which adjusts the amplitude of the output K0 of the SDM modulator module and outputs K1 to the modulation coding module, and K1 = y*K0.

[0012] Preferably, the SDM modulator module adopts a 2nd-order 1-bit modulation structure.

[0013] Preferably, the output K0 of the SDM modulator module is an integer sequence of two states, the upper limit +1 and the lower limit -1 of FD1, and 0 < x + y*FD1 < 1, -1 < FD1 < 1. According to the limit operation, the upper limit is x + y = 1, the lower limit is x - y = 0, and the maximum values of x and y are both 0.5.

[0014] Preferably, the sequence K2 is a sequence composed of two numbers, FN and FN + 1.

[0015] Preferably, the SDM modulator module includes a first-order integrator, a second-order integrator and a quantizer. The mapped FD1 and K0*G2*G1 serve as inputs of the first-order integrator. The first-order integrator outputs H1 after integrating the two input data. H1 and K0*G2 serve as inputs of the second-order integrator. The second-order integrator outputs H2 after integrating the two input data. The quantizer quantizes H2 to obtain the output K0 of the SDM modulator module. G1 and G2 are constants less than 1.

[0016] Compared with the prior art, the fractional frequency divider of the present invention is implemented in a fully digital form, avoiding the use of larger capacitors and relatively complex analog integrated circuit devices with relatively complex process transplantation, thereby greatly saving chip area; the SDM modulator module uses a two-order 1-bit modulation structure, modulates a -0.5 to +0.5 division ratio and then loads it to a fixed division ratio, so that the aperture jitter of the entire fractional frequency divider is greatly reduced, thereby optimizing the aperture jitter performance.

[0017] The present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, which are used to illustrate embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural schematic diagram of the fractional frequency divider of the present invention. DETAILED DESCRIPTION

[0019] Embodiments of the present invention are now described with reference to the accompanying drawings, in which like element numbers represent like elements. As described above, the present invention provides a fractional frequency divider, which is a fully digital design, reduces aperture jitter, does not involve module integrated circuits, greatly reduces chip footprint, and is more conducive to high chip integration.

[0020] Please refer to Figure 1 , Figure 1This is a schematic structural diagram of the fractional frequency divider of the present invention. As shown in the figure, the aperture jitter of the fractional frequency divider of the present invention is set to 1, and it includes a frequency division coefficient decoding module, an SDM modulator module, a modulation coding module, and a multi-mode frequency divider module; the frequency division coefficient decoding module splits the received real-time frequency division coefficient into two parts, an integer frequency division ratio FN and a fractional frequency division ratio FD, where 0 < FD < 1, and maps the frequency division ratio FN + FD into: FN+(x + y*FD1), FD = x + y*FD1, both x and y are constants and are decimals less than 1, and FN + x and FD1 are respectively output; specifically, the values of x and y can be determined according to the set value of the aperture jitter. In the present invention, the aperture jitter is set to 1, and FD1 related to the fractional frequency division ratio FD is used as the input of the SDM modulator module, and its value is -1 < FD1 < 1. The SDM modulator module performs integral quantization processing on the mapped FD1 and outputs a sequence K0 containing only 1 or -1, and the average value of the sum of the numbers in the sequence K0 is FD1; as a preferred embodiment of the present invention, the SDM modulator module adopts a 2nd-order 1-bit modulation structure, and the output range of the 1-bit modulation structure is from -1 to +1. At the same time, the amplitude range of the output value K0 of the SDM modulator module is the upper and lower limit values of the input signal FD1, that is, 1 and -1, that is, K0 is a sequence containing only 1 or -1, and the average value of the sum of the numbers in the sequence K0 is FD1. Therefore, after passing through the SDM modulator module, the sequence K0 can correctly represent the value of FD1, and FD1 = (FD - x) / y.

[0021] In addition, as a preferred embodiment of the present invention, the fractional frequency divider further includes an amplitude control module. The amplitude control module adjusts the amplitude of the output K0 of the SDM modulator module and outputs K1 to the modulation coding module, and K1 = y*K0; y is the matching amplitude required for the output signal K0 of the SDM modulator module, and K1 is the value obtained after amplitude matching of K0, that is: K1 = y or K1 = -y, and the value of y can be preset according to the design requirements.

[0022] The modulation and encoding module receives FN+x output by the frequency division coefficient decoding module and the sequence K0 output by the SDM modulator module, and performs modulation and encoding to form a frequency division ratio K2. Moreover, K2 is a sequence composed of (FN+x)+y and (FN+x)-y. Specifically, in the present invention, the sequence input to the modulation and encoding module is K0 after amplitude adjustment, that is, FN+x and the sequence K1 are input to the modulation and encoding module. The modulation and encoding module performs modulation and encoding on the input FN+x and the sequence K1 to form the final frequency division ratio K2. As described above, since the input of the SDM modulator module is FD1, and FD1 is a stable floating-point number between -1 and +1, and the output K0 of the SDM modulator module is an integer sequence of two states, namely the upper limit +1 and the lower limit -1 of FD1, and the average value of this integer sequence is the same as FD1. Also, according to the previous definition of the fractional frequency division ratio range: 0<x+y*FD1<1 and -1<FD1<1, when taking the limit of FD1, there is an upper limit of x+y = 1 and a lower limit of x-y = 0. Thus, it can be obtained that the maximum values of x and y are 0.5. And the final frequency division ratio K2 is the sum of the inherent frequency division ratio FN+x and K1, that is, K2 = FN+x+K1. Therefore, the output K2 of the modulation and encoding module is a sequence composed of (FN+x)+y and (FN+x)-y. Then, according to the upper limit x+y = 1 and the lower limit x-y = 0, it can be obtained that x = 0.5 and y = 0.5, and K2 has two frequency division ratios, namely FN and FN+1. Thus, the difference between the frequency division ratios is very small, so the aperture jitter is also very small. Among them, the values of x and y can be specifically and flexibly set according to the fractional part of the input frequency division coefficient and the requirements for the amplitude of the output signal of the SDM modulator module, as long as they do not exceed the maximum value of 0.5.

[0023] The multi-mode frequency divider module receives the sequence K2 and divides the input clock according to the values of the K2 sequence, so as to finally obtain an output clock that meets the design requirements.

[0024] In addition, as a preferred embodiment of the present invention, the SDM modulator module includes a first-order integrator H1(S), a second-order integrator H2(S), and a quantizer; as Figure 1As shown, the mapped FD1 and K0*G2*G1 are used as inputs of the first-order integrator H1(S), which outputs H1 after integrating the two input data. H1 and K0*G2 are used as inputs of the second-order integrator H2(S), which outputs H2 after integrating the two input data. The quantizer quantizes H2, and quantizes the decimal H2 obtained after the second-order integration into an integer to obtain the output K0 of the SDM modulator module. K0 is a sequence of 1 and -1. G1 and G2 are constants less than 1 as feedback coefficients of the integrator, and their specific values ​​are related to the range of the input signal FD1 of the SDM modulator module, the output range of the SDM modulator module and the modulation accuracy of the SDM modulator module.

[0025] In summary, the fractional divider of the present invention is implemented in a fully digital form, avoiding the use of larger capacitors and relatively complex analog integrated circuit devices with relatively complex process transplantation, thereby greatly saving chip area; and the SDM modulator module uses a two-order 1-bit modulation structure, modulating a division ratio of -0.5 to +0.5 and then loading it to a fixed division ratio, so that the aperture jitter of the entire fractional divider is greatly reduced, thereby optimizing the aperture jitter performance.

[0026] The present invention has been described above in conjunction with the best embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations based on the essence of the present invention.

Claims

1. A fractional frequency divider, with aperture jitter set to 1, characterized in that including a frequency division coefficient decoding module, which splits the received real-time frequency division coefficient into two parts, an integer frequency division ratio FN and a fractional frequency division ratio FD, where 0 < FD < 1, and maps the frequency division ratio FN+FD into: FN+(x+y*FD1), FD = x+y*FD1, -1 < FD1 < 1, and both x and y are constants and are fractions less than 1; an SDM modulator module, which performs integral quantization processing on the mapped FD1 and outputs a series of numbers K0 containing only 1 or -1, and the average value of the sum of each number in the series K0 is FD1; a modulation coding module, which receives FN+x output by the frequency division coefficient decoding module and the series of numbers K0 output by the SDM modulator module to perform modulation coding to form a frequency division ratio K2, and K2 is a series of numbers composed of (FN+x)+y and (FN+x)-y; a multi-mode frequency divider module, which receives the series of numbers K2 and divides the input clock according to the values of the K2 series; 2. The fractional frequency divider according to claim 1, wherein: further including an amplitude control module, which adjusts the amplitude of the output K0 of the SDM modulator module and outputs K1 to the modulation coding module, and K1 = y*K0; 3. The fractional frequency divider according to claim 2, wherein: the SDM modulator module adopts a 2nd-order 1-bit modulation structure; 4. The fractional frequency divider according to claim 3, characterized in that: the output K0 of the SDM modulator module is an integer series of two states, the upper limit +1 and the lower limit -1 of FD1, and 0 < x+y*FD1 < 1, -1 < FD1 < 1. According to the limit operation, the upper limit is x+y = 1, the lower limit is x-y = 0, and the maximum values of x and y are both 0.5; 5. The fractional frequency divider according to claim 4, characterized in that: the series of numbers K2 is a series of numbers composed of two numbers, FN and FN+1; 6. The fractional frequency divider according to any one of claims 2 to 5, characterized in that: the SDM modulator module includes a first-order integrator, a second-order integrator and a quantizer. The mapped FD1 and K0*G2*G1 are used as the inputs of the first-order integrator. The first-order integrator performs integral operation on the two input data and outputs H1. H1 and K0*G2 are used as the inputs of the second-order integrator. The second-order integrator performs integral operation on the two input data and outputs H2. The quantizer quantizes H2 to obtain the output K0 of the SDM modulator module, and G1 and G2 are constants less than 1.

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