Fast and high linearity frequency source system based on two-point modulation

Abstract

The present invention discloses a fast, highly linear frequency source system based on two-point modulation. The system comprises two modulation paths: a high-pass frequency modulation path and a low-pass phase-locked path. The high-pass frequency modulation path comprises a ramp generator, a LUT, a DAC, a low-pass filter, and a VCO, while the low-pass phase-locked path comprises a VCO, an injection-locked frequency divider (ILFD), a current-mode logic (CML) frequency divider, a programmable frequency divider, a DSM modulator, a phase-frequency detector (PFD), a charge pump, and a loop filter. The system uses a DAC and a phase-locked loop (PLL) to perform two-point modulation of the VCO, reducing chirp time and accelerating chirp frequency modulation rate. An undersampling loop is used for phase locking, optimizing in-band phase noise, and eliminating the power consumption of the frequency division link to the PLL system. The system also features digital SPI controllable point frequency, triangle wave frequency modulation, and sawtooth wave frequency modulation outputs. The system supports multiple reference clock types and has controllable frequency modulation information.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit systems, and in particular to a two-point modulated fast, high-linearity (frequency modulated continuous wave) FMCW frequency source system. Background Art

[0002] CMOS millimeter-wave frequency-modulated continuous-wave radar plays an important role in various application scenarios such as autonomous driving. The frequency source is one of its core modules. Its phase noise, spurious, frequency modulation linearity, frequency modulation rate, power consumption and other indicators have an extremely important impact on the performance of the radar system. Because its frequency modulation rate, frequency modulation linearity and frequency modulation bandwidth will directly affect the radar system's core indicators such as the intermediate frequency signal-to-noise ratio and detection resolution, there is also a great demand for high-performance frequency sources used in frequency-modulated continuous-wave radar systems.

[0003] The range resolution of a radar system is inversely proportional to the frequency source's sweep bandwidth. The wider the frequency source's sweep bandwidth, the smaller the radar system's minimum range resolution. Fast frequency modulation is also necessary for close-range target detection. Because the intermediate frequency is pushed beyond the receiver's 1 / f noise, the signal-to-noise ratio (SNR) at the target frequency is also improved.

[0004] Traditional FM frequency sources can be implemented using fractional-N phase-locked loops (PLLs), which modulate the output frequency by changing the division ratio. Frequency accuracy can be achieved by increasing the decimal places of the delta-sigma modulator (DSM). Furthermore, the PLL is a closed-loop feedback system, and the error in its output frequency is comparable to the error in the input reference frequency. However, considering the stability of the loop, the PLL has a low loop bandwidth, which severely limits the FM rate.

[0005] The open-loop modulation mode based on the digital-to-analog converter (DAC) can achieve very high frequency modulation speeds. However, in order to ensure sufficiently high frequency accuracy, a very high-bit lookup table (LUT) is required to suppress process, voltage, and temperature (PVT) variations and nonlinearity, which consumes huge power. Summary of the Invention

[0006] The purpose of the present invention is to address the technical deficiencies in the prior art and provide a novel high-performance FMCW frequency source system, specifically a fast, highly linear, broadband frequency source system based on a two-point modulation architecture.

[0007] The technical solution adopted to achieve the purpose of the present invention is:

[0008] A fast, highly linear frequency source system based on two-point modulation consists of two modulation paths: a high-pass frequency modulation path and a low-pass phase-locked path. The high-pass frequency modulation path consists of a ramp generator, a LUT, a DAC, a low-pass filter, and a VCO. The low-pass phase-locked path is a fractional-N phase-locked loop structure consisting of a VCO, an injection-locked frequency divider (ILFD), a current-mode logic (CML) frequency divider, a programmable frequency divider, a DSM modulator, a phase-frequency detector (PFD), a charge pump, and a loop filter.

[0009] The output end of the ramp generator is connected to the input end of the LUT, the output end of the LUT is connected to the input end of the DAC, the output end of the DAC is connected to the input end of the low-pass filter, and the output end of the low-pass filter is connected to the FM signal input end of the VCO; the ramp generator is connected to the DSM modulator, the signal output end of the DSM modulator is connected to the modulation signal input end of the programmable frequency divider, the frequency divider signal input end of the programmable frequency divider is connected to the signal output end of the current mode logic frequency divider CML, the signal output end of the programmable frequency divider is connected to the frequency divider signal input end of the phase frequency detector PFD, the output end of the phase frequency detector PFD is connected to the input end of the dead zone, the input end of the dead zone is connected to the input end of the charge pump, the output end of the charge pump is connected to the input end of the loop filter, and the output end of the loop filter is connected to the PLL signal input end of the VCO.

[0010] A VCO differential output is connected to a buffer, an output of the buffer is connected to a signal input of a subsampling phase detector SSPD, the signal output of the subsampling phase detector SSPD is connected to a signal input of a subsampling charge pump SSCP, and the signal output of the subsampling charge pump SSCP is connected to a signal input of a loop filter; a quantization error extractor for extracting error sign information is provided at the output of the charge pump, and a signal output of the quantization error extractor is connected to an error signal input of a LUT;

[0011] The other end of the differential output of the VCO is connected to the input end of the injection locked frequency divider, the output end of the injection locked frequency divider is connected to the input end of the current mode logic frequency divider CML, and the output end of the current mode logic frequency divider CML is connected to the input end of the digital programmable frequency divider.

[0012] The DTC signal input terminal of the SSPD is connected to the signal output terminal of the digital delay converter DTC, and the input terminal of the delay converter DTC is used to receive the control word.

[0013] The SPI signal input terminal of the ramp wave generator is connected to the signal output terminal of the SPI.

[0014] The present invention is based on a fast, high-linearity frequency source system with two-point modulation. By adopting a DAC and a phase-locked loop to perform two-point modulation of a voltage-controlled oscillator (VCO), the chirp time is reduced, the chirp frequency modulation rate is accelerated, an undersampling loop is used for phase locking, the in-band phase noise is optimized, and the power consumption contributed by the frequency division link to the PLL system is eliminated. The digital SPI can control the point frequency, triangle wave frequency modulation, and sawtooth wave frequency modulation output, supports multiple reference clock types, and the frequency modulation information is controllable. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic diagram of a fast, high-linearity frequency source system based on two-point modulation according to the present invention. DETAILED DESCRIPTION

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0017] like Figure 1 As shown, the fast, high-linearity frequency source system based on two-point modulation in an embodiment of the present invention consists of two modulation paths, wherein baseband data is transmitted to the chip through the serial peripheral interface SPI. The high-pass frequency modulation path consists of a ramp generator (Ramp Generation), a digital-to-analog converter DAC, a lookup table LUT, a low-pass filter Filter (RC filter), and a voltage-controlled oscillator VCO. The low-pass phase-locked path is a traditional fractional-N phase-locked loop structure, consisting of a voltage-controlled oscillator VCO, an injection-locked divider ILFD Div2, a current-mode logic divider CML, a programmable digital frequency divider, a DSM modulator, a phase frequency detector PFD, a dead zone (delay circuit used to control and offset the switching delay of the charge pump), a charge pump Charge Pump, and a loop filter Loop Filter; wherein the phase frequency detector PFD also receives an Fref signal.

[0018] The output end of the ramp generator is connected to the input end of the LUT, the output end of the LUT is connected to the input end of the DAC, the output end of the DAC is connected to the input end of the low-pass filter, the output end of the low-pass filter is connected to the Vtune (frequency tuning control signal) of the VCO and the FM signal input end; the ramp generator is connected to the DSM modulator, the signal output end of the DSM modulator is connected to the modulation signal input end of the programmable frequency divider, the frequency divider signal input end of the programmable frequency divider is connected to the signal output end of the current mode logic frequency divider CML, the signal output end of the programmable frequency divider is connected to the frequency divider signal input end of the phase frequency detector PFD, the output end of the phase frequency detector PFD is connected to the input end of the dead zone, the input end of the dead zone is connected to the input end of the charge pump, the output end of the charge pump is connected to the input end of the loop filter, and the output end of the loop filter is connected to the Vtune (frequency tuning control signal) of the VCO and the PLL signal input end.

[0019] A VCO differential output is connected to a buffer, an output of the buffer is connected to a signal input of a subsampling phase detector SSPD, the signal output of the subsampling phase detector SSPD is connected to a signal input of a subsampling charge pump SSCP, and the signal output of the subsampling charge pump SSCP is connected to a signal input of a loop filter; a quantization error extractor for extracting error sign information is provided at the output of the charge pump, and a signal output of the quantization error extractor is connected to an error signal input of a LUT;

[0020] The other end of the differential output of the VCO is connected to the input end of the injection locked frequency divider, the output end of the injection locked frequency divider is connected to the input end of the current mode logic frequency divider CML, and the output end of the current mode logic frequency divider CML is connected to the input end of the digital programmable frequency divider.

[0021] The DTC signal input terminal of the SSPD is connected to the signal output terminal of the digital delay converter DTC, and the input terminal of the delay converter DTC is used to receive the control word.

[0022] The SPI signal input terminal of the ramp wave generator is connected to the signal output terminal of the SPI.

[0023] The signal processing flow of the fast, high-linearity frequency source system with two-point modulation according to the embodiment of the present invention is as follows:

[0024] The baseband control information is input to the chip from the off-chip FPGA through SPI. By controlling the ramp wave generator through SPI, the frequency source output point frequency mode and FMCW frequency modulation mode can be set. In the FMCW frequency modulation mode, the frequency modulation period and frequency modulation waveform can also be set through SPI.

[0025] The ramp generator performs digital logic processing on the control information output by the SPI and outputs the obtained frequency division ratio information to the DSM. The DSM quantizes the high-precision digital code into a low-bit digital code sequence, and the DSM transmits the digital sequence with the frequency division ratio information to the programmable frequency divider.

[0026] On the other hand, the ramp generator transmits the DAC control information to the LUT first, and then sends it to the DAC after LUT compensation calibration to control the DAC output voltage. After low-pass filtering by the filter, Vtune is generated and FM is used to control the VCO.

[0027] Among them, the VCO will output a radio frequency signal of a certain oscillation frequency according to the size of the input Vtune and FM. The radio frequency signal is pre-divided by ILFD Div2 and then divided by eight by CML Div8 to reduce the radio frequency signal to around 1GHz. The signal can then be input to the programmable divider and divided more widely according to the control of DSM. The signal after the programmable divider is F Dvi , F Dvi On the one hand, it is fed back to the PFD to compare its phase and frequency with the reference clock Fref; on the other hand, it is used as a digital clock for the DSM and ramp generator to perform digital processing.

[0028] Among them, the PFD compares the reference clock and the feedback clock, and outputs a pulse signal with a phase difference between the two. After delay processing in the dead zone, the switch tube of the charge pump is controlled to control the charge pump to charge and discharge the loop filter, and the control voltage Vtune, PLL of the VCO is obtained. Finally, the VCO outputs the RF signal of the corresponding frequency through the two tuning voltages of Vtune, PLL and Vtune, FM.

[0029] This architecture also supports undersampling mode. The digital baseband signal sends the control word to the DTC, which obtains the sampling clock with the target phase information through digital delay conversion. The RF signal output by the VCO is buffered and isolated and sent to the SSPD. The SSPD uses the sampling clock output by the DTC to sample the VCO signal and sends the sampled voltage signal to the SSCP. The SSCP compares the sampled voltage with the reference voltage to determine whether to charge or discharge the loop filter, thereby controlling the output frequency of the voltage-controlled oscillator.

[0030] In an embodiment of the present invention, an undersampling loop is used for phase locking, in-band phase noise is optimized, and the power consumption contributed by the frequency division link to the PLL system is eliminated. The undersampling loop is composed of a baseband control word, a digital delay converter DTC, an undersampling phase detector SSPD, and an undersampling charge pump SSCP.

[0031] One VCO differential output is connected to the buffer of the subsampling loop. After isolation and amplification by the buffer, the phase information is transmitted to the subsampling phase detector (SSPD). Phase lock is achieved through the subsampling charge pump (SSCP). The other differential output of the VCO is connected to the injection-locked 2-divider (ILFD Div2), the CML Div8 divider, and the digitally programmable divider. The desired division ratio can be controlled by a control word, and the VCO output signal (Fout) is generated.

[0032] In addition, to offset the nonlinear error in the frequency modulation path, an embodiment of the present invention adds a quantization error extractor to monitor Vtune (frequency tuning control signal), the changes in the PLL, extract the error sign information, and feed it back to the LUT to compensate the initial DAC code, add or subtract a calibration code to the original code, and ultimately reduce the modulation error.

[0033] Among them, the signal input end of the DSM modulator is connected to the signal output end of the programmable frequency divider, receives the Fdvi signal, and performs DSM modulation processing according to the signal; the frequency division signal input end of the ramp wave generator is connected to the signal output end of the programmable frequency divider, receives the Fdvi signal and forms a ramp wave according to the signal.

[0034] The ramp wave generator further receives a mode control signal Mod_Ctrl for mode control and receives a start signal Start for start control.

[0035] In the frequency source system of the embodiment of the present invention, baseband data is converted into an analog voltage by a DAC to directly modulate the output frequency of a voltage-controlled oscillator (VCO), thereby reducing the frequency modulation time and accelerating the frequency modulation rate. Furthermore, the baseband data is simultaneously input to a DSM modulator to control the frequency division ratio of a frequency divider. As long as the gain and phase matching of the two modulation paths is ensured, the transfer function from the baseband data to the output end exhibits an all-pass characteristic, and the frequency modulation speed is no longer limited by the loop bandwidth of the phase-locked loop. At the same time, due to the feedback effect of the PLL loop, its output frequency is always locked at the required frequency, thereby achieving the requirement of fast frequency modulation.

[0036] The frequency source system design of the embodiment of the present invention mainly includes the following steps:

[0037] S1. Determine the radar system power consumption, ranging resolution, and ranging range requirements. Calculate the specific requirements for the frequency source's frequency modulation bandwidth, frequency modulation rate, frequency modulation error, phase noise, power consumption, and other aspects.

[0038] S2. Allocate the frequency source to the VCO, frequency divider, charge pump and other circuit modules according to the set system bandwidth, phase noise, power consumption and other indicators, and set the input and output interface information and driving capability of each module as required.

[0039] S3. Determine the number of DAC bits, minimum integral error, power consumption and other indicators based on the frequency modulation period, frequency modulation linearity and other indicators, and determine the number of LUT calibration bits based on the VCO's own nonlinearity.

[0040] S4. Design a digital ramp wave generator control circuit, set the counter parameters and indicators such as frequency modulation period and frequency modulation rate according to the reference clock, and make the dot frequency, sawtooth wave, and triangle wave output controllable.

[0041] The two-point modulation architecture introduced in the present invention combines the traditional DAC-based open-loop direct frequency modulation with the phase-locked loop closed-loop feedback modulation, taking advantage of their strengths and overcoming their weaknesses to achieve fast, high-linearity frequency modulation.

[0042] The present invention adopts an undersampling loop to perform phase locking, which can greatly reduce the power consumption contributed by the frequency division link on the one hand, and reduce the contribution of the loop to the in-band noise on the other hand.

[0043] The digital SPI of the present invention can control the dot frequency, triangle wave frequency modulation, and sawtooth wave frequency modulation output, supports multiple reference clock types, and the chirp information is controllable.

[0044] The present invention detects nonlinearity through a nonlinear error quantization extraction module and then calibrates the nonlinearity by referencing a lookup table, thereby greatly improving the frequency modulation linearity.

[0045] The basic principles, main features and advantages of the present invention are shown and described above. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments and that the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0046] Therefore, from any point of view, the embodiments should be regarded as illustrative and non-restrictive, and the scope of the invention is limited by the appended claims rather than the above description. Therefore, it is intended that all changes that fall within the meaning and range of equivalent elements of the claims are included in the present invention, and any figure signs in the claims should not be regarded as limiting the claims involved.

[0047] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A fast, high linearity frequency source system based on two-point modulation, characterized by: It consists of two modulation paths: a high-pass FM path and a low-pass PLL path. The high-pass FM path consists of a ramp generator, LUT, DAC, low-pass filter, and VCO. The low-pass PLL path is a fractional-N PLL structure, consisting of a VCO, an injection-locked frequency divider ILFD, a current-mode logic frequency divider CML, a programmable frequency divider, a DSM modulator, a phase frequency detector PFD, a charge pump, and a loop filter. The output end of the ramp generator is connected to the input end of the LUT, the output end of the LUT is connected to the input end of the DAC, the output end of the DAC is connected to the input end of the low-pass filter, and the output end of the low-pass filter is connected to the FM signal input end of the VCO; the ramp generator is connected to the DSM modulator, the signal output end of the DSM modulator is connected to the modulation signal input end of the programmable frequency divider, the frequency divider signal input end of the programmable frequency divider is connected to the signal output end of the current mode logic frequency divider CML, the signal output end of the programmable frequency divider is connected to the frequency divider signal input end of the phase frequency detector PFD, the output end of the phase frequency detector PFD is connected to the input end of the dead zone, the input end of the dead zone is connected to the input end of the charge pump, the output end of the charge pump is connected to the input end of the loop filter, and the output end of the loop filter is connected to the PLL signal input end of the VCO; A VCO differential output is connected to a buffer, an output of the buffer is connected to a signal input of a subsampling phase detector SSPD, the signal output of the subsampling phase detector SSPD is connected to a signal input of a subsampling charge pump SSCP, and the signal output of the subsampling charge pump SSCP is connected to a signal input of a loop filter; a quantization error extractor for extracting error sign information is provided at the output of the charge pump, and a signal output of the quantization error extractor is connected to an error signal input of a LUT; The other end of the differential output of the VCO is connected to the input end of the injection locked frequency divider, the output end of the injection locked frequency divider is connected to the input end of the current mode logic frequency divider CML, and the output end of the current mode logic frequency divider CML is connected to the input end of the digital programmable frequency divider.

2. The fast, high linearity frequency source system based on two-point modulation according to claim 1, characterized in that: The DTC signal input terminal of the SSPD is connected to the signal output terminal of the digital delay converter DTC, and the input terminal of the delay converter DTC is used to receive the control word.

3. The fast, high linearity frequency source system based on two-point modulation according to claim 1, characterized in that: The SPI signal input terminal of the ramp wave generator is connected to the signal output terminal of the SPI.

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