Power supply control device

Abstract

In the power supply control device (10), an N-channel type first FET (20a) and a second FET (20b) are configured in the current path of the current flowing from the positive terminal (Tp) to the negative terminal (Tn). For the first FET (20a), the drain is configured downstream of the source. For the second FET (20b), the drain is configured upstream of the source. The cathode of the first diode (26) is connected to the negative terminal Tn. The first drive circuit (21a) and the second drive circuit (21b) switch the first FET (20a) and the second FET (20b) to be on or off by adjusting the gates of the first FET (20a) and the second FET (20b) to a reference potential equal to the potential of the cathode of the first diode (26).

Description

Technical Field

[0001] This disclosure relates to power supply control devices.

[0002] This application claims priority based on Japanese Application No. 2020-045529, filed on March 16, 2020, and invokes all the contents of that Japanese application. Background Technology

[0003] Patent Document 1 discloses a power supply control device for a vehicle that controls the supply of power to a load from a DC power supply detachably connected between a first terminal and a second terminal. When the positive and negative terminals of the DC power supply are connected to the first and second terminals respectively, the DC power supply is connected correctly. When the positive and negative terminals of the DC power supply are connected to the second and first terminals respectively, the DC power supply is connected in reverse. The user may incorrectly connect the DC power supply, i.e., connect it in reverse.

[0004] In the power supply control device described in Patent Document 1, two N-channel FETs (Metal Oxide Semiconductor Field Effect Transistors) are arranged in the current path of the current flowing from the first terminal to the second terminal. For one FET, the drain is positioned downstream of the source in the current path. For the other FET, the drain is positioned upstream of the source in the current path. The resistance between the drain and source is adjusted by adjusting the gate voltages of the two FETs. The two FETs are switched on by adjusting their resistance values ​​to a sufficiently small value. The two FETs are switched off by adjusting their resistance values ​​to a sufficiently large value.

[0005] Parasitic diodes are formed in two FETs, with their cathodes and anodes connected to the drain and source, respectively. In the power supply control device described in Patent Document 1, the cathodes of the two parasitic diodes are interconnected. Therefore, when the DC power supply is connected in reverse, current will not flow from the second terminal to the first terminal as long as the two FETs are disconnected.

[0006] Prior art literature

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2007-82374 Summary of the Invention

[0009] One aspect of the power supply control device disclosed herein controls the supply of power from a DC power source detachably connected between a first terminal and a second terminal to a load. The power supply control device includes: an N-channel first FET, the drain of which is disposed downstream of the source of the first FET in a current path flowing from the first terminal to the second terminal; an N-channel second FET, the drain of which is disposed upstream of the source of the second FET in the current path; a diode, the cathode of which is connected to the second terminal; and a switching circuit that switches the first FET and the second FET to on or off by adjusting the gate voltages of the first FET and the second FET, wherein the reference potential of the gate voltages of the first FET and the second FET is the potential of the anode of the diode, and parasitic diodes are formed for the first FET and the second FET, with the cathode and anode respectively connected to the drain and source of the first FET and the second FET. Attached Figure Description

[0010] Figure 1 This is a block diagram showing the main structural components of the power supply system in Implementation 1.

[0011] Figure 2 This is a timing diagram used to illustrate the operation of the first FET.

[0012] Figure 3 This is a timeline used to illustrate the switching time of the first FET and the second FET.

[0013] Figure 4 This is a circuit diagram of the first driving circuit and the second driving circuit.

[0014] Figure 5 This is an explanatory diagram of the effect of the first diode.

[0015] Figure 6 This is a block diagram showing the main structural components of the power supply system in Embodiment 2.

[0016] Figure 7 This is a block diagram showing the main structural components of the power supply system in Embodiment 3.

[0017] Figure 8 This is a block diagram showing the main structural components of the power supply system in Embodiment 4.

[0018] Figure 9 This is a circuit diagram of the first driving circuit and the second driving circuit.

[0019] Figure 10 This is a block diagram showing the main structural components of the power supply system in Implementation 5. Detailed Implementation

[0020] [The problem this disclosure aims to solve]

[0021] In the power supply control device described in Patent Document 1, when the DC power supply is connected in reverse, no power is supplied to the switching circuit that switches the two FETs to be on or off, and the switching circuit does not operate. However, the switching circuit adjusts the voltage of the two gates, which is based on the potential of the second terminal. Therefore, the switching circuit is connected to the second terminal. When the DC power supply is connected in reverse, the voltage of the DC power supply may be applied to the gates of the two FETs via the switching circuit.

[0022] When a DC voltage is applied to the gates of both FETs, current may flow from the second terminal to the first terminal via the load due to the decrease in resistance between the drain and source of the two FETs. In this case, the load may malfunction.

[0023] Therefore, the objective is to provide a power supply control device in which the voltage of the DC power supply is not applied to the gates of the two FETs via a switching circuit when the positive and negative terminals of the DC power supply are connected to the second and first terminals.

[0024] [The Effects of This Disclosure]

[0025] According to this disclosure, when the positive and negative terminals of the DC power supply are connected to the second terminal and the first terminal, the voltage of the DC power supply will not be applied to the gates of the first EFT and the second FET via the switching circuit.

[0026] [Description of embodiments of this disclosure]

[0027] First, embodiments of this disclosure will be described. At least some of the embodiments described below may be combined arbitrarily.

[0028] (1) One aspect of the power supply control device disclosed herein controls the supply of power from a DC power source detachably connected between a first terminal and a second terminal to a load, wherein the power supply control device comprises: an N-channel type first FET, wherein the drain of the first FET is disposed downstream of the source of the first FET in a current path of current flowing from the first terminal to the second terminal; an N-channel type second FET, wherein the drain of the second FET is disposed upstream of the source of the second FET in the current path; a diode, wherein the cathode of the diode is connected to the second terminal; and a switching circuit that switches the first FET and the second FET to be on or off by adjusting the voltage of the gates of the first FET and the second FET, wherein the reference potential of the gate voltage of the first FET and the second FET is the potential of the anode of the diode, and parasitic diodes are formed for the first FET and the second FET, wherein the cathode and the anode are respectively connected to the drain and the source of the first FET and the second FET.

[0029] In the above configuration, the cathode of the diode is connected to the second terminal. The switching circuit adjusts the reference potential to the voltage of the diode's anode, and therefore the switching circuit is connected to the diode's anode. Thus, when the positive and negative terminals of the DC power supply are connected to the second and first terminals respectively, the voltage of the DC power supply is not applied to the gates of the first and second FETs via the switching circuit.

[0030] (2) One aspect of the power supply control device disclosed herein includes a second diode, the cathode and anode of which are respectively connected to the first terminal and the anode of the diode.

[0031] In the above configuration, the cathode and anode of the second diode are respectively connected to the first terminal and the anode of the diode. Therefore, even when the positive and negative terminals of the DC power supply are connected to the first terminal and the second terminal respectively, the voltage between the negative terminal of the DC power supply and the anode of the diode remains stable.

[0032] (3) One aspect of the power supply control device disclosed herein includes a switch connected between the first terminal and the anode of the diode. The switch is disconnected when the positive and negative terminals of the DC power supply are respectively connected to the first terminal and the second terminal, and is connected when the negative and positive terminals of the DC power supply are respectively connected to the first terminal and the second terminal.

[0033] In the above configuration, the switch is turned on when the positive and negative terminals of the DC power supply are connected to the first and second terminals, respectively. Therefore, even when the positive and negative terminals of the DC power supply are connected to the first and second terminals, the voltage at the anode of the diode, whose reference potential is the potential of the negative terminal of the DC power supply, remains stable.

[0034] (4) In one embodiment of the power supply control device disclosed herein, the switch is a semiconductor switch that is turned on when the voltage at the control terminal is above a predetermined voltage, the reference potential of the voltage at the control terminal is the potential of the anode of the diode, and the control terminal of the switch is connected to the second terminal.

[0035] In the above configuration, when the voltage of the DC power supply is higher than the specified voltage, and the positive and negative terminals of the DC power supply are connected to the second terminal and the first terminal respectively, the voltage at the control terminal of the switch becomes a voltage higher than the specified voltage, and the switch is switched to ON.

[0036] (5) One aspect of the power supply control device disclosed herein includes: a boost circuit for boosting the voltage of the first terminal; and a resistor connected between the drain and source of the first FET, wherein in the current path, the first FET is disposed upstream of the second FET and the second FET is disposed upstream of the load, and the switching circuit, when instructed to switch the first FET and the second FET to be turned on, applies the voltage boosted by the boost circuit to the gates of the first FET and the second FET when the voltage at the connection node between the first FET and the second FET is above a second predetermined voltage.

[0037] In the above configuration, a resistor is connected between the drain and source of the FET on the first terminal side of the first FET and the second FET. When the first FET and the second FET are off, current does not flow through them. Therefore, when the first FET and the second FET are off, the voltage at the connection node is the same as the voltage at the first terminal. When the first FET and the second FET are instructed to switch on, the voltage at the connection node, i.e., the voltage at the first terminal, is assumed to be above a second predetermined voltage. At this time, the switching circuit can switch the first FET and the second FET on by applying the voltage boosted by the boost circuit, and apply the voltage boosted by the boost circuit to the gates of the first FET and the second FET.

[0038] (6) In one embodiment of the power supply control device of the present disclosure, when the switching circuit is instructed to switch the first FET to turn on before the second FET.

[0039] In the configuration described above, the switching circuit switches the first FET to ON before the second FET. Therefore, during the switching process of the first and second FETs to ON, current does not flow through the parasitic diode.

[0040] (7) In one embodiment of the power supply control device of the present disclosure, when the switching circuit is instructed to switch the first FET to off after the second FET, the switching circuit switches the first FET to off after the second FET.

[0041] In the configuration described above, the switching circuit switches the first FET to off after the second FET. Therefore, during the switching process of both the first and second FETs to off, current does not flow through the parasitic diode.

[0042] [Details of the embodiments of this disclosure]

[0043] Hereinafter, specific examples of power supply systems according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present invention is not limited to these examples, but is disclosed in the claims and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0044] (Implementation Method 1)

[0045] <Structure of Power Supply System>

[0046] Figure 1 This is a block diagram showing the main structure of the power system 1 in Embodiment 1. The power system 1 is preferably mounted in a vehicle and includes a power supply control device 10, a load 11, and a DC power supply 12. The power supply control device 10 has an N-channel first FET 20a and an N-channel second FET 20b. The first FET 20a and the second FET 20b are, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Regarding the first FET 20a, a first parasitic diode Da is formed, with the drain and source terminals connected to the cathode and anode, respectively. Similarly, regarding the second FET 20b, a second parasitic diode Db is formed, with the drain and source terminals connected to the cathode and anode, respectively. The DC power supply 12 is, for example, a battery.

[0047] The source of the first FET 20a is connected to the positive terminal Tp. The drain of the first FET 20a is connected to the drain of the second FET 20b. The source of the second FET 20b is connected to one end of the load 11. The other end of the load 11 is connected to the negative terminal Tn.

[0048] A DC power supply 12, such as a battery, can be detachably connected between the positive terminal Tp and the negative terminal Tn. The positive terminal Tp and the negative terminal Tn function as the first and second terminals, respectively. When the positive and negative terminals of the DC power supply 12 are connected to the positive terminal Tp and the negative terminal Tn, respectively, the DC power supply 12 is connected correctly. When the positive and negative terminals of the DC power supply 12 are connected to the negative terminal Tn and the positive terminal Tp, respectively, the DC power supply 12 is connected in reverse. The user of the power supply control device 10 may incorrectly connect the DC power supply 12, i.e., connect it in reverse.

[0049] Load 11 is an electrical device mounted on the vehicle. The first FET 20a and the second FET 20b function as switches. Regarding the first FET 20a and the second FET 20b respectively, when they are in the ON state, the resistance between the drain and source is sufficiently small, and current may flow through the drain and source. Regarding the first FET 20a and the second FET 20b respectively, when they are in the OFF state, the resistance between the drain and source is sufficiently large, and current will not flow through the drain and source.

[0050] When the DC power supply 12 is normally connected, and the first FET 20a and the second FET 20b are turned on, current flows from the positive terminal Tp in the order of the first FET 20a, the second FET 20b, and the load 11. Thus, power is supplied from the DC power supply 12 to the load 11, and the load 11 operates. Similarly, when the first FET 20a and the second FET 20b are turned off, current does not flow through the first FET 20a and the second FET 20b, and power supply from the DC power supply 12 to the load 11 stops. At this time, the load 11 does not operate.

[0051] In the current path from the positive terminal Tp through the first FET 20a and the second FET 20b to the negative terminal Tn, the drain of the first FET 20a is positioned downstream of the source. In the same current path, the drain of the second FET 20b is positioned upstream of the source. In the aforementioned current path, the first FET 20a is positioned upstream of the second FET 20b, and the second FET 20b is positioned upstream of the load 11.

[0052] When the DC power supply 12 is connected normally, the power supply control device 10 controls the power supply from the DC power supply 12 to the load 11 by switching the first FET 20a and the second FET 20b on or off. When the DC power supply 12 is connected in reverse, the power supply control device 10 keeps the first FET 20a and the second FET 20b off. Therefore, when the DC power supply 12 is connected in reverse, the load 11 does not operate.

[0053] <Structure of Power Supply Control Device 10>

[0054] In addition to the first FET 20a and the second FET 20b, the power supply control device 10 also includes a first drive circuit 21a, a second drive circuit 21b, a first filter circuit 22a, a second filter circuit 22b, a microcomputer (hereinafter referred to as a microcomputer) 23, a device resistor 24, a boost circuit 25, a first diode 26, and a second diode 27. The first filter circuit 22a includes a first resistor 30 and a first capacitor 31. The second filter circuit 22b includes a second resistor 40, a second capacitor 41, and a circuit diode 42. The boost circuit 25 has an input terminal for the input voltage, an output terminal for the output voltage, and a ground terminal.

[0055] The gate of the first FET 20a is connected to the first driving circuit 21a. In the first filter circuit 22a, one end of the first resistor 30 is connected to one end of the first capacitor 31. The first driving circuit 21a is also connected to the connection node between the first resistor 30 and the first capacitor 31. The other end of the first capacitor 31 is connected to the anode of the first diode 26 and the second diode 27. The gate of the second FET 20b is connected to the second driving circuit 21b. In the second filter circuit 22b, one end of the second resistor 40 is connected to one end of the second capacitor 41 and the anode of the circuit diode 42. The second driving circuit 21b is also connected to the connection node between the second resistor 40 and the second capacitor 41. The other end of the second capacitor 41 is connected to the anode of the first diode 26 and the second diode 27.

[0056] The other end of the second resistor 40 is connected to the other end of the first resistor 30 and the cathode of the circuit diode 42. The connection node between the first resistor 30 and the second resistor 40 is connected to the microcomputer 23. The microcomputer 23 is also connected to the anode of the first diode 26 and the second diode. A device resistor 24 is connected between the drain and source of the first FET 20a. The positive terminal Tp is connected to the input terminal of the boost circuit 25. The output terminal of the boost circuit 25 is connected to the first drive circuit 21a and the second drive circuit 21b. The ground terminal of the boost circuit 25 is connected to the anode of the first diode 26 and the second diode 27.

[0057] The connection node between the first FET 20a and the second FET 20b is connected to the first driving circuit 21a and the second driving circuit 21b. The first driving circuit 21a and the second driving circuit 21b are also connected to the anodes of the first diode 26 and the second diode 27, respectively. The cathodes of the first diode 26 and the second diode 27 are connected to the negative terminal Tn and the positive terminal Tp, respectively.

[0058] For both the first FET 20a and the second FET 20b, the resistance between the drain and source varies depending on the gate voltage, which is the source potential relative to the reference potential. For both the first FET 20a and the second FET 20b, the state is "on" when the gate voltage, which is the source potential relative to the reference potential, is above a certain turn-on voltage. For both the first FET 20a and the second FET 20b, the state is "off" when the gate voltage, which is the source potential relative to the reference potential, is below a certain turn-off voltage. The turn-on voltage exceeds the turn-off voltage. The turn-off voltage is a positive voltage.

[0059] With the DC power supply 12 connected normally, the boost circuit 25 boosts the voltage at the positive terminal Tp, which is referenced to the potential of the cathode of the first diode 26, and outputs the boosted voltage to the first drive circuit 21a and the second drive circuit 21b. Hereinafter, the potential of the cathode of the first diode 26 will be referred to as the diode potential. The voltage boosted by the boost circuit 25 will be referred to as the boost voltage. The reference potential of the boost voltage is the diode potential.

[0060] The first driving circuit 21a applies a boost voltage to the gate of the first FET 20a. As a result, in the first FET 20a, the gate voltage, where the reference potential is the source potential, becomes a voltage above the turn-on voltage, and the first FET 20a switches to turn-on. The second driving circuit 21b also applies a boost voltage to the gate of the second FET 20b. As a result, in the second FET 20b, the gate voltage, where the reference potential is the source potential, becomes a voltage above the turn-on voltage, and the second FET 20b switches to turn-on.

[0061] The first driving circuit 21a stops applying the boost voltage and adjusts the gate potential of the first FET 20a to a diode potential. Therefore, in the first FET 20a, the gate voltage, where the reference potential is the source potential, is less than the turn-off voltage, and the first FET 20a switches off. The second driving circuit 21b also stops applying the boost voltage to the second FET 20b and adjusts the gate potential of the second FET 20b to a diode potential. Therefore, in the second FET 20b, the gate voltage, where the reference potential is the source potential, is less than the turn-off voltage, and the second FET 20b switches off. The first driving circuit 21a and the second driving circuit 21b together function as a switching circuit.

[0062] The microprocessor 23 outputs voltage to the first filter circuit 22a and the second filter circuit 22b. The reference potential for the output voltage from the microprocessor 23 to the first filter circuit 22a and the second filter circuit 22b is the diode potential. The microprocessor 23 indicates the switching of the first FET 20a and the second FET 20b to turn on by switching the output voltage from a low level to a high level. The microprocessor 23 indicates the switching of the first FET 20a and the second FET 20b to turn off by switching the output voltage from a high level to a low level. The high level voltage is, for example, 5V. The low level voltage is lower than the high level voltage, for example, 0V.

[0063] Hereinafter, the switching indications of the first FET 20a and the second FET 20b to be turned on will be described as turn-on indications. The switching indications of the first FET 20a and the second FET 20b to be turned off will be described as turn-off indications.

[0064] The first filter circuit 22a and the second filter circuit 22b output voltages to the first drive circuit 21a and the second drive circuit 21b, respectively. The reference potential of the output voltages of the first filter circuit 22a and the second filter circuit 22b is the diode potential. The output voltage of the first filter circuit 22a is the voltage across the first capacitor 31. The output voltage of the second filter circuit 22b is the voltage across the second capacitor 41.

[0065] When the microcomputer 23 switches the output voltage from a low level to a high level, the output voltages of the first filter circuit 22a and the second filter circuit 22b rise. When the output voltage of the first filter circuit 22a reaches a voltage above a certain threshold voltage, the first drive circuit 21a receives an on / off indication. The reference potential for the threshold voltage is the diode potential. The threshold voltage exceeds the low level voltage but is less than the high level voltage. When the output voltage of the second filter circuit 22b reaches a voltage above a certain threshold voltage, the second drive circuit 21b receives an on / off indication.

[0066] When the microcomputer 23 switches the output voltage from a high level to a low level, the output voltages of the first filter circuit 22a and the second filter circuit 22b decrease. When the output voltage of the first filter circuit 22a becomes lower than a certain threshold voltage, the first drive circuit 21a receives a disconnection instruction. When the output voltage of the second filter circuit 22b becomes lower than a certain threshold voltage, the second drive circuit 21b receives a disconnection instruction.

[0067] When the first drive circuit 21a receives an on instruction, it switches the first FET 20a to on when the voltage at the connection node between the first FET 20a and the second FET 20b is above a certain reference voltage. Hereinafter, the voltage at the connection node between the first FET 20a and the second FET 20b will be described as an intermediate voltage. The reference potential of the intermediate voltage is the diode potential. A positive reference voltage corresponds to a second predetermined voltage. When the first drive circuit 21a receives an off instruction or when the intermediate voltage becomes lower than the reference voltage, it switches the first FET 20a to off.

[0068] When the second drive circuit 21b receives an on instruction and the intermediate voltage is above the reference voltage, it switches the second FET 20b to on. When the second drive circuit 21b receives an off instruction or the intermediate voltage becomes less than the reference voltage, it switches the second FET 20b to off.

[0069] When the voltage at the positive terminal Tp of the diode (which is the reference potential) is above the reference voltage, the boost voltage of the boost circuit 25 is sufficient to switch the first FET 20a and the second FET 20b on. When the voltage at the positive terminal Tp of the diode (which is the reference potential) is below the reference voltage, there is a possibility that the boost voltage is lower than the voltage required to switch the first FET 20a and the second FET 20b on due to insufficient boosting by the boost circuit 25. In this case, due to the applied boost voltage of the boost circuit 25, there is a possibility that the resistance between the drain and source of the first FET 20a and the second FET 20b may not decrease to a sufficiently small value.

[0070] <Operation of the first FET20a>

[0071] Figure 2 This is a timing diagram used to illustrate the operation of the first FET20a. Figure 2 The diagram shows the transitions in the output voltage and intermediate voltage of the microprocessor 23, the output voltage of the first filter circuit 22a, and the state of the first FET 20a. The horizontal axis represents time in relation to these transitions. Figure 2 In this context, the high-level voltage, low-level voltage, reference voltage, and threshold voltage are represented by H, L, Vr, and Vth, respectively. Figure 2 The reference potential of the output voltage of the first filter circuit 22a shown is the diode potential. Figure 2 The displacements shown are those when DC power supply 12 is connected normally. Figure 2 The example shown is a low-level voltage of 0V.

[0072] With the first FET 20a and the second FET 20b off, current does not flow through the first FET 20a and the second FET 20b, nor does it flow through the device resistor 24. Therefore, the intermediate voltage is the same as the voltage at the positive terminal Tp of the diode, which is the reference potential. The magnitude of the voltage drop that occurs when current flows in the order of the anode and cathode of the first diode 26 is recorded as the forward voltage. The intermediate voltage is substantially the same as the voltage obtained by subtracting the forward voltage of the first diode 26 from the voltage of the DC power supply 12.

[0073] As described above, the device resistor 24 is connected between the drain and source of the first FET 20a. Therefore, even if the first FET 20a and the second FET 20b are disconnected, the intermediate voltage is consistent with the voltage of the positive terminal Tp of the diode, which is the reference potential.

[0074] When the DC power supply 12 is reverse-connected, and the first FET 20a and the second FET 20b are disconnected, the current flows in the order of load 11, second parasitic diode Db, and device resistor 24. If current continues to flow through the second parasitic diode Db, the temperature of the second FET 20b may rise to an abnormal temperature. If the temperature of the second FET 20b rises to an abnormal temperature, the second FET 20b may malfunction. Therefore, a resistor with a very large resistance value is used as the device resistor 24. In this case, even assuming the DC power supply 12 is reverse-connected, the current flowing through the second parasitic diode Db is essentially 0A, and the temperature of the second FET 20b will not rise to an abnormal temperature.

[0075] When the first FET 20a is turned on, the intermediate voltage is also consistent with the voltage at the positive terminal Tp of the diode, which is the reference potential. Here, the voltage drop generated by the first FET 20a is ignored. Therefore, the intermediate voltage is always substantially consistent with the voltage obtained by subtracting the forward voltage of the first diode 26 from the voltage of the DC power supply 12. Since the forward voltage of the first diode 26 is substantially constant, the intermediate voltage shifts in the same manner as the voltage of the DC power supply 12. Figure 2 In the example, the intermediate voltage is initially maintained at a voltage higher than the reference voltage Vr. Then, for example, as the output voltage of DC power supply 12 decreases, the intermediate voltage decreases and is maintained at a voltage lower than the reference voltage Vr.

[0076] When the output voltage of the microcomputer 23 is a low-level voltage, and the first capacitor 31 has not accumulated power, the output voltage of the first filter circuit 22a is 0V, which is less than the threshold voltage Vth. When the output voltage of the first filter circuit 22a is less than the threshold voltage Vth, the first drive circuit 21a keeps the first FET 20a off. As mentioned above, the threshold voltage Vth exceeds the low-level voltage but is less than the high-level voltage.

[0077] When the microcomputer 23 switches the output voltage from a low level to a high level, current flows from the microcomputer 23 in the order of the first resistor 30 and the first capacitor 31, charging the first capacitor 31. As a result, the output voltage of the first filter circuit 22a increases over time. If the resistance value of the first resistor 30 and the capacitance of the first capacitor 31 are denoted as R1 and C1 respectively, the smaller the first time constant represented by R1·C1, the faster the output voltage of the first filter circuit 22a rises. "·" indicates a product.

[0078] As previously stated, when the output voltage of the first filter circuit 22a becomes a voltage above the threshold voltage Vth, the first drive circuit 21a receives an on-state instruction. Upon receiving the on-state instruction, when the intermediate voltage is above the reference voltage Vr, the first drive circuit 21a switches the first FET 20a on by applying the boost voltage from the boost circuit 25, thus applying the boost voltage to the gate of the first FET 20a. Therefore, the first FET 20a is switched on. When the output voltage of the first filter circuit 22a becomes a high-level voltage, the charging of the first capacitor 31 ends. After charging ends, while the output voltage of the microcomputer 23 is at a high-level voltage, the output voltage of the first filter circuit 22a remains at a high-level voltage.

[0079] When the microprocessor 23 switches the output voltage from a high level to a low level, current flows from the first capacitor 31 in the order of the first resistor 30 and the microprocessor 23, causing the first capacitor 31 to discharge. As a result, the output voltage of the first filter circuit 22a decreases over time. The smaller the first time constant, the faster the output voltage of the first filter circuit 22a decreases. When the output voltage of the first filter circuit 22a is less than the threshold voltage Vth, the first drive circuit 21a receives a disconnection instruction and switches the first FET 20a to disconnect.

[0080] As previously stated, the first driving circuit 21a switches the first FET 20a to disconnect when it receives a disconnection instruction or when the intermediate voltage becomes less than the reference voltage Vr. Therefore, when the intermediate voltage becomes less than the reference voltage Vr while the output voltage of the first filter circuit 22a is above the threshold voltage Vth, the first driving circuit 21a also switches the first FET 20a to disconnect.

[0081] The discharge of the first capacitor 31 ends when the output voltage of the first filter circuit 22a becomes 0V (low level voltage). After the discharge ends, the output voltage of the first filter circuit 22a remains at 0V while the output voltage of the microcomputer 23 is at a low level voltage.

[0082] <The Action of the Second FET20b>

[0083] The output voltage of the second filter circuit 22b shifts in the same manner as the output voltage of the first filter circuit 22a. When the microcomputer 23 switches the output voltage from a low level to a high level, current flows from the microcomputer 23 in the order of the second resistor 40 and the second capacitor 41, charging the second capacitor 41. Therefore, the output voltage of the second filter circuit 22b increases over time.

[0084] With the resistance value of the second resistor 40 and the capacitance of the second capacitor 41 denoted as R2 and C2 respectively, the smaller the second time constant represented by R2·C2, the faster the output voltage of the second filter circuit 22b rises. When the output voltage of the second filter circuit 22b reaches a high level, the charging of the second capacitor 41 ends. The first time constant is smaller than the second time constant. Therefore, the rise rate of the output voltage of the second filter circuit 22b is slower than the rise rate of the output voltage of the first filter circuit 22a.

[0085] When the microprocessor 23 switches the output voltage from a high level to a low level, current flows from the second capacitor 41 in sequence through the circuit diode 42 and the microprocessor 23, causing the second capacitor 41 to discharge. As a result, the output voltage of the second filter circuit 22b decreases over time. With the second capacitor 41 discharging, current flows through the circuit diode 42, therefore the output voltage of the second filter circuit 22b decreases faster than the output voltage of the first filter circuit 22a. The discharge of the second capacitor 41 ends when the output voltage of the second filter circuit 22b reaches 0V (low level voltage).

[0086] As previously stated, when the output voltage of the second filter circuit 22b becomes less than the threshold voltage Vth, the second drive circuit 21b receives a disconnect instruction. The second drive circuit 21b functions similarly to the first drive circuit 21a. Therefore, when the second drive circuit 21b receives a disconnect instruction, if the intermediate voltage is above the reference voltage Vr, the application of the boost voltage from the boost circuit 25 can switch the second FET 20b to the on, applying the boost voltage to the gate of the second FET 20b. Thus, the second FET 20b is switched on. The second drive circuit 21b switches the second FET 20b to the off when the output voltage of the second filter circuit 22b becomes less than the threshold voltage Vth or when the intermediate voltage becomes less than the reference voltage Vr.

[0087] <Switching time between the first FET20a and the second FET20b>

[0088] Figure 3 This is a timing diagram used to illustrate the switching time of the first FET20a and the second FET20b. Figure 3 The diagram shows the output voltage of the microcomputer 23, the output voltage of the first filter circuit 22a, the output voltage of the second filter circuit 22b, the state of the first FET 20a, and the state of the second FET 20b. The horizontal axis represents time. Figure 3 In, with Figure 2 Similarly, the high-level voltage, low-level voltage, and threshold voltage are represented by H, L, and Vth, respectively. The following describes the switching time of the first FET 20a and the second FET 20b when the DC power supply 12 is normally connected and the intermediate voltage is above the reference voltage.

[0089] When the microcomputer 23 instructs the switching of the first FET 20a and the second FET 20b to be turned on, that is, when the microcomputer 23 switches the output voltage from a low level voltage to a high level voltage, the output voltages of the first filter circuit 22a and the second filter circuit 22b rise as described above. Since the first time constant is smaller than the second time constant, the rise rate of the output voltage of the first filter circuit 22a is faster than the rise rate of the output voltage of the second filter circuit 22b. Therefore, the output voltage of the first filter circuit 22a reaches a voltage above the threshold voltage Vth before the output voltage of the second filter circuit 22b. Therefore, when the microcomputer 23 instructs the switching of the first FET 20a and the second FET 20b to be turned on, the first FET 20a is switched on before the second FET 20b by the first drive circuit 21a. After the first FET 20a is switched on, the second drive circuit 21b switches the second FET 20b on.

[0090] With the DC power supply 12 properly connected, when the first FET 20a and the second FET 20b are off and on respectively, the current flows in the order of the first parasitic diode Da, the second FET 20b, and the load 11. If current continues to flow through the first parasitic diode Da, the temperature of the first FET 20a may rise to an abnormal level. In this case, a malfunction may occur in the first FET 20a. However, since the first FET 20a switches on before the second FET 20b, current does not flow through the first parasitic diode Da during the switching process from the first FET 20a to the second FET 20b.

[0091] When the microcomputer 23 instructs the switching of the first FET 20a and the second FET 20b to be off, that is, when the microcomputer 23 switches the output voltage from a high level voltage to a low level voltage, the output voltages of the first filter circuit 22a and the second filter circuit 22b decrease as described above. In the second filter circuit 22b, the second capacitor 41 discharges through the circuit diode 42, so the output voltage of the first filter circuit 22a decreases more slowly than the output voltage of the second filter circuit 22b. Therefore, the output voltage of the first filter circuit 22a becomes a voltage lower than the threshold voltage Vth after the output voltage of the second filter circuit 22b. Therefore, when the microcomputer 23 instructs the switching of the first FET 20a and the second FET 20b to be off, the second FET 20b is first switched off by the second drive circuit 21b. After the second FET 20b is switched off, the first FET 20a is switched off by the first drive circuit 21a.

[0092] As mentioned earlier, when the DC power supply 12 is normally connected, current flows through the first parasitic diode Da when the first FET 20a and the second FET 20b are off and on, respectively. However, since the first FET 20a switches off after the second FET 20b, current does not flow through the first parasitic diode Da during the switching process from the first FET 20a to the second FET 20b.

[0093] <Structure of the first driving circuit 21a>

[0094] Figure 4This is a circuit diagram of the first driving circuit 21a and the second driving circuit 21b. The first driving circuit 21a has an upper FET 50u, a lower FET 50d, and a first driving section 51. The upper FET 50u is a P-channel MOSFET. The lower FET 50d is an N-channel MOSFET. An upper parasitic diode 5u is formed on the upper FET 50u, with its source and drain connected to the cathode and anode, respectively. A lower parasitic diode 5d is formed on the lower FET 50d, with its drain and source connected to the cathode and anode, respectively.

[0095] The source of the upper FET 50u is connected to the output of the boost circuit 25. Therefore, the voltage at the source of the upper FET 50u, whose reference potential is the diode potential, is the boost voltage. The drain of the upper FET 50u is connected to the drain of the lower FET 50d. The source of the lower FET 50d is connected to the anode of the first diode 26. The connection node between the drains of the upper FET 50u and the lower FET 50d is connected to the gate of the first FET 20a. The gate of the upper FET 50u is connected to the gate of the lower FET 50d. The connection node between the gates of the upper FET 50u and the lower FET 50d is connected to the first driving unit 51. The first driving unit 51 is also connected to the connection node between the first resistor 30 and the first capacitor 31 in the first filter circuit 22a, the source of the lower FET 50d, and the connection node between the first FET 20a and the second FET 20b.

[0096] The upper FET 50u and the lower FET 50d function as switches. When the upper FET 50u and lower FET 50d are in the ON state, the resistance between the drain and source is sufficiently small, allowing current to flow through both the drain and source. When the upper FET 50u and lower FET 50d are in the OFF state, the resistance between the drain and source is sufficiently large, preventing current flow. The resistance between the drain and source changes according to the gate voltage, which is the reference potential of the source.

[0097] Regarding the upper FET 50u, when the gate voltage at the source potential (reference potential) is less than a certain second turn-on voltage, the state is on. Regarding the upper FET 50u, when the gate voltage at the source potential (reference potential) is greater than or equal to a certain second turn-off voltage, the state is off. The second turn-on voltage is less than the second turn-off voltage. The second turn-off voltage is a negative voltage.

[0098] Regarding the lower FET 50d, it is in the ON state when the gate voltage at the source potential (reference potential) is above a certain third turn-on voltage. Regarding the lower FET 50d, it is in the OFF state when the gate voltage at the source potential (reference potential) is below a certain third turn-off voltage. The third turn-on voltage exceeds the third turn-off voltage. The third turn-off voltage is a positive voltage.

[0099] This describes the operation of the first drive unit 51 when the DC power supply 12 is normally connected. When the output voltage of the first filter circuit 22a is above the threshold voltage, and the intermediate voltage is above the reference voltage, the first drive unit 51 causes the gate voltages of the upper FET 50u and the lower FET 50d to decrease. Here, the reference potential of the gate voltage is the diode potential. When the gate voltages of the upper FET 50u and the lower FET 50d decrease, in the upper FET 50u, the gate voltage, where the reference potential is the source potential, decreases to a voltage lower than the second turn-on voltage; in the lower FET 50d, the gate voltage, where the reference potential is the source potential, decreases to a voltage lower than the third turn-off voltage. As a result, the upper FET 50u and the lower FET 50d switch to turn on and off, respectively. Consequently, the boost voltage of the boost circuit 25 is applied to the gate of the first FET 20a via the upper FET 50u, and the first FET 20a switches to turn on.

[0100] When the output voltage of the first filter circuit 22a becomes less than a threshold voltage or the intermediate voltage becomes less than a reference voltage, the first driving unit 51 raises the gate voltages of the upper FET 50u and the lower FET 50d. Here, the reference potential of the gate voltage is a diode potential. When the gate voltages of the upper FET 50u and the lower FET 50d rise, in the upper FET 50u, the gate voltage, whose reference potential is the source potential, rises to a voltage greater than or equal to a second off voltage, and in the lower FET 50d, the gate voltage, whose reference potential is the source potential, rises to a voltage greater than or equal to a third on voltage. As a result, the upper FET 50u and the lower FET 50d switch to off and on, respectively. As a result, the application of the boost voltage stops, and the gate potential of the first FET 20a is adjusted to a diode potential. As a result, the first FET 20a switches to off.

[0101] As described above, when the DC power supply 12 is connected normally, the first drive unit 51 switches the first FET 20a to the on state by switching the upper FET 50u and the lower FET 50d to the on state and the off state, respectively. Furthermore, the first drive unit 51 switches the first FET 20a to the off state by switching the upper FET 50u and the lower FET 50d to the on state and the off state, respectively. When the DC power supply 12 is connected in reverse, the first drive unit 51 keeps the upper FET 50u and the lower FET 50d off. For example, regarding the upper FET 50u and the lower FET 50d, the upper FET 50u and the lower FET 50d are disconnected by adjusting the voltage between the gate and source to 0V, respectively.

[0102] <Structure of the second driving circuit 21b>

[0103] The first driving circuit 21a includes an upper FET 60u, a lower FET 60d, and a second driving section 61. The upper FET 60u is a P-channel MOSFET. The lower FET 60d is an N-channel MOSFET. An upper parasitic diode 6u is formed on the upper FET 60u, with its source and drain terminals connected to the cathode and anode, respectively. A lower parasitic diode 6d is formed on the lower FET 60d, with its drain and source terminals connected to the cathode and anode, respectively.

[0104] The source of the upper FET 60u is connected to the output of the boost circuit 25. Therefore, the voltage at the source of the upper FET 60u, whose reference potential is the diode potential, is the boost voltage. The drain of the upper FET 60u is connected to the drain of the lower FET 60d. The source of the lower FET 60d is connected to the anode of the first diode 26. The connection node between the gates of the upper FET 60u and the lower FET 60d is connected to the gate of the second FET 20b. The gate of the upper FET 60u is connected to the gate of the lower FET 60d. The connection node between the gates of the upper FET 60u and the lower FET 60d is connected to the second driving unit 61. The second driving unit 61 is also connected to the connection node between the second resistor 40 and the second capacitor 41 in the second filter circuit 22b, the source of the lower FET 60d, and the connection node between the first FET 20a and the second FET 20b.

[0105] The upper FET 60u and lower FET 60d are configured in the same way as the upper FET 50u and lower FET 50d. When the DC power supply 12 is connected normally, the second drive unit 61, like the first drive unit 51, switches the upper FET 60u and lower FET 60d to be on or off respectively.

[0106] Therefore, when the output voltage of the second filter circuit 22b is above the threshold voltage, and the intermediate voltage is above the reference voltage, the second drive unit 61 switches the upper FET 60u and the lower FET 60d to be on and off, respectively. As a result, a boost voltage is applied to the gate of the second FET 20b, and the first FET 20a is switched on. The second FET 20b is switched on. When the output voltage of the second filter circuit 22b is below the threshold voltage or the intermediate voltage is below the reference voltage, the second drive unit 61 switches the upper FET 60u and the lower FET 60d to be off and on, respectively. As a result, the application of the boost voltage stops, and the potential of the gate of the second FET 20b is adjusted to a diode potential. Consequently, the second FET 20b is switched off. When the DC power supply 12 is connected in reverse, the second drive unit 61 keeps the upper FET 60u and the lower FET 60d off.

[0107] <Effect of Diode 26>

[0108] Figure 5 This is an explanatory diagram of the effect of the first diode 26. Figure 5 The diagram shows a structure in which the first diode 26 is removed from the power supply control device 10. Specifically, this structure is one in which the two ends of the first diode 26 in the power supply control device 10 are short-circuited. In this structure, as... Figure 5 As shown, when the DC power supply 12 is connected in reverse, the voltage of the DC power supply 12 is applied to the gate of the first FET 20a via the lower parasitic diode 5d, and to the gate of the second FET 20b via the lower parasitic diode 6d. Consequently, the gate voltages of the first FET 20a and the second FET 20b, where the reference potential is the source potential, rise, and the resistance between the drain and source decreases with respect to both the first FET 20a and the second FET 20b. Therefore, current may flow through the first FET 20a and the second FET 20b.

[0109] When the DC power supply 12 is connected in reverse, as current flows through the first FET 20a and the second FET 20b, the current flows from the negative terminal Tn in the order of load 11, second FET 20b, first FET 20a, and positive terminal Tp. As a result, the load 11 may operate inappropriately. For example, if the load 11 is a motor, the motor may rotate in a direction different from its normal direction.

[0110] However, due to Figure 1The power supply control device 10 shown has a first diode 26. Therefore, when the DC power supply 12 is connected in reverse, the voltage of the DC power supply 12 is not applied to the gates of the first FET 20a and the second FET 20b via the first drive circuit 21a and the second drive circuit 21b, respectively. As mentioned above, when the DC power supply 12 is connected in reverse, the upper FETs 50u and 60u and the lower FETs 50d and 60d are disconnected. The gates of the first FET 20a and the second FET 20b are connected to the cathode of the first diode 26, for example, via two resistors (not shown). Therefore, when the voltage of the DC power supply 12 is not applied to the gates of the first FET 20a and the second FET 20b, the voltage of the gate, which is the reference potential of the diode, is low for the first FET 20a and the second FET 20b, and the first FET 20a and the second FET 20b remain disconnected.

[0111] In addition, such as Figure 1 As shown, the cathode and anode of the second diode 27 are connected to the positive terminal Tp and the anode of the first diode 26, respectively. Therefore, even when the DC power supply 12 is connected in reverse, the voltage between the negative terminal of the DC power supply 12 and the anode of the first diode 26 remains stable.

[0112] <Postscript>

[0113] The threshold voltage of the output voltage of the first filter circuit 22a can also be different from the threshold voltage of the output voltage of the second filter circuit 22b. The first time constant can also be a value greater than or equal to the second time constant. As long as the first FET 20a switches on before the second FET 20b and switches off after the second FET 20b, the threshold voltage, the first time constant, and the second time constant can be set to arbitrary values. For example, if the first time constant and the second time constant are the same, the threshold voltage of the output voltage of the first filter circuit 22a can be set to a value lower than the threshold voltage of the output voltage of the second filter circuit 22b. Thus, the aforementioned structure can be achieved.

[0114] (Implementation Method 2)

[0115] In Embodiment 1, a second diode 27 is used to stabilize the voltage between the negative terminal of the DC power supply 12 and the cathode of the first diode 26 even when the DC power supply 12 is connected in reverse. However, the component used to stabilize the voltage between the negative terminal of the DC power supply 12 and the cathode of the first diode 26 even when the DC power supply 12 is connected in reverse is not limited to the second diode 27.

[0116] Hereinafter, regarding Embodiment 2, the differences from Embodiment 1 will be explained. Except for the structure described later, the other structures are the same as in Embodiment 1. Therefore, for structural parts common to Embodiment 1, the same reference numerals as in Embodiment 1 will be used, and their descriptions will be omitted.

[0117] <Structure of Power Supply Control Device 10>

[0118] Figure 6 This is a block diagram showing the main structure of the power supply system 1 in Embodiment 2. When comparing the power supply system 1 in Embodiment 2 with the power supply system 1 in Embodiment 1, the structure of the power supply control device 10 differs. The power supply control device 10 in Embodiment 2 has all the structural components of the power supply control device 10 in Embodiment 1 except for the second diode 27. The power supply control device 10 in Embodiment 2 replaces the second diode 27 with a switch 70.

[0119] Switch 70 is an N-channel MOSFET. A MOSFET is a type of semiconductor switch. A parasitic diode 71 is formed in switch 70, with its drain and source connected to the cathode and anode, respectively. The drain, source, and gate of switch 70 are connected to the positive terminal Tp, the anode of the first diode 26, and the negative terminal Tn, respectively.

[0120] Regarding switch 70, when it is in the ON state, the resistance between the drain and source is sufficiently small, and current may flow through both the drain and source. Regarding switch 70, when it is in the OFF state, the resistance between the drain and source is sufficiently large, and current will not flow through both the drain and source. Regarding switch 70, it is in the ON state when the gate voltage at the source potential (reference potential) is a certain fourth ON voltage or higher. Regarding switch 70, it is in the ON state when the gate voltage at the source potential (reference potential) is a certain fourth OFF voltage or higher. The fourth ON voltage exceeds the fourth OFF voltage. The fourth OFF voltage is a positive voltage. The source potential of switch 70 is the potential of the anode of the first diode 26. The gate of switch 70 functions as a control terminal. The fourth ON voltage is equivalent to the specified voltage.

[0121] With the DC power supply 12 properly connected, current flows through the first diode 26 in the order of anode and cathode. Therefore, in switch 70, the voltage across the gate, which is at the source potential, is negative and less than the fourth disconnect voltage. Thus, with the DC power supply 12 properly connected, switch 70 is open.

[0122] When the DC power supply 12 is connected in reverse, the reference potential is the source voltage at the drain, which is the voltage of the DC power supply 12. At this time, in switch 70, the gate voltage at the source, which is the reference potential, is above the fourth turn-on voltage, and switch 70 is turned on. Therefore, the cathode of the first diode 26 is connected to the positive terminal Tp, which is the negative terminal of the DC power supply 12. Thus, even when the DC power supply 12 is connected in reverse, the voltage at the anode of the first diode 26, which is the negative terminal of the DC power supply 12, is fixed and stable at 0V.

[0123] <Power supply control device 10>

[0124] The power supply control device 10 in Embodiment 2 also performs the same effects as the power supply control device 10 in Embodiment 1, except for the effects obtained by using the second diode 27.

[0125] <Postscript>

[0126] In embodiment 2, switch 70 is not limited to an N-channel MOSFET; for example, it could also be an IGBT (Insulated Gate Bipolar Transistor). In this case, the collector, emitter, and gate of switch 70 are connected, for example, to the anode, positive terminal Tp, and negative terminal Tn of the first diode 26. Furthermore, switch 70 is not limited to a semiconductor switch; for example, it could also be a relay contact.

[0127] (Implementation Method 3)

[0128] In Embodiment 1, in the current path of the current flowing from the positive terminal Tp to the negative terminal Tn, the first FET 20a is disposed upstream of the second FET 20b. However, the location where the first FET 20a is disposed is not limited to the upstream side of the second FET 20b.

[0129] Hereinafter, regarding Embodiment 3, the differences from Embodiment 1 will be explained. Except for the structure described later, the other structures are the same as in Embodiment 1. Therefore, for structural parts common to Embodiment 1, the same reference numerals as in Embodiment 1 will be used, and their descriptions will be omitted.

[0130] <Structure of Power Supply Control Device 10>

[0131] Figure 7This is a block diagram showing the main structural components of the power supply system 1 in Embodiment 3. When comparing the power supply system 1 in Embodiment 3 with the power supply system 1 in Embodiment 1, the structure of the power supply control device 10 differs. The power supply control device 10 in Embodiment 3 has all the structural components of the power supply control device 10 in Embodiment 1 except for the device resistor 24.

[0132] In Embodiment 3, the drain and source of the first FET 20a are connected to the positive terminal Tp and the source of the second FET 20b, respectively. The drain of the second FET 20b is connected to one end of the load 11. When the DC power supply 12 is normally connected, and the first FET 20a and the second FET 20b are turned on, current flows from the positive terminal Tp in the order of the second FET 20b, the first FET 20a, the load 11, and the negative terminal Tn. Therefore, in the current path from the positive terminal Tp to the negative terminal Tn, the first FET 20a is positioned downstream of the second FET 20b. Furthermore, in Embodiment 3, the first driving section 51 of the first driving circuit 21a and the second driving section 61 of the second driving circuit 21b are connected to the positive terminal Tp, replacing the connection node between the first FET 20a and the second FET 20b.

[0133] In Embodiment 1, the intermediate voltage is the same as the voltage of the positive terminal Tp, which is the reference potential of the diode. In Embodiment 4, the first driving unit 51 and the second driving unit 61 respectively replace the intermediate voltage and directly monitor the voltage of the positive terminal Tp, which is the reference potential of the diode. Similar to Embodiment 1, the first FET 20a and the second FET 20b are switched on or off.

[0134] Therefore, the operation of the first drive unit 51 when the DC power supply 12 is connected normally is as follows. When the output voltage of the first filter circuit 22a becomes a voltage above the threshold voltage, and the voltage at the positive terminal Tp (which is the diode potential) is above the reference voltage, the first drive unit 51 switches the upper FET 50u and lower FET 50d to on and off, respectively. As a result, a boost voltage is applied to the gate of the first FET 20a, and the first FET 20a is switched on. When the output voltage of the first filter circuit 22a becomes a voltage below the threshold voltage or the voltage at the positive terminal Tp (which is the diode potential) becomes a voltage below the reference voltage, the first drive unit 51 switches the upper FET 50u and lower FET 50d to off and on, respectively. As a result, the application of the boost voltage stops, and the potential of the gate of the first FET 20a is adjusted to the diode potential. Consequently, the first FET 20a is switched off. When the DC power supply 12 is connected in reverse, the first drive unit 51 keeps the upper FET 50u and the lower FET 50d disconnected, similar to Embodiment 1.

[0135] When the DC power supply 12 is normally connected, the operation of the second drive unit 61 is the same as that of the first drive unit 51 when the DC power supply 12 is normally connected. Here, the second FET 20b, the upper FET 60u, and the lower FET 60d correspond to the first FET 20a, the upper FET 50u, and the lower FET 50d, respectively. When the DC power supply 12 is reverse connected, similar to Embodiment 1, the second drive unit 61 keeps the upper FET 60u and the lower FET 60d disconnected.

[0136] <Effect of Diode 26>

[0137] Without the first diode 26, i.e., when the two ends of the first diode 26 in the power supply control device 10 of Embodiment 3 are short-circuited, the DC power supply 12 is assumed to be connected in reverse. In this case, as described in Embodiment 1, when the voltage of the DC power supply 12 is applied to the gates of the first FET 20a and the second FET 20b, the resistance between the drain and source decreases with respect to the first FET 20a and the second FET 20b, respectively, and current may flow through the first FET 20a and the second FET 20b. As a result, the load 11 may operate inappropriately. However, since the power supply control device 10 in Embodiment 3 has the first diode 26, when the DC power supply 12 is connected in reverse, the voltage of the DC power supply 12 will not be applied to the gates of the first FET 20a and the second FET 20b through the first drive circuit 21a and the second drive circuit 21b, respectively.

[0138] As previously described, when the DC power supply 12 is connected in reverse, the upper FETs 50u and 60u and the lower FETs 50d and 60d are disconnected. The gates of the first FET 20a and the second FET 20b are connected to the cathode of the first diode 26, for example, via two resistors (not shown). Therefore, when the voltage of the DC power supply 12 is not applied to the gates of the first FET 20a and the second FET 20b, the voltage at the gate of the diode (within the reference potential) is low, and the first FET 20a and the second FET 20b remain disconnected.

[0139] <Effects and Postscript of Power Supply Control Device 10>

[0140] The power supply control device 10 in Embodiment 3 also performs the same function as the power supply control device 10 in Embodiment 1.

[0141] In Embodiment 3, similarly to Embodiment 2, the switch 70 can be used instead of the second diode 27. In this case, the power supply control device 10 in Embodiment 3 also performs the same function as the power supply control device 10 in Embodiment 2.

[0142] (Implementation Method 4)

[0143] In Embodiment 1, the first FET 20a and the second FET 20b are disposed upstream of the load 11 in the current path of the current flowing from the positive terminal Tp to the negative terminal Tn. However, the first FET 20a and the second FET 20b may also be disposed downstream of the load 11. Hereinafter, regarding Embodiment 4, the differences from Embodiment 1 will be explained. The structure other than that described later is common to Embodiment 1. Therefore, the structural parts common to Embodiment 1 are marked with the same reference numerals as in Embodiment 1, and their descriptions are omitted.

[0144] <Structure of Power System 1>

[0145] Figure 8 This is a block diagram showing the main structure of the power system 1 in Embodiment 4. When comparing the power system 1 in Embodiment 4 with the power system 1 in Embodiment 1, the configuration of the load 11 differs. The positive terminal Tp is connected to one end of the load 11. The other end of the load 11 is connected to the source of the first FET 20a. The source of the second FET 20b is connected to the negative terminal Tn.

[0146] With the DC power supply 12 properly connected, when the first FET 20a and the second FET 20b are turned on, current flows from the positive terminal Tp in the order of load 11, first FET 20a, and second FET 20b. Thus, power is supplied from the DC power supply 12 to the load 11, and the load 11 operates. Similarly, when the first FET 20a and the second FET 20b are turned off, current does not flow through them, and power supply from the DC power supply 12 to the load 11 stops. At this time, the load 11 does not operate.

[0147] <Structure of Power Supply Control Device 10>

[0148] The power supply control device 10 of Embodiment 4 has the same structure as the power supply control device 10 of Embodiment 1, except for the device resistor 24 and the boost circuit 25. The first drive circuit 21a and the second drive circuit 21b are connected to the positive terminal Tp instead of the output terminal of the boost circuit 25. The first drive circuit 21a and the second drive circuit 21b are not connected to the connection node between the first FET 20a and the second FET 20b. Similar to Embodiment 3, instead of an intermediate voltage, the voltage of the positive terminal Tp, whose reference potential is the diode potential, is monitored.

[0149] When the DC power supply 12 is connected normally, the first drive circuit 21a switches the first FET 20a to the on by applying the voltage of the DC power supply 12 to the first FET 20a. When the first drive circuit 21a stops applying the voltage of the DC power supply 12, it switches the first FET 20a to the off by adjusting the potential of the gate of the first FET 20a to the diode potential.

[0150] Similarly, when the DC power supply 12 is connected normally, the second drive circuit 21b switches the second FET 20b to the on by applying the voltage of the DC power supply 12 to the second FET 20b. When the second drive circuit 21b stops applying the voltage of the DC power supply 12, it switches the second FET 20b to the off by adjusting the potential of the gate of the second FET 20b to the diode potential.

[0151] <Structure of the first driving circuit 21a and the second driving circuit 21b>

[0152] Figure 9 This is a circuit diagram of the first driving circuit 21a and the second driving circuit 21b. (See diagram for example.) Figure 9 As shown, the first driving unit 51 and the second driving unit 61 respectively replace the connection node between the first FET 20a and the second FET 20b and are connected to the positive terminal Tp.

[0153] When the DC power supply 12 is connected normally, similarly to Embodiment 3, the first driving unit 51 of the first driving circuit 21a switches the upper FET 50u and the lower FET 50d to on or off, respectively, based on the voltage of the positive terminal Tp (which is the reference potential of the diode) and the output voltage of the first filter circuit 22a. When the upper FET 50u and the lower FET 50d are on and off, respectively, the voltage of the DC power supply 12 is applied to the gate of the first FET 20a, and the first FET 20a is switched on. When the upper FET 50u and the lower FET 50d are off and on, respectively, the application of the boost voltage stops, and the potential of the gate of the first FET 20a is adjusted to the diode potential. As a result, the first FET 20a is switched off. When the DC power supply 12 is connected in reverse, similarly to Embodiment 3, the first driving unit 51 keeps the upper FET 50u and the lower FET 50d off.

[0154] Similarly, when the DC power supply 12 is connected normally, as in Embodiment 3, the second drive unit 61 of the second drive circuit 21b switches the upper FET 60u and the lower FET 60d to on or off, respectively, based on the voltage of the positive terminal Tp (which is the reference potential of the diode) and the output voltage of the second filter circuit 22b. When the upper FET 60u and the lower FET 60d are on and off, respectively, the voltage of the DC power supply 12 is applied to the gate of the second FET 20b, and the second FET 20b is switched on. When the upper FET 60u and the lower FET 60d are off and on, respectively, the application of the boost voltage stops, and the potential of the gate of the second FET 20b is adjusted to the diode potential. As a result, the second FET 20b is switched off. When the DC power supply 12 is connected in reverse, as in Embodiment 3, the second drive unit 61 keeps the upper FET 60u and the lower FET 60d off.

[0155] <Effect of Diode 26>

[0156] Without the first diode 26, i.e., when the first diode 26 in the power supply control device 10 of Embodiment 4 is short-circuited, the DC power supply 12 is assumed to be connected in reverse. In this case, as described in Embodiment 1, when the voltage of the DC power supply 12 is applied to the gates of the first FET 20a and the second FET 20b, the resistance between the drain and source decreases with respect to the first FET 20a and the second FET 20b, respectively, and current may flow through the first FET 20a and the second FET 20b. As a result, the load 11 may operate inappropriately. However, since the power supply control device 10 in Embodiment 4 has the first diode 26, the voltage of the DC power supply 12 will not be applied to the gates of the first FET 20a and the second FET 20b via the first drive circuit 21a and the second drive circuit 21b, respectively, when the DC power supply 12 is connected in reverse.

[0157] As previously described, when the DC power supply 12 is connected in reverse, the upper FETs 50u and 60u and the lower FETs 50d and 60d are disconnected. The gates of the first FET 20a and the second FET 20b are connected to the cathode of the first diode 26, for example, via two resistors (not shown). Therefore, when the voltage of the DC power supply 12 is not applied to the gates of the first FET 20a and the second FET 20b, the voltage at the gate of the diode (within the reference potential) is low, and the first FET 20a and the second FET 20b remain disconnected.

[0158] <Effects and Postscript of Power Supply Control Device 10>

[0159] The power supply control device 10 in Embodiment 4 also performs the same function as the power supply control device 10 in Embodiment 1.

[0160] In Embodiment 4, similarly to Embodiment 2, a switch 70 may be used instead of the second diode 27. In this case, the power supply control device 10 in Embodiment 4 also performs the same function as the power supply control device 10 in Embodiment 2.

[0161] (Implementation Method 5)

[0162] In embodiment 4, in the current path of the current flowing from the positive terminal Tp to the negative terminal Tn, the first FET 20a is disposed upstream of the second FET 20b. However, the location where the first FET 20a is disposed is not limited to the upstream side of the second FET 20b.

[0163] Hereinafter, regarding Embodiment 5, the differences from Embodiment 4 will be explained. Except for the structure described later, the other structures are the same as in Embodiment 4. Therefore, for structural parts common to Embodiment 4, the same reference numerals as in Embodiment 4 will be used, and their descriptions will be omitted.

[0164] <Structure of Power Supply Control Device 10>

[0165] Figure 10 This is a block diagram showing the main structure of the power system 1 in Embodiment 5. When comparing the power system 1 in Embodiment 5 with the power system 1 in Embodiment 1, the structure of the power supply control device 10 differs. When comparing the power supply control device 10 in Embodiment 5 with the power supply control device 10 in Embodiment 4, the placement of the first FET 20a and the second FET 20b differs.

[0166] The drain and source of the first FET 20a are connected to the other end of the load 11 and the source of the second FET 20b, respectively. The drain of the second FET 20b is connected to the negative terminal Tn.

[0167] <Effect of Diode 26>

[0168] Similar to Embodiment 4, the first drive circuit 21a switches the first FET 20a to on or off. Similarly, similarly to Embodiment 4, the second drive circuit 21b also switches the second FET 20b to on or off. When the DC power supply 12 is normally connected, and both the first FET 20a and the second FET 20b are on, current flows from the positive terminal Tp in the order of load 11, second FET 20b, first FET 20a, and negative terminal Tn. Therefore, in the current path from the positive terminal Tp to the negative terminal Tn, the first FET 20a is positioned downstream of the second FET 20b.

[0169] Without the first diode 26, i.e., when the first diode 26 in the power supply control device 10 of Embodiment 5 is short-circuited, the DC power supply 12 is assumed to be connected in reverse. In this case, as described in Embodiment 4, when the voltage of the DC power supply 12 is applied to the gates of the first FET 20a and the second FET 20b, the resistance between the drain and source decreases with respect to the first FET 20a and the second FET 20b, respectively, and current may flow through the first FET 20a and the second FET 20b. As a result, the load 11 may operate inappropriately. However, since the power supply control device 10 in Embodiment 5 has the first diode 26, when the DC power supply 12 is connected in reverse, the voltage of the DC power supply 12 will not be applied to the gates of the first FET 20a and the second FET 20b via the first drive circuit 21a and the second drive circuit 21b, respectively.

[0170] Similar to Embodiment 4, when the DC power supply 12 is connected in reverse, the upper FETs 50u and 60u and the lower FETs 50d and 60d are disconnected. The gates of the first FET 20a and the second FET 20b are connected to the cathode of the first diode 26, for example, via two resistors (not shown). Therefore, when the voltage of the DC power supply 12 is not applied to the gates of the first FET 20a and the second FET 20b, the voltage at the gate of the first FET 20a and the second FET 20b, which has a reference potential equal to the diode potential, is low, and the first FET 20a and the second FET 20b remain disconnected.

[0171] <Effects and Postscript of Power Supply Control Device 10>

[0172] The power supply control device 10 of embodiment 5 also performs the same effect as the power supply control device 10 of embodiment 4.

[0173] In Embodiment 5, similarly to Embodiment 2, a switch 70 may be used instead of the second diode 27. In this case, the power supply control device 10 of Embodiment 5 also performs the same function as the power supply control device 10 of Embodiment 2.

[0174] <Variation Example>

[0175] In embodiments 1 to 5, the first driving circuit 21a is any circuit that can apply a voltage to the gate of the first FET 20a via a ground terminal when the DC power supply 12 is connected in reverse. Therefore, the structure of the first driving circuit 21a is not limited to using an upper FET 50u and a lower FET 50d. Similarly, the second driving circuit 21b is any circuit that can apply a voltage to the gate of the second FET 20b via a ground terminal when the DC power supply 12 is connected in reverse. Therefore, the structure of the second driving circuit 21b is not limited to using an upper FET 60u and a lower FET 60d.

[0176] It should be considered that the disclosed embodiments 1 to 5 are illustrative in all respects and not restrictive. The scope of the invention is defined not by the foregoing but by the claims and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0177] Label Explanation

[0178] 1 Power System

[0179] 5d lower-side parasitic diode

[0180] 5u upper parasitic diode

[0181] 6d lower parasitic diode

[0182] 6u upper parasitic diode

[0183] 10 Power supply control device

[0184] 11 Load

[0185] 12 DC power supply

[0186] 20a First FET

[0187] 20b Second FET

[0188] 21a First drive circuit (part of the switching circuit)

[0189] 21b Second drive circuit (part of the switching circuit)

[0190] 22a First Filter Circuit

[0191] 22b Second Filter Circuit

[0192] 23 Microcomputer

[0193] 24. Device resistance

[0194] 25. Boost circuit

[0195] 26 First Diode

[0196] 27 Second Diode

[0197] 30 First resistor

[0198] 31 First Capacitor

[0199] 40 Second resistor

[0200] 41 Second capacitor

[0201] 42 Circuit Diode

[0202] 50d, 60d lower-side FET

[0203] 50u, 60u upper FET

[0204] 51 First Drive Unit

[0205] 61 Second Drive Unit

[0206] 70 Switch

[0207] 71 Parasitic Diode

[0208] Da First Parasitic Diode

[0209] Db Second Parasitic Diode

[0210] Tn negative terminal (second terminal)

[0211] Tp positive terminal (first terminal).

Claims

1. A power supply control device for controlling the supply of power from a DC power source detachably connected between a first terminal and a second terminal to a load, wherein, The power supply control device includes: In the N-channel type first FET, in the current path of the current flowing from the first terminal to the second terminal, the drain of the first FET is configured downstream of the source of the first FET. In the current path, the drain of the second FET is configured upstream of the source of the second FET; A diode, the cathode of which is connected to the second terminal; and The switching circuit switches the first and second FETs to on or off by adjusting the gate voltages of the first and second FETs. The reference potential of the gate voltages of the first and second FETs is the potential of the anode of the diode. Parasitic diodes are formed in both the first and second FETs, with the cathode and anode of the parasitic diodes connected to the drain and source, respectively. The power supply control device includes a switch connected between the first terminal and the anode of the diode. The switch is open when the positive and negative terminals of the DC power supply are connected to the first and second terminals respectively, and is closed when the negative and positive terminals of the DC power supply are connected to the first and second terminals respectively.

2. The power supply control device according to claim 1, wherein, The power supply control device includes a second diode, the cathode and anode of which are respectively connected to the first terminal and the anode of the diode.

3. The power supply control device according to claim 1, wherein, The switch is a semiconductor switch that is turned on when the voltage at the control terminal of the switch is above a specified voltage, and the reference potential of the voltage at the control terminal of the switch is the potential of the anode of the diode. The control terminal of the switch is connected to the second terminal.

4. The power supply control device according to any one of claims 1 to 3, wherein, The power supply control device includes: A boost circuit boosts the voltage at the first terminal; and A resistor is connected between the drain and source of the first FET. In the current path, the first FET is configured upstream of the second FET, and the second FET is configured upstream of the load. When the switching circuit is instructed to switch the first FET and the second FET to turn on, and the voltage at the connection node between the first FET and the second FET is above a second predetermined voltage, the voltage boosted by the boost circuit is applied to the gates of the first FET and the second FET.

5. The power supply control device according to any one of claims 1 to 3, wherein, When the switching circuit is instructed to switch the first FET and the second FET to turn on, the first FET will be switched on before the second FET.

6. The power supply control device according to any one of claims 1 to 3, wherein, When the switching circuit is instructed to switch the first FET and the second FET to off, it switches the first FET to off after the second FET.

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