Power on system, power on method, readable storage medium and electronic device

Abstract

The present disclosure relates to a power-on system, a power-on method, a readable storage medium, and an electronic device, so as to reduce the power consumption of the device when it is in sleep mode and improve the battery life of the device. The power-on system includes: an IO interface, a wake-up detection device, and a power supply of a high-voltage power domain, wherein the wake-up detection device is connected to the IO interface, and the IO interface and the wake-up detection device are both arranged in the high-voltage power domain, so that the power supply of the high-voltage power domain supplies power to the IO interface and the wake-up detection device; the IO interface is used to control the level change of the IO interface according to preset IO configuration information when receiving a target event; the wake-up detection device is used to be connected to the power supply of the low-voltage power domain, detect the level change of the IO interface, and when the level change meets the preset wake-up condition, send a start instruction to the power supply of the low-voltage power domain to energize the low-voltage power domain and thus wake up the system chip.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technology, and in particular, to a power-on system, a power-on method, a readable storage medium, and an electronic device. Background Art

[0002] IoT (Internet of Things) devices are small in size and have smaller batteries. To extend battery life and enhance the user experience, a sleep mode is often designed into these devices. This mode places the system on chip (SOC) in the IoT device into sleep mode when it's not operating. When an external event triggers a request, the SOC is awakened and resumes operation.

[0003] For example, in a remote control device, to minimize standby power consumption, the system-on-chip (SOC) of the remote control device enters a low-power sleep mode when idle. When a wake-up event (e.g., a key press, a serial interface transmission signal, an IO flip, etc.) is detected, the system-on-chip (SOC) exits the low-power sleep mode and enters the working mode to complete the event processing.

[0004] However, in the related art, when the system chip (SOC) of the IoT device enters a low-power sleep mode, it is necessary to detect whether a wake-up event occurs. Therefore, the relevant detection circuit needs to work normally, that is, the internal power supply of the IoT product needs to work normally to power the relevant detection circuit. As a result, the IoT device consumes too much power when in standby or sleep mode, and the battery life is poor. Summary of the Invention

[0005] The purpose of the present disclosure is to provide a power-on system, a power-on method, a readable storage medium, and an electronic device, so as to effectively reduce the power consumption of the device when it is in sleep mode and improve the battery life of the device.

[0006] To achieve the above objectives, the present disclosure provides, in a first aspect, a power-on system, comprising: an I / O interface, a wake-up detection device, and a power supply of a high-voltage power domain, wherein the wake-up detection device is connected to the I / O interface, and the power supply of the high-voltage power domain supplies power to the I / O interface and the wake-up detection device;

[0007] The IO interface is used to control the level change of the IO interface according to preset IO configuration information when receiving a target event;

[0008] The wake-up detection device is used to be connected to the power supply of the low-voltage power domain, detect the level change of the IO interface, and when the level change meets the preset wake-up condition, send a start instruction to the power supply of the low-voltage power domain to power on the low-voltage power domain and thus wake up the system chip, wherein the power supply of the low-voltage power domain is disconnected when the system chip enters the sleep state.

[0009] Optionally, the target event includes a key being pressed; the IO configuration information includes a type identifier, a resistance identifier, and an output level of each IO interface, wherein the type identifier includes an input interface identifier and an output interface identifier, and the resistance identifier includes a pull-up resistor identifier and a pull-down resistor identifier;

[0010] When a key is pressed, the level of the input interface corresponding to the key changes to be consistent with the output level of the output interface.

[0011] Optionally, the wake-up condition includes a level of the input interface changing from a first level to a second level, and / or changing from a second level to a first level, wherein the first level is different from the second level.

[0012] Optionally, the wake-up detection device includes an IO interface level detection module, a wake-up judgment module and a state conversion module connected in sequence;

[0013] The IO interface level detection module is connected to the IO interface and is used to detect the level change of the IO interface;

[0014] The wake-up judgment module is used to obtain the wake-up condition, judge whether the level change meets the wake-up condition, and send the judgment result to the state conversion module;

[0015] The state conversion module is configured to generate a power-on instruction for instructing the low-voltage power domain to turn on the power supply when the judgment result indicates that the level change satisfies the preset wake-up condition, and send the power-on instruction to the power supply of the low-voltage power domain.

[0016] Optionally, the system further includes: a latch, the latch being used to store the IO configuration information and the wake-up condition;

[0017] The IO interface is connected to the latch and is used to obtain the IO configuration information from the latch;

[0018] The wake-up judgment module is connected to the latch and is used to obtain the wake-up condition from the latch.

[0019] Optionally, the IO configuration information and the wake-up condition are both set by the system chip before entering the sleep state.

[0020] Optionally, the target event includes a transmission signal of a serial interface, the IO configuration information includes a type identifier indicating that the IO interface is an input interface and an initial level of the IO interface; the wake-up condition includes the IO interface changing from the initial level to a level opposite to the initial level;

[0021] When the IO interface detects an event in which the serial interface transmits a signal, the IO interface changes the level of the IO interface from the initial level to a level opposite to the initial level.

[0022] A second aspect of the present disclosure provides a power-on method, which is applied to the power-on system provided in the first aspect of the present disclosure. The method includes:

[0023] In response to the received target event, control the level change of the IO interface according to the preset IO configuration information;

[0024] Determining whether the level change meets a preset wake-up condition;

[0025] When the wake-up condition is met, a start instruction is sent to the power supply of the low-voltage power domain, so as to power on the low-voltage power domain and thus wake up the system chip.

[0026] A third aspect of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method provided in the second aspect of the present disclosure.

[0027] A fourth aspect of the present disclosure provides an electronic device, comprising: a system chip, a power supply of a low-voltage power domain, and the power-on system provided by the first aspect of the present disclosure, wherein the power-on system is connected to the power supply of the low-voltage power domain, and the power supply of the low-voltage power domain is connected to the system chip;

[0028] The power on system is used to turn on the power of the low voltage power domain when the system chip switches from a sleep state to a working state, so as to power on the low voltage power domain and wake up the system chip.

[0029] Through the above technical solution, the IO interface and the wake-up detection device are both arranged in the high-voltage power domain, so that the power supply of the high-voltage power domain can be used to power the IO interface and the wake-up detection device. In this way, when the system chip SOC is in a dormant state, the power supply of the low-voltage power domain can be in a power-off state, avoiding the power consumption of the low-voltage power supply when the system chip is in a dormant state, reducing the dormant power consumption of the electronic device, and thus improving the battery life of the electronic device. In addition, when the system chip SOC is in a dormant state, the IO interface and the wake-up detection device can operate normally to detect whether an event to wake up the system chip SOC occurs, and when an event to wake up the system chip SOC is detected, the low-voltage power domain is powered on, thereby waking up the system chip SOC. In this way, while effectively reducing the dormant power consumption of the electronic device, it can ensure that the system chip is awakened normally so that the electronic device can operate normally.

[0030] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0032] Figure 1 is a block diagram of a power-on system according to an exemplary embodiment.

[0033] Figure 2 is a block diagram showing another power-on system according to an exemplary embodiment.

[0034] Figure 3 The flowchart of a system chip entering a sleep state is shown according to an exemplary embodiment.

[0035] Figure 4 The figure is a flowchart showing a method of waking up a system chip according to an exemplary embodiment.

[0036] Figure 5 The figure is a schematic diagram showing a key scan matrix according to an exemplary embodiment.

[0037] Figure 6 The figure is a flowchart showing a method for starting a power supply according to an exemplary embodiment.

[0038] Figure 7 It is a block diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0039] Typically, whether clock gate technology or power gate technology is used to reduce the power consumption of IoT devices, at least high-voltage and low-voltage power supplies are required, and the system-on-chip (SOC) is divided into a wake-up source identification circuit and other circuits. In sleep mode, the wake-up source identification circuit operates normally, while other circuits do not.

[0040] Because the wake-up source identification circuit requires the IoT device's low-voltage power supply, the low-voltage power supply must function properly during sleep mode. When the low-voltage power supply is functioning properly, the IoT device's power consumption includes: the low-frequency clock, key scanning circuit power, GPIO detection power, serial port wake-up detection circuit power, power consumption of the control circuit maintaining the power gate, power consumption of the power gate cell itself, and power consumption of the low-voltage power supply itself. This results in increased power consumption in standby or sleep mode, failing to effectively reduce the IoT device's power consumption during sleep, resulting in poor battery life.

[0041] In view of this, the present disclosure provides a power-on system, a power-on method, a readable storage medium, and an electronic device to effectively reduce the power consumption of the device when it is in sleep mode and improve the battery life of the device.

[0042] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0043] Figure 1 The present invention is a block diagram of a power-on system according to an exemplary embodiment. The power-on system is used to turn on the power of a low-voltage power domain, where the power of the low-voltage power domain is the internal power supply of an electronic device (e.g., an IoT device, a remote control, etc.), that is, the power supply that powers the electronic device's system-on-chip (SOC).

[0044] like Figure 1 As shown, the power-on system 100 may include an IO interface 101, a wake-up detection device 102, and a power supply 103 in a high-voltage power domain. The wake-up detection device 102 is connected to the IO interface 101, and both the IO interface 101 and the wake-up detection device 102 are disposed in the high-voltage power domain, so that the power supply 103 in the high-voltage power domain supplies power to the IO interface 101 and the wake-up detection device 102. Furthermore, the power supply 103 in the high-voltage power domain refers to an external power source for the electronic device.

[0045] The system chip of an electronic device can be awakened by a keystroke, a serial interface, a GPIO (General-purpose input / output), and so on. These awakening methods are collectively referred to as IO wakeup. Therefore, in this disclosure, the IO interface 101 can be used as a keystroke interface, a serial interface, a GPIO interface, and so on.

[0046] In the present disclosure, the IO interface 101 is configured to control the voltage level of the IO interface 101 according to preset IO configuration information upon receiving a target event. The target event may be an event for waking up the system-on-chip (SOC), such as a button being pressed, a serial interface signal being transmitted, or the like. In other words, when an event occurs that wakes up the system-on-chip (SOC), the IO interface 101 may control the voltage level of the IO interface 101 according to the preset IO configuration information. For example, the voltage level may be changed from a low level to a high level, or vice versa.

[0047] In addition, the wake-up detection device 102 is connected to the power supply 200 of the low-voltage power domain, detects the level change of the IO interface 101, and when the level change meets the preset wake-up condition, sends a start instruction to the power supply 200 of the low-voltage power domain to power on the low-voltage power domain and thus wake up the system chip.

[0048] It's worth noting that because the wake-up detection device is deployed in the high-voltage power domain and uses the power supply in that domain, when the system-on-chip (SOC) enters a sleep state, the power supply 200 in the low-voltage power domain can be directly shut down. That is, the low-voltage power domain can be completely powered off when the system-on-chip (SOC) is in a sleep state. For example, the circuit generating the low-voltage VDD can be controlled to be in a disconnected state, thereby keeping the power supply in the low-voltage power domain in a powered-off state. This effectively reduces the power consumption of the low-voltage power supply when the system-on-chip (SOC) is in a sleep state.

[0049] By adopting the above technical solution, the IO interface and the wake-up detection device are both arranged in the high-voltage power domain, so that the power supply of the high-voltage power domain can be used to power the IO interface and the wake-up detection device. In this way, when the system chip SOC is in a dormant state, the power supply of the low-voltage power domain can be in a power-off state, avoiding the low-voltage power domain from generating power consumption, reducing the dormant power consumption of the electronic device, and thus improving the battery life of the electronic device. Moreover, when the system chip SOC is in a dormant state, the IO interface and the wake-up detection device can operate normally to detect whether an event to wake up the system chip SOC occurs, and when an event to wake up the system chip SOC is detected, the low-voltage power domain is controlled to be powered on, thereby waking up the system chip SOC. In this way, while effectively reducing the dormant power consumption of the electronic device, it can ensure that the system chip is awakened normally so that the electronic device can operate normally.

[0050] Figure 2 FIG. 1 is a block diagram of another power-on system according to an exemplary embodiment. Figure 2 As shown, the wake-up detection device 102 may include an IO interface level detection module 1021 , a wake-up judgment module 1022 and a state conversion module 1023 which are connected in sequence.

[0051] The IO interface level detection module 1021 is connected to the IO interface 101 and is used to detect level changes in the IO interface 101. The wake-up judgment module 1022 is used to obtain a wake-up condition, determine whether the level change meets the wake-up condition, and send the judgment result to the state transition module 1023. The state transition module 1023 is used to generate a power-on instruction for instructing the low-voltage power domain to turn on the power supply, and send the instruction to the power supply 200 of the low-voltage power domain when the judgment result indicates that the level change meets the preset wake-up condition. In addition, the state transition module 1023 can also be used to generate an instruction for instructing the low-voltage power domain to remain in the off state when the judgment result indicates that the level change does not meet the preset wake-up condition, so as to control the power supply 200 of the low-voltage power domain to remain in the off state.

[0052] It's worth noting that, in this disclosure, the IO configuration information and wake-up conditions are set before the system chip enters a sleep state. In other words, the IO configuration information and wake-up conditions are set in the low-voltage power domain. To ensure that the IO interface 101 and wake-up detection device 102 operating in the high-voltage power domain can properly utilize the IO configuration information and wake-up conditions after the power supply 200 in the low-voltage power domain is powered off, the high-voltage power domain must obtain the IO configuration information and wake-up conditions before the power supply 200 in the low-voltage power domain is powered off.

[0053] The power-on system 100 may further include a latch that can temporarily store the IO configuration information and wake-up conditions set by the system chip in normal working mode to maintain a certain state, so that when the system chip is in sleep mode, the power of the low-voltage power domain can be turned on according to the IO configuration information and wake-up conditions to wake up the system chip.

[0054] For example, the latch is connected to the system chip and can obtain IO configuration information and wake-up conditions from the system chip and store the IO configuration information and wake-up conditions. The IO interface is connected to the latch and can obtain IO configuration information from the latch, and the wake-up determination module is connected to the latch and can obtain the wake-up conditions from the latch.

[0055] In the present disclosure, the latches may be one or two groups. When the power-on system 10 includes one group of latches, the IO configuration information and the wake-up condition are stored in the group of latches. When the power-on system 10 includes two groups of latches (hereinafter referred to as the first latch and the second latch), the IO configuration information may be stored in the first latch, and the wake-up condition may be stored in the second latch. Figure 2 As shown, the IO interface 101 is connected to the first latch 104 and can obtain the IO configuration information from the first latch 104. The wake-up judgment module 1022 is connected to the second latch 105 and can obtain the wake-up condition from the second latch 105. It is worth noting that Figure 2 It is not shown that the first latch 104 and the second latch 105 are connected to the system chip.

[0056] Figure 3 FIG. 1 is a flow chart showing a system chip entering a sleep state according to an exemplary embodiment. Figure 3 As shown, the process of the system chip entering the sleep state includes: first, the system chip sets the IO configuration information and wake-up conditions before entering the sleep mode, then the latch in the high-voltage power domain obtains and stores the IO configuration information and wake-up conditions from the system chip, and then the state transition module controls the power supply of the low-voltage power domain to cut off to put the system chip into the sleep state.

[0057] It is worth noting that the IO interface level detection module and the wake-up judgment module may be in a working state all the time, or may enter a working state only after the system chip enters a sleep state, and this disclosure does not make any specific limitation on this.

[0058] Figure 4 FIG. 1 is a flowchart showing a method of waking up a system chip according to an exemplary embodiment. Figure 4 As shown, the process of waking up the system chip includes: first, the IO interface level detection module detects the level change of the IO interface, then the wake-up judgment module judges whether the level change meets the wake-up condition to determine whether the event occurring in the IO interface is a wake-up event, and then, when the judgment result is that the level change meets the wake-up condition, the state conversion module controls the power supply of the low-voltage power domain to turn on and wake up the system chip.

[0059] Thus, according to the above method, while effectively reducing the sleep power consumption of the electronic device, the system chip can be controlled to enter the sleep state, and the system chip can be controlled to be normally awakened to enable the electronic device to operate normally.

[0060] In one embodiment, the electronic device is a key-activated wake-up device, that is, a system chip is activated by a key. Therefore, the target event includes a key being pressed.

[0061] In the related art, when a key is used to wake up a system chip, the output interface will periodically output a low level or a high level according to a certain pattern, the input interface will periodically connect to a pull-up resistor or a pull-down resistor according to a certain pattern, and the level of the input interface will be periodically detected according to a certain pattern. When the level of the input interface is detected to change from a high level to a low level or from a low level to a high level, it is determined that a key has been pressed. It is worth noting that in order for the output interface to periodically output a low level or a high level according to a certain pattern, the input interface to periodically connect to a pull-up resistor or a pull-down resistor according to a certain pattern, and the level of the input interface to be periodically detected according to a certain pattern, a clock is required for control, and the clock also consumes power when it is working.

[0062] To further reduce sleep power consumption, the present disclosure utilizes a simplified key scanning method to detect whether a key is pressed. For example, the periodic output of the output interface can be changed to a fixed output, the periodic connection of the input interface to a pull-up resistor or a pull-down resistor can be changed to a fixed connection to a pull-up resistor or a pull-down resistor, and the periodic detection of the input interface level can be changed to real-time detection. This eliminates the need for clock control, i.e., eliminates the need for clock operation, thus avoiding power consumption during clock operation and further reducing sleep power consumption.

[0063] In this embodiment, the IO configuration information includes the type identification of each IO interface, the resistance identification of the resistor connected to each IO interface, and the output level of the output interface. Among them, the type identification includes the input interface identification and the output interface identification, and the resistance identification includes the pull-up resistor identification and the pull-down resistor identification. It is worth noting that when the IO interface is connected to the pull-up resistor, the level of the IO interface is a high level, and when the IO interface is connected to the pull-down resistor, the level of the IO interface is a low level. The resistor described here can be a resistor (or resistance wire) in the conventional sense or a MOS tube used as a resistor function, and this disclosure does not make specific limitations on this.

[0064] For example, the IO configuration information includes the output enable signal OE, the input enable signal IE, the pull-up enable signal PU, the pull-down enable signal PD, and the output level O of the output interface. If the IO configuration information of a certain IO interface is OE=1, IE=0, PU=0, PD=0, O=0, it indicates that the IO interface is an output interface, and the output level of the output interface is fixed low. If the IO configuration information of a certain interface is OE=0, IE=1, PU=1, PD=0, it indicates that the IO interface is an input interface, and the input interface is connected to a pull-up resistor. In this way, the IO interface can be divided into an input interface and an output interface according to the above IO configuration.

[0065] It is worth noting that the configuration information of the three output interfaces included in the A group IO interface can be the same or different. Similarly, the configuration information of the three input interfaces included in the B group IO interface can be the same or different. This disclosure does not impose any restrictions on this.

[0066] For example, Figure 5 FIG. 1 is a schematic diagram showing a key scan matrix according to an exemplary embodiment. Figure 5 As shown, it is assumed that the IO interfaces of group A (including A1, A2, and A3) are output interfaces, and the IO interfaces of group B (including B1, B2, and B3) are input interfaces. When a key is pressed, the level of the input interface corresponding to the key changes to be consistent with the output level of the output interface. The input interface corresponding to the key mentioned here refers to the input interface where the key is located. Figure 5 In the example, if the key at the intersection of the A1 interface and the B1 interface is pressed, the level of the input interface, that is, the B1 interface, changes to be consistent with the output level of the output interface, that is, consistent with the output level of the A1 interface.

[0067] Accordingly, the above-mentioned wake-up condition may include the level of the input interface changing from a first level to a second level, and / or changing from a second level to a first level, wherein the first level is different from the second level. For example, if the first level is a low level, then the second level is a high level. Assuming that the level of the B1 interface changes from a low level to a high level, and / or the level of the B1 interface changes from a high level to a low level, it is considered that at least one of the three buttons where the B1 interface is located is pressed.

[0068] For example, if the A1 interface is set to output a fixed low level and the B1 interface is connected to a pull-up resistor, when the B1 interface outputs a low level (that is, the level of the B1 interface changes from a high level to a low level), it can be considered that the key is pressed. If the A1 interface is set to output a fixed high level and the B1 interface is connected to a pull-down resistor, when the B1 interface outputs a high level (that is, the level of the B1 interface changes from a low level to a high level), it can be considered that the key is pressed.

[0069] In another embodiment, the electronic device is a device that is awakened by a serial interface transmission signal, that is, the system chip is awakened by a serial interface transmission signal, and therefore, the above-mentioned target event includes a serial interface transmission signal. The IO configuration information may include a type identifier for indicating that the IO interface is an input interface and an initial level of the IO interface. Accordingly, the wake-up condition includes the level of the IO interface changing from the initial level to a level opposite to the initial level. When the IO interface detects an event of a serial interface transmission signal, the IO interface changes the level of the IO interface from the initial level to a level opposite to the initial level. It is worth noting that in this embodiment, the serial interface is the IO interface.

[0070] In this way, when the wake-up detection device detects that the level of the IO interface changes from the initial level to the level opposite to the initial level, it sends a start instruction to the power supply of the low-voltage power domain to power on the low-voltage power domain and thus wake up the system chip, thereby realizing the use of serial interface transmission signals to wake up the system chip.

[0071] In one embodiment, the IO interface is connected to a pull-up resistor, and its initial level is set to a high level. In this case, the level opposite to the initial level is a low level. That is, when the wake-up condition is that the level of the IO interface changes from a high level to a low level, the IO interface correspondingly changes the level of the IO interface from a high level to a low level when detecting an event that the serial interface transmits a signal. In another embodiment, the IO interface is connected to a pull-down resistor, and its initial level is set to a low level. In this case, the level opposite to the initial level is a high level. That is, when the wake-up condition is that the level of the IO interface changes from a low level to a high level, the IO interface correspondingly changes the level of the IO interface from a low level to a high level when detecting an event that the serial interface transmits a signal.

[0072] It is worth noting that in the embodiment where the IO interface is connected to the pull-down resistor, that is, the initial level is a low level, since the Universal Asynchronous Receiver / Transmitter (UART) protocol defaults to a high level for the serial interface when there is no transmission signal, and the level is pulled down to a low level when the signal is transmitted, if the wake-up condition is set so that the level of the IO interface changes from a low level to a high level, the serial interface level needs to be pulled down to a low level first, and then pulled up to a high level, which will result in low detection efficiency.

[0073] Based on the same inventive concept, the present disclosure also provides a power-on method. Figure 6 FIG. 1 is a flow chart showing a power-on method according to an exemplary embodiment, and the power-on method is applied to the power-on system provided by the present disclosure. Figure 6 As shown, the method may include the following steps.

[0074] In step 601, in response to a received target event, the level change of the IO interface is controlled according to preset IO configuration information;

[0075] In step 602, it is determined whether the level change satisfies a preset wake-up condition;

[0076] In step 603, when the wake-up condition is met, a start instruction is sent to the power supply of the low-voltage power domain to power on the low-voltage power domain and thus wake up the system chip.

[0077] Regarding the method in the above embodiment, the specific manner of performing the operation in each step has been described in detail in the embodiment of the system and will not be elaborated here.

[0078] The present disclosure also provides an electronic device, which includes: a system chip, a power supply of a low-voltage power domain, and the power-on system provided by the present disclosure, wherein the power-on system is connected to the power supply of the low-voltage power domain, and the power supply of the low-voltage power domain is connected to the system chip; the power-on system is used to turn on the power supply of the low-voltage power domain when the system chip switches from a sleep state to a working state, so that the low-voltage power domain is powered on and the system chip is woken up.

[0079] The electronic device can be a remote control. To minimize standby power consumption and put the system chip into a low-power sleep mode when idle, the IO interface and wake-up detection device are placed in the high-voltage power domain, powered by the power supply in the high-voltage power domain. This allows the system chip to be powered directly by the power supply in the low-voltage domain when it is in sleep mode. When an event such as a key press, a serial port transmission request, or an IO flip is detected, the power supply in the low-voltage domain is controlled to power on, powering the system chip, waking it up, and entering operating mode to complete event processing.

[0080] For example, Figure 7 FIG. 1 is a block diagram of an electronic device according to an exemplary embodiment. Figure 7 As shown, the electronic device 700 may include: a processor 701 , a memory 702 , and may further include one or more of a multimedia component 703 , an input / output (I / O) interface 704 , and a communication component 705 .

[0081] The processor 701 is used to control the overall operation of the electronic device 700 to complete all or part of the steps in the power-on method described above. The memory 702 is used to store various types of data to support the operation of the electronic device 700. Such data may include, for example, instructions for any application or method operating on the electronic device 700, as well as application-related data, such as contact information, sent and received messages, pictures, audio, video, etc. The memory 702 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The multimedia component 703 may include a screen and an audio component. The screen may be, for example, a touch screen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signal may be further stored in the memory 702 or sent via the communication component 705. The audio component also includes at least one speaker for outputting audio signals. The I / O interface 704 provides an interface between the processor 701 and other interface modules. The above-mentioned other interface modules may be a keyboard, a mouse, buttons, etc. These buttons may be virtual buttons or physical buttons. The communication component 705 is used for wired or wireless communication between the electronic device 700 and other devices. Wireless communication, such as Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, 4G, NB-IOT, eMTC, or other 5G, etc., or a combination of one or more thereof, is not limited here. Therefore, the corresponding communication component 705 may include: a Wi-Fi module, a Bluetooth module, an NFC module, etc.

[0082] In an exemplary embodiment, the electronic device 700 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above-mentioned power-on method.

[0083] In another exemplary embodiment, a computer-readable storage medium including program instructions is further provided. When the program instructions are executed by a processor, the steps of the above-described power-on method are implemented. For example, the computer-readable storage medium may be the aforementioned memory 702 including the program instructions. The program instructions may be executed by the processor 701 of the electronic device 700 to implement the above-described power-on method.

[0084] In another exemplary embodiment, a computer program product is further provided. The computer program product includes a computer program executable by a programmable device, and has a code portion for executing the above power-on method when executed by the programmable device.

[0085] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details of the above embodiments. Within the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the scope of protection of the present disclosure.

[0086] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.

[0087] In addition, the various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.

Claims

1. A power on system, characterized in that: The system includes: an IO interface, a wake-up detection device, and a power supply of a high-voltage power domain, wherein the wake-up detection device is connected to the IO interface, and the power supply of the high-voltage power domain supplies power to the IO interface and the wake-up detection device; The IO interface is used to control the level change of the IO interface according to preset IO configuration information when receiving a target event; The wake-up detection device is used to be connected to the power supply of the low-voltage power domain, detect the level change of the IO interface, and send a start instruction to the power supply of the low-voltage power domain when the level change meets the preset wake-up condition, so as to power on the low-voltage power domain and thus wake up the system chip, wherein the power supply of the low-voltage power domain is disconnected when the system chip enters the sleep state, and before entering the sleep state, the system chip sets and latches the IO configuration information and the wake-up condition; The target event includes a key being pressed; the IO configuration information includes a type identifier, a resistance identifier, and an output level of each IO interface, wherein the type identifier includes an input interface identifier and an output interface identifier, and the resistance identifier includes a pull-up resistor identifier and a pull-down resistor identifier; Among them, when a button is pressed, the level of the input interface corresponding to the button changes to be consistent with the output level of the output interface, so as to change the output of the output interface into a fixed output, change the input interface into a fixed connection with a pull-up resistor or a pull-down resistor, and change the periodic detection of the level of the input interface into real-time detection.

2. The power-on system according to claim 1, wherein: The wake-up condition includes a level of the input interface changing from a first level to a second level, and / or changing from a second level to a first level, wherein the first level is different from the second level.

3. The power-on system according to any one of claims 1 to 2, characterized in that: The wake-up detection device includes an IO interface level detection module, a wake-up judgment module and a state conversion module connected in sequence; The IO interface level detection module is connected to the IO interface and is used to detect the level change of the IO interface; The wake-up judgment module is used to obtain the wake-up condition, judge whether the level change meets the wake-up condition, and send the judgment result to the state conversion module; The state conversion module is configured to generate a power-on instruction for instructing the low-voltage power domain to turn on the power supply when the judgment result indicates that the level change satisfies the preset wake-up condition, and send the power-on instruction to the power supply of the low-voltage power domain.

4. The power-on system according to claim 3, wherein: The system further includes: a latch, the latch being used to store the IO configuration information and the wake-up condition; The IO interface is connected to the latch and is used to obtain the IO configuration information from the latch; The wake-up judgment module is connected to the latch and is used to obtain the wake-up condition from the latch.

5. The power-on system according to any one of claims 1 to 2, characterized in that: The target event includes a transmission signal of a serial interface, the IO configuration information includes a type identifier indicating that the IO interface is an input interface and an initial level of the IO interface; the wake-up condition includes a level of the IO interface changing from the initial level to a level opposite to the initial level; When the IO interface detects an event in which the serial interface transmits a signal, the IO interface changes the level of the IO interface from the initial level to a level opposite to the initial level.

6. A power-on method, characterized in that: Applied to the power-on system according to any one of claims 1 to 5, the method comprises: In response to the received target event, control the level change of the IO interface according to the preset IO configuration information; Determining whether the level change satisfies a preset wake-up condition, the system chip setting and latching the IO configuration information and the wake-up condition before entering the sleep state; When the wake-up condition is met, sending a start instruction to the power supply of the low-voltage power domain to power on the low-voltage power domain and thus wake up the system chip; The target event includes a key being pressed; the IO configuration information includes a type identifier, a resistance identifier, and an output level of each IO interface, wherein the type identifier includes an input interface identifier and an output interface identifier, and the resistance identifier includes a pull-up resistor identifier and a pull-down resistor identifier; Among them, when a button is pressed, the level of the input interface corresponding to the button changes to be consistent with the output level of the output interface, so as to change the output of the output interface into a fixed output, change the input interface into a fixed connection with a pull-up resistor or a pull-down resistor, and change the periodic detection of the level of the input interface into real-time detection.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to claim 6 are implemented.

8. An electronic device, characterized in that: include: A system chip, a power supply of a low-voltage power domain, and a power-on system according to any one of claims 1 to 5, wherein the power-on system is connected to the power supply of the low-voltage power domain, and the power supply of the low-voltage power domain is connected to the system chip; The power on system is used to turn on the power of the low voltage power domain when the system chip switches from a sleep state to a working state, so as to power on the low voltage power domain and wake up the system chip.

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