A timing drive circuit division method

Abstract

The application relates to a timing-driven circuit partitioning method, which comprises the following steps: obtaining a first hypergraph and a path set; performing weighting processing on each path in the path set to obtain a second hypergraph; performing multi-stage clustering processing on the second hypergraph to obtain a third hypergraph; performing partitioning on the third hypergraph by using an iterative two-way partitioning method, and obtaining k partitions after multiple iterations; after each iteration partitioning, first, using a node movement-based improvement algorithm to optimize the cut cost of the partitioning result, and then performing system-level layout to obtain a fourth hypergraph; according to the inverse process of clustering, dispersing the node groups, and at each stage, moving the nodes at the boundary in the fourth hypergraph to obtain gain values of moving to all other partitions, and obtaining a fifth hypergraph according to the gain values. When the circuit partitioning is performed, the influence of the cut cost and the maximum path delay can be considered simultaneously, and the partitioning result has good timing performance.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and relates to a timing-driven circuit partitioning method. BACKGROUND

[0002] With the increasing complexity of circuit design, multi-FPGA (Field Programmable Gate Array) systems are becoming more and more popular in logic simulation and rapid prototyping. Large-scale circuit design is divided into multiple parts at the partitioning stage, and the number of interconnections between sub-circuits far exceeds the actual number of physical connections of FPGAs. In order to solve the interconnection problem, TDM (time-division multiplexing) technology is usually used. TDM technology allows multiple signals to communicate between two FPGAs through the same I / O port. The TDM ratio is the ratio of the number of signals that need to communicate and the channel capacity. It can be considered that the TDM delay between two FPGAs is proportional to the TDM ratio, and the delay can be represented by the TDM ratio. Although TDM technology solves the problem of too few I / O ports, it has a negative impact on system performance and reduces the overall frequency of the design. If the delay caused by TDM technology between FPGAs is considered at the partitioning stage, the timing performance of the system will be better.

[0003] Most current circuit partitioning schemes use the minimum cut optimization objective, i.e., the minimum cut cost. The partitioning method is generally based on a multi-level partitioning framework, which consists of clustering, initial partitioning and improvement. The purpose of clustering is to reduce the size of the hypergraph. By gradually aggregating nodes with high correlation in batches, a multi-level clustering result is formed. After clustering to a certain extent, the size of the hypergraph is greatly reduced, and at this time, initial partitioning is performed, and a high-quality initial solution can be quickly obtained. Then, according to the reverse process of clustering, the aggregated nodes are gradually dispersed, and the position of each node is adjusted to improve the quality of the solution.

[0004] A small number of circuit partitioning schemes use a single timing performance as an indicator, such as the maximum path delay represented by the TDM ratio. First, the wire net is weighted according to the path information, then the minimum cut partitioning scheme is used to obtain the partitioning result, and finally the system-level layout scheme based on iterative exchange is used to optimize the maximum path delay.

[0005] In the field of circuit partition, the minimum cut cost cannot completely represent the optimal timing performance. In the common timing-driven partition scheme, circuit partition and system-level placement are implemented in two stages, that is, system-level placement is performed after the completion of partition, and the partition is usually optimized with the minimum cut as the optimization target. This approach can make the system-level placement and different partitioners integrate, and has strong flexibility. However, the partitioning step lacks consideration of path delay, and the system-level placement cannot optimize the cut cost, and the two-step separation scheme makes the result fall into local optimum. Moreover, the scheme cannot optimize the maximum path delay and the cut cost simultaneously.

[0006] Therefore, how to optimize the cut cost and the maximum path delay simultaneously when partitioning a circuit has become a technical problem to be solved. SUMMARY

[0007] In order to solve the above problems in the prior art, the present application provides a timing-driven circuit partition method. The technical problem to be solved by the present application is solved by the following technical scheme:

[0008] The timing-driven circuit partition method provided by the embodiment of the present application comprises:

[0009] Step 1, obtaining a first hypergraph and a path set, the first hypergraph comprising a plurality of nodes, and the path set comprising a plurality of paths, each path being composed of ordered nodes;

[0010] Step 2, performing weighted processing on each path in the path set to obtain a second hypergraph;

[0011] Step 3, performing multi-level clustering processing on the second hypergraph to obtain a third hypergraph;

[0012] Step 4, performing partitioning on the third hypergraph by using an iterative two-way partition method, and after a plurality of iterations, obtaining k partitions, and after each iteration partitioning, first using a node movement-based improvement algorithm to optimize the cut cost of the partitioning result, and then performing system-level placement to obtain a fourth hypergraph;

[0013] Step 5, according to the inverse process of clustering, dispersing the node groups, and at each level, moving the nodes at the boundary in the fourth hypergraph to obtain gain values of moving to all other partitions, and obtaining a fifth hypergraph according to the gain values.

[0014] In an embodiment of the present application, the step 2 comprises:

[0015] Step 2.1, obtaining a node pair on the path, the node pair being two adjacent nodes on the same path;

[0016] Step 2.2, the node pairs are weighted by using the weight Wp to obtain a second hypergraph, wherein the weight Wp is calculated according to the following formula:

[0017]

[0018] wherein maxL is a maximum path length, minL is a minimum path length, Pw is a path weight parameter, and Pl is a path length of the node pair.

[0019] In an embodiment of the present application, the step 3 comprises:

[0020] Step 3.1, the correlation degree of the two node groups of the current level is calculated according to a correlation degree calculation formula, wherein each level comprises a plurality of node groups;

[0021] Step 3.2, all node groups of the current level are sorted according to the correlation degree, and a plurality of node groups are clustered two by two according to the order, and the clustering operation of the current level is completed;

[0022] Step 3.3, the next level clustering operation is performed according to the manner of step 3.1 and step 3.2, until a preset condition is reached, and the clustering is stopped, to obtain the third hypergraph.

[0023] In an embodiment of the present application, the correlation degree calculation formula is:

[0024]

[0025] wherein R(p,q) is the correlation degree of the node group p and the node group q, m(p,q) is the path weight of the node group p and the node group q, r(p) is the resource proportion of the node group p, r(q) is the resource proportion of the node group q, w n is a hyperedge weight, and x n is the number of nodes in the hyperedge.

[0026] In an embodiment of the present application, the step 4 comprises:

[0027] In the first iteration division, the third hypergraph is divided into two subparts, and in each iteration, the multiple subparts are respectively divided into two, and after multiple iterations, k divisions are obtained; after each iteration division, all nodes on the boundary are moved, and each time a node is randomly selected from all nodes on the boundary, the reduction amount of the cut cost of the node moving to all other divisions is calculated, and the movement with the maximum cut cost reduction amount and greater than zero is performed, and if the cut cost reduction amount is less than or equal to zero, no movement is performed; and after each movement ends, the divisions passed by the first n paths with greater path delay are selected, and each selected division is exchanged with other divisions to obtain the timing performance using the probability-based delay estimation method, and the time when the timing performance is improved the most is taken as the final exchanged division, and the system-level layout is ended until the timing performance is improved; the above operation is repeated until the fourth hypergraph is obtained.

[0028] In an embodiment of the present application, the calculation formula of the gain value is:

[0029]

[0030] Wherein, Gain is the gain value, ΔC is the reduction amount of the cut cost, C is the cut cost, ΔD is the reduction amount of the maximum path delay, D is the maximum path delay, β are the proportional adjustment coefficients, respectively.

[0031] In an embodiment of the present application, the timing performance obtained using the probability-based delay estimation method comprises:

[0032] S1, using Floyd algorithm to process FPGA graph to obtain multi-source shortest path;

[0033] S2, constructing a division interconnection matrix according to the characteristics of the line network, wherein the division interconnection matrix represents the interconnection weight between each division, and the interconnection weight is the weight sum corresponding to the line network;

[0034] S3, obtaining the routing probability of each shortest path according to the path capacity, and dispersing the interconnection weight of two divisions to each shortest path according to the routing probability, wherein the path capacity is the average value of the interconnection weight on the path, the routing probability of each shortest path is proportional to the path capacity, and the total value of the routing probability between the same two divisions is 1;

[0035] S4, constructing a delay lookup table composed of path delays of all FPGA pairs according to the TDM ratio, wherein the TDM ratio is the ratio of the interconnection usage and the interconnection capacity between two FPGAs, and the interconnection usage is the interconnection weight between two FPGAs;

[0036] S5, querying the path delay of the selected partition after exchange from the delay lookup table, and obtaining the path delay of the partition according to the sum of the path delay of the selected partition after exchange, taking the maximum value of all the path delays corresponding to all the exchanges of the partition as the maximum path delay, and taking the time when the reduction is the largest as the timing performance, wherein the reduction is the difference between the path delay of the partition before exchange and the path delay of the partition after exchange.

[0037] In an embodiment of the present application, the S4 comprises:

[0038] For the FPGA pair with interconnection line, the TDM ratio is used as the path delay of the FPGA pair, and for the FPGA pair without interconnection line, the path delays of all the shortest paths between the FPGA pair are calculated first, and then the average value of all the path delays is taken as the path delay of the FPGA pair.

[0039] In an embodiment of the present application, the step 5 comprises:

[0040] According to the inverse process of clustering, the node group is scattered, and at each level, the nodes on the boundary in the fourth hypergraph are moved, one node is randomly selected from all the nodes on the boundary each time, the gain value of the movement of the node to all the partitions is calculated, and the movement with the maximum gain value and greater than zero is executed, and if the gain value is less than or equal to zero, the movement is not executed, until the final fifth hypergraph is obtained.

[0041] Compared with the prior art, the present application has the following beneficial effects:

[0042] When the circuit is partitioned, the present application can consider the influence of the cut cost and the maximum path delay at the same time, and the partition result has good timing performance.

[0043] The present application proposes a delay estimation method based on probability when partitioning, which can quickly and accurately estimate the path delay, so that the time cost of considering the path delay in the partition stage is small.

[0044] Other aspects and features of the present application will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the application. It should be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the application, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise specified, they are merely intended to conceptually illustrate the structures and procedures described herein. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 A schematic diagram of a hypergraph provided for an embodiment of the present application;

[0046] Figure 2 A flowchart illustrating a timing drive circuit partitioning method provided in an embodiment of the present invention;

[0047] Figure 3 A flowchart of a timing drive circuit partitioning method provided in an embodiment of the present invention;

[0048] Figure 4 A schematic diagram of an iterative binary partitioning and system-level layout provided for an embodiment of the present invention;

[0049] Figure 5 This invention provides a probability distribution diagram of multiple shortest paths and wiring between two points, which is provided in an embodiment of the invention. Detailed Implementation

[0050] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0051] Example 1

[0052] In this embodiment, a circuit can be represented by circuit instances and their connections, which is similar to a hypergraph describing the relationships between objects. Therefore, the circuit partitioning problem is often transformed into a hypergraph partitioning problem. A hypergraph H(N,E) consists of a set of nodes N and a set of hyperedges E, where a hyperedge can contain multiple nodes. For example... Figure 1 As shown, nodes in a hypergraph represent circuit modules, and hyperedges represent connections between modules. While edges in a graph can only connect two nodes, a hypergraph better represents the complex connections within a circuit. The hyperedges cut during the partitioning process are called nets, and each FPGA that a hyperedge crosses is called a net pin.

[0053] A path set is an ordered collection of nodes. When partitioning circuits, the path delay between FPGAs is generally considered to be greater, thus ignoring the internal delay of the FPGA. Therefore, when two adjacent nodes on a path are in the same partition (or FPGA), their delay is zero; if the nodes are in different partitions, their delay is the TDM delay between the two FPGAs. The path delay is the sum of the delays of all adjacent nodes on the path, and the maximum path delay is the maximum value among all path delays.

[0054] In this embodiment, an undirected weighted graph G(V,E) is used to represent a multi-FPGA system. The vertex set and V represent the set of FPGAs, and the edge set E represents the connections between all FPGAs. The connections between each pair of FPGAs are called FPGA edges or channels, and the graph G(V,E) is also called the FPGA graph. In the FPGA graph, each vertex contains nine weights, representing the nine resource capacities of the FPGA, which serve as constraints during circuit partitioning; each edge has a weight representing the capacity of the interconnect resources.

[0055] Please see Figure 2 and Figure 3 , Figure 2 This is a flowchart illustrating a timing drive circuit partitioning method provided in an embodiment of the present invention. Figure 3 This is a flowchart of a timing drive circuit partitioning method provided by an embodiment of the present invention. The present invention provides a timing drive circuit partitioning method, which includes steps 1-5, wherein:

[0056] Step 1: Obtain the first hypergraph and the path set. The first hypergraph includes several nodes, and the path set includes several paths. Each path consists of ordered nodes.

[0057] Specifically, the system reads in the hypergraph file information corresponding to the design (i.e., the first hypergraph), paths, multi-FPGA system interconnection information, etc. The first hypergraph contains the following: node information (i.e., all nodes), and connection nets between nodes. Each net corresponds to a weight, and the larger the weight, the more important the net is. Each path consists of several ordered nodes, for example, the path is {1,2,4,3}.

[0058] Step 2: Weight each path in the path set to obtain the second hypergraph.

[0059] Specifically, in order to mitigate path fragmentation, preprocessing is performed first, increasing the aggregation weight of nodes on the path, that is, weighting all paths, and the processed first hypergraph is the second hypergraph.

[0060] In one specific embodiment, step 2 may specifically include steps 2.1-2.2, wherein:

[0061] Step 2.1: Obtain node pairs on the path. A node pair is two adjacent nodes on the same path. For example, for the path {1,2,4,3}, node 1 and node 2 are a node pair, node 2 and node 4 are a node pair, and node 4 and node 3 are a node pair.

[0062] Step 2.2: Assign weights to node pairs using weights Wp to obtain the second hypergraph. The formula for calculating weight Wp is:

[0063]

[0064] Where maxL is the maximum path length (i.e., the longest path length in the entire hypergraph), minL is the minimum path length (i.e., the shortest path length in the entire hypergraph), Pw is the path weight parameter, which defaults to 1, and Pl is the path length of the node pair. Note that Wp is zero when the path length is the minimum path length.

[0065] One way to reduce path latency is to reduce the number of path cuts. By assigning extra weights to the pairs of nodes connected along a path, the relevance of these pairs is enhanced during clustering, increasing the clustering priority. During the initial partitioning, nodes within clusters are not separated, so path weighting can alleviate path cutting to some extent.

[0066] Step 3: Perform multi-level clustering on the second hypergraph to obtain the third hypergraph.

[0067] Specifically, after path weighting, clustering is performed on the hypergraph. The clustering results are multi-level; the higher the level, the fewer the nodes. Considering path weights, resource balancing, and relevance, nodes are aggregated multiple times into smaller clusters. The clustering algorithm employs a multi-level model, where nodes clustered together are called clusters. Each clustering level merges a certain number of nodes (clusters). The higher the clustering level, the smaller the number of clusters and the coarser the granularity. The number of clusters after each clustering level is no less than half the number before clustering. Clustering terminates when the total number of clusters no longer changes or becomes sufficiently small.

[0068] In one specific embodiment, step 3 may specifically include steps 3.1-3.3, wherein:

[0069] Step 3.1: During each level of clustering, the correlation between the two node clusters at the current level is calculated according to the correlation calculation formula. Each level includes several node clusters.

[0070] Specifically, the relevance calculation considers the connectivity of node clusters, resource balance, and path weights. When a hyperedge has a weight of w... n The number of nodes in the hyperedge is x n When the correlation between two node cliques p and q is R(p,q), then:

[0071]

[0072] Where R(p,q) is the relevance between node clusters p and q, m(p,q) is the path weight between node clusters p and q, r(p) is the resource proportion of node cluster p, and r(q) is the resource proportion of node cluster q, which is calculated as the average proportion of the corresponding node cluster's resources to the total node cluster's resources, w n x is the weight of the hyperedge. n This represents the number of nodes in the superedge.

[0073] In the first level, each node is a node cluster, so it is necessary to calculate the correlation between two nodes (node ​​pairs).

[0074] Step 3.2: Sort all node clusters at the current level according to their relevance, and then perform pairwise clustering on the larger node clusters in order to complete the clustering operation at the current level. For example, the sorting order can be to sort the node clusters in descending order of relevance.

[0075] Preferably, the number of node clusters after each clustering level is not less than half the number before clustering.

[0076] Step 3.3: Perform the next level of clustering operation in the manner of steps 3.1 and 3.2 until the preset conditions are met, then stop clustering to obtain the third hypergraph.

[0077] Preferably, clustering will terminate when the total number of node clusters no longer changes or the total number of node clusters is small enough (e.g., 10 times the number of FPGAs).

[0078] Step 4: Use the iterative binary partitioning method to partition the third hypergraph. After multiple iterations, k partitions are obtained. After each iteration, the cut cost of the partitioning result is optimized by the node movement-based improvement algorithm, and then the system-level layout is performed to obtain the fourth hypergraph.

[0079] Specifically, after clustering, initial partitioning is performed. At the coarsest level, node clusters are partitioned, and these partitions are mapped onto the FPGA. For example... Figure 4 As shown, the initial partitioning uses an iterative binary partitioning method, dividing the hypergraph into two sub-parts each time. Each iteration further divides multiple sub-parts into two parts, resulting in k partitions after multiple iterations. k can be any integer greater than 1, preferably between 2 and 500. After each iteration, an improved algorithm based on node movement is used to optimize the cut cost of the partitioning result. To further optimize temporal performance, a system-level placement is then performed. To quickly evaluate the placement results, a probability-based delay prediction method is used to obtain the temporal performance.

[0080] This embodiment performs iterative binary partitioning of nodes in the hypergraph at the coarsest level, while simultaneously performing system-level placement to optimize maximum path delay. To obtain the path delay, the delay of each FPGA edge traversed by the path, i.e., the TDM ratio, needs to be known. However, the exact path direction and the TDM ratio between FPGAs cannot be known before system-level routing is completed. Considering that obtaining the path delay during the partitioning phase is sufficient, and the exact routing result is not required, the routing result can be estimated to guide the partitioning. By assigning probabilities to nets traversing different paths, the estimated routing result is obtained. Based on this, the delay between each FPGA is obtained, thereby calculating the path delay.

[0081] In one specific embodiment, step 4 may include:

[0082] In the first iteration, the third hypergraph is divided into two sub-parts. In each subsequent iteration, these sub-parts are further divided into two parts, resulting in k partitions after multiple iterations. After each iteration, all nodes on the boundary are moved. Each time, a node is randomly selected from all nodes on the boundary, and the reduction in cut cost for moving that node to all other partitions is calculated. The move with the largest reduction in cut cost that is greater than zero is executed. If the reduction in cut cost is less than or equal to zero, the move is not executed. After each move, the partitions traversed by the first n paths with larger path delays are selected, and each selected partition is swapped with other partitions (i.e., partitions other than those traversed by the selected n paths). A probability-based delay prediction method is used to obtain the timing performance, and the partition with the largest improvement in timing performance is selected as the final swap. This process continues until there is no improvement in timing performance, at which point the system-level layout ends. The above operations are repeated until the fourth hypergraph is obtained.

[0083] In one specific embodiment, a probability-based delay prediction method is used to obtain timing performance, including:

[0084] S1. Use the Floyd algorithm to process the FPGA graph to obtain the shortest path for multiple sources.

[0085] Specifically, first, a shortest path lookup table is constructed to find multiple shortest paths between all FPGAs. The weight of all edges in the FPGA graph is set to 1. The Floyd algorithm is used to calculate the multi-source shortest path. Typically, the Floyd algorithm uses a two-dimensional array to store path lengths and another two-dimensional array to record path information, which represents nodes between two nodes. Expanding the two-dimensional array to three dimensions allows for recording multiple path information between two nodes. When relaxing nodes, if the current distance between two nodes is equal to the shortest distance, the node is inserted into the path information recording array; if a better shortest path is found (i.e., the current distance between two nodes is less than the shortest distance), the path information between the two nodes is cleared before inserting the node. This allows the creation of a shortest path lookup table recording the nodes traversed by the shortest path between two nodes. For the path information recorded between two points, a depth-first search algorithm can be used to backtrack multiple shortest paths. The shortest path solution is as follows: Figure 5 As shown in (a), there are 3 shortest paths from node 2 to node 6, namely {2,3,6}, {2,4,6}, and {2,5,6}.

[0086] S2. Construct a partitioning interconnection matrix based on the characteristics of the wire mesh. The partitioning interconnection matrix represents the interconnection weights between the partitions, and the interconnection weights are the sum of the weights of the corresponding wire meshes.

[0087] Specifically, an interconnection matrix is ​​constructed based on the characteristics of the nets. The interconnection matrix represents the interconnection weights between different partitions. The weight of each interconnection weight is the sum of the weights of the corresponding nets. For example, the weight between partitions i and j is the sum of the weights of all nets containing only pins i and j, where pin i is in partition i and pin j is in partition j. When the number of pins in a net is greater than 2, it needs to be split. Here, it is split into multiple nets from the driver node to the load node. For example, if a net includes pins 1, 2, and 3, and pins 1, 2, and 3 are located in three different partitions, with pin 1 being the driver node, then it is split into nets from pin 1 to pin 2 and nets from pin 1 to pin 3.

[0088] S3. Obtain the routing probability of each shortest path based on the path capacity, and distribute the interconnection weights of the two partitions to each shortest path according to the routing probability. The path capacity is the average interconnection capacity on the path, and the routing probability of each shortest path is proportional to the path capacity. The total routing probability between the same two partitions is 1. Each edge has a weight, and the interconnection capacity represents the capacity of the interconnection resources, which is the number of interconnections. Therefore, after calculating the path capacity of a path by averaging the interconnection capacity on each path, the path capacity of all shortest paths between the two partitions can be obtained. Based on this, the routing probability of all shortest paths between the two partitions can be determined.

[0089] Specifically, for all interconnections between partitions, their routing probability distribution is obtained. In the case of multiple shortest paths, the larger the path capacity (the more interconnect resources), the higher the probability of traversing that path. The path capacity is set to the average of the interconnect capacities along the path. The routing probability of each shortest path is set to be proportional to the path capacity, with a total probability of 1. For example... Figure 5 As shown in (b), suppose we need to determine the routing probability distribution between partition 2 and partition 6. The interconnect capacity of the relevant FPGA edges is as follows. Figure 5 As shown in (b), the average interconnection capacity of paths {2, 3, 6} is 200, the average interconnection capacity of paths {2, 4, 6} is 100, and the average interconnection capacity of paths {2, 5, 6} is 100. Therefore, the path capacities of the shortest paths from left to right are 200, 100, and 100, respectively. Since the probability of traversing a path is proportional to its path capacity, we obtain... Figure 5 The probability distribution results are shown in (b). Therefore, after determining the routing probability of each shortest path, the interconnection weights between two nodes can also be distributed according to the routing probability, for example... Figure 5 In (b), there is a weight of 400 between partition 2 and partition 6. Therefore, 200 weights will be allocated to (2,3) and (3,6), 100 weights will be allocated to (2,4) and (4,6), and 100 weights will be allocated to (2,5) and (5,6).

[0090] S4. Construct a delay lookup table based on the TDM ratio, which consists of the path delays of all FPGA pairs. The TDM ratio is the ratio of interconnect usage to interconnect capacity between two FPGAs. Interconnect usage is the interconnect weight between two FPGAs, which is the sum of the weights of the nets between the two FPGAs. One partition is set on one FPGA.

[0091] Specifically, for FPGA pairs with interconnects, their TDM ratio is used as the path delay of the FPGA pair. For FPGA pairs without interconnects, the path delay of all shortest paths between the FPGA pairs is first calculated, and then the average of all path delays is used as the path delay of the FPGA pair. Thus, the path delay between any FPGA pairs can be obtained. The delay lookup table records the path delay between any two FPGAs.

[0092] S5. Query the path delay of the selected partition (i.e., the partition traversed by the first n paths with larger path delays) from the delay lookup table after the swap, and obtain the path delay of the partition based on the sum of the path delays of the selected partition after the swap. Take the maximum value of all path delays obtained in all swaps of the partition as the maximum path delay, and take the one with the largest reduction as the timing performance. The reduction is the difference between the path delay corresponding to the partition before the swap and the path delay corresponding to the partition after the swap.

[0093] In this embodiment, a system-level layout is performed after each iteration of the partitioning improvement. The system-level layout involves adjusting the FPGA where the partition is located. The interconnect resources between FPGAs are often different, and the connections between different partitions are also different. The goal is to ensure that signals with higher interconnect weights communicate between FPGAs with more interconnect resources, thereby minimizing the maximum path delay and improving timing performance.

[0094] The system-level layout employs an iterative swapping approach, exchanging the positions of two partitions based on the initial solution to improve the layout result. Since partitioning requires multiple iterations of binary search, the initial solution for each layout iteration is the solution from the previous iteration, while the initial solution for the first iteration is randomly generated. Note that swapping all partitions pairwise would result in significant time complexity. To optimize timing performance more efficiently, the focus is on optimizing the partition positions traversed by the n paths with the largest delays. These partitions are swapped with other partitions experimentally, and a probability-based delay prediction method is used to evaluate and record whether there is an improvement in timing performance. After all trials are completed, the swap with the largest improvement in timing performance is executed. This process is repeated; if there is no improvement in timing performance, the system-level layout process ends.

[0095] Step 5: Following the reverse process of clustering, disperse the node clusters and move the nodes at the boundaries of the fourth hypergraph at each level to obtain the gain value for moving to all other partitions. The fifth hypergraph is then derived based on this gain value. After the initial partitioning is completed, multi-level improvements are performed to gradually refine the multi-level data structure formed by clustering, improving the quality of the solution at each level.

[0096] Specifically, gradually dispersing the node clusters can be seen as the reverse process of clustering. At each level, the partitioning of nodes is adjusted, simultaneously improving cut cost and maximum path delay. The improvement algorithm employs a random greedy search approach, randomly selecting nodes on the boundary for movement (the movement method is the same as in step 4). If the result improves, the algorithm is executed. For the single-point movement improvement algorithm, a single movement of a non-boundary node cannot improve the cut cost. This is because all hyperedges associated with non-boundary nodes are not cut; moving them to another partition would inevitably make them boundary nodes, leading to an increase in cut edges. After the improvement is complete, the partitioning result is output.

[0097] In this embodiment, the gain value is used to evaluate the improvement brought by the move. Trial moves are performed on all nodes on the boundary. Each time, one node on the boundary is randomly selected, and the gain value for moving to all other partitions is calculated. The move with the largest gain value (greater than zero) is executed; that is, the node on the boundary is moved to the partition with the largest gain value (greater than zero). If the gain value is less than or equal to zero, the node on the boundary is not moved. The gain value is calculated as follows:

[0098]

[0099] Where Gain is the gain value, ΔC is the reduction in cut cost, C is the cut cost, ΔD is the reduction in maximum path delay, and D is the maximum path delay. β are the proportional adjustment coefficients. Adjusting these two values ​​can change the bias towards the two optimization objectives; the larger the value, the stronger the bias. The two coefficients are equal and set to 1 by default. Gain consists of the reduction rate of cutting cost and the reduction rate of maximum path delay.

[0100] This invention optimizes both slicing cost and maximum path delay simultaneously during circuit partitioning, and proposes a probability-based delay prediction method to obtain path delay. Timing performance during partitioning is mainly related to two factors: firstly, the number of times the critical path traverses between FPGAs. Currently, the delay between FPGAs is considered a bottleneck for system performance; the more times a signal is transmitted between FPGAs, the greater the delay. Secondly, the delay between FPGAs traversed by the critical path also affects system performance. The TDM ratio is generally used to represent the delay between FPGAs; a higher ratio indicates a greater delay. Simultaneously, reducing the slicing cost can reduce the TDM ratio to some extent, which helps optimize timing performance. Therefore, it is necessary to optimize both slicing cost and delay simultaneously during the partitioning stage.

[0101] The core circuit partitioning algorithm of this invention is based on a multi-level partitioning framework. It incorporates consideration of path delay in multiple steps, such as path weighting before clustering, considering path weights during clustering, using a probability-based delay prediction method to evaluate system performance during initial partitioning, and considering the impact of movement on path delay during improvement.

[0102] The timing-driven circuit partitioning method proposed in this invention is based on a multi-level partitioning framework, which can simultaneously optimize the cutting cost and the maximum path delay.

[0103] The multi-level partitioning framework of this invention can be widely used in the field of circuit partitioning because it can produce high-quality results in a short time.

[0104] In the description of the invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0105] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or feature data point described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or feature data points described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0106] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for partitioning a timing-driven circuit, characterized in that, The timing drive circuit partitioning method includes: Step 1: Obtain a first hypergraph and a path set. The first hypergraph includes several nodes, and the path set includes several paths, each of which is composed of ordered nodes. Step 2: Perform weighted processing on each path in the path set to obtain the second hypergraph; Step 3: Perform multi-level clustering on the second hypergraph to obtain the third hypergraph; Step 4: Partition the third hypergraph using an iterative binary partitioning method. After multiple iterations, k partitions are obtained. After each iteration, an improvement algorithm based on node movement is used to optimize the cut cost of the partitioning result, and then a system-level layout is performed to obtain the fourth hypergraph; specifically including: In the first iteration, the third hypergraph is divided into two sub-parts. In each subsequent iteration, these sub-parts are further divided into two parts, resulting in k partitions after multiple iterations. After each iteration, all nodes on the boundary are moved. Each time, a node is randomly selected from all nodes on the boundary, and the reduction in cut cost for moving that node to all other partitions is calculated. The move with the largest reduction in cut cost that is greater than zero is executed. If the reduction in cut cost is less than or equal to zero, the move is not executed. After each move, the partitions traversed by the first n paths with the largest path delays are selected, and each selected partition is swapped with other partitions to obtain the timing performance using a probability-based delay prediction method. The partition with the largest improvement in timing performance is selected as the final swapped partition. This process continues until there is no improvement in timing performance, at which point the system-level layout ends. The above operations are repeated until the fourth hypergraph is obtained. Step 5: Following the inverse process of clustering, disperse the node clusters, and at each level, move the nodes at the boundaries of the fourth hypergraph to obtain the gain value of moving to all other partitions, so as to obtain the fifth hypergraph based on the gain value.

2. The timing drive circuit partitioning method according to claim 1, characterized in that, Step 2 includes: Step 2.1: Obtain the node pairs on the path, where each node pair consists of two adjacent nodes on the same path. Step 2.2: Assign weights to the node pairs using weight Wp to obtain the second hypergraph, wherein the formula for calculating the weight Wp is: Where maxL is the maximum path length, minL is the minimum path length, Pw is the path weight parameter, and Pl is the path length of the node pair.

3. The timing drive circuit partitioning method according to claim 1, characterized in that, Step 3 includes: Step 3.1: During each level of clustering, the correlation between the two node clusters at the current level is calculated according to the correlation calculation formula. Each level includes several node clusters. Step 3.2: Sort all node clusters at the current level according to their relevance, and then cluster the larger node clusters pairwise in order to complete the clustering operation at the current level. Step 3.3: Perform the next level of clustering operation in the manner of steps 3.1 and 3.2 until the preset conditions are met, then stop clustering to obtain the third hypergraph.

4. The timing drive circuit partitioning method according to claim 3, characterized in that, The formula for calculating the relevance is: Where R(p,q) is the relevance between node clusters p and q, m(p,q) is the path weight between node clusters p and q, r(p) is the resource proportion of node cluster p, r(q) is the resource proportion of node cluster q, and w n x is the weight of the hyperedge. n This represents the number of nodes in the superedge.

5. The timing drive circuit partitioning method according to claim 1, characterized in that, The formula for calculating the gain value is: Where Gain is the gain value, ΔC is the reduction in cut cost, C is the cut cost, ΔD is the reduction in maximum path delay, and D is the maximum path delay. β represents the proportional adjustment coefficient.

6. The timing drive circuit partitioning method according to claim 1, characterized in that, The method of obtaining timing performance using a probability-based delay prediction method includes: S1. Use the Floyd algorithm to process the FPGA graph and obtain the shortest path for multiple sources; S2. Construct a partitioning interconnection matrix based on the characteristics of the wire mesh, wherein the partitioning interconnection matrix represents the interconnection weights between each partition, and the interconnection weights are the sum of the weights of the corresponding wire meshes; S3. Obtain the routing probability of each shortest path based on the path capacity, and distribute the interconnection weights of the two partitions to each shortest path according to the routing probability. The path capacity is the average value of the interconnection weights on the path. The routing probability of each shortest path is proportional to the path capacity, and the total routing probability between the same two partitions is 1. S4. Construct a delay lookup table consisting of the path delays of all FPGA pairs based on the TDM ratio, wherein the TDM ratio is the ratio of interconnect usage to interconnect capacity between two FPGAs, and the interconnect usage is the interconnect weight between two FPGAs. S5. Query the path delay of the selected partition through the FPGA after the exchange from the delay lookup table, and obtain the path delay of the partition according to the sum of the path delays of the selected partition through the FPGA after the exchange. Take the maximum value of all path delays obtained in all exchanges of the partition as the maximum path delay, and take the one with the largest reduction as the timing performance, wherein the reduction is the difference between the path delay corresponding to the partition before the exchange and the path delay corresponding to the partition after the exchange.

7. The timing drive circuit partitioning method according to claim 6, characterized in that, S4 includes: For FPGA pairs with interconnects, the TDM ratio is used as the path delay of the FPGA pair. For FPGA pairs without interconnects, the path delay of all shortest paths between the FPGA pairs is calculated first, and then the average of all path delays is used as the path delay of the FPGA pair.

8. The timing drive circuit partitioning method according to claim 1, characterized in that, Step 5 includes: Following the inverse process of clustering, the node clusters are dispersed, and at each level, the nodes at the boundary of the fourth hypergraph are moved. Each time, one node is randomly selected from all the nodes on the boundary, the gain value of moving that node to all other partitions is calculated, and the move with the largest gain value that is greater than zero is executed. If the gain value is less than or equal to zero, it is not executed, until the final fifth hypergraph is obtained.

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