Wafer classification method and device, electronic device and storage medium

Abstract

The present disclosure relates to a wafer classification method and device, electronic equipment and computer readable storage medium, and belongs to the technical field of semiconductor production and manufacturing, and can be applied to the scenario of classifying wafers. The method comprises: obtaining associated information of a wafer to be classified; the associated information comprises repair circuit information of the wafer to be classified and historical reference wafer information corresponding to a historical reference wafer; and based on the repair circuit information and the historical reference wafer information, the wafer to be classified is compared with the historical reference wafer one by one to obtain a current wafer category; the current wafer category comprises a current reference wafer and a current abnormal wafer. The present disclosure can quickly classify wafers according to the repair circuit information of the wafers to provide subsequent problem tracking of failed wafers.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor production and manufacturing, and particularly relates to a wafer classification method, a wafer classification device, an electronic device and a computer readable storage medium. BACKGROUND

[0002] In the circuit probe test (CP Test) stage, the failure bit (FB) information corresponding to all test items can be obtained, and the redundancy allocation (RA) is performed according to the failure position corresponding to the failure bit; in the fuse stage, the actual position is repaired according to the RA result, and the repair result is recorded in the fuse usage (FU) file.

[0003] Generally, the FB file is very large, and when wafer analysis is performed based on the FB file, only some specific items / wafers are usually selected for failure shape analysis (FSA), and the time spent by FSA is usually tens of times of that of RA.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present disclosure is to provide a wafer classification method, a wafer classification device, an electronic device and a computer readable storage medium, so as to at least partially overcome the problem that the existing wafer failure analysis method takes a long time and has low classification efficiency, which is not conducive to failure problem tracking analysis.

[0006] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0007] According to a first aspect of the present disclosure, a wafer classification method is provided, comprising: obtaining associated information of a wafer to be classified; the associated information comprising repair circuit information of the wafer to be classified and historical reference wafer information corresponding to a historical reference wafer; comparing the wafer to be classified with the historical reference wafer one by one based on the repair circuit information and the historical reference wafer information, to obtain a current wafer category; the current wafer category comprising a current reference wafer and a current abnormal wafer.

[0008] In one exemplary embodiment of this disclosure, before obtaining the association information of the wafers to be classified, the method further includes: obtaining historical wafers and determining multiple historical partition wafers corresponding to the historical wafers; obtaining a target test mode from multiple test modes and determining the number of repair circuits in each of the historical partition wafers under the target test mode; grouping the historical wafers according to the number of repair circuits to obtain historical wafer grouping results; and generating the historical reference wafer information according to the historical wafer grouping results.

[0009] In one exemplary embodiment of this disclosure, the step of grouping the historical wafers according to the number of repair circuits to obtain historical wafer grouping results includes: obtaining a repair circuit threshold; determining the failure degree of each partitioned wafer based on the number of repair circuits and the repair circuit threshold; determining a first grouping number; the first grouping number is the number used to group the historical wafers; and performing hierarchical clustering grouping on the historical wafers based on the failure degree to obtain the first grouping number of historical wafer groups.

[0010] In one exemplary embodiment of this disclosure, determining the number of the first group includes: generating a corresponding first-level structure tree based on the historical wafer; determining the sum of squares within the first group corresponding to the historical wafer based on the first-level structure tree; and determining the number of the first group based on the sum of squares within the first group.

[0011] In one exemplary embodiment of this disclosure, after obtaining the first group number of historical wafer groups, the method further includes: determining the number of wafers contained in each wafer group, processing each wafer number in descending order to obtain a grouping sorting result; obtaining a pre-configured type division threshold; and determining the grouping type corresponding to each wafer group based on the type division threshold and the multiple wafer numbers.

[0012] In one exemplary embodiment of this disclosure, determining the grouping type corresponding to each wafer group based on the type classification threshold and the plurality of wafer quantities includes: if the number of wafers is greater than the type classification threshold, then determining the grouping type as a baseline wafer category; if the number of wafers is less than the type classification threshold, then determining the grouping type as an abnormal wafer category.

[0013] In one exemplary embodiment of this disclosure, the method further includes: identifying wafers whose grouping type is the reference wafer category in all said test modes as historical reference wafers.

[0014] In one exemplary embodiment of this disclosure, the method further includes: obtaining a set of reference wafers identified as the reference wafer category, the set of reference wafers including at least one reference wafer; obtaining a set of abnormal wafers identified as the abnormal wafer category, the set of abnormal wafers including at least one abnormal wafer; performing a similarity comparison between each of the abnormal wafers and the reference wafers, and determining a screened reference wafer from the abnormal wafers based on the comparison results; the screened reference wafers are reference wafers that were misjudged as the abnormal wafers after classification processing based on multiple test modes; and re-adding the screened reference wafers to the wafer database as the historical reference wafers.

[0015] In one exemplary embodiment of this disclosure, the step of comparing each wafer to be classified with the historical reference wafer based on the repair circuit information and the historical reference wafer information to obtain the current wafer category includes: determining the wafer similarity between each wafer to be classified and the historical reference wafer; if the wafer similarity is greater than or equal to a similarity threshold, then the wafer to be classified is determined as the current reference wafer; if the wafer similarity is less than the similarity threshold, then the wafer to be classified is determined as the current abnormal wafer.

[0016] In one exemplary embodiment of this disclosure, the method further includes: partitioning the current abnormal wafer to obtain multiple partitioned abnormal wafers; obtaining a target test mode from multiple test modes, and determining the number of second repair circuits for each partitioned abnormal wafer under the target test mode; determining a second failure degree for each partitioned abnormal wafer based on the number of second circuit repairs; determining a second grouping number, and performing hierarchical clustering grouping on the partitioned abnormal wafers based on the second failure degree to obtain the second grouping number of abnormal wafer categories.

[0017] In one exemplary embodiment of this disclosure, determining the number of the second group includes: generating a corresponding second-level structure tree based on the current abnormal wafer; determining the sum of squares within the second group corresponding to the current abnormal wafer according to the second-level structure tree; and determining the number of the second group according to the sum of squares within the second group.

[0018] In one exemplary embodiment of this disclosure, the method further includes: if the wafer to be classified is the current reference wafer, generating and displaying a current reference wafer map of the current reference wafer; if the wafer to be classified is the current abnormal wafer, obtaining the abnormal wafer category corresponding to the current abnormal wafer; and generating and displaying an abnormal wafer category map corresponding to the abnormal wafer category.

[0019] According to a second aspect of this disclosure, a wafer classification device is provided, comprising: an association information acquisition module, configured to acquire association information of wafers to be classified; the association information includes repair circuit information of the wafers to be classified and historical reference wafer information corresponding to historical reference wafers; and a wafer comparison module, configured to compare each wafer to be classified with the historical reference wafers based on the repair circuit information and the historical reference wafer information to obtain a current wafer category; the current wafer category includes a current reference wafer and a current abnormal wafer.

[0020] In one exemplary embodiment of this disclosure, the wafer classification device further includes a historical information acquisition module, used to acquire historical wafers, determine multiple historical partition wafers corresponding to the historical wafers; acquire a target test mode from multiple test modes, determine the number of repair circuits in each of the historical partition wafers under the target test mode; group the historical wafers according to the number of repair circuits to obtain historical wafer grouping results; and generate the historical reference wafer information according to the historical wafer grouping results.

[0021] In one exemplary embodiment of this disclosure, the historical information acquisition module includes a historical grouping module, used to acquire a repair circuit threshold, determine the failure degree of each partitioned wafer based on the number of repair circuits and the repair circuit threshold; determine a first grouping number; the first grouping number is the number used to group the historical wafers; and perform hierarchical clustering grouping processing on the historical wafers based on the failure degree to obtain the first grouping number of historical wafer groups.

[0022] In one exemplary embodiment of this disclosure, the historical grouping module includes a first grouping quantity determination unit, configured to generate a corresponding first-level structure tree based on the historical wafer; determine the sum of squares within a first group corresponding to the historical wafer based on the first-level structure tree; and determine the first grouping quantity based on the sum of squares within the first group.

[0023] In one exemplary embodiment of this disclosure, the historical grouping module further includes a grouping type determination unit, used to determine the number of wafers contained in each wafer group, process the number of wafers in descending order to obtain a grouping sorting result; obtain a pre-configured type division threshold; and determine the grouping type corresponding to each wafer group based on the type division threshold and the number of wafers.

[0024] In one exemplary embodiment of this disclosure, the grouping type determination unit includes a grouping result determination subunit, configured to determine the grouping type as a baseline wafer category if the number of wafers is greater than the type classification threshold; and to determine the grouping type as an abnormal wafer category if the number of wafers is less than the type classification threshold.

[0025] In one exemplary embodiment of this disclosure, the historical grouping module further includes a first reference wafer determination unit, which is used to determine the wafers whose grouping type is the reference wafer category in all test modes as historical reference wafers.

[0026] In one exemplary embodiment of this disclosure, the historical grouping module further includes a second reference wafer determination unit, configured to: acquire a set of reference wafers identified as the reference wafer category, the reference wafer set including at least one reference wafer; acquire a set of abnormal wafers identified as the abnormal wafer category, the abnormal wafer set including at least one abnormal wafer; perform similarity comparisons between the abnormal wafers and the reference wafers one by one, and determine a screened reference wafer from the abnormal wafers based on the comparison results; the screened reference wafers are reference wafers that were misjudged as the abnormal wafers after classification processing based on multiple test modes; and re-add the screened reference wafers to the wafer database as the historical reference wafers.

[0027] In one exemplary embodiment of this disclosure, the wafer comparison module includes a wafer comparison unit for determining the wafer similarity between each wafer to be classified and the historical reference wafer; if the wafer similarity is greater than or equal to a similarity threshold, the wafer to be classified is determined as the current reference wafer; if the wafer similarity is less than the similarity threshold, the wafer to be classified is determined as the current abnormal wafer.

[0028] In one exemplary embodiment of this disclosure, the wafer classification device includes a wafer classification module, configured to partition the current abnormal wafer to obtain multiple partitioned abnormal wafers; obtain a target test mode from multiple test modes, determine the number of second repair circuits for each partitioned abnormal wafer under the target test mode; determine a second failure degree for each partitioned abnormal wafer based on the number of second circuit repairs; determine a second grouping number, and perform hierarchical clustering grouping of the partitioned abnormal wafers based on the second failure degree to obtain the second grouping number of abnormal wafer categories.

[0029] In one exemplary embodiment of this disclosure, the wafer classification module includes a second group quantity determination unit, configured to generate a corresponding second-level structure tree based on the current abnormal wafer; determine the sum of squares within the second group corresponding to the current abnormal wafer according to the second-level structure tree; and determine the second group quantity according to the sum of squares within the second group.

[0030] In one exemplary embodiment of this disclosure, the wafer sorting device further includes a wafer map generation module, configured to generate and display a current reference wafer map of the current reference wafer if the wafer to be sorted is a current reference wafer; obtain the abnormal wafer category corresponding to the current abnormal wafer if the wafer to be sorted is a current abnormal wafer; and generate and display an abnormal wafer category map corresponding to the abnormal wafer category.

[0031] According to a third aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory storing computer-readable instructions that, when executed by the processor, implement the wafer sorting method according to any one of the preceding claims.

[0032] According to a fourth aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the wafer sorting method according to any one of the preceding claims.

[0033] The technical solution provided in this disclosure may include the following beneficial effects:

[0034] The wafer classification method in the exemplary embodiments of this disclosure, on the one hand, compares the wafer to be classified with historical reference wafer information based on the repair circuit information of the wafer to be classified, thereby determining the specific category of the wafer to be classified and improving the classification efficiency. On the other hand, after determining the specific category of the wafer, wafer failure problems can be effectively tracked according to the specific category of the wafer.

[0035] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0037] Figure 1 A flowchart illustrating an exemplary embodiment of a wafer sorting method according to the present disclosure is shown schematically;

[0038] Figure 2 The diagram schematically illustrates an overall flowchart of the sorting process for wafers to be sorted according to an exemplary embodiment of the present disclosure;

[0039] Figure 3The illustration schematically shows the effect of partitioning a historical wafer according to an exemplary embodiment of the present disclosure;

[0040] Figure 4 The diagram schematically illustrates a hierarchical structure tree generated using a hierarchical clustering method according to an exemplary embodiment of the present disclosure;

[0041] Figure 5 A schematic diagram illustrating the relationship between the sum of squares within groups and the number of clusters according to an exemplary embodiment of this disclosure is provided.

[0042] Figure 6 The illustration schematically shows a visualization of a wafer to be classified after being classified according to an exemplary embodiment of the present disclosure;

[0043] Figure 7 A block diagram of a wafer sorting apparatus according to an exemplary embodiment of the present disclosure is shown schematically;

[0044] Figure 8 A block diagram of an electronic device according to an exemplary embodiment of the present disclosure is shown schematically;

[0045] Figure 9 The illustration shows a schematic diagram of a computer-readable storage medium according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0046] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0047] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0048] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0049] During wafer testing, failure bits can be repaired using Reliability Analysis (RA). Theoretically, the less redundancy (Red) is used, the fewer failure locations there are, and the better the wafer quality. Since failure shape analysis (FB) files are typically very large, only specific test items / wafers are usually selected for Failure Shape Analysis (FSA), and FSA usually takes tens of times longer than RA.

[0050] Based on this, in this example embodiment, a wafer sorting method is first provided. The wafer sorting method of this disclosure can be implemented using a server or using a terminal device. The terminal described in this disclosure can include mobile terminals such as mobile phones, tablets, laptops, handheld computers, and personal digital assistants (PDAs), as well as fixed terminals such as desktop computers. Figure 1 A schematic diagram illustrating a wafer sorting method flow according to some embodiments of the present disclosure is shown. Reference Figure 1 The wafer sorting method may include the following steps:

[0051] Step S110: Obtain the association information of the wafer to be classified; the association information includes the repair circuit information of the wafer to be classified and the historical reference wafer information corresponding to the historical reference wafer.

[0052] According to some exemplary embodiments of this disclosure, the wafer to be classified can be a wafer that currently requires classification processing. Associated information can be all information associated with the wafer to be classified. Repair circuit information can be related information about all repair circuits that have performed repair processing on the wafer that has completed probe testing using repair circuit Red; for example, repair circuit information can include the specific location of the repair circuit. Historical reference wafers can be wafers that have passed CP testing and been classified into a reference category within a certain period of time. Historical reference wafer information can be related information corresponding to historical reference wafers, such as the repair circuit used to perform repair processing on historical reference wafers.

[0053] In wafer commutation (CP) testing, multiple wafers need to be classified. Typically, all wafers that have completed CP testing and repaired successfully in the current cycle are considered as wafers to be classified. After identifying the wafers to be classified, their associated information can be determined. This associated information is stored in a wafer information database. This information includes the repair circuit information of the wafer to be classified, as well as historical reference wafer information identified through previous classification processes. The historical reference wafer information may include relevant information about the repair circuits that have been repaired based on the historical reference circuits.

[0054] refer to Figure 2 , Figure 2 The diagram schematically illustrates an overall flowchart of a wafer classification process according to an exemplary embodiment of the present disclosure. A wafer information database may store repair circuit information of the wafer to be classified, as well as historical reference wafer information that has undergone classification in the past. This associated information is retrieved from the wafer information database to classify the wafer to be classified based on this associated information.

[0055] Step S120: Based on the repair circuit information and historical reference wafer information, compare each wafer to be classified with the historical reference wafer to obtain the current wafer category; the current wafer category includes the current reference wafer and the current abnormal wafer.

[0056] According to some exemplary embodiments of this disclosure, the current wafer category can be a specific category determined after the wafers to be classified have undergone classification processing. The current abnormal wafer can be a wafer that has been determined to be an abnormal wafer category after the wafers to be classified have undergone classification processing.

[0057] After obtaining the aforementioned related information, the wafers to be classified can be compared one by one with the historical reference wafers based on the repair circuit information and historical reference wafer information. For example, the historical reference wafer information includes the specific location of the repair circuit. A similarity comparison analysis is performed between the wafers to be classified and the historical reference wafers, and the current wafer category corresponding to the wafer to be classified is determined based on the similarity comparison results. For example, the current wafer category can include the current reference wafer and the current abnormal wafer.

[0058] According to the wafer classification method in this example embodiment, on the one hand, by comparing the wafer to be classified with the historical reference wafer information based on the repair circuit information of the wafer to be classified, the specific category of the wafer to be classified can be determined, thereby improving the classification efficiency. On the other hand, after determining the specific category of the wafer, the failure problem of the wafer can be effectively tracked according to the specific category of the wafer.

[0059] The wafer sorting method in steps S110 to S120 of this disclosure will be further explained below.

[0060] In one exemplary embodiment of this disclosure, historical wafers are acquired, and multiple historical partition wafers corresponding to the historical wafers are identified; a target test mode is acquired from multiple test modes, and the number of repair circuits in each historical partition wafer under the target test mode is determined; the historical wafers are grouped according to the number of repair circuits to obtain historical wafer grouping results; and historical reference wafer information is generated based on the historical wafer grouping results.

[0061] Here, "historical wafer" can refer to all wafers that passed CP testing within a certain period. "Historical partitioned wafer" refers to wafers obtained by partitioning historical wafers. "Test mode" refers to the failure mode (FM) used to test the wafer under test. "Target test mode," also known as the target failure mode, refers to the test mode used to test the current wafer. "Number of repair circuits" refers to the number of repair circuits corresponding to the historical partitioned wafers under the target test mode. "Historical wafer grouping result" refers to the result obtained after grouping historical wafers.

[0062] Continue to refer to Figure 2 The classification of historical wafers is determined by categorizing them. First, historical wafers are acquired. These historical wafers can be all wafers that passed CP testing within a certain period, for example, all wafers that passed CP testing within the past month. After identifying the historical wafers, to ensure the efficiency and accuracy of classification, they are partitioned, resulting in multiple historical partition wafers. Specifically, pre-configured wafer partitioning rules can be used, which can be determined empirically. (Reference) Figure 3 , Figure 3 The illustration schematically depicts the effect of partitioning a historical wafer according to an exemplary embodiment of this disclosure. Figure 3 As can be seen, through partitioning, 16 areas are obtained, which are 16 historical partition wafers.

[0063] After obtaining the aforementioned historical partition wafers, a target test mode (FM) can be selected to determine the number of repair circuit reds (Reds) on each historical partition wafer under the target test mode. Specifically, multiple wafers have multiple partition areas, and each area contains multiple dies. Under the target test mode, the number of reds on the dies in each partition is counted.

[0064] After determining the number of Reds (Reds), historical wafers can be grouped according to this number. When grouping historical wafers, the number of groups can be determined based on the number of Reds, dividing the historical groups into multiple groups of the corresponding number. These multiple groups are then further subdivided to determine the final historical wafer grouping results. The historical wafer grouping results typically include historical base line (BL) wafers and historical excursion (EX) wafers. After determining the historical wafer grouping results, relevant data such as repair circuits for the historical base wafers can be determined, generating historical base wafer information. Subsequent classification of wafers to be categorized can be based on this historical base wafer information.

[0065] In one exemplary embodiment of this disclosure, a repair circuit threshold is obtained, and the failure degree of each partition wafer is determined based on the number of repair circuits and the repair circuit threshold; the number of first groups is determined; the number of first groups is the number used to group historical wafers; hierarchical clustering grouping is performed on the historical wafers based on the failure degree to obtain the number of historical wafer groups in the first group.

[0066] The repair circuit threshold can be a value compared to the number of repair circuits in each partition wafer, used to determine whether a die in a certain historical partition wafer has failed. The failure degree of the partition wafer can be an indicator of whether a die in a certain historical partition wafer has failed. The first group number can be the specific number of groups obtained after grouping the historical wafers. The historical wafer grouping can be multiple groups obtained after grouping the historical wafers.

[0067] Continue to refer to Figure 2 Before grouping historical wafers, a repair quantity threshold can be determined for comparison with the repair circuits of each historical partition wafer. For example, after determining the repair circuits for each historical partition wafer, a specific percentile (e.g., 95%) value can be selected as a fixed repair circuit threshold, which can be used as the basis for subsequent determination of whether a die has failed.

[0068] After counting the number of red dots (Red) on each die within the same area across multiple wafers, the red dots can be sorted from largest to smallest. The red dots in the top 95% are used as a fixed threshold, i.e., the repair circuit threshold. This threshold is used to determine the failure level of the dies within the area. Specifically, if the number of red dots in a die is higher than the repair circuit threshold, the die is considered failed; if the number of red dots is lower than or equal to the fixed threshold, the die is considered not failed. The failure level of historical partitioned wafers can be represented by the failure rate, as calculated using Formula 1.

[0069] Failure rate = Number of failed dies / Total number of dies in historical partitioned wafers (Formula 1)

[0070] After determining the failure rate of historical wafer areas, the historical wafers are classified. During this classification process, the number of the first group can be predetermined, which represents the final number of groups obtained after classifying the historical wafers. Specifically, a hierarchical clustering method can be used to classify the historical wafers. By calculating the similarity between different wafers, a hierarchical nested clustering tree is created; the smaller the distance between wafers, the higher the similarity.

[0071] Hierarchical clustering methods can include bottom-up clustering and top-down clustering. Taking bottom-up clustering as an example, firstly, each wafer is considered a cluster, and the two closest clusters are merged into one cluster. This process is repeated until a desired number of clusters is reached or the distance between clusters meets the requirements, such as reaching a specified number of clusters or a sample distance threshold. In this embodiment, before grouping historical wafers, the number of the first group can be predetermined. That is, after grouping historical wafers, the number of historical wafer groups is determined. Through the above grouping process, wafers with similar characteristics can be divided into groups, and feature factors for wafer classification can be extracted to determine the specific category of the wafer in subsequent processes. Specifically, the process of determining the number of the first group is as follows:

[0072] In one exemplary embodiment of this disclosure, a first-level structure tree is generated based on historical wafers; the sum of squares within a first group corresponding to the historical wafers is determined based on the first-level structure tree; and the number of first groups is determined based on the sum of squares within the first group.

[0073] The hierarchical structure tree can be a tree-like structure obtained by clustering multiple wafers. The sum of squares within a group, also known as the sum of squares within a cluster, is the sum of the squares of the distances from all sample points (wafers) in a cluster to the centroid. The first sum of squares within a group can be the sum of the squares of the distances from each wafer in the hierarchical structure tree composed of historical wafers to the centroid of the current cluster. A cluster is the result of clustering; intuitively, a cluster is a group of data clustered together, and the mean of all data in a cluster is usually called the centroid of that cluster.

[0074] When generating the hierarchical structure tree corresponding to historical wafers, Euclidean distance can be used as a measure of similarity. Hierarchical clustering can be established using the complete connectivity method, referencing... Figure 4 , Figure 4 The diagram schematically illustrates a hierarchical structure tree generated using a hierarchical clustering method according to an exemplary embodiment of the present disclosure. Two clusters with the highest similarity can be connected by a connecting line to form a new cluster. Then, two more clusters with the highest similarity can be connected to form another new cluster, and so on, until a result is obtained. Figure 4The hierarchical structure tree shown is used to calculate the within-cluster sums of squares (WSS) of the historical wafers after generating the hierarchical structure tree. Specifically, the distance from the sample point to the centroid can be calculated using a formula...

[0075] The distance shown in Equation 2 is used for measurement.

[0076]

[0077] Where, x i It can be any wafer in the hierarchical structure tree; μ i It can be the centroid of the cluster to which the wafer belongs in the hierarchical structure tree.

[0078] The calculation method for the sum of squares within the first group is shown in Formula 3.

[0079]

[0080] Where, x i It can be any wafer in the hierarchical structure tree; μ i It can be the centroid of the cluster to which the wafer belongs in the hierarchical structure tree.

[0081] Using the above calculation method, the sum of squares within the first group corresponding to this hierarchical structure tree can be calculated, and the number of the first group can be determined based on the calculated sum of squares within the first group. (Reference) Figure 5 , Figure 5 A graph illustrating the relationship between the sum of squares within groups and the number of clusters according to an exemplary embodiment of this disclosure is shown. Figure 5 The horizontal axis represents the number of clusters, and the vertical axis represents the sum of squares within each group. The line graph showing their relationship reveals that as the number of clusters increases, the number of elements in each cluster decreases, and the elements become closer together. Therefore, the sum of squares within the first group decreases as the number of clusters increases. Thus, when determining the number of clusters for the first group based on the sum of squares within the first group, the focus is on the slope. When the sum of squares within the first group decreases very slowly, it is considered that further increasing the number of clusters will not enhance the effect. This "elbow point" represents the optimal number of clusters. Figure 5 The optimal number of clusters can be 5, that is, the number of the first group is 5.

[0082] In one exemplary embodiment of this disclosure, the number of wafers contained in each wafer group is determined, and the number of wafers is processed in descending order to obtain the grouping sorting result; a pre-configured type division threshold is obtained; and the grouping type corresponding to each wafer group is determined according to the type division threshold and the number of wafers.

[0083] The grouping and sorting results can be obtained by sorting the wafers contained in a wafer group from largest to smallest. The type classification threshold can be a specific value used when classifying wafer groups into types.

[0084] After grouping the historical wafers according to the first group quantity, the number of wafers in each wafer group is determined. Then, the wafer quantities of multiple groups are sorted in descending order to obtain the grouping sorting result. After determining the grouping sorting result, a type classification threshold is obtained. Based on the type classification threshold, the wafers in multiple groups are classified according to type to obtain the historical wafer grouping result.

[0085] In one exemplary embodiment of this disclosure, if the number of wafers is greater than the type classification threshold, the grouping type is determined as the baseline wafer category; if the number of wafers is less than the type classification threshold, the grouping type is determined as the abnormal wafer category.

[0086] The reference wafer category can be a grouping category in which wafers belong to the reference wafer category. The abnormal wafer category can be a grouping category in which wafers belong to the abnormal wafer category.

[0087] When classifying wafers, the principle of normal distribution can be used. For example, the type classification threshold can be set to 85%. Wafers can be classified according to the grouping and sorting results. In the grouping results, if the number of wafers in the top-ranked group exceeds the type classification threshold, its group type is determined as the baseline wafer category; otherwise, its group type is determined as the abnormal wafer category. For example, the group containing the vast majority (e.g., 85%) of wafers is the baseline wafer type, i.e., the BL wafer group; the rest are all abnormal wafer types, i.e., the EX wafer group.

[0088] In one exemplary embodiment of this disclosure, wafers that are grouped into the reference wafer category in all test modes are identified as historical reference wafers.

[0089] When identifying historical reference wafers, multiple failure modes can be used to perform failure testing on the wafer. This involves repeating the process described above for determining wafer grouping types, identifying the grouping type of the historical wafer under each test mode. If a historical wafer is defined as a reference wafer category BL on all failure modes (FMs), it is identified as a historical reference wafer, and its relevant information is stored in the wafer information database. Even after testing a historical wafer under multiple test modes, it is still considered a reference wafer, providing universal applicability for wafer classification across all process technologies.

[0090] In one exemplary embodiment of this disclosure, a set of benchmark wafers identified as benchmark wafer categories is obtained, the set of benchmark wafers including at least one benchmark wafer; a set of abnormal wafers identified as abnormal wafer categories is obtained, the set of abnormal wafers including at least one abnormal wafer; the abnormal wafers and benchmark wafers are compared one by one for similarity, and benchmark wafers are selected from the abnormal wafers based on the comparison results; the selected benchmark wafers are those that were misjudged as abnormal wafers after classification processing based on multiple test modes; the selected benchmark wafers are added back to the wafer database as historical benchmark wafers.

[0091] The set of reference wafers can be a collection of reference wafers. For example, after classifying wafers based on multiple test modes, one or more reference wafers can constitute a set of reference wafers. The set of abnormal wafers can be a collection of abnormal wafers. The reference wafers to be screened can be those that have been misclassified as abnormal wafers after being classified based on multiple test modes. For example, a wafer identified as an abnormal wafer type under multiple test modes can be compared again with the reference wafers for similarity. If the similarity exceeds a similarity threshold, the abnormal wafer can be considered a misclassified wafer and can be reclassified as a reference wafer.

[0092] To ensure the accuracy of historical wafer classification, anomalous wafers identified after classification under multiple test modes can be compared again with wafers classified as baseline wafers. The similarity comparison result then determines whether the anomalous wafer was misclassified. Therefore, after classification based on multiple test modes, a baseline wafer set (identified as baseline wafers) and a set of anomalous wafers (identified as anomalous wafers) can be obtained. The baseline wafer set contains all wafers identified as baseline wafers, while the anomalous wafer set may include one or more anomalous wafers. Baseline wafers and anomalous wafers are then obtained from the baseline wafer set and the anomalous wafer set, respectively, and their similarity is compared.

[0093] Specifically, each abnormal wafer is compared with a reference wafer for similarity. For example, the similarity is determined based on the Euclidean distance between the two wafers, and then the abnormal wafer is reclassified based on the similarity comparison results. For instance, if the similarity between an abnormal wafer and multiple reference wafers is greater than a similarity threshold, the abnormal wafer can be considered a misclassified wafer. Therefore, this abnormal wafer can be re-identified as a reference wafer, i.e., used as a screening reference wafer. This screened reference wafer is then added to the wafer database as a historical reference wafer to ensure the accuracy of the wafer classification model used.

[0094] Since new wafers that pass the CP test will be continuously generated during the wafer CP testing process, which means new wafers to be classified will be generated for a new time period, the continuous reliability of wafer classification can be ensured by reclassifying these wafers according to the time period.

[0095] In one exemplary embodiment of this disclosure, the wafer similarity between each wafer to be classified and a historical reference wafer is determined; if the wafer similarity is greater than or equal to a similarity threshold, the wafer to be classified is determined as the current reference wafer; if the wafer similarity is less than the similarity threshold, the wafer to be classified is determined as the current abnormal wafer.

[0096] Specifically, wafer similarity refers to the degree of similarity between the wafer to be classified and historical benchmark wafers, and wafer similarity can be determined using Euclidean distance. The similarity threshold can be a specific numerical value used to determine the specific category of the wafer to be classified.

[0097] After obtaining the wafers to be classified, the corresponding repair circuit data (i.e., CP FU data) tested by probes can be retrieved from the wafer database. CP FU data records the test items of the die and the information of its repairable backup circuit (i.e., repair circuit), with each test item corresponding to a specific failure mode. Based on the CP FU data, each wafer to be classified is compared with a historical reference wafer for similarity. For example, the Red information corresponding to each wafer to be classified is determined based on the CP FU data. Red information can include the number and location of Red indicators, etc., and the Red information corresponding to the historical reference wafer is retrieved from the historical reference wafer information. Based on the two sets of Red information, the wafer similarity between the wafer to be classified and the historical reference wafer can be determined.

[0098] After determining the wafer similarity, a similarity threshold can be obtained. The wafer similarity is compared with the similarity threshold. If the wafer similarity is greater than or equal to the similarity threshold, the wafer to be classified is considered to have a high similarity with the historical reference wafer, and the wafer to be classified can be identified as the current reference wafer. If the wafer similarity is less than the similarity threshold, the wafer to be classified is considered to have a low similarity with the historical reference wafer, and the wafer to be classified is identified as the current abnormal wafer, thus completing the initial classification process of the wafer to be classified.

[0099] In one exemplary embodiment of this disclosure, the current abnormal wafer is partitioned to obtain multiple partitioned abnormal wafers; a target test mode is obtained from multiple test modes, and the number of second repair circuits for each partitioned abnormal wafer under the target test mode is determined; a second failure degree of each partitioned abnormal wafer is determined based on the number of second circuit repairs; a second grouping number is determined, and the partitioned abnormal wafers are hierarchically clustered and grouped based on the second failure degree to obtain a second grouping number of abnormal wafer categories.

[0100] Specifically, the partitioned abnormal wafer can be a partitioned wafer obtained after partitioning the current abnormal wafer that has been identified as an abnormal category. The second number of repair circuits can be the number of repair circuits used in the partitioned abnormal wafer. The second failure degree can be an indicator used to characterize whether the die in the current abnormal wafer has failed. The second number of groups can be the number of groups obtained after grouping the current abnormal wafer. The abnormal wafer category can be the specific category to which the current abnormal wafer belongs. For wafers with abnormalities, they can be further classified to determine the specific category.

[0101] After initial classification of the wafers to be classified, resulting in the current abnormal wafer, further classification can be performed to determine its specific category. This allows testers to use the determined category to guide subsequent problem tracking. The specific steps for classifying the current abnormal wafer are similar to those for determining historical baseline wafers based on historical wafers. The details are as follows:

[0102] The current faulty wafer is partitioned to obtain multiple partitioned faulty wafers. For example, the faulty wafer can be divided into 16 partitioned faulty wafers. After determining the partitioned faulty wafers, all failure modes for processing the wafer are obtained. A target test mode is selected from all failure modes, and the number of repair circuits used for each partitioned faulty wafer in the target test mode is determined, i.e., the second repair circuit number. The second failure degree corresponding to the current faulty wafer can be determined based on the second repair circuit number. The specific calculation method of failure degree has been explained in the above content and will not be repeated here.

[0103] After determining the number of the second group, the abnormal wafers in the partition can be grouped according to the second degree of failure. For example, a hierarchical clustering method can be used to group them to obtain the number of abnormal wafer categories in the second group.

[0104] In one exemplary embodiment of this disclosure, a second-level structure tree is generated based on the current abnormal wafer; the sum of squares within the second group corresponding to the current abnormal wafer is determined according to the second-level structure tree; and the number of the second group is determined according to the sum of squares within the second group.

[0105] The second group of intra-square sums can be determined based on the hierarchical structure tree of the current abnormal wafers.

[0106] After identifying the current anomalous wafer, a corresponding second-level structure tree can be constructed based on the similarity between the wafers in the current anomalous wafer group. After obtaining the second-level structure tree, the sum of squares of the distances between each anomalous wafer in a cluster and the centroid of that cluster can be determined, i.e., the sum of squares within the second group. Based on the sum of squares within the second group, the number of second groups can be determined, thus dividing the current anomalous wafer into that number of second groups.

[0107] In one exemplary embodiment of this disclosure, if the wafer to be classified is the current reference wafer, a current reference wafer map of the current reference wafer is generated and displayed; if the wafer to be classified is the current abnormal wafer, the abnormal wafer category corresponding to the current abnormal wafer is obtained; and an abnormal wafer category map corresponding to the abnormal wafer category is generated and displayed.

[0108] After the wafers to be classified are sorted, corresponding visualizations can be generated based on the specific category of the wafer. (Continue to refer to...) Figure 2 If the wafer to be classified is the current reference wafer, then a current reference wafer map is generated and displayed. (Reference) Figure 6 , Figure 6 The illustration schematically shows a visualization of a wafer to be sorted according to an exemplary embodiment of the present disclosure. From Figure 6 It can be seen from this that Figure 6 The 610 wafer in the middle is the current reference wafer diagram.

[0109] Additionally, if the wafer to be classified is a currently abnormal wafer, then the abnormal wafer category corresponding to the current abnormal wafer is obtained, and an abnormal wafer category map corresponding to the abnormal wafer category is generated. (Continue to refer to...) Figure 6 , Figure 6 The document displays a visual map of nine different abnormal wafer categories, illustrating the specific abnormal characteristics of each type. By providing these visual wafer maps, testers can intuitively observe the specific features of abnormal wafers and reference wafers, facilitating rapid problem tracking.

[0110] It should be noted that the terms "first," "second," etc., used in this disclosure are only for distinguishing different numbers of groups, different degrees of wafer failure, and different sums of squares within groups, and should not impose any limitations on this disclosure.

[0111] In summary, the wafer classification method disclosed herein obtains the associated information of the wafers to be classified. This associated information includes the repair circuit information of the wafer to be classified and the historical reference wafer information corresponding to the historical reference wafer. Based on the repair circuit information and the historical reference wafer information, each wafer to be classified is compared with the historical reference wafer to obtain the current wafer category. The current wafer category includes the current reference wafer and the current abnormal wafer. The current abnormal wafer is then classified to obtain the abnormal wafer category. On one hand, by using a classification method based on similarity calculation, the evaluation criteria for reference wafers and abnormal wafers are determined, enabling rapid wafer classification. On the other hand, for wafers judged as abnormal, the abnormal category can be further refined, allowing for the tracking and analysis of problems with failed wafers, providing corresponding effective analysis samples for different problem tracking. Furthermore, this wafer classification method can be applied to subsequent experimental processes to select wafers of different qualities, saving costs and improving yield.

[0112] It should be noted that although the steps of the method in this invention are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0113] Furthermore, in this example embodiment, a wafer sorting device is also provided. (See reference...) Figure 7 The wafer sorting device 700 may include: an associated information acquisition module 710 and a wafer comparison module 720.

[0114] Specifically, the association information acquisition module 710 is used to acquire the association information of the wafers to be classified; the association information includes the repair circuit information of the wafers to be classified and the historical reference wafer information corresponding to the historical reference wafers; the wafer comparison module 720 is used to compare the wafers to be classified one by one with the historical reference wafers based on the repair circuit information and the historical reference wafer information to obtain the current wafer category; the current wafer category includes the current reference wafer and the current abnormal wafer.

[0115] In one exemplary embodiment of this disclosure, the wafer sorting device 700 further includes a historical information acquisition module, used to acquire historical wafers, determine multiple historical partition wafers corresponding to the historical wafers; acquire a target test mode from multiple test modes, determine the number of repair circuits in each historical partition wafer under the target test mode; group the historical wafers according to the number of repair circuits to obtain historical wafer grouping results; and generate historical reference wafer information based on the historical wafer grouping results.

[0116] In one exemplary embodiment of this disclosure, the historical information acquisition module includes a historical grouping module, used to acquire a repair circuit threshold, determine the failure degree of each partition wafer based on the number of repair circuits and the repair circuit threshold, determine the number of first groups, the number of first groups being the number used to group the historical wafers, and perform hierarchical clustering grouping of the historical wafers based on the failure degree to obtain the number of historical wafer groups in the first group.

[0117] In one exemplary embodiment of this disclosure, the historical grouping module includes a first grouping quantity determination unit, configured to generate a corresponding first-level structure tree based on historical wafers; determine the sum of squares within the first group corresponding to the historical wafers based on the first-level structure tree; and determine the first grouping quantity based on the sum of squares within the first group.

[0118] In one exemplary embodiment of this disclosure, the historical grouping module further includes a grouping type determination unit, which is used to determine the number of wafers contained in each wafer group, process the number of wafers in descending order to obtain the grouping sorting result; obtain a pre-configured type division threshold; and determine the grouping type corresponding to each wafer group according to the type division threshold and the number of wafers.

[0119] In one exemplary embodiment of this disclosure, the grouping type determination unit includes a grouping result determination subunit, which determines the grouping type as a baseline wafer category if the number of wafers is greater than the type classification threshold, and determines the grouping type as an abnormal wafer category if the number of wafers is less than the type classification threshold.

[0120] In one exemplary embodiment of this disclosure, the historical grouping module further includes a first reference wafer determination unit, which is used to determine wafers whose grouping type is the reference wafer category in all test modes as historical reference wafers.

[0121] In one exemplary embodiment of this disclosure, the historical grouping module further includes a second reference wafer determination unit, configured to: obtain a set of reference wafers identified as reference wafer categories, the set of reference wafers including at least one reference wafer; obtain a set of abnormal wafers identified as abnormal wafer categories, the set of abnormal wafers including at least one abnormal wafer; perform similarity comparisons between abnormal wafers and reference wafers one by one, and determine and screen reference wafers from the abnormal wafers based on the comparison results; screen reference wafers are reference wafers that were misjudged as abnormal wafers after classification processing based on multiple test modes; and re-add the screened reference wafers to the wafer database as historical reference wafers.

[0122] In one exemplary embodiment of this disclosure, the wafer comparison module 720 includes a wafer comparison unit for determining the wafer similarity between each wafer to be classified and a historical reference wafer; if the wafer similarity is greater than or equal to a similarity threshold, the wafer to be classified is determined as the current reference wafer; if the wafer similarity is less than the similarity threshold, the wafer to be classified is determined as the current abnormal wafer.

[0123] In one exemplary embodiment of this disclosure, the wafer sorting device 700 includes a wafer sorting module for partitioning the current abnormal wafer to obtain multiple partitioned abnormal wafers; obtaining a target test mode from multiple test modes and determining the number of second repair circuits for each partitioned abnormal wafer under the target test mode; determining a second failure degree for each partitioned abnormal wafer based on the number of second circuit repairs; determining a second grouping number; and performing hierarchical clustering grouping of the partitioned abnormal wafers based on the second failure degree to obtain a second grouping number of abnormal wafer categories.

[0124] In one exemplary embodiment of this disclosure, the wafer classification module includes a second group quantity determination unit, which is used to generate a corresponding second-level structure tree based on the current abnormal wafer; determine the sum of squares within the second group corresponding to the current abnormal wafer according to the second-level structure tree; and determine the second group quantity according to the sum of squares within the second group.

[0125] In one exemplary embodiment of this disclosure, the wafer sorting device further includes a wafer map generation module, configured to generate and display a current reference wafer map of the current reference wafer if the wafer to be sorted is the current reference wafer; obtain the abnormal wafer category corresponding to the current abnormal wafer if the wafer to be sorted is the current abnormal wafer; and generate and display an abnormal wafer category map corresponding to the abnormal wafer category.

[0126] The specific details of the virtual modules of each wafer sorting device mentioned above have been described in detail in the corresponding wafer sorting methods, so they will not be repeated here.

[0127] It should be noted that although several modules or units of the wafer sorting apparatus have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0128] Furthermore, in an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0129] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented as entirely hardware embodiments, entirely software embodiments (including firmware, microcode, etc.), or embodiments combining hardware and software aspects, collectively referred to herein as “circuit,” “module,” or “system.”

[0130] The following is for reference. Figure 8 To describe an electronic device 800 according to such an embodiment of the present disclosure. Figure 8 The electronic device 800 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0131] like Figure 8 As shown, the electronic device 800 is presented in the form of a general-purpose computing device. The components of the electronic device 800 may include, but are not limited to: at least one processing unit 810, at least one storage unit 820, a bus 830 connecting different system components (including storage unit 820 and processing unit 810), and a display unit 840.

[0132] The storage unit stores program code that can be executed by the processing unit 810, causing the processing unit 810 to perform the steps described in the "Exemplary Methods" section above, according to various exemplary embodiments of this disclosure.

[0133] Storage unit 820 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 821 and / or cache memory 822, and may further include a read-only memory (ROM) 823.

[0134] Storage unit 820 may include a program / utility 824 having a set (at least one) of program modules 825, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0135] Bus 830 can represent one or more of several bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0136] Electronic device 800 can also communicate with one or more external devices 870 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 800, and / or with any device that enables electronic device 800 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 850. Furthermore, electronic device 800 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 860. As shown, network adapter 860 communicates with other modules of electronic device 800 via bus 830. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 800, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0137] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0138] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the invention described in the "Exemplary Methods" section above.

[0139] refer to Figure 9 As shown, a program product 900 for implementing the above-described method according to an embodiment of the present invention is described. It may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0140] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0141] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0142] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0143] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0144] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0145] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0146] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A wafer sorting method, characterized in that, include: Obtain the associated information of the wafer to be classified; the associated information includes the repair circuit information of the wafer to be classified and the historical reference wafer information corresponding to the historical reference wafer; Based on the repair circuit information and the historical reference wafer information, the wafers to be classified are compared one by one with the historical reference wafers to obtain the current wafer category; The current wafer category includes the current reference wafer and the current abnormal wafer; Prior to obtaining the association information of the wafers to be classified, the method further includes: Obtain historical wafers and identify multiple historical partition wafers corresponding to the historical wafers; Obtain the target test mode from multiple test modes, and determine the number of repair circuits in each of the historical partition wafers under the target test mode; The historical wafers are grouped according to the number of repaired circuits to obtain the historical wafer grouping results; The historical reference wafer information is generated based on the historical wafer grouping results.

2. The method according to claim 1, characterized in that, The step of grouping the historical wafers according to the number of repaired circuits to obtain the historical wafer grouping results includes: Obtain a repair circuit threshold, and determine the failure degree of each partitioned wafer based on the number of repair circuits and the repair circuit threshold; Determine the number of the first group; the number of the first group is the number used to group the historical wafers. Based on the degree of failure, the historical wafers are subjected to hierarchical clustering and grouping to obtain the first group of historical wafer groups.

3. The method according to claim 2, characterized in that, Determining the number of the first group includes: A first-level structure tree is generated based on the historical wafers; The first group of inner squares corresponding to the historical wafer is determined based on the first-level structure tree. The number of the first group is determined based on the sum of squares within the first group.

4. The method according to claim 3, characterized in that, After obtaining the first group of historical wafer groups, the method further includes: Determine the number of wafers contained in each wafer group, and sort the number of wafers in descending order to obtain the grouping results; Obtain the pre-configured type division threshold; The grouping type corresponding to each wafer group is determined based on the type classification threshold and the number of wafers.

5. The method according to claim 4, characterized in that, The step of determining the grouping type corresponding to each wafer group based on the type classification threshold and the multiple wafer quantities includes: If the number of wafers is greater than the type classification threshold, then the grouping type is determined as the baseline wafer category; If the number of wafers is less than the type classification threshold, the grouping type is determined as an abnormal wafer category.

6. The method according to claim 5, characterized in that, The method further includes: Wafers whose grouping type is the baseline wafer category in all the test modes are identified as historical baseline wafers.

7. The method according to claim 5, characterized in that, The method further includes: Obtain a set of reference wafers that have been identified as the reference wafer category, the set of reference wafers including at least one reference wafer; Obtain a set of abnormal wafers that have been identified as the abnormal wafer category, the set of abnormal wafers including at least one abnormal wafer; The similarity of each abnormal wafer and the reference wafer is compared one by one, and the reference wafer is selected from the abnormal wafers based on the comparison results; the reference wafer is the reference wafer that was misjudged as the abnormal wafer after being classified based on multiple test modes. The selected benchmark wafer is re-added to the wafer database as the historical benchmark wafer.

8. The method according to claim 1, characterized in that, The process involves comparing each wafer to be classified with the historical reference wafer information based on the repair circuit information to obtain the current wafer category, including: Determine the wafer similarity between each of the wafers to be classified and the historical reference wafers; If the wafer similarity is greater than or equal to the similarity threshold, then the wafer to be classified is determined as the current reference wafer; If the wafer similarity is less than the similarity threshold, then the wafer to be classified is determined as the current abnormal wafer.

9. The method according to claim 1, characterized in that, The method further includes: The current abnormal wafer is partitioned to obtain multiple partitioned abnormal wafers; Obtain the target test mode from multiple test modes, and determine the number of second repair circuits for each partitioned abnormal wafer under the target test mode; The second degree of failure of each partitioned abnormal wafer is determined based on the number of the second repair circuits; Determine the number of second groups, and perform hierarchical clustering grouping on the partitioned abnormal wafers based on the second failure degree to obtain the number of abnormal wafer categories in the second group.

10. The method according to claim 9, characterized in that, Determining the number of the second group includes: A second-level structure tree is generated based on the current abnormal wafer; The second set of inner squares corresponding to the current abnormal wafer is determined according to the second-level structure tree. The number of the second group is determined based on the sum of squares within the second group.

11. The method according to claim 1, characterized in that, The method further includes: If the wafer to be classified is the current reference wafer, then a current reference wafer map of the current reference wafer is generated and displayed; If the wafer to be classified is the current abnormal wafer, then obtain the abnormal wafer category corresponding to the current abnormal wafer; Generate and display the abnormal wafer category map corresponding to the abnormal wafer category.

12. A wafer sorting device, characterized in that, include: The associated information acquisition module is used to acquire the associated information of the wafer to be classified; the associated information includes the repair circuit information of the wafer to be classified and the historical reference wafer information corresponding to the historical reference wafer; The wafer comparison module is used to compare each wafer to be classified with the historical reference wafer based on the repair circuit information and the historical reference wafer information to obtain the current wafer category; the current wafer category includes the current reference wafer and the current abnormal wafer; The association information acquisition module, before acquiring the association information of the wafers to be classified, is further configured to: Obtain historical wafers and identify multiple historical partition wafers corresponding to the historical wafers; Obtain the target test mode from multiple test modes, and determine the number of repair circuits in each of the historical partition wafers under the target test mode; The historical wafers are grouped according to the number of repaired circuits to obtain the historical wafer grouping results; The historical reference wafer information is generated based on the historical wafer grouping results.

13. An electronic device, characterized in that, include: processor; as well as A memory storing computer-readable instructions that, when executed by the processor, implement the wafer sorting method according to any one of claims 1 to 11.

14. A computer-readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing the wafer sorting method according to any one of claims 1 to 11.

Images