System and method for parameterized pv level modeling and read threshold voltage estimation

Abstract

The present disclosure relates to systems and methods of parametric PV level modeling and read threshold voltage estimation. Embodiments provide a scheme of parametric PV level modeling and optimal read threshold voltage estimation in a memory system. A controller performs a read operation on a cell using a read threshold voltage; generates a CMF sample based on the read operation; and receives a first CDF value and a second CDF value corresponding to the CMF sample, each CDF value representing a skewed normal distribution. The controller estimates a first set of probability distribution parameters and a second set of probability distribution parameters corresponding to the first CDF value and the second CDF value, respectively; determines a first PDF value and a second PDF value using the first set of probability distribution parameters and the second set of probability distribution parameters, respectively; and estimates a read threshold voltage corresponding to a cross point of the first PDF value and the second PDF value as an optimal read threshold voltage.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a scheme for determining an optimal read threshold voltage in a memory system. BACKGROUND

[0002] A computer environment paradigm has shifted to ubiquitous computing systems that can be used anytime and anywhere. Accordingly, the use of portable electronic devices, such as mobile phones, digital cameras, and notebook computers, has increased rapidly. These portable electronic devices generally use a memory system having a memory device, i.e., a data storage device. The data storage device is used as a main memory device or an auxiliary memory device of the portable electronic devices.

[0003] A memory system using a memory device has excellent stability, durability, a high information access speed, and low power consumption since it does not have moving parts. Examples of the memory system having such advantages include a universal serial bus (USB) memory device, a memory card having various interfaces such as universal flash storage (UFS), and a solid state drive (SSD). The memory system can determine an optimal read threshold voltage among read threshold voltages according to various schemes. SUMMARY

[0004] Aspects of the present disclosure include systems and methods for parameterized PV level modeling and optimal read threshold voltage estimation based on parameterized PV level modeling.

[0005] In an aspect, a memory system includes a memory device including a plurality of cells and a controller. The controller performs a read operation on the plurality of cells using a plurality of read threshold voltages; generates a cumulative merit function (CMF) sample based on a result of the read operation; receives a first cumulative distribution function (CDF) value and a second CDF value selected from among a plurality of CDF values corresponding to the CMF sample, each of the first and second CDF values representing a skewed normal distribution; estimates a first set of probability distribution parameters and a second set of probability distribution parameters corresponding to the first and second CDF values, respectively; determines a first probability density function (PDF) value and a second PDF value corresponding to the first and second CDF values, respectively, using the first and second sets of probability distribution parameters, respectively; and estimates a read threshold voltage corresponding to a crossing point of the first and second PDF values as an optimal read threshold voltage.

[0006] In another aspect, a method for operating a memory system including a memory device including a plurality of cells and a controller, the method includes: performing a read operation on the plurality of cells using a plurality of read threshold voltage; generating a cumulative mass function (CMF) sample based on a result of the read operation; receiving a first cumulative distribution function (CDF) value and a second cumulative distribution function (CDF) value selected from among a plurality of CDF values corresponding to the CMF sample, each of the first CDF value and the second CDF value representing a skewed normal distribution; estimating a first set of probability distribution parameters and a second set of probability distribution parameters corresponding to the first CDF value and the second CDF value, respectively; determining a first probability density function (PDF) value and a second probability density function (PDF) value corresponding to the first CDF value and the second CDF value, respectively, using the first set of probability distribution parameters and the second set of probability distribution parameters, respectively; and estimating a read threshold voltage corresponding to a crossing point of the first PDF value and the second PDF value as an optimal read threshold voltage.

[0007] Other aspects of the application will become apparent based on the following description. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram illustrating a data processing system.

[0009] Figure 2 is a block diagram illustrating a memory system.

[0010] Figure 3 is a circuit diagram illustrating a memory block of a memory device.

[0011] Figure 4 is a diagram illustrating a state distribution of different types of cells of a memory device.

[0012] Figure 5A is a diagram illustrating an example of Gray coding of a multi-level cell (MLC).

[0013] Figure 5B is a diagram illustrating a state distribution of a page of a multi-level cell (MLC).

[0014] Figure 6A is a diagram illustrating an example of Gray coding of a triple-level cell (TLC).

[0015] Figure 6B is a diagram illustrating a state distribution of a page of a triple-level cell (TLC).

[0016] Figure 7 is a diagram illustrating a flow of an error recovery algorithm in a memory system.

[0017] Figure 8 This is a diagram illustrating the operation used to estimate the optimal read threshold voltage through various eBoost algorithms.

[0018] Figure 9A and Figure 9B The distribution of read threshold voltage (Vt) for memory cells is shown.

[0019] Figure 10 This is a diagram illustrating a memory system according to an embodiment of the present invention.

[0020] Figure 11 This is a diagram illustrating a neural network according to an embodiment of the present invention.

[0021] Figure 12 This is a diagram illustrating a training component according to an embodiment of the present invention.

[0022] Figure 13 This is a diagram illustrating a reasoning component according to an embodiment of the present invention.

[0023] Figure 14 The operation for determining the optimal read threshold voltage according to an embodiment of the present invention is illustrated.

[0024] Figure 15 A graph showing an example optimal readout threshold voltage determined for two distribution curves according to an embodiment of the present invention is provided. Detailed Implementation

[0025] Various embodiments are described in more detail below with reference to the accompanying drawings. However, this aspect may be implemented in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of the invention to those skilled in the art. Furthermore, references herein to “embodiment,” “another embodiment,” etc., are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. The term “embodiment” as used herein does not necessarily refer to all embodiments. Throughout this disclosure, the same reference numerals refer to the same parts in the drawings and embodiments of the invention.

[0026] The present application can be implemented in numerous ways, including as a process; an apparatus; a system; a computer program product; and / or as a processor such as a processor configured to fetch and execute instructions stored in a memory coupled to the processor. In this specification, these implementations, or any other form that the application can take, can be referred to as techniques. In general, the order of the steps of disclosed processes can be altered, unless otherwise specified. An apparatus described as suitable for performing a task can be implemented as a general-purpose apparatus that is temporarily configured to perform the task at a given time or as a special-purpose apparatus that is manufactured to perform the task. As used in this document, the term "processor" refers to one or more devices, circuits, and / or processing cores configured to process data, such as computer program instructions.

[0027] A detailed description of embodiments of the application is provided below with reference to the accompanying drawings. The application is described in connection with such embodiments, but the application is not limited to any embodiment. The scope of the application is limited only by the claims. Numerous alternatives, modifications, and equivalents of the application are encompassed by the scope of the claims. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the application. These details are provided in this document to provide examples of embodiments of the application. The application can be practiced without some or all of these specific details. In other instances, well known structures and processes are not elaborated upon in order to not obscure the application. For the sake of clarity, the description will be divided into sections, and the sections can be arranged in different orders than the order in which they are presented here.

[0028] Figure 1 is a block diagram illustrating a data processing system 2 according to an embodiment of the application.

[0029] Referring to Figure 1 The data processing system 2 can include a host device 5 and a memory system 10. The memory system 10 can receive requests from the host device 5 and operate in response to the received requests. For example, the memory system 10 can store data to be accessed by the host device 5.

[0030] The host device 5 can be implemented with any of various electronic devices. In various embodiments, the host device 5 can include an electronic device such as a desktop computer, a workstation, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, and / or a digital video recorder and a digital video player. In various embodiments, the host device 5 can include a portable electronic device such as a mobile phone, a smart phone, an electronic book, an MP3 player, a portable multimedia player (PMP), and / or a portable game player.

[0031] The memory system 10 can be implemented with any one of various storage devices such as a solid state drive (SSD) and a memory card. In various embodiments, the memory system 10 can be provided as one of various components in an electronic device such as a computer, an ultra mobile personal computer (PC) (UMPC), a workstation, a netbook computer, a personal digital assistant (PDA), a portable computer, a web tablet PC, a wireless phone, a mobile phone, a smart phone, an electronic book reader, a portable multimedia player (PMP), a portable game device, a navigation device, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a 3-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device of a data center, a device capable of receiving and transmitting information in a wireless environment, a radio frequency identification (RFID) device, one of various electronic devices of a home network, one of various electronic devices of a computer network, one of electronic devices of a telematics network, or one of various components of a computing system.

[0032] The memory system 10 can include a memory controller 100 and a semiconductor memory device 200. The memory controller 100 can control overall operations of the semiconductor memory device 200.

[0033] The semiconductor memory device 200 can perform one or more erase operations, program operations, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive a command CMD, an address ADDR, and data DATA through an input / output line. The semiconductor memory device 200 can receive power PWR through a power line and a control signal CTRL through a control line. The control signal CTRL can include a command latch enable signal, an address latch enable signal, a chip enable signal, a write enable signal, a read enable signal, and other operation signals, according to the design and configuration of the memory system 10.

[0034] The memory controller 100 and the semiconductor memory device 200 can be integrated in a single semiconductor device such as a solid state drive (SSD). The SSD can include a storage device that stores data in the SSD. When the semiconductor memory system 10 is used in the SSD, the operating speed of a host device (e.g., the host device 5 of FIG. 1) coupled to the memory system 10 can be significantly improved. Figure 1

[0035] ​The memory controller 100 and the semiconductor memory device 200 can be integrated in a single semiconductor device such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated as a Personal Computer (PC) card configured by the Personal Computer Memory Card International Association (PCMCIA), a CompactFlash (CF) card, a Smart Media (SM) card, a Memory Stick, a MultiMediaCard (MMC), a Reduced Size MMC (RS-MMC), an MMC in a micro-size version (MMCmicro), a Secure Digital (SD) card, a mini Secure Digital (miniSD) card, a micro Secure Digital (microSD) card, a Secure Digital High Capacity (SDHC), and / or a Universal Flash Storage (UFS).

[0036] Figure 2 is a block diagram illustrating a memory system according to an embodiment of the present application. For example, Figure 2 The memory system of Figure 1 illustrated in FIG. 1.

[0037] Referring to Figure 2 , the memory system 10 can include a memory controller 100 and a semiconductor memory device 200. The memory system 10 can operate in response to a request from a host device (e.g., the host device 5 of Figure 1 , and in particular, store data to be accessed by the host device.

[0038] The semiconductor memory device 200 can store data to be accessed by the host device.

[0039] The semiconductor memory device 200 can be implemented with a volatile memory device such as Dynamic Random Access Memory (DRAM) and / or Static Random Access Memory (SRAM) or a non-volatile memory device such as Read Only Memory (ROM), Mask ROM (MROM), Programmable ROM (PROM), Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), Ferroelectric Random Access Memory (FRAM), Phase-Change RAM (PRAM), Magneto-resistive RAM (MRAM), and / or Resistive RAM (RRAM).

[0040] The memory controller 100 can control data to be stored in the semiconductor memory device 200. For example, the memory controller 100 can control the semiconductor memory device 200 in response to a request from the host device. The memory controller 100 can provide data read from the semiconductor memory device 200 to the host device, and can store data provided by the host device into the semiconductor memory device 200.

[0041] The memory controller 100 can include a storage 110 coupled through a bus 160, a control component 120 which can be implemented as a processor such as a central processing unit (CPU), an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150.

[0042] The storage 110 can serve as a working memory of the memory system 10 and the memory controller 100, and store data for driving the memory system 10 and the memory controller 100. When the memory controller 100 controls the operation of the semiconductor memory device 200, the storage 110 can store data used for operations such as a read operation, a write operation, a program operation, and an erase operation by the memory controller 100 and the semiconductor memory device 200.

[0043] The storage 110 can be implemented with a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM). As described above, the storage 110 can store data used by the host device in the semiconductor memory device 200 for a read operation and a write operation. To store the data, the storage 110 can include a program memory, a data memory, a write buffer, a read buffer, a mapping buffer, etc.

[0044] The control component 120 can control a general operation of the memory system 10, and control a write operation or a read operation to the semiconductor memory device 200 in response to a write request or a read request from the host device. The control component 120 can drive firmware called a flash translation layer (FTL) to control the general operation of the memory system 10. For example, the FTL can perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block handling. The L2P mapping is called logical block addressing (LBA).

[0045] The ECC component 130 can detect and correct errors in data read from the semiconductor memory device 200 during a read operation. When the number of error bits is greater than or equal to a threshold number of correctable error bits, the ECC component 130 cannot correct the error bits, and can output an error correction failure signal indicating a failure in correcting the error bits.

[0046] In various embodiments, the ECC component 130 can perform error correction operations based on coding modulation such as Low-Density Parity-Check (LDPC) codes, Bose-Chaudhri-Hocquenghem (BCH) codes, Turbo codes, Turbo Product Codes (TPC), Reed-Solomon (RS) codes, Convolutional codes, Recursive Systematic Codes (RSC), Trellis-Coded Modulation (TCM), or Block-Coded Modulation (BCM). However, error correction is not limited to these techniques. As such, the ECC component 130 can include any and all circuitry, systems, or apparatuses for appropriate error correction operations.

[0047] The host interface 140 can communicate with a host device through one or more of various interface protocols such as Universal Serial Bus (USB), Multi-Media Card (MMC), Peripheral Component Interconnect Express (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advance Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE).

[0048] The memory interface 150 can provide an interface between the memory controller 100 and the semiconductor memory device 200 to allow the memory controller 100 to control the semiconductor memory device 200 in response to a request from the host device. The memory interface 150 can generate a control signal for the semiconductor memory device 200 and process data under the control of the control component 120. When the semiconductor memory device 200 is a flash memory such as NAND flash memory, the memory interface 150 can generate a control signal for the memory and process data under the control of the control component 120.

[0049] The semiconductor memory device 200 can include a memory cell array 210, a control circuit 220, a voltage generating circuit 230, a row decoder 240, a page buffer 250 (the page buffer 250 can be in the form of an array of page buffers), a column decoder 260, and an input and output (input / output) circuit 270. The memory cell array 210 can include a plurality of memory blocks 211 that can store data. The voltage generating circuit 230, the row decoder 240, the page buffer 250, the column decoder 260, and the input / output circuit 270 can form a peripheral circuit of the memory cell array 210. The peripheral circuit can perform a program operation, a read operation, or an erase operation on the memory cell array 210. The control circuit 220 can control the peripheral circuit.

[0050] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as an erase voltage and a pass voltage.

[0051] The row decoder 240 can be in electrical communication with the voltage generation circuit 230 and the plurality of memory blocks 211. The row decoder 240 can select at least one memory block among the plurality of memory blocks 211 in response to a row address generated by the control circuit 220, and transmit an operating voltage provided by the voltage generation circuit 230 to the selected memory block.

[0052] The page buffer 250 can be coupled to the memory cell array 210 through a bit line BL (not shown). The page buffer 250 can pre-charge the bit line BL with a positive voltage in response to a page buffer control signal generated by the control circuit 220, send and receive data to and from the selected memory block in a program operation and a read operation, or temporarily store the sent data. Figure 3

[0053] The column decoder 260 can send and receive data to and from the page buffer 250. The column decoder 260 can also interface with the input / output circuit 270 to send and receive data to and from the input / output circuit 270.

[0054] The input / output circuit 270 can send a command and an address received from an external device (e.g., a memory controller 100) to the control circuit 220 through the input / output circuit 270, send data from the external device to the column decoder 260, and / or output data from the column decoder 260 to the external device. Figure 1

[0055] The control circuit 220 can control the peripheral circuit in response to the command and the address.

[0056] Figure 3 FIG. 1 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present application. For example, the memory block of the semiconductor memory device can be any one of the memory blocks 211 of the memory cell array 210 illustrated in FIG. 1. Figure 3 Figure 2

[0057] Referring to FIG. 2, the exemplary memory block 211 can include a plurality of word lines WL0 to WLn-1 coupled to the row decoder 240, a drain select line DSL, and a source select line SSL. These lines can be arranged in parallel with the plurality of word lines between the DSL and the SSL. Figure 3

[0058] ​​​​​The example memory block 211 can further include a plurality of cell strings 221 coupled to bit lines BL0 through BLm-1, respectively. Each column of cell strings can include one or more drain select transistors DST and one or more source select transistors SST. In the illustrated embodiment, each cell string has one DST and one SST. Within the cell string, a plurality of memory cells or memory cell transistors MC0 through MCn-1 can be connected in series between the select transistors DST and SST. Each of the memory cells can be formed as a single-level cell (SLC) storing 1 bit of data, a multi-level cell (MLC) storing 2 bits of data, a triple-level cell (TLC) storing 3 bits of data, and a quad-level cell (QLC) storing 4 bits of data.

[0059] The source of the SST in each cell string can be coupled to a common source line CSL, and the drain of each DST can be coupled to a respective bit line. The gate of the SST in a cell string can be coupled to the SSL, and the gate of the DST in a cell string can be coupled to the DSL. The gates of the memory cells on a cell string can be coupled to respective word lines. That is, the gate of memory cell MC0 is coupled to a respective word line WL0, the gate of memory cell MC1 is coupled to a respective word line WL1, and so on. A group of memory cells coupled to a particular word line can be referred to as a physical page. Thus, the number of physical pages in the memory block 211 can correspond to the number of word lines.

[0060] The page buffer 250 can include a plurality of page buffers 251 coupled to the bit lines BL0 through BLm-1. The page buffers 251 can operate in response to page buffer control signals. For example, the page buffers 251 can temporarily store data received through the bit lines BL0 through BLm-1 or sense voltages or currents of the bit lines during a read or verify operation.

[0061] In some embodiments, the memory block 211 can include NAND-type flash memory cells. However, the memory block 211 is not limited to this type of cell, but can include NOR-type flash memory cells. The memory cell array 210 can be implemented as a hybrid flash memory incorporating two or more types of memory cells, or a single NAND flash memory with the controller embedded inside the memory chip.

[0062] Figure 4 is a graph illustrating a state distribution or program voltage (PV) level for different types of cells for a memory device.

[0063] Referring to Figure 4Each of the memory cells can be implemented with a particular type of cell, such as a single-level cell (SLC) that stores 1 bit of data, a multi-level cell (MLC) that stores 2 bits of data, a triple-level cell (TLC) that stores 3 bits of data, and a quad-level cell (QLC) that stores 4 bits of data. Typically, all of the memory cells in a particular memory device are of the same type, but that is not required.

[0064] An SLC can include two states P0 and P1. P0 can indicate an erased state and P1 can indicate a programmed state. Since an SLC can be set to one of two different states, each SLC can program or store 1 bit according to a set encoding method. An MLC can include four states P0, P1, P2, and P3. Among these states, P0 can indicate an erased state and P1 through P3 can indicate programmed states. Since an MLC can be set to one of four different states, each MLC can program or store 2 bits according to a set encoding method. A TLC can include eight states P0 through P7. Among these states, P0 can indicate an erased state and P1 through P7 can indicate programmed states. Since a TLC can be set to one of eight different states, each TLC can program or store 3 bits according to a set encoding method. A QLC can include sixteen states P0 through P15. Among these states, P0 can indicate an erased state and P1 through P15 can indicate programmed states. Since a QLC can be set to one of sixteen different states, each QLC can program or store 4 bits according to a set encoding method.

[0065] Referring back to Figure 2 and Figure 3 The semiconductor memory device 200 can include a plurality of memory cells (e.g., NAND flash memory cells). The memory cells can be arranged in rows and columns as shown in FIG. 2A. Each row of memory cells can be referred to as a page. Each page can include a number of memory cells, such as 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, or another number of memory cells. Each column of memory cells can be referred to as a word line. Each memory cell can be a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC). Figure 3The illustrated array arrangement of rows and columns. The cells in each row are connected to a word line (e.g., WL0), while the cells in each column are coupled to a bit line (e.g., BL0). These word lines and bit lines are used for read operations and write operations. During a write operation, the data to be written (“1” or “0”) is provided at the bit line when the word line is asserted. During a read operation, the word line is again asserted and then the threshold voltage of each cell can be acquired from the bit line. Multiple pages can share memory cells that belong to (i.e., are coupled to) the same word line. When the memory cells are MLC, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cells are TLC, the multiple pages include a MSB page, a center significant bit (CSB) page, and a LSB page. When the memory cells are QLC, the multiple pages include a MSB page, a center most significant bit (CMSB) page, a center least significant bit (CLSB) page, and a LSB page. The memory cells can be programmed using an encoding scheme (e.g., Gray code) to increase the capacity of the memory system 10, such as an SSD.

[0066] Figure 5A is a diagram illustrating an example of Gray coding for a multi-level cell (MLC).

[0067] Referring to Figure 5A A set of types of encoding can be used to program a MLC. The MLC can have 4 program states, including an erase state E (or PV0) and first through third program states PV1-PV3. The erase state E (or PV0) can correspond to “11”. The first program state PV1 can correspond to “10”. The second program state PV2 can correspond to “00”. The third program state PV3 can correspond to “01”.

[0068] In a MLC, as Figure 5B illustrated, there are 2 types of pages: LSB pages and MSB pages. One or two thresholds can be applied to retrieve data from the MLC. For MSB pages, a single threshold is VT1. VT1 distinguishes the first program state PV1 and the second program state PV2. For LSB pages, there are two thresholds: VT0 and VT2. VT0 distinguishes the erase state E and the first program state PV1. VT2 distinguishes the second program state PV2 and the third program state PV3.

[0069] Figure 6A is a diagram illustrating an example of Gray coding for a triple-level cell (TLC).

[0070] Referring to Figure 6AGray coding can be used to program the TLC. The TLC can have 8 program states, including an erase state E (or PV0) and first through seventh program states PV1-PV7. The erase state E (or PV0) can correspond to "111". The first program state PV1 can correspond to "011". The second program state PV2 can correspond to "001". The third program state PV3 can correspond to "000". The fourth program state PV4 can correspond to "010". The fifth program state PV5 can correspond to "110". The sixth program state PV6 can correspond to "100". The seventh program state PV7 can correspond to "101".

[0071] In the TLC, as shown in Figure 6B , there are 3 types of pages: LSB pages, CSB pages, and MSB pages. 2 or 3 thresholds can be applied to retrieve data from the TLC. For MSB pages, there are two thresholds: VT0 that distinguishes the erase state E and the first program state PV1, and VT4 that distinguishes the fourth program state PV4 and the fifth program state PV5. For CSB pages, there are three thresholds: VT1, VT3, and VT5. VT1 distinguishes the first program state PV1 and the second program state PV2. VT3 distinguishes the third program state PV3 and the fourth program state PV4. VT5 distinguishes the fifth program state PV5 and the sixth program state PV6. For LSB pages, there are two thresholds: VT2 and VT6. VT2 distinguishes the second program state PV2 and the third program state PV3. VT6 distinguishes the sixth program state PV6 and the seventh program state PV7.

[0072] After being programmed, including in a memory array comprising a plurality of memory cells as described in Figure 5A and Figure 6A , when a read operation is performed on the memory array using a particular reference voltage such as a read threshold voltage (also referred to as a "read voltage level" or "read threshold"), the charge levels of the memory cells (e.g., the threshold voltage levels of the transistors of the memory cells) are compared to the one or more reference voltages to determine the state of the individual memory cells. For example, when a particular read threshold is applied to the memory array, those memory cells having a threshold voltage level higher than the particular reference voltage turn on and are detected as "on" cells, while those memory cells having a threshold voltage level lower than the particular reference voltage turn off and are detected as "off" cells. Thus, each read threshold is arranged between adjacent threshold voltage distribution windows corresponding to different program states, so that each read threshold can distinguish between these program states by turning on or off the memory cell transistors.

[0073] When read operations are performed on memory cells in a data storage device using MLC techniques, the threshold voltage levels of the memory cells are compared to more than one read threshold to determine the state of each memory cell. Read errors can be caused by distorted or overlapping threshold voltage distributions. Due to, for example, program and erase (P / E) cycles, cell-to-cell interference, and / or data retention errors, the ideal memory cell threshold voltage distribution can become significantly distorted or shifted to overlap with adjacent threshold voltage distributions. For example, as program and erase cycles increase, the margin between adjacent threshold voltage distributions for different program states decreases and eventually the distributions overlap. Thus, memory cells with threshold voltages that fall within the overlapping region of adjacent distributions can be read as being programmed to a different value than the original target value, resulting in a read error. In most cases, such read errors can be managed by using error correction codes (ECC). When the number of bit errors associated with a read operation exceeds the ECC correction capability of the data storage device, the read operation using the set read threshold voltage fails. The set read threshold voltage can be a previously used read threshold voltage (i.e., a historical read threshold voltage). The historical read threshold voltage can be the read threshold voltage used at the last successful decode, i.e., the read voltage used in a read operation that passed before any read retry operations were performed. When the read operation using the set read threshold voltage fails, the controller 120 can control Figure 7 the performance of the error recovery algorithm illustrated.

[0074] Referring to Figure 7 , the controller 120 can perform one or more read retry operations on the memory cells using one or more read threshold voltages applied in a set order (SI 00). For example, there can be N (e.g., N is 5 or 10) read threshold voltages (or read voltage levels) including a first read threshold voltage to an Nth read threshold voltage. The first read threshold voltage can be a previously used read threshold voltage (i.e., a historical read threshold voltage). The historical read threshold voltage can be the read threshold voltage used at the last successful decode, i.e., the read voltage used in a last read operation that passed before any read retry operations were performed. The controller 120 can perform read retry operations until a decode associated with a respective read retry operation is determined to be successful.

[0075] When all of the read retry operations using read threshold voltages fail, the controller 120 can perform additional recovery operations. For example, the additional recovery operations can include an optimal read threshold voltage search (S200), soft decoding using error correction codes (ECC) (S300), and redundant array of independent disks (RAID) recovery (S400).

[0076] As described above, in a memory system such as a NAND flash memory system, after a read command is received, a series of data recovery steps are performed with the goal of retrieving noiseless data from the memory device (i.e., NAND flash memory device). In a first attempt, a read operation using a historical read threshold voltage is performed (i.e., historical read). Each physical block can maintain its own historical read, which can be updated if the decoding associated with the historical read fails. If the historical read fails, one or more read retry attempts are performed, which are commonly referred to as high priority read retries (HRRs). The HRRs maintain the same series of read threshold voltages (i.e., Vt) throughout the process. The HRR read retry threshold voltages do not change in response to changes in NAND conditions nor do they depend on the physical location of the data to be read. Typically, 5 to 10 HRR read attempts are made. If all HRR read attempts fail, an optimal read threshold voltage is found through an optimal read level search (i.e., eBoost algorithm) and then soft read and soft decode operations are performed with the optimal read threshold voltage. The eBoost algorithm can perform multiple reads to find the best center Vt for soft read. There are many different eBoost algorithms, such as Gaussian Modeling (GM) algorithm, Cumulative Cell Count Search (CCS) algorithm, and Advanced Valley Search (AVA) algorithm.

[0077] Figure 8 is a diagram illustrating the operations to estimate the optimal read threshold voltage through various eBoost algorithms such as the GM algorithm, CCS algorithm, and AVA algorithm.

[0078] Referring to Figure 8 , a comparison of the read threshold voltages obtained through each of the GM algorithm, CCS algorithm, and AVA algorithm to the optimal read threshold voltage OPT is shown. Assuming that all PV states (i.e., PV11, PV12) follow a Gaussian distribution with a known / constant variance and unknown mean, the GM algorithm attempts to find the read threshold voltage (Vt). The CCS algorithm attempts to find the Vt such that the number of cells on each side of Vt is equal. The AVA is attempting to find the lowest point in the valley of the distribution as the Vt. As shown in Figure 8 , when one of the two PV states (e.g., PV12) is not symmetric and has a heavier tail than the other state, each of these algorithms can estimate a read threshold voltage (i.e., GM, CCS, AVA) that is offset or deviated from the optimal read threshold voltage OPT.

[0079] Figure 9A and Figure 9B illustrate examples of threshold voltage (Vt) distributions or programmed states for three-layer cells (TLC) and quad-layer cells (QLC), respectively.

[0080] One or more of the PV states can be asymmetric and have a heavy tail compared to other states. In Figure 9A the example, three of the states PV25 to PV27 among PV21 to PV27 are asymmetric and have a heavy tail. In Figure 9B the example, the state PV315 among PV301 to PV315 is asymmetric and has a heavy tail. In these cases, each of the above existing algorithms would give biased Vt estimates. Therefore, it is desirable to provide a scheme for estimating the read threshold voltage to overcome the deficiencies of these existing algorithms.

[0081] Embodiments use deep learning and provide a parameterized framework for programming voltage or program verify (PV) level modeling and optimal read threshold voltage (Vt) estimation.

[0082] Figure 10 is a diagram showing a memory system 10 according to an embodiment of the present application.

[0083] Referring to Figure 10 , the memory system 10 can include a memory controller 100 and a semiconductor memory device 200. The semiconductor memory device 200 can include a plurality of memory cells (e.g., NAND flash memory cells) 210. The memory cells are arranged in an array arrangement of rows and columns as shown in Figure 3 Each cell in a row is connected to a word line (e.g., WL0), while each cell in a column is coupled to a bit line (e.g., BL0). These word lines and bit lines are used for read operations and write operations. During a write operation, data to be written (“1” or “0”) is provided at the bit line when the word line is asserted. During a read operation, the word line is again asserted and then the threshold voltage of each cell can be acquired from the bit line. Multiple pages can share memory cells belonging to (i.e., coupled to) the same word line. When the memory cells are implemented with MLC, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cells are implemented with TLC, the multiple pages include a MSB page, a center significant bit (CSB) page, and a LSB page. When the memory cells are implemented with QLC, the multiple pages include a MSB page, a center most significant bit (CMSB) page, a center least significant bit (CLSB) page, and a LSB page. The memory cells can be programmed using an encoding scheme (e.g., Gray coding) to increase the capacity of the memory system 10 such as an SSD.

[0084] The memory controller 100 can include a read processor 1010, a decoder 1020, and an optimal read threshold determiner 1030. Although these components of the memory controller 100 are shown as being implemented separately, one or more of these components can be implemented as an internal component (i.e., firmware (FW)) of the control component 120 in Figure 2 Although not shown in Figure 10 , the memory controller 100 and the semiconductor memory device 200 can include various other components as shown in Figure 2 .

[0085] The read processor 1010 can control one or more read operations to the semiconductor memory device 200 in response to a read request from a host (e.g., the host device 5 of Figure 1 ). The read processor 1010 can control the read operations using various read thresholds. The decoder 1020 can decode data associated with the read operations.

[0086] In some embodiments, the read processor 1010 can control read operations to memory cells using a selected read threshold from a set of read levels. In some embodiments, the set of read levels can include a plurality of read thresholds, one of which can be a default read threshold. The selected read threshold can be any one of the plurality of read thresholds in the set of read levels. When performing read operations to MSB pages of TLC, a first read threshold and a second read threshold [VT0, VT4] as shown in Figure 6B may be selected. The first read threshold VT0 is used to distinguish between an erased state (i.e., E) and a first programmed state (i.e., PV1), and the second read threshold VT4 is used to distinguish between a fourth programmed state (i.e., PV4) and a fifth programmed state (i.e., PV5). When performing read operations to LSB pages of TLC, a first read threshold and a second read threshold [VT2, VT6] as shown in Figure 6B may be selected. The first read threshold VT2 is used to distinguish between a second programmed state (i.e., PV2) and a third programmed state (i.e., PV3), and the second read threshold VT6 is used to distinguish between a sixth programmed state (i.e., PV6) and a seventh programmed state (i.e., PV7).

[0087] Depending on the decoding results of the decoder 1020, it can be determined whether the read operation using the selected read threshold from the set of read thresholds is successful or failed. When the read operation using the selected read threshold fails, the read processor 1010 can control one or more read retry operations to the memory cells using a read retry threshold as shown in Figure 7 .

[0088] The optimal read threshold determiner 1030 can provide a parameterized framework for programming voltage or program verify (PV) level modeling and optimal read threshold voltage (Vt) estimation. The optimal read threshold determiner 1030 can be implemented with one or more deep neural networks (DNNs). For a parameterized DNN framework, the optimal read threshold determiner 1030 can include a training component 1030A and an inference component 1030B.

[0089] Figure 11 is a diagram illustrating an example of a neural network 1100 according to an embodiment of the application. In some embodiments, the neural network 1100 can be included in a memory controller 100 of a memory system 10 in Figure 10 .

[0090] Referring to Figure 11 A feature map 1102 associated with one or more input conditions can be input to the neural network 1100. The feature map 1102 includes one or more features associated with the one or more input conditions. The neural network 1100 uses the feature map 1102 to generate and output information 1104. As shown, the neural network 1100 includes an input layer 1110, one or more hidden layers 1120, and an output layer 1130. Features from the feature map 1102 can be connected to input nodes in the input layer 1110. The information 1104 can be generated from output nodes of the output layer 1130. One or more hidden layers 1120 can exist between the input layer 1110 and the output layer 1130. The neural network 1100 can be pre-trained to process features from the feature map 1102 through the different layers 1110, 1120, and 1130 to output the information 1104.

[0091] The neural network 1100 can be a multi-layer neural network that represents a network of interconnected nodes, such as an artificial deep neural network, where knowledge about the nodes (e.g., information about particular features represented by the nodes) is shared across layers and knowledge is also retained for each layer. Each node represents a piece of information. Knowledge can be exchanged between nodes through node-to-node interconnections. An input to the neural network 1100 can activate a set of nodes. This set of nodes can in turn activate other nodes, propagating knowledge about the input. This process of activation can be repeated on other nodes until nodes in the output layer 1130 are selected and activated.

[0092] As shown, the neural network 1100 includes a hierarchy of layers, which represents a hierarchy of layers of nodes interconnected in a feed-forward manner. An input layer 1110 can exist at the lowest level. The input layer 1110 can include a set of nodes referred to herein as input nodes. When a feature map 1102 is input to the neural network 1100, each of the input nodes of the input layer 1110 can be connected to each feature of the feature map 1102. Each of the connections can have a weight, each of which is derived from a training of the neural network 1100. The weights represent a set of parameters of the neural network 1100. The input nodes can transform the features by applying an activation function to the features. Information derived from the transformation can be passed to nodes at a higher level of the hierarchy.

[0093] An output layer 1130 can exist at the highest level. The output layer 1130 can include one or more output nodes. When the output layer 1130 outputs an output information 1104, each of the output nodes can provide a specific value of the output information 1104. Examples of the output information 1104 and the specific values of the output information 1104 are described below. The number of output nodes depends on how many specific values of the output information 1104 are needed. In other words, there is a one-to-one correspondence or mapping between the number of output nodes and the number of values or strips of the output information.

[0094] A hidden layer 1120 can exist between the input layer 1110 and the output layer 1130. There can be N hidden layers 1120, where “N” is an integer greater than or equal to 1. Each of the hidden layers 1120 can include a set of nodes referred to herein as hidden nodes. Example hidden layers can include an up-sampling layer, a convolutional layer, a fully connected layer, and / or a data transformation layer.

[0095] At the lowest level of the hidden layers 1120, the hidden nodes of the layer can be interconnected with the input nodes. At the highest level of the hidden layers 1120, the hidden nodes of the layer can be interconnected with the output nodes. The input nodes can not be directly interconnected with the output nodes. If there are multiple hidden layers, the input nodes are interconnected with the hidden nodes of the lowest hidden layer. In turn, these hidden nodes are interconnected with the hidden nodes of the next hidden layer. An interconnection can represent a piece of information learned about two interconnected nodes. The interconnection can have a numerical weight that can be adjusted (e.g., based on a training data set) so that the neural network 1100 adapts to the input and is able to learn.

[0096] Typically, hidden layer 1120 allows knowledge about the input nodes of input layer 1110 to be shared among the output nodes of output layer 1130. For this purpose, a transformation f can be applied to the input nodes via hidden layer 1120. In this example, the transformation f is non-linear. Different non-linear transformations f, including, for example, the rectifier function f(x) = max(0,x), are available. In this example, a specific non-linear transformation f is selected based on cross-validation.

[0097] For example, neural network 1100 can be a deep learning neural network for a memory system including a NAND flash memory device. A deep learning neural network can be created using "K" input nodes and output nodes, where "K" is the number of factors (e.g., features) defining the input conditions for the memory system. The output nodes (multiple) can be used to execute activation functions for specific combinations of the input conditions. The number of layers in neural network 1100 and the size of each layer can depend on the NAND flash memory device and the amount of data that the memory can store.

[0098] The inventors observed that in some cases (e.g., Figure 9A The curves indicated by PV26 and PV27 in the figure, the cell level distribution corresponding to a specific threshold voltage range of PV levels, can be modeled using a skewed normal distribution. Typically, a skewed normal distribution is defined as a continuous probability distribution that generalizes the normal distribution to allow for non-zero skew. Each cumulative distribution function (CDF) value can represent a skewed normal distribution model for a specific PV level. To describe the characteristics of a skewed normal distribution, probability distribution parameters can include position ξ, scale ω, and shape α, which can be collectively referred to as a set of parameters.

[0099] In some embodiments, the neural network 1100 can be Figure 12 and / or Figure 13 The system can be configured with either a first deep neural network (DNN1) or a second deep neural network (DNN2). As input, DNN1 can receive one or more CDF values ​​of the sample corresponding to the reading operation and can output probability distribution parameters as output information 1104. For example, neural network 1100 (e.g., DNN1) can be pre-trained to process features (e.g., CDF values) from feature map 1102 through different layers 1110, 1120, and 1130 to output probability distribution parameters 1104. As input, DNN2 can receive one or more probability distribution parameters and output probability density function (PDF) values ​​as output information 1104.

[0100] Figure 12 This is a diagram illustrating a training component 1030A according to an embodiment of the present invention.

[0101] Referring Figure 12 To train the first deep neural network (DNN1) 1200, a synthetic dataset (or data) can be collected by the synthetic model 1210. The synthetic dataset can be arbitrary production data that is suitable for a given situation but not obtained from a memory device (e.g., a NAND flash memory device) by direct measurement. In some embodiments, the deep neural network 1200 can be used for a memory system including a NAND flash memory device. As described above, the threshold voltage (Vt) distribution (i.e., PV level) of a memory cell can be modeled by a parametric distribution (i.e., skew-normal distribution). The skew-normal distribution is characterized by a cumulative distribution function (CDF), as shown below:

[0102]

[0103]

[0104] T(h, a) is Owen's T function.

[0105] As expressed in the above equation, the skew-normal distribution has 3 parameters, i.e., location ξ, scale ω, and shape a. In other words, for a read threshold voltage range corresponding to each PV level, 3 probability distribution parameters can be used to describe the probability distribution of each PV level. In the above equation, x represents a sampled read threshold voltage (i.e., PV level) and T(h, a) defines Owen's T function.

[0106] The synthetic model 1210 can generate a synthetic dataset (x, CDF(x)) based on a probability distribution parameter p collectively representing the 3 parameters (i.e., ξ, ω, and a). The DNN1 1200 can be trained on the synthetic dataset including CDF values CDF(x) of the parametric distribution at various sampled voltages x, and output a probability distribution parameter p' as a training result. The probability distribution parameter p' can be used to determine the characteristics of the voltage range curve of a memory cell.

[0107] The training result generated by the DNN1 1200 can be provided to a loss function component 1220. The loss function component 1220 can use a loss function (or cost function) to find an optimal solution for the trained probability distribution parameter p'. The DNN1 1200 can be trained to improve the probability distribution parameter such that a difference (or error) between the actual probability distribution parameter p of the synthetic model 1210 and the probability distribution parameter p' predicted by the DNN1 1200 is minimized.

[0108] Thus, the relationship between the CDF value CDF(x) and the probability distribution parameter Θ can be trained by the DNN1 1200. Once trained, the inference component 1030B can use the training results.

[0109] Figure 13 is a diagram illustrating an inference component 1030B according to an embodiment of the application.

[0110] Referring to Figure 13 , the inference component 1030B can include a first deep neural network (DNN1) 1200A, 1200B, a second deep neural network (DNN2) 1300A, 1300B, and a crosspoint computation component 1310. Each DNN1 1200A, 1200B can be trained as shown in Figure 12 Each of the DNN1 and DNN2 can be implemented in an SoC or FW depending on the size of the DNN used.

[0111] In Figure 13 , PV A and PV B (e.g., 1502 and 1504 in Figure 15 ) represent two adjacent PV voltage levels. CDF A (x i ) represents the CDF value of the PV i at the threshold voltage distribution sampled at voltage x A . CDF B (x i ) represents the CDF value of the PV i at the threshold voltage distribution sampled at voltage x B . p A represents the probability distribution parameter of the PV A . p B represents the probability distribution parameter of the PV B . The optimal read threshold voltage Vt_opt represents the crosspoint voltage between the threshold voltage distributions of the PV A and the PV B .

[0112] The threshold voltage distribution of a cell at a PV level can be modeled by a parametric distribution (i.e., a skewed normal distribution). The parametric distribution models the relationship between the CDF value and the probability distribution parameter p for each PV level. PV A and PV B are modeled by the probability distribution parameters p A and p B , respectively.

[0113] For n-bit multi-level cell NAND flash memory, the threshold voltage of each cell can be programmed to 2 n possible values. In ideal multi-level cell NAND flash memory, each value falls into a non-overlapping threshold voltage range. However, in many systems, due to operating conditions, adjacent threshold voltage ranges for individual values can partially overlap. An example of such overlap is shown in Figure 8 to Figure 9B .

[0114] DNN1 1200A can receive a first CDF value CDF A (x i ) representing a skewed normal distribution model of a first threshold voltage range. The first CDF value CDF A (x i ) can be generated by iterative modeling to determine a parametric representation of the threshold voltage range, as shown in Figure 12 . The first CDF value CDF A (x i ) can correspond to a first level of a multi-level cell NAND flash memory. Each multi-level cell has multiple levels based on how many bits are stored in the cell. In one example, a triple-level cell (TLC) stores three bits and has 2 n levels, or eight levels. Each of the eight levels of a three-bit TLC corresponds to a range of voltages that can be represented by the first CDF value CDF A (x i ). DNN1 1200B can receive a second CDF value CDF B (x i ) representing a skewed normal distribution model of a second threshold voltage range. The second CDF value CDF B (x i ) can correspond to a second level of a multi-level cell.

[0115] Each DNN1 1200A, 1200B can estimate a probability distribution parameter p based on a CDF value given by measurements of a memory cell. For example, DNN1 1200A can estimate a probability distribution parameter p A based on the first CDF value CDF i (x A ). DNN1 1200B can estimate a probability distribution parameter p B based on the second CDF sample CDF i (x B ). The probability distribution parameter is represented as p A = (ξ A , ω A , α A ) and p B= (ξ B , ω B , α B ).

[0116] Each DNN2 1300A, 1300B can determine a PDF value of the distribution of individual candidate read threshold voltages based on the estimated probability distribution parameters p. For example, DNN2 1300A can receive the estimated probability distribution parameters p A and determine a PDF value PDF A based on the estimated probability distribution parameters p A . DNN2 1300B can receive the estimated probability distribution parameters p B and determine a PDF value PDF B based on the estimated probability distribution parameters p B . In some embodiments, each DNN2 1300A, 1300B can determine a PDF value of the distribution of individual candidate read threshold voltages based on the estimated probability distribution parameters p by using the following equation:

[0117] where ξ represents location, ω denotes scale and α stands for shape, which are the probability distribution parameters p.

[0118] In some embodiments, each DNN2 1300A, 1300B can include a lookup table (LUT) storing the relationship between the probability distribution parameters and the PDF values.

[0119] The intersection computing component 1310 can find two candidate read threshold voltages that produce approximately equal PDF values. Further, the intersection computing component 1310 can determine the intersection of the two candidate read threshold voltages as the optimal read threshold voltage Vt opt.

[0120] As such, the inference component 1030B can estimate the intersection (crosspoint) of the underlying PDF values based on several noisy samples of the CDF values.

[0121] Figure 14 An operation of obtaining ICMF samples for estimating an optimal read threshold voltage according to an embodiment of the present application is illustrated. The operation can be performed by the read processor 1010 of the memory controller 100 in Figure 10 . For example, the ICMF samples can be obtained to estimate the optimal read threshold voltage for the LSB page of the TLC.

[0122] In Figure 14 , 1410 represents a parameter distribution corresponding to the threshold voltage distribution of the PV levels of the TLC, as Figure 6AThe distribution of the TLC includes eight zones, as shown, including Zone 0 through Zone 7 and each zone corresponds to a program state or PV level.

[0123] At operation S1410, the memory controller 100 can read the LSB page, the MSB page, and the CSB page to generate a PV state count. Further, the memory controller 100 can generate a first ICMF sample set for PV 2, PV 3, PV 6, PV 7 based on the PV state count. Here, ICMF denotes an inverse of a cumulative mass function (CMF). In some embodiments, for each read threshold voltage, a cumulative mass function (CMF) value can be determined based on a number of cells (cell count) and a number of particular binary values (1 or 0) among the cells that are associated with a read operation using each read threshold voltage. For example, each CMF value can be determined as {number of 1s or 0s (e.g., 1) / cell count}, i.e., a percentage of 1s or 0s.

[0124] 1420 denotes the first ICMF sample set for PV 2, PV 3, PV 6, PV 7 generated at S1410. The samples for each page in the first ICMF sample set are generated from the parametric distribution at the respective read threshold voltages. In the example shown, for the MSB page, ICMF samples are generated at read threshold voltages Vt0, Vt4. The ICMF sample at read threshold voltage Vt0 includes 75% of 1s and 25% of 0s, while the ICMF sample at read threshold voltage Vt4 includes 80% of 1s and 20% of 0s. For the CSB page, ICMF samples are generated at read threshold voltages Vt1, Vt3, Vt5. The ICMF sample at read threshold voltage Vt1 includes 10% of 1s and 90% of 0s, the ICMF sample at read threshold voltage Vt3 includes 30% of 0s and 70% of 1s, and the ICMF sample at read threshold voltage Vt5 includes 30% of 1s and 70% of 0s. For the LSB page, ICMF samples are generated at read threshold voltages Vt2, Vt6. The ICMF sample at read threshold voltage Vt2 includes 40% of 1s and 60% of 0s, while the ICMF sample at read threshold voltage Vt6 includes 40% of 0s and 60% of 1s.

[0125] At operation S1420, the memory controller 100 can read one or more LSB pages and CSB pages to generate the second and third ICMF sample sets for PV 2, PV 3, PV 6, PV 7. In the illustrated embodiment, 2 LSB pages and a CSB page can be read in 1430. This embodiment considers a skewed normal model (SNM) based distribution. The number of LSB pages and CSB pages to be read can vary depending on the distribution model. For a distribution of an improved Gaussian model (IGM), 1 LSB page and a CSB page can be read. For a distribution of a non-central model (NCTM), 3 LSB pages and a CSB page can be read.

[0126] 1430 represents the second and third ICMF sample sets for PV 2, PV 3, PV 6, PV 7 generated at S1420. The samples for each page in the second ICMF sample set are generated from the parametric distribution at the respective read threshold voltages. In the illustrated example, for the CSB page, ICMF samples are generated at read threshold voltages Vt'3, Vt'5. For the LSB pages, ICMF samples are generated at read threshold voltages Vt'2, Vt'6. The samples for each page in the third ICMF sample set are generated from the parametric distribution at the respective read threshold voltages. In the illustrated example, for the CSB page, ICMF samples are generated at read threshold voltages Vt”3, Vt”5. For the LSB pages, ICMF samples are generated at read threshold voltages Vt”2, Vt”6. Although not shown, each ICMF sample in the second and third ICMF sample sets indicates a percentage of 0 and a percentage of 1.

[0127] As such, operations S1410 and S1420 are performed to estimate the distribution of a particular page (i.e., the LSB page) and to eliminate other components (e.g., noise). At operation S1430, the memory controller 100 can provide the ICMF samples to the DNN1 1200A, 1200B to estimate the optimal read threshold voltage. In some embodiments, CDF values corresponding to the ICMF samples (or CMF samples) can be provided to the DNN1 1200A, 1200B, as shown. Figure 13

[0128] Figure 15 A chart 1500 illustrating example voltage read thresholds generated according to embodiments of the present application is shown.

[0129] Referring to Figure 15 ​In the illustrated example, the first curve 1502 and the second curve 1504 depict a log function of the probability distribution parameters p = (ξ, ω, α) over the two voltage ranges. Each of the first voltage range 1508 and the second voltage range 1510 is modeled by a set of skewed normal distribution parameters, which is shown in the legend of the chart 1500. Figure 15 In the illustrated example, the first curve 1502 and the second curve 1504 depict a log function of the probability distribution parameters p = (ξ, ω, α) over the two voltage ranges. Each of the first voltage range 1508 and the second voltage range 1510 is modeled by a set of skewed normal distribution parameters, which is shown in the legend of the chart 1500.

[0130] As described above, embodiments provide a scheme for parametric PV level modeling and optimal read threshold voltage estimation. Embodiments model the threshold voltage distribution of a memory cell as a parametric distribution (i.e., a skewed normal distribution) and estimate the optimal read threshold voltage based on the parametric distribution. Thus, embodiments improve the reliability of read operations for arbitrary PV-like states that are asymmetric and have heavier tails.

[0131] While the forgoing embodiments have been described in some detail for purposes of clarity and the known illustration, it will be appreciated by those skilled in the art that various alternatives to the embodiments described herein can be employed in accordance with the teachings of the present application without departing from the scope of the present application. Accordingly, the disclosed embodiments are illustrative and not restrictive. The application is intended to include all modifications and alternatives coming within the scope of the following claims.

Claims

1. A memory system, comprising: A memory device comprising multiple cells; as well as Controller, the controller: The read operation is performed on the plurality of units using multiple read threshold voltages; Based on the results of the read operation, a cumulative quality function sample, namely a CMF sample, is generated, wherein each CMF sample has a percentage of 1 or 0 of the data stored in the plurality of cells; Receive a first cumulative distribution function value, i.e., a first CDF value, and a second cumulative distribution function value, i.e., a second CDF value, selected from a plurality of CDF values ​​corresponding to the CMF sample, wherein each of the first CDF value and the second CDF value represents a skewed normal distribution; Estimate the first probability distribution parameter set and the second probability distribution parameter set corresponding to the first CDF value and the second CDF value, respectively; The first probability distribution parameter set and the second probability distribution parameter set are used respectively to determine the first probability density function value (i.e., the first PDF value) and the second probability density function value (i.e., the second PDF value) corresponding to the first CDF value and the second CDF value, respectively; and The estimated read threshold voltage corresponding to the intersection of the first PDF value and the second PDF value is used as the optimal read threshold voltage.

2. The memory system of claim 1, wherein the controller further uses the optimal read threshold voltage to perform a next read operation on the plurality of cells.

3. The memory system of claim 1, wherein each of the first probability distribution parameter set and the second probability distribution parameter set includes the position, scale, and shape of a curve associated with the skewed normal distribution.

4. The memory system of claim 1, wherein each of the first probability distribution parameter set and the second probability distribution parameter set is estimated by a neural network, the neural network being trained to output a plurality of probability distribution parameter sets corresponding to a plurality of CDF values, respectively.

5. The memory system of claim 4, wherein the neural network is trained to receive each of the plurality of CDF values ​​and to output each of the plurality of probability distribution parameter sets based on a synthetic model.

6. The memory system of claim 1, wherein each of the first PDF value and the second PDF value is determined by a neural network trained to receive the first probability distribution parameter set and the second probability distribution parameter set and output the first PDF value and the second PDF value corresponding to the first probability distribution parameter set and the second probability distribution parameter set, respectively.

7. The memory system of claim 1, wherein the first PDF value of the intersection is the same as the second PDF value.

8. The memory system of claim 7, wherein the optimal read threshold voltage corresponds to the intersection of a first read threshold voltage having the first PDF value and a second read threshold voltage having the second PDF value.

9. A method of operating a memory system, the memory system comprising a memory device and a controller, the memory device comprising a plurality of cells, the method comprising: performing a read operation on the plurality of cells using a plurality of read threshold voltages; generating cumulative mass function samples (CMF samples) based on results of the read operation, wherein each CMF sample has a percentage of 1s or Os of data stored in the plurality of cells; receiving a first cumulative distribution function value (first CDF value) and a second cumulative distribution function value (second CDF value) selected from among a plurality of CDF values corresponding to the CMF samples, each of the first and second CDF values representing a skewed normal distribution; estimating a first set of probability distribution parameters and a second set of probability distribution parameters corresponding to the first and second CDF values, respectively; determining a first probability density function value (first PDF value) and a second probability density function value (second PDF value) corresponding to the first and second CDF values, respectively, using the first and second sets of probability distribution parameters, respectively; and estimating a read threshold voltage corresponding to a crossing point of the first and second PDF values as an optimal read threshold voltage.

10. The method of claim 9, further comprising: performing a next read operation on the plurality of cells using the optimal read threshold voltage.

11. The method of claim 9, wherein each of the first and second sets of probability distribution parameters comprises a location, a scale, and a shape of a curve associated with the skewed normal distribution.

12. The method of claim 9, wherein each of the first and second sets of probability distribution parameters is estimated by a neural network trained to output a plurality of sets of probability distribution parameters corresponding to a plurality of CDF values, respectively.

13. The method of claim 12, wherein the neural network is trained to receive each of the plurality of CDF values and output each of the plurality of sets of probability distribution parameters based on a synthetic model.

14. The method of claim 9, wherein each of the first and second PDF values is determined by a neural network trained to receive the first and second sets of probability distribution parameters and output the first and second PDF values corresponding to the first and second sets of probability distribution parameters, respectively.

15. The method of claim 9, wherein the first PDF value of the crossing point is the same as the second PDF value.

16. The method of claim 15, wherein the optimal read threshold voltage corresponds to a crossing point of a first read threshold voltage having the first PDF value and a second read threshold voltage having the second PDF value.

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