Information detection method and device, and electronic device

Abstract

The present disclosure relates to an information detection method and device, electronic equipment and computer readable storage medium, and belongs to the technical field of semiconductor production and manufacturing, and can be applied to the scene of detecting the authenticity of SPD information in a DRAM memory bank. The method comprises: obtaining a to-be-detected memory, and determining a memory parameter corresponding to the to-be-detected memory; the memory parameter is obtained based on at least one of an operation code and a test vector; obtaining a chip record parameter from a detection chip corresponding to the to-be-detected memory; comparing the memory parameter and the chip record parameter for consistency to obtain a comparison result, so as to determine the authenticity of the chip record parameter according to the comparison result. The present disclosure can detect whether the SPD information in the DRAM memory bank is real.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor production and manufacturing, and particularly relates to an information detection method, an information detection device and an electronic device. BACKGROUND

[0002] Currently, a serial presence detect (SPD) chip is installed on a dynamic random access memory (DRAM) memory bar, and the SPD chip records many important information of the memory, such as chip and module manufacturers, working frequency, working voltage and other parameters of the memory.

[0003] The SPD information is generally written into the SPD chip by the memory module manufacturer according to the actual performance of the DRAM chip before leaving the factory. When starting the computer, the basic input output system (BIOS) of the motherboard will configure the memory working timing and control register according to the parameters in the SPD, so as to fully exert the performance of the memory bar. However, the parameter information in the SPD can be modified by a tool, which will lead to the fact that the real memory information cannot be queried in actual use.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present disclosure is to provide an information detection method, an information detection device, an electronic device and a computer readable storage medium, so as to at least partially overcome the problem that the SPD information in the DRAM memory bar cannot be detected whether it is real or not.

[0006] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0007] According to a first aspect of the present disclosure, an information detection method is provided, comprising: obtaining a to-be-detected memory, and determining a memory parameter corresponding to the to-be-detected memory; the memory parameter is obtained based on at least one of an operation code and a test vector; obtaining a chip record parameter from a detection chip corresponding to the to-be-detected memory; comparing the memory parameter and the chip record parameter for consistency, obtaining a comparison result, and determining the authenticity of the chip record parameter according to the comparison result.

[0008] In an example embodiment of the present disclosure, the memory parameter includes a first memory parameter, and the determining the memory parameter corresponding to the to-be-detected memory includes: detecting a power-on state of a device system board; in response to detecting that the power-on state is a powered-on state, generating the operation code; reading the first memory parameter from the to-be-detected memory through the operation code; and the first memory parameter includes manufacturer information and capacity information of the to-be-detected memory.

[0009] In an example embodiment of the present disclosure, the memory parameter further includes a second memory parameter, and the determining the memory parameter corresponding to the to-be-detected memory includes: generating a test vector for obtaining the memory parameter; performing a data read-write operation on the to-be-detected memory based on the test vector, and determining the second memory parameter according to a data read-write result.

[0010] In an example embodiment of the present disclosure, the second memory parameter includes a working frequency, and the performing a data read-write operation on the to-be-detected memory based on the test vector and determining the second memory parameter according to a data read-write result includes: obtaining an initial working frequency vector, writing a register parameter in the initial working frequency vector to obtain a working frequency vector; the register parameter includes a candidate working frequency of the to-be-detected memory; writing first test data into the to-be-detected memory based on the working frequency vector; reading the written first test data from the to-be-detected memory as first read-out data based on a candidate working frequency corresponding to a data write operation; and taking a candidate working frequency that is consistent between the first read-out data and the first test data as a target working frequency.

[0011] In an example embodiment of the present disclosure, the writing first test data into the to-be-detected memory based on the working frequency vector includes: sending an activation command based on the working frequency vector, sending a data write command after a first time interval; sending the first test data to the to-be-detected memory, and writing the first test data into a specific position of the to-be-detected memory one by one after a second time interval; in response to a write completion event of a current row in the to-be-detected memory, sending a pre-charge command and a refresh command; performing a data write operation on a next row of the current row until all rows and all columns of the to-be-detected memory have been written with the first test data.

[0012] In an example embodiment of the present disclosure, the reading of the first test data written in the to-be-detected memory as the first readout data based on the candidate working frequency corresponding to the data write operation comprises: sending an activation command based on the candidate working frequency, sending a data read command after a first time interval; reading the first test data from a current data row in the to-be-detected memory after a third time interval; sending a pre-charge command after a third time interval in response to a read completion event of the current data row; repeating the data read operation for the data row until all the first test data in the to-be-detected memory is read, obtaining the first readout data.

[0013] In an example embodiment of the present disclosure, the second memory parameter comprises a memory refresh time, and the data read / write operation on the to-be-detected memory based on the test vector and the determination of the second memory parameter according to the data read / write result comprise: obtaining an initial refresh time vector, writing a register parameter in the initial refresh time vector to obtain a refresh time vector; the register parameter comprises a candidate refresh time value, and the candidate refresh time value is determined based on a memory capacity; writing second test data into the to-be-detected memory based on the refresh time vector; reading the written second test data from the to-be-detected memory as second readout data; adjusting the currently configured candidate refresh time value and determining the data read / write result corresponding to different candidate refresh time values; determining the target refresh time value according to the candidate refresh time value in which the second readout data is consistent with the second test data.

[0014] In an example embodiment of the present disclosure, the writing of the second test data into the to-be-detected memory based on the refresh time vector comprises: sending an activation command based on the refresh time vector, sending a data write command after a first time interval; sending the second test data to the to-be-detected memory and writing the second test data into a specific position in the to-be-detected memory one by one after a second time interval; sending a pre-charge command and a refresh command in response to a write completion event of a current memory bank of the to-be-detected memory.

[0015] In an example embodiment of the present disclosure, the reading of the written second test data from the to-be-detected memory as the second readout data comprises: sending an activation command based on the refresh time vector, sending a data read command after a first time interval; reading the written second test data from a current data row of the to-be-detected memory after a third time interval; obtaining the second readout data in response to a read completion event of all data rows in the to-be-detected memory; sending a pre-charge command after a fourth time interval.

[0016] In an example embodiment of the present disclosure, the second memory parameter comprises an instruction response interval time, the data read-write operation on the to-be-tested memory based on the test vector, and the determination of the second memory parameter according to the data read-write result comprises: obtaining an initial response interval time vector, writing a register parameter in the initial response interval time vector to obtain a response interval time vector; the register parameter comprises a response interval time value; writing third test data into the to-be-tested memory based on the response interval time vector; performing a self-refresh configuration operation based on a clock cycle, updating a current response interval time value through the self-refresh configuration operation; reading the written third test data from the to-be-tested memory as third readout data by using different response interval time values; and determining a target response interval time value according to the response interval time value at which the third readout data is consistent with the third test data.

[0017] In an example embodiment of the present disclosure, the writing of the third test data into the to-be-tested memory based on the response interval time vector comprises: sending an activation command based on the response interval time vector, sending a data write command after a first time interval; sending the third test data to the to-be-tested memory, and writing the third test data into specific positions of the to-be-tested memory one by one after a second time interval; and sending a pre-charge command and a refresh command in response to a write completion event of all data rows of the to-be-tested memory.

[0018] In an example embodiment of the present disclosure, the reading of the written third test data from the to-be-tested memory as third readout data by using different response interval time values comprises: sending an activation command based on the response interval time vector, sending a data read command after a first time interval; reading the written third test data from the current data row of the to-be-tested memory after a third time interval; and obtaining the third readout data and sending a pre-charge command in response to a read completion event of all data rows in the to-be-tested memory.

[0019] In an example embodiment of the present disclosure, the method further comprises: if the comparison result is that the chip record parameter is inconsistent with the memory parameter, the chip record parameter is not a real memory parameter, determining that the memory parameter is sent to a corresponding input-output system chip of the to-be-tested memory; and if the comparison result is that the chip record parameter is consistent with the memory parameter, the chip record parameter is a real memory parameter, and a system board is started based on the chip record parameter.

[0020] According to a second aspect of the present disclosure, an information detection device is provided, comprising: a memory parameter determination module configured to determine a memory parameter corresponding to a memory to be detected; the memory parameter is obtained based on at least one of an operation code and a test vector; a chip parameter acquisition module configured to acquire a chip record parameter from a detection chip corresponding to the memory to be detected; and a parameter comparison module configured to compare the memory parameter and the chip record parameter for consistency to obtain a comparison result, and determine the authenticity of the chip record parameter according to the comparison result.

[0021] In an exemplary embodiment of the present disclosure, the memory parameter comprises a first memory parameter, and the memory parameter determination module comprises a first parameter determination module configured to detect a power-on state of a device system board; generate the operation code in response to detecting that the power-on state is a powered-on state; read the first memory parameter from the memory to be detected through the operation code; and the first memory parameter comprises manufacturer information and capacity information of the memory to be detected.

[0022] In an exemplary embodiment of the present disclosure, the memory parameter further comprises a second memory parameter, and the memory parameter determination module further comprises a second parameter determination module configured to generate a test vector for acquiring the memory parameter; perform a data read-write operation on the memory to be detected based on the test vector, and determine the second memory parameter according to a data read-write result.

[0023] In an exemplary embodiment of the present disclosure, the second memory parameter comprises a working frequency, and the second parameter determination module comprises a frequency parameter determination unit configured to acquire an initial working frequency vector, write a register parameter in the initial working frequency vector to obtain a working frequency vector; the register parameter comprises a candidate working frequency of the memory to be detected; write first test data into the memory to be detected based on the working frequency vector; read the first test data that has been written from the memory to be detected based on a candidate working frequency corresponding to a data write operation, as first read-out data; and take a candidate working frequency that is consistent between the first read-out data and the first test data as a target working frequency.

[0024] In an example embodiment of the present disclosure, the frequency parameter determination unit comprises a first data write subunit, which is configured to send an activation command based on the working frequency vector, send a data write command after a first time interval, send the first test data to the to-be-detected memory, and write the first test data to specific positions in the to-be-detected memory one by one after a second time interval, send a pre-charge command and a refresh command in response to a write completion event of a current row in the to-be-detected memory, and perform a data write operation on a next row of the current row until all rows and all columns of the to-be-detected memory have been written with the first test data.

[0025] In an example embodiment of the present disclosure, the frequency parameter determination unit comprises a first data read subunit, which is configured to send an activation command based on the candidate working frequency, send a data read command after a first time interval, read the first test data from a current data row in the to-be-detected memory after a third time interval, send a pre-charge command after a third time interval in response to a read completion event of the current data row, and repeat a data read operation on a data row until all first test data in the to-be-detected memory have been read to obtain the first readout data.

[0026] In an example embodiment of the present disclosure, the second parameter determination module comprises a refresh time determination unit, which is configured to obtain an initial refresh time vector, write a register parameter in the initial refresh time vector to obtain a refresh time vector, the register parameter comprising a candidate refresh time value determined based on a memory capacity, write second test data into the to-be-detected memory based on the refresh time vector, read the written second test data from the to-be-detected memory as second readout data, adjust the currently configured candidate refresh time value, determine data read-write results corresponding to different candidate refresh time values, and determine the target refresh time value according to the candidate refresh time value under which the second readout data is consistent with the second test data.

[0027] In an example embodiment of the present disclosure, the refresh time determination unit comprises a second data write subunit, which is configured to send an activation command based on the refresh time vector, send a data write command after a first time interval, send the second test data to the to-be-detected memory, and write the second test data to specific positions in the to-be-detected memory one by one after a second time interval, and send a pre-charge command and a refresh command in response to a write completion event of a current memory bank of the to-be-detected memory.

[0028] In an example embodiment of the present disclosure, the refresh time determination unit comprises a second data reading subunit, configured to send an activate command based on the refresh time vector, send a data reading command after a first time interval, read the written second test data from a current data row of the to-be-tested memory after a third time interval, obtain the second readout data in response to a reading completion event of all data rows in the to-be-tested memory, and send a pre-charge command after a fourth time interval.

[0029] In an example embodiment of the present disclosure, the second memory parameter comprises an instruction response interval time, and the second parameter determination module comprises a response interval time determination unit, configured to obtain an initial response interval time vector, write a register parameter in the initial response interval time vector to obtain a response interval time vector, the register parameter comprising a response interval time value, write third test data into the to-be-tested memory based on the response interval time vector, perform a self-refresh configuration operation based on a clock cycle, update a current response interval time value through the self-refresh configuration operation, read the written third test data from the to-be-tested memory as third readout data using different response interval time values, and determine a target response interval time value according to the response interval time value at which the third readout data is consistent with the third test data.

[0030] In an example embodiment of the present disclosure, the response interval time determination unit comprises a third data writing subunit, configured to send an activate command based on the response interval time vector, send a data writing command after a first time interval, send the third test data to the to-be-tested memory, and write the third test data into specific positions of the to-be-tested memory one by one after a second time interval, and send a pre-charge command and a refresh command in response to a writing completion event of all data rows of the to-be-tested memory.

[0031] In an example embodiment of the present disclosure, the response interval time determination unit comprises a third data reading subunit, configured to send an activate command based on the response interval time vector, send a data reading command after a first time interval, read the written third test data from a current data row of the to-be-tested memory after a third time interval, obtain the third readout data in response to a reading completion event of all data rows in the to-be-tested memory, and send a pre-charge command.

[0032] In an example embodiment of the present disclosure, the information detection apparatus further comprises a parameter usage module configured to, if the comparison result is that the chip-recorded parameter is inconsistent with the memory parameter, determine that the chip-recorded parameter is not a real memory parameter, and send the memory parameter to the input-output system chip corresponding to the memory to be detected; and if the comparison result is that the chip-recorded parameter is consistent with the memory parameter, determine that the chip-recorded parameter is a real memory parameter, and start the system board based on the chip-recorded parameter.

[0033] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory having computer readable instructions stored thereon, the computer readable instructions being executed by the processor to implement the information detection method according to any one of the above.

[0034] According to a fourth aspect of the present disclosure, a computer readable storage medium is provided, having a computer program stored thereon, the computer program being executed by a processor to implement the information detection method according to any one of the above.

[0035] The technical solution provided by the present disclosure can include the following beneficial effects:

[0036] The information detection method in the example embodiment of the present disclosure compares the memory parameter obtained through the operation code or the test vector with the chip-recorded parameter directly obtained from the detection chip, and determines the authenticity of the chip-recorded parameter, and starts the system board based on the chip-recorded parameter in the detection chip.

[0037] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0038] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. It is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor. In the drawings:

[0039] Figure 1 A flowchart of an information detection method according to an example embodiment of the present disclosure is schematically shown;

[0040] Figure 2 A connection relationship diagram between a plurality of modules included in an execution subject of an information detection method according to an example embodiment of the present disclosure is schematically shown;

[0041] Figure 3 An overall flowchart of performing parameter authenticity detection according to an example embodiment of the present disclosure is schematically shown;

[0042] Figure 4 An overall flowchart of writing and reading first test data to a memory to be monitored according to an example embodiment of the present disclosure is schematically shown;

[0043] Figure 5 An overall flowchart of writing and reading second test data to a memory to be monitored according to an example embodiment of the present disclosure is schematically shown;

[0044] Figure 6 An overall flowchart of writing and reading third test data to a memory to be monitored according to an example embodiment of the present disclosure is schematically shown;

[0045] Figure 7 A block diagram of an information detection apparatus according to an example embodiment of the present disclosure is schematically shown;

[0046] Figure 8 A block diagram of an electronic device according to an example embodiment of the present disclosure is schematically shown;

[0047] Figure 9 A schematic diagram of a computer readable storage medium according to an example embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0048] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the several views.

[0049] Moreover, described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the techniques described can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the disclosure.

[0050] The block diagrams shown in the drawings are merely functional entities and do not necessarily have to correspond to physically independent entities. That is, the functional entities can be implemented in the form of software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0051] At present, DRAM memory sticks, such as Registered-Dual-Inline-Memory-Modules (RDIMM), Unregistered Dual-Inline-Memory-Modules (UDIMM) and Small Outline Dual-Inline-Memory-Modules (SODIMM) and the like, are all installed with an SPD chip, which is essentially an Electrically Erasable Programmable Read-Only Memory (EEPROM) chip.

[0052] When starting a computer, the motherboard BIOS reads the information in the memory SPD, and then automatically configures the corresponding memory working timing and control registers according to these parameters, so as to fully exert the performance of the memory stick. However, the parameter information in the SPD can be modified by a tool. For example, a DRAM memory chip can only support a working frequency of 2933Mhz, but the parameter in the SPD shows that the DRAM chip can support a working frequency of 3200Mhz. When the BIOS reads the SPD information, it will work at a working frequency of 3200Mhz, which will cause the motherboard to not boot or work unstably.

[0053] Based on this, in the present example embodiment, first, an information detection method is provided, which can be implemented by a server or a terminal device. The terminal described in the present disclosure can include mobile terminals such as mobile phones, tablet computers, notebook computers, palmtop computers, Personal Digital Assistants (PDAs), and the like, as well as fixed terminals such as desktop computers. Figure 1 A schematic diagram of the information detection method flow according to some embodiments of the present disclosure is shown schematically. Referring to Figure 1 The information detection method can include the following steps:

[0054] In step S110, the memory to be detected is acquired, and the memory parameter corresponding to the memory to be detected is determined; the memory parameter is obtained based on at least one of an operation code and a test vector;

[0055] In step S120, the chip record parameter is acquired from the detection chip corresponding to the memory to be detected;

[0056] In step S130, the memory parameter and the chip record parameter are compared for consistency, and a comparison result is obtained, so as to determine the authenticity of the chip record parameter according to the comparison result.

[0057] According to the information detection method in the example embodiment, the memory parameter obtained through the operation code or the test vector is compared with the chip record parameter directly acquired from the detection chip for consistency, so as to determine the authenticity of the chip record parameter, and the system board is started based on the chip record parameter in the detection chip.

[0058] In the following, the information detection method in the example embodiment will be further described.

[0059] In step S110, the memory to be detected is acquired, and the memory parameter corresponding to the memory to be detected is determined; the memory parameter is obtained based on at least one of an operation code and a test vector;

[0060] In some example embodiments of the disclosure, the memory to be detected can be a memory waiting for parameter detection. The memory parameter can be a real memory parameter obtained from the memory to be detected itself based on the operation code and the test vector. The operation code can be a parameter acquisition code adopted by an execution subject of the information detection method to acquire the first memory parameter from the memory to be detected. The test vector can be a vector containing the timing characteristics of the test memory. In a narrow sense, the test vector is a truth table of the memory chip.

[0061] The information detection method of the disclosure aims to detect whether the SPD memory information in the DRAM memory is real, and reference Figure 2 , Figure 2 The connection relationship diagram between a plurality of modules included in an execution subject of the information detection method according to the example embodiments of the disclosure is schematically shown. The execution subject of the method (i.e., the information detection subject 210) can include a master control module 211, a storage module 212, a power supply module 213, a display module 214, and a buzzer 215, and is directly connected to a system board (i.e., a mainboard). When the memory to be detected is acquired, the information detection subject 210 can determine the memory parameter corresponding to the memory to be detected through the operation code or the test vector.

[0062] In an example embodiment of the present disclosure, a power-on state of a detection device system board is detected; an operation code is generated in response to detecting that the power-on state is a powered-on state; a first memory parameter is read from a to-be-detected memory by the operation code; and the first memory parameter includes manufacturer information and capacity information of the to-be-detected memory.

[0063] The device system board can be a mainboard of a device used by the information detection method execution subject. The power-on state can be a specific state of whether the device system board is powered on. The powered-on state is a state in which the device system board is powered on. The first memory parameter can be manufacturer information and capacity information of the to-be-detected memory, and the like. The manufacturer information can be related information of a manufacturer of the to-be-detected memory. The capacity information can be related information of a capacity size of the to-be-detected memory.

[0064] According to the overall connection structure of the information detection subject, it can be known that the information detection subject is directly connected to the mainboard of the computer device. When determining the first memory parameter of the to-be-detected memory, the power-on state of the system board of the computer device can be detected first. Referring to Figure 3 , Figure 3 An overall flowchart of performing parameter authenticity detection according to an example embodiment of the present disclosure is schematically shown. In Figure 3 If it is detected that the power-on state of the system board of the detection device is a powered-on state, it means that the system board of the detection device has been powered on, and at this time, the information detection subject 210 can generate an operation code (Operation Code) for obtaining a first memory parameter, and the host module obtains the production manufacturer and storage capacity of the to-be-detected memory (i.e., a DRAM particle) through the Operation Code 310.

[0065] In an example embodiment of the present disclosure, a test vector for obtaining a memory parameter is generated; a data read-write operation is performed on a to-be-detected memory based on the test vector, and a second memory parameter is determined according to a data read-write result.

[0066] The data read-write result can be a consistency comparison result of the written data and the read data after performing a data write operation and a data read operation on the to-be-detected memory. The second memory parameter can be a core timing parameter of the memory. The second memory parameter can be a real parameter of the to-be-detected memory determined based on the test vector. For example, the second memory parameter can include a working frequency, a memory refresh time, and an instruction response interval time, and the like.

[0067] Since the to-be-detected memory also includes a core timing parameter (Core Timing), a working frequency, and the like, which are second memory parameters, these second memory parameters cannot be directly obtained and can be obtained through different test vectors (test patterns). Therefore, inFigure 3 In some embodiments, the information detection subject can further generate a plurality of test patterns for obtaining the second memory parameter, and then obtain the working frequency and other working parameters of the DRAM particle 320 through different test patterns. Specifically, the information detection subject can perform data read / write operations on the to-be-detected memory based on the test vector, such as writing test data into the to-be-detected memory at a specific working parameter value, and reading the written test data from the to-be-detected memory according to the working parameter value, to determine whether the read data obtained through the data read operation is consistent with the written test data, and then determine the corresponding second memory parameter.

[0068] In an exemplary embodiment of the present disclosure, an initial working frequency vector is obtained, a register parameter is written in the initial working frequency vector to obtain a working frequency vector; the register parameter includes a candidate working frequency of the to-be-detected memory; first test data is written into the to-be-detected memory based on the working frequency vector; the written first test data is read from the to-be-detected memory as first read data based on the candidate working frequency corresponding to the data write operation; and a target working frequency is determined from the candidate working frequencies in which the first read data is consistent with the first test data.

[0069] In some embodiments, the initial working frequency vector can be an initial configuration test vector for determining the working frequency. The register parameter can be a parameter used when performing data read / write operations on the to-be-detected memory. The working frequency vector can be a vector obtained after the register parameter is written in the initial working frequency vector. The candidate working frequency can be a plurality of working frequencies used when performing read / write operations on the to-be-detected memory. The first test data can be test data used to determine the working frequency of the to-be-detected memory. The first read data can be data obtained by performing a data read operation on the to-be-detected memory in which the first test data has been written. The target working frequency can be the real working frequency of the to-be-detected memory.

[0070] The register parameter can include a unit clock cycle (Clock Cycle Time, tCK), a row address to column address delay time (RAS to CAS Delay, also referred to as: Acitve to CMD, tRCD), a column address write delay time (CAS Write Latency, tCWL), a write recovery delay time (Write Recovery Time, tWR), a column address controller latency time before memory read / write operation (CAS Lantency Control, tCL), a read to precharge time (tRTP), and a memory row address controller precharge time (Row Precharge Timing, also referred to as: Precharge to Active, tRP).

[0071] The embodiment can read the maximum working frequency information of the DRAM particle according to the working frequency test vector, as the target working frequency. The specific processing process is as follows: when determining the target working frequency, initialization processing can be performed first. An initial working frequency vector for determining the target working frequency is obtained, and the related information of the pre-configured register parameters (Mode Register) of the DRAM particle is written into the initial working frequency vector to obtain a working frequency vector. Since in the embodiment, the maximum working frequency information of the DRAM particle needs to be determined through the working frequency vector, the register parameters can include a plurality of candidate working frequencies, and the target working frequency is determined according to the data read-write results under the plurality of candidate working frequencies.

[0072] Specifically, taking the working frequency of 2666Mhz as an example, according to the Joint Electron Device Engineering Council (JEDEC) standard, the remaining register parameters can be configured as tCK=0.75ns, tRCD=20ns, tCWL=18ns, tWR=24ns, tCL=20ns, tRTP=32ns, tRP=20ns, etc.

[0073] After obtaining the working frequency vector, the first test data can be written into the to-be-detected memory based on the working frequency vector. When writing the first test data, a data write operation can be performed on a certain data row (Row) in the to-be-detected memory. When the data write operation of the current data row is completed, the first test data written in the to-be-detected memory can be read based on the candidate working frequency used in the data write operation, and the read data is taken as the first read data.

[0074] After obtaining the first read data, the first read data and the first test data can be compared for consistency, and the target working frequency is determined from the candidate working frequencies consistent with the first read data and the first test data.

[0075] Taking the working frequency of 2666Mhz as an example, after the processing step, part of the first read data 0x000000A9, 0x00000065, etc. is obtained, which is consistent with the first test data written, so the DRAM particle can work normally at the working frequency of 2666Mhz.

[0076] In an example embodiment of the present disclosure, an activation command is sent based on a working frequency vector, a data write command is sent after a first time interval; first test data is sent to a memory to be detected, and the first test data is written to a specific location of the memory to be detected one by one after a second time interval; a pre-charge command and a refresh command are sent in response to a write completion event of a current row in the memory to be detected; a data write operation is performed for a next row of the current row until all rows and all columns of the memory to be detected have been written with the first test data.

[0077] The activation command can be an instruction triggering a data write operation on the memory to be detected. The first time interval can be a time interval value determined according to a row addressing to column addressing delay time, for example, the first time interval can be equal to the row addressing to column addressing delay time. The data write command can be a command indicating to write data into the memory to be detected. The second time interval can be a time interval value determined according to a write recovery latency, for example, the second time interval can be equal to the write recovery latency. The write completion event can be an event that the test data has been written into the memory to be detected. The pre-charge command can be an instruction to close a row of a double data rate synchronous dynamic random access memory (DDR SDRAM) that has been opened. The refresh command can be an instruction to prevent data stored in the memory from being lost due to leakage of a storage cell. The data write operation can be an operation of writing data into the memory to be detected.

[0078] Reference Figure 4 , Figure 4 An overall flowchart of writing and reading first test data to a memory to be monitored according to an example embodiment of the present disclosure is schematically shown. After obtaining a working frequency vector, an activation command can be sent based on the working frequency vector, and then a data write command is sent after a first time interval (e.g., tRCD = 20 ns), at which time custom first test data can be sent to a DRAM die. After waiting for a second time interval (e.g., tWR = 24 ns), the first test data is saved to a certain data column (Column) of a current data row (Row) of the memory to be detected, i.e., the first test data is written to a specific location of the memory to be detected. The next data is then sent to the next Column of the Row, and the data is written in the same data row of the memory to be detected through a LoopCol++ operation until the first test data is written to all Columns of the current Row.

[0079] If all Columns of the current data row have been written with the first test data, a write completion event of the current data row is triggered. In response to the write completion event of the current data row, a precharge command is sent to close the current data row, and a refresh command is also sent to prevent data loss due to cell leakage.

[0080] If the data write operation of the current data row is completed, a data write operation is performed on a next data row of the current data row, and the data write operation on other rows can be performed by LoopRow++. If all data rows of the current bank have been written with the first test data, a data write operation can be performed on other banks, and the data write operation on other banks can be performed by LoopBank++ so as to subsequently perform a data read operation based on the written first test data.

[0081] In an exemplary embodiment of the present disclosure, an active command is sent based on a candidate operating frequency, a data read command is sent after a first time interval, the first test data is read from a current data row in the to-be-detected memory after a third time interval, a precharge command is sent after a fourth time interval in response to a read completion event of the current data row, and a data read operation is repeated for the data row until all the first test data in the to-be-detected memory is read to obtain first readout data.

[0082] The data read command can be an instruction to read data from the to-be-detected memory. The current data row can be a data row on which the data read operation is currently performed. The third time interval can be a time interval value determined according to a delay time of column address access, for example, the third time interval can be equal to the delay time of column address access. The read completion event can be an event that all positions in the current data row have been read. The data read operation can be an operation to read data from the to-be-detected memory.

[0083] If all Columns of the current Row of the to-be-detected memory complete the data write operation, a data read operation is performed. The specific steps of the data read operation are as follows: an Active command is sent based on the operating frequency vector, a data read command (Read command) is sent after a first time interval (tRCD=20 ns), and the written first test data is read from the current data row in the to-be-detected memory after a first time interval (tCL=20 ns). Similar to the data write operation, in order to read all Column data of the current Row, a Loop Col++ operation is also required to read out all Column data of the current Row.

[0084] If all the Column data of the current Row have been read out, a read completion event is triggered, at this time, a Precharge command can be sent after waiting for a fourth time interval (tRTP = 32), at this time, the first readout data of the current Row can be obtained. Similarly, when reading the first test data written in the to-be-detected memory, the data read operation for different data rows can be performed through Loop Row++. The data read operation for other memory banks can be performed through Loop Bank++.

[0085] After the data write operation for all the Banks, Rows is completed, the first test data written can be read out from all the Banks, Rows, and the first test data written is compared with the first readout data read out, if the data is consistent, it can be indicated that the DRAM particle can work normally at the candidate operating frequency.

[0086] It can be known from the above processing steps that the processing sequence (Sequence) of the test Pattern of the operating frequency can be: Initial →

Activate command (ACT) → Data write command (WR) → Precharge command (PRG) → Refresh command (REF) → Activate command (ACT) → Data read command (RD) → Precharge command (PRG) (data row loop loop row → memory bank loop loop bank)

[0087] In an exemplary embodiment of the present disclosure, an initial refresh time vector is obtained, a register parameter is written in the initial refresh time vector to obtain a refresh time vector; the register parameter includes a candidate refresh time value, the candidate refresh time value is determined based on a memory capacity; second test data is written into the to-be-detected memory based on the refresh time vector; the second test data written is read from the to-be-detected memory as second readout data; the currently configured candidate refresh time value is adjusted, and data read-write results corresponding to different candidate refresh time values are determined; and a target refresh time value is determined according to the candidate refresh time value in which the second readout data is consistent with the second test data.

[0088] The memory refresh time (RowRefresh Cycle Time, tRFC) can be a SDRAM row refresh cycle time, that is, the time required by the DRAM particle to refresh a single row in the same bank. The initial refresh time vector can be a test vector initially configured to determine the memory refresh time parameter. The refresh time vector can be a vector obtained after the register parameter is written in the initial refresh time vector. The candidate refresh time value can be a plurality of specific values of the memory refresh time configured in advance. The memory capacity can be the storage capacity of the to-be-detected memory.

[0089] The process of determining the memory refresh time is as follows: first, initialization processing is performed, an initial refresh time vector for determining a target refresh time value is obtained, a pre-configured Mode Register of a DRAM particle is written into the initial refresh time vector, and a refresh time vector is obtained. Taking a working frequency of 2666Mhz as an example, according to the JEDEC standard, tCK = 0.75ns, tRCD = 20ns, tCWL = 18ns, tWR = 24ns, tCL = 20ns, tRTP = 32ns, tRAS = 48ns, tRP = 20ns, and the like. In addition, the register parameters also include candidate refresh time values, and the candidate refresh time values can be determined based on the memory capacity.

[0090] After obtaining the refresh time vector, second test data can be written into the to-be-detected memory based on the refresh time vector. After the second test data is written into the to-be-detected memory, the written second test data can be read from the to-be-detected memory as second readout data based on the same current refresh time value. After the data read / write operation is completed under the current refresh time value, the current refresh time value can be adjusted based on the candidate refresh time value, the adjusted refresh time value is taken as a new current refresh time value, and data read / write operations are performed based on the current refresh time value to determine the corresponding data read / write result.

[0091] Specifically, when the current refresh time value is adjusted, the following steps can be performed: after the data write operation is completed and the Refresh command is sent, the Active command can be sent after waiting for a time interval of the current refresh time value, and the Precharge command can be sent after waiting for a time interval of tRAS = 48, at which time different tRFC values can be modified for testing, such as testing from 150ns to 500ns, and the testing is repeated 8192 times. Through the above steps, the target refresh time value corresponding to the to-be-detected memory can be determined.

[0092] In an exemplary embodiment of the present disclosure, an Active command is sent based on the refresh time vector, a data write command is sent after a first time interval; second test data is sent to the to-be-detected memory, and the second test data is written into a specific location in the to-be-detected memory one by one after a second time interval; a Precharge command is sent in response to a write completion event of a current data row of the to-be-detected memory; and a Refresh command is sent in response to a write completion event of a current bank of the to-be-detected memory.

[0093] The second test data can be test data used to determine the memory refresh time of the to-be-detected memory. The current bank can be a bank currently acted on by the data write operation.

[0094] Reference Figure 5 , Figure 5 The overall flowchart of writing and reading second test data to the memory to be monitored according to an example embodiment of the present disclosure is schematically shown. After obtaining the refresh time vector, an active command can be sent based on the refresh time vector, and then a data write command is sent after waiting for a first time interval (such as tRCD=20 ns), at which time the second test data can be sent to the DRAM chip. After waiting for a second time interval (such as tWR=24 ns), the second test data is saved to a certain column of data in the current row of the memory to be detected. At this time, the Loop Col++ operation can be performed until the second test data is written to all columns in the current data row.

[0095] If all columns of the current row are written, a write completion event of the current data row is triggered. In response to the write completion event of the current data row, a precharge command is sent, and data is written to all rows, i.e., the Loop Row++ operation is implemented. If the second test data has been written to all data rows of the memory to be detected, a write completion event of the current bank is triggered. In response to the write completion event of the current bank, a refresh command can be sent to prevent the data saved in the cell from being lost due to cell leakage.

[0096] In an example embodiment of the present disclosure, an active command is sent based on the refresh time vector, a data read command is sent after a first time interval, the second test data written is read from the current data row of the memory to be detected after a third time interval, second read data is obtained in response to a read completion event of all data rows of the memory to be detected, and a precharge command is sent after a fourth time interval.

[0097] The second read data can be data obtained by performing a data read operation on the memory to be detected to which the second test data has been written. The fourth time interval can be a time interval value determined according to the time from reading to precharging, for example, the fourth time interval can be equal to the time from reading to precharging.

[0098] Continuing to refer to Figure 5When the data write operation is completed, the data read operation can be performed. Similar to the data write command, the Active command can be sent first, and then the Read command can be sent after a first time interval (tRCD=20 ns). The second test data can be read from the memory under test after a third time interval (tCL=20 ns). Similarly, in order to read all the Column data of this Row, the Loop Col++ operation needs to be performed, and then the Loop Row operation is performed. After the data read operation is completed, the second read data can be compared with the second test data for consistency. If the current memory bank (Bank) in the memory under test completes the data read / write operation, the Precharge command can be sent after a fourth time interval (tRTP=32 ns).

[0099] After the above processing, the test result of the Pattern test can be obtained. The read / write test this time includes eight particles U1-U8 in total, and the tRFC parameters all meet the requirements of the JEDEC standard. Table 1 shows the details.

[0100] Table 1

[0101]

[0102] From the above processing steps, it can be known that the processing sequence of the memory refresh time test Pattern can be: Initial→

ACT→WR→PRG→REF→tRFC→ACT→RD→PRG(loop row loop bank)

[0103] In an example embodiment of the present disclosure, an initial response interval time vector is obtained, a register parameter is written in the initial response interval time vector to obtain a response interval time vector; the register parameter includes a response interval time value; third test data is written into the memory under test based on the response interval time vector; a self-refresh configuration operation is performed based on a clock cycle, and the current response interval time value is updated through the self-refresh configuration operation; the third test data written into the memory under test is read as third read data by using different response interval time values; and a target response interval time value is determined according to the response interval time value at which the third read data is consistent with the third test data.

[0104] The instruction response interval time (Exit Self Refresh to commands not requiring a locked DLL, tXS) can be the minimum time required by the memory bank to perform the next instruction after exiting self-refresh. The initial response interval time vector can be an initial configured test vector for determining the instruction response interval time. The response interval time vector can be a vector obtained after writing the register parameters in the initial response interval time vector. The response interval time value can be a specific value of the pre-configured response interval time.

[0105] The reading operation of the tXS parameter can be performed by the following steps: according to the JEDEC standard, the minimum time of tXS can be Trfc+10ns, tRFC+10ns, i.e. 360ns, taking the working frequency of 2666Mhz as an example, tXS(min)=480clk.

[0106] First, the initialization process is performed to obtain an initial response interval time vector for determining a target response interval time value, and the pre-configured Mode Register of the DRAM grain is written into the initial response interval time vector to obtain a response interval time vector. Taking the working frequency of 2666Mhz as an example, according to the JEDEC standard, tCK=0.75ns, tRCD=20ns, tCWL=18ns, tWR=24ns, tCL=20ns, tRTP=32ns, tRAS=48ns, tRP=20ns, etc. In addition, the register parameters also include a plurality of response interval time values, which can be based on a plurality of different response interval time values in the subsequent data read / write operation process.

[0107] After obtaining the response interval time vector, the third test data can be written into the to-be-detected memory based on the response interval time vector. When the current memory bank of the to-be-detected memory has been written with the third test data, a self-refresh configuration operation can be performed based on the clock cycle, and in the present embodiment, the current response interval time value can be updated by the self-refresh configuration operation. After updating the current response interval time value, a plurality of different response interval time values obtained can be used to perform data read operation to obtain third readout data.

[0108] After obtaining the third readout data, the third readout data and the written third test data can be compared for consistency, and the target response interval time value can be determined from the response interval time value consistent with the third readout data and the third test data.

[0109] In an exemplary embodiment of the present disclosure, an activation command is sent based on a response interval time vector, a data write command is sent after a first time interval; third test data is sent to the memory to be detected, and the third test data is written to a specific location of the memory to be detected one by one after a second time interval; a pre-charge command and a refresh command are sent in response to a write completion event of all data rows of the memory to be detected.

[0110] The third test data can be test data used to determine the instruction response interval time of the memory to be detected. The specific location can be a storage location of a data row in the memory to be detected.

[0111] Reference Figure 6 , Figure 6 The overall flowchart of determining the instruction response interval time according to the exemplary embodiment of the present disclosure is schematically shown. After obtaining the response interval time vector, an Active command can be sent based on the response interval time vector, and then a Write command is sent after waiting for a first time interval (tRCD=20). At this time, the third test data defined by the user can be sent to the DRAM grain. After waiting for a second time interval (tWR=24), the third test data sent to the DRAM grain can be saved to a certain Column of the current Row, and the next data can be sent to the next Column of the Row by performing a Loop Col++ operation, until the third test data is written to all Columns of the current Row. If all Columns of the current Row are written, a write completion event of the current Row will be triggered. In response to the write completion event of the current Row, a Precharge command is sent, and a data write operation can be performed on all Rows by performing a Loop Row++ operation.

[0112] After the Precharge command is completed, a self-refresh configuration operation can be performed. Referring to Figure 6 , the specific operation is as follows: a self-refresh entry command (Self Refresh Entry command) is sent, a self-refresh exit command (Self Refresh Exit command) is sent after waiting for a first specified number of clock cycle time intervals (such as 19 clk), the Self Refresh Entry command is re-sent after waiting for a tXS command, the Self Refresh Exit command is sent again after waiting for a second specified number of clock cycle time intervals (such as 24 clk), and finally 1000 clk is waited for. At this time, different tXS values can be modified for testing, such as testing from 480 clk to 900 clk, and the testing is repeated 8192 times. Through the above processing steps, the third test data can be written to the memory to be detected based on the corresponding test vector.

[0113] In one exemplary embodiment of the present disclosure, the activation command is sent based on the response interval time vector, the data read command is sent after a first time interval, the third test data written is read from the current data row of the memory under test after a third time interval, the third read data is obtained in response to a read completion event of all data rows in the memory under test, and a pre-charge command is sent.

[0114] The third test data can be test data used to determine the instruction response interval time of the memory under test. The third read data can be data obtained from the memory under test after the third test data is written.

[0115] With reference to the above Figure 6 After 8192 cycles are completed, the data read operation can be performed. Similar to the data write command, the Active command is first sent, then the Read command is sent after a first time interval (tRCD=20), and the data is read after a third time interval (tCL=20). Similarly, to read all Column data of this Row, the Loop Col++ and Loop Row++ operations are required, and the Precharge command is finally sent.

[0116] After the data read / write operation is completed, the third test data written with different tXS values can be compared with the third read data, and the actual parameter value of tXS can be obtained. After the data comparison operation is performed using the above steps, the corresponding data comparison result is obtained. In this test, the tXS values from 488 clk to 968 clk are passed. Since the Spec specifies that the minimum value of tXS is 480 clk, a larger value is tried during the data read / write test, and the result is determined whether it can pass. If it fails, it means that tXS cannot meet the minimum value requirement of the Spec. Meanwhile, a smaller tXS value does not need to be tested again, because if a smaller value can pass, it means that the parameter value is better than the Spec requirement.

[0117] From the above processing steps, the processing sequence of the test pattern of the command response interval time can be: initialization (Initial) → activation command (ACT) → data write command (WR) → pre-charge command (PRG) →

self-refresh entry command (SRE) → wait for 19 clock cycles (19T) → self-refresh exit command (SRX) → modify tXS command (tXS) → self-refresh entry command (SRE) → wait for 24 clock cycles (24T) → self-refresh exit command (SRX) → activation command (ACT) → data read command (RD) → pre-charge command (PRG) (data row loop loop row → memory bank loop loop bank)

[0118] It is easy for those skilled in the art to understand that the first detection data, the second detection data and the third detection data can be the same or different, and the present disclosure does not make any special limitation thereon.

[0119] With reference to the foregoing Figure 1 In step S120, the chip record parameter is obtained from the detection chip corresponding to the to-be-detected memory.

[0120] In some example embodiments of the present disclosure, the detection chip can be an SPD chip corresponding to the to-be-detected memory. The chip record parameter can be a related parameter of the to-be-detected memory recorded in the SPD chip.

[0121] With reference to the foregoing Figure 2 After the memory parameter is determined, the chip record parameter can be obtained from the serial presence detection SPD chip (i.e., the detection chip) of the DIMM module 220. Specifically, with reference to the foregoing Figure 3 The parameter information in the SPD chip 330 can be read through an Inter-Integrated Circuit (IIC) communication mode. The IIC communication protocol is a kind of half-duplex communication mode, and its most important advantage is its simplicity and effectiveness. Since the interface is directly on the component, the IIC bus occupies very small space, reduces the space of the circuit board and the number of chip pins, and reduces the interconnection cost. In addition, it supports multi-master, in which any device capable of sending and receiving can become the master bus. The SPD chip records a lot of important information, such as Byte 4 records the capacity and bank information of DRAM, Byte 25 records the tRCD parameter information of DRAM, etc.

[0122] With reference to the foregoing Figure 1 In step S130, the consistency of the memory parameter and the chip record parameter is compared, and a comparison result is obtained to determine the authenticity of the chip record parameter according to the comparison result.

[0123] In some example embodiments of the present disclosure, the comparison result can be a consistency comparison between the memory parameter and the chip record parameter, and a result of whether the two are consistent.

[0124] After obtaining the chip record parameter, with reference back to Figure 3 In step S310, it is determined whether the information matches. The chip record parameter is compared with the real working parameter (i.e. the memory parameter) inside the DRAM grain, and the authenticity of the chip record parameter is determined according to the comparison result.

[0125] In an example embodiment of the present disclosure, if the comparison result is that the chip record parameter is inconsistent with the memory parameter, the chip record parameter is not the real memory parameter, and it is determined that the memory parameter is sent to the input and output system chip corresponding to the to-be-detected memory; if the comparison result is that the chip record parameter is consistent with the memory parameter, the chip record parameter is the real memory parameter, and the system board is started to run based on the chip record parameter.

[0126] With reference back to Figure 3 When the chip record parameter read through the IIC communication protocol is inconsistent with the memory parameter tested by the Pattern, such as tCL = 22 tested by the Pattern, but tCL = 20 shown in the SPD parameter, it is indicated that the information does not match, the chip record parameter is not the real memory parameter, at this time the buzzer 215 of the information detection main body 210 alarms, and the real parameter information is sent to the BIOS chip 230 for adoption, so that the main board works with the real parameter information. If the comparison result is that the chip record parameter is consistent with the memory parameter, the chip record parameter is the real memory parameter, and the system board is started to run based on the chip record parameter. Therefore, whether the chip record parameter is real or not, the system board can run based on the real memory parameter.

[0127] It should be noted that the terms "first", "second", "third", "fourth" and the like used in the present disclosure are only used to distinguish different time intervals, test data, etc., and should not impose any limitation on the present disclosure.

[0128] To sum up, the memory to be detected is acquired, and the memory parameter corresponding to the memory to be detected is determined; the memory parameter is obtained based on at least one of an operation code and a test vector; the chip record parameter is acquired from the detection chip corresponding to the memory to be detected; the memory parameter and the chip record parameter are compared for consistency, and a comparison result is obtained, so as to determine the authenticity of the chip record parameter according to the comparison result. On the one hand, the memory parameter determined and the chip record parameter are compared for consistency, so that the authenticity of the chip record parameter can be determined, and whether the chip record parameter in the detection chip is maliciously modified can be judged. On the other hand, by constructing different test vectors to perform read and write operations, a plurality of real working parameters of the memory to be detected can be determined.

[0129] It should be noted that although the steps of the method in the present application are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired result. In addition or alternatively, some steps can be omitted, a plurality of steps can be combined into one step, and / or one step can be divided into a plurality of steps, etc.

[0130] In addition, in the present example embodiment, an information detection device is also provided. Referring to Figure 7 The information detection device 700 can include a memory parameter determination module 710, a chip parameter acquisition module 720, and a parameter comparison module 730.

[0131] Specifically, the memory parameter determination module 710 is configured to determine the memory parameter corresponding to the memory to be detected; the memory parameter is obtained based on at least one of an operation code and a test vector; the chip parameter acquisition module 720 is configured to acquire the chip record parameter from the detection chip corresponding to the memory to be detected; and the parameter comparison module 730 is configured to compare the memory parameter and the chip record parameter for consistency, obtain a comparison result, and determine the authenticity of the chip record parameter according to the comparison result.

[0132] In an example embodiment of the present disclosure, the memory parameter includes a first memory parameter, the memory parameter determination module 710 includes a first parameter determination module, the first parameter determination module is configured to detect the power-on state of the device system board; in response to detecting that the power-on state is a powered-on state, an operation code is generated; the first memory parameter is read from the memory to be detected through the operation code; and the first memory parameter includes the manufacturer information and the capacity information of the memory to be detected.

[0133] In an example embodiment of the present disclosure, the memory parameter further includes a second memory parameter, the memory parameter determination module 710 further includes a second parameter determination module, the first parameter determination module is configured to generate a test vector for obtaining the memory parameter; perform a data read-write operation on the to-be-tested memory based on the test vector, and determine the second memory parameter according to a data read-write result.

[0134] In an example embodiment of the present disclosure, the second memory parameter includes a working frequency, and the second parameter determination module includes a frequency parameter determination unit, the frequency parameter determination unit is configured to obtain an initial working frequency vector, write a register parameter in the initial working frequency vector to obtain a working frequency vector; the register parameter includes a candidate working frequency of the to-be-tested memory; write first test data into the to-be-tested memory based on the working frequency vector; read the written first test data from the to-be-tested memory as first read data based on a candidate working frequency corresponding to the data write operation; and take the candidate working frequency, in which the first read data is consistent with the first test data, as a target working frequency.

[0135] In an example embodiment of the present disclosure, the frequency parameter determination unit includes a first data write subunit, the first data write subunit is configured to send an activation command based on the working frequency vector, send a data write command after a first time interval; send the first test data to the to-be-tested memory, and write the first test data into a specific position of the to-be-tested memory one by one after a second time interval; send a pre-charge command and a refresh command in response to a write completion event of a current row in the to-be-tested memory; perform a data write operation on a next row of the current row until all rows and all columns of the to-be-tested memory have been written with the first test data.

[0136] In an example embodiment of the present disclosure, the frequency parameter determination unit includes a first data read subunit, the first data read subunit is configured to send an activation command based on the candidate working frequency, send a data read command after a first time interval; read the first test data from a current data row in the to-be-tested memory after a third time interval; send a pre-charge command after the third time interval in response to a read completion event of the current data row; repeat the data read operation on the data row until all the first test data in the to-be-tested memory are read to obtain the first read data.

[0137] In an example embodiment of the present disclosure, the second parameter determination module includes a refresh time determination unit, the refresh time determination unit being configured to obtain an initial refresh time vector, write register parameters in the initial refresh time vector to obtain a refresh time vector, the register parameters including candidate refresh time values determined based on a memory capacity, write second test data into the to-be-detected memory based on the refresh time vector, read the written second test data from the to-be-detected memory as second readout data, adjust the currently configured candidate refresh time values, and determine data read-write results corresponding to different candidate refresh time values, and determine a target refresh time value based on the candidate refresh time values in which the second readout data is consistent with the second test data.

[0138] In an example embodiment of the present disclosure, the refresh time determination unit includes a second data write subunit, the second data write subunit being configured to send an activation command based on the refresh time vector, send a data write command after a first time interval, send second test data to the to-be-detected memory, and write the second test data into specific positions in the to-be-detected memory one by one after a second time interval, and send a pre-charge command and a refresh command in response to a write completion event of a current memory bank of the to-be-detected memory.

[0139] In an example embodiment of the present disclosure, the refresh time determination unit includes a second data read subunit, the second data read subunit being configured to send an activation command based on the refresh time vector, send a data read command after a first time interval, read the written second test data from a current data row of the to-be-detected memory after a third time interval, obtain second readout data in response to a read completion event of all data rows in the to-be-detected memory, and send a pre-charge command after a fourth time interval.

[0140] In an example embodiment of the present disclosure, the second memory parameter includes an instruction response interval time, and the second parameter determination module includes a response interval time determination unit, the response interval time determination unit being configured to obtain an initial response interval time vector, write register parameters in the initial response interval time vector to obtain a response interval time vector, the register parameters including a response interval time value, write third test data into the to-be-detected memory based on the response interval time vector, perform a self-refresh configuration operation based on a clock cycle, update the current response interval time value through the self-refresh configuration operation, read the written third test data from the to-be-detected memory as third readout data using different response interval time values, and determine a target response interval time value based on the response interval time value in which the third readout data is consistent with the third test data.

[0141] In an example embodiment of the present disclosure, the response interval time determination unit comprises a third data write sub-unit, configured to send an activation command based on the response interval time vector, send a data write command after a first time interval; send third test data to the to-be-detected memory, and write the third test data to specific locations of the to-be-detected memory one by one after a second time interval; and send a pre-charge command and a refresh command in response to a write completion event of all data rows of the to-be-detected memory.

[0142] In an example embodiment of the present disclosure, the response interval time determination unit comprises a third data read sub-unit, configured to send an activation command based on the response interval time vector, send a data read command after a first time interval; read the written third test data from a current data row of the to-be-detected memory after a third time interval; and obtain third readout data and send a pre-charge command in response to a read completion event of all data rows of the to-be-detected memory.

[0143] In an example embodiment of the present disclosure, the information detection apparatus 700 further comprises a parameter use module, configured to, if the comparison result is that the chip-recorded parameter and the memory parameter are inconsistent, determine that the chip-recorded parameter is not the real memory parameter, send the determined memory parameter to a corresponding input-output system chip of the to-be-detected memory; and if the comparison result is that the chip-recorded parameter and the memory parameter are consistent, determine that the chip-recorded parameter is the real memory parameter, and start a system board to run based on the chip-recorded parameter.

[0144] The specific details of the virtual modules of the information detection apparatuses in the above embodiments have been described in detail in the corresponding information detection methods, and thus will not be described here again.

[0145] It should be noted that, although several modules or units of the information detection apparatus are mentioned in the above detailed description, such division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into a plurality of modules or units.

[0146] In addition, in an example embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

[0147] Those skilled in the art can understand that each aspect of the present application can be implemented as a system, a method or a program product. Therefore, each aspect of the present application can be embodied in a form of entirely hardware, entirely software (including firmware, microcode, etc.), or a combination of hardware and software, which can be collectively referred to as "circuitry", "module" or "system" herein.

[0148] The electronic device 800 according to this embodiment of the present disclosure will be described below with reference to Figure 8 Figure 8 The electronic device 800 is merely an example and should not impose any limitation on the function and use range of the embodiments of the present disclosure.

[0149] As Figure 8 shown, the electronic device 800 is in the form of a general computing device. The components of the electronic device 800 can include, but are not limited to, the at least one processing unit 810 described above, the at least one storage unit 820 described above, a bus 830 connecting different system components (including the storage unit 820 and the processing unit 810), and a display unit 840.

[0150] The storage unit stores program codes which can be executed by the processing unit 810, so that the processing unit 810 performs the steps described in the above "Exemplary Method" section according to various exemplary embodiments of the present disclosure.

[0151] The storage unit 820 can include a readable medium in the form of a volatile storage unit, such as a random access memory (RAM) 821 and / or a cache memory 822, and can further include a read-only memory (ROM) 823.

[0152] The storage unit 820 can include program / utility 824 having a set of program modules 825, such as an operating system, one or more application programs, other program modules, and program data, and each of these examples, or some combination thereof, can include implementation of a network environment.

[0153] The bus 830 can represent one or more of several types of bus structures, including a storage unit bus or storage unit controller, a peripheral bus, a graphics acceleration port, a processing unit or a local bus using any of a variety of bus architectures.

[0154] ​Electronic device 800 can also communicate with one or more external devices 870 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 800, and / or with any device that enables electronic device 800 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 850. Furthermore, electronic device 800 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 860. As shown, network adapter 860 communicates with other modules of electronic device 800 via bus 830. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 800, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0155] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0156] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the invention described in the "Exemplary Methods" section above.

[0157] refer to Figure 9 As shown, a program product 900 for implementing the above-described method according to an embodiment of the present invention is described. It may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0158] The program product can employ any combination of one or more computer-readable media. The computer-readable media can be a computer-readable storage medium or a computer-readable signal medium. The computer-readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include the following: an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0159] The computer-readable signal medium can include a computer-readable storage medium that is propagated as a carrier wave. The computer-readable signal medium can further be any computer-readable medium that is not a storage medium. The computer-readable signal medium can be a computer-readable storage medium that is a propagated signal on a computer-readable storage medium.

[0160] The program code embodied on the computer-readable media can be transmitted using any appropriate medium, including but not limited to wireless, wired, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0161] The program code can be executed by one or more programmable processors, which can be implemented in one or more computer systems. In this context, a computer system generally includes a plurality of these programmable processors, which can be coupled together by one or more communication buses. The computer system can include a bus system, which can be any of a variety of bus architectures including a memory bus or memory controller, a peripheral bus, or a local bus, or any combination thereof. The bus system can include a bus, which can be any one of several types of bus structures including a memory bus, memory controller, peripheral bus, or local bus, using any one or more of bus architectures, including 12-bit bus, 64-bit bus, etc. The bus system can also include one or more memories, including read-only memory (ROM), random access memory (RAM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, etc.

[0162] Furthermore, the above-described diagrams are merely schematic illustrations of the processes included in the method according to the exemplary embodiments of the present application, and are not intended to be limiting. It is readily understood that the processes shown in the above-described diagrams do not indicate or limit the time sequence of the processes. In addition, it is readily understood that the processes can be executed synchronously or asynchronously, for example, in a plurality of modules.

[0163] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

[0164] It should be understood that the present disclosure is not limited to the precise structures as herein described and illustrated in the drawings, and that various modifications and changes can be made without departing from its scope. The scope of the present disclosure is limited only by the claims that follow.

Claims

1. An information detection method, characterized in that, comprising: acquiring a to-be-detected memory, and determining a memory parameter corresponding to the to-be-detected memory; the memory parameter is obtained based on at least one of an operation code and a test vector; acquiring a chip record parameter from a detection chip corresponding to the to-be-detected memory; comparing the memory parameter and the chip record parameter for consistency to obtain a comparison result, so as to determine the authenticity of the chip record parameter according to the comparison result; wherein the memory parameter comprises a first memory parameter, and the determination of the memory parameter corresponding to the to-be-detected memory comprises: detecting the power-on state of a detection device system board; in response to detecting that the power-on state is a powered-on state, generating the operation code; reading the first memory parameter from the to-be-detected memory through the operation code; the first memory parameter comprises manufacturer information and capacity information of the to-be-detected memory; wherein the memory parameter further comprises a second memory parameter, and the determination of the memory parameter corresponding to the to-be-detected memory comprises: generating a test vector for acquiring the memory parameter; performing data read-write operation on the to-be-detected memory based on the test vector, and determining the second memory parameter according to the data read-write result; wherein the second memory parameter comprises a working frequency, and the determination of the second memory parameter according to the data read-write result based on the test vector comprises: acquiring an initial working frequency vector, writing a register parameter in the initial working frequency vector to obtain a working frequency vector; the register parameter comprises a candidate working frequency of the to-be-detected memory; writing first test data into the to-be-detected memory based on the working frequency vector; reading the written first test data from the to-be-detected memory as first read-out data based on the candidate working frequency corresponding to the data write operation; taking the candidate working frequency consistent with the first read-out data and the first test data as a target working frequency.

2. The method of claim 1, wherein, the writing of the first test data into the to-be-detected memory based on the working frequency vector comprises: sending an activation command based on the working frequency vector, and sending a data write command after a first time interval; sending the first test data to the to-be-detected memory, and writing the first test data into specific positions of the to-be-detected memory one by one after a second time interval; in response to a write completion event of a current row in the to-be-detected memory, sending a pre-charge command and a refresh command; performing data write operation on a next row of the current row until all rows and all columns of the to-be-detected memory have been written with the first test data.

3. The method of claim 2, wherein, the reading of the written first test data from the to-be-detected memory as first read-out data based on the candidate working frequency corresponding to the data write operation comprises: sending an activation command based on the candidate operating frequency, and sending a data read command after a first time interval; reading the first test data from a current data row in the memory under test after a third time interval; sending a pre-charge command in response to a read completion event of the current data row after a third time interval; repeating the data read operation for the data row until all the first test data in the memory under test is read, to obtain the first readout data. 4.The method of claim 1, wherein the second memory parameter comprises a memory refresh time, and the determining the second memory parameter based on the data read / write operation on the memory under test comprises: obtaining an initial refresh time vector, and writing a register parameter in the initial refresh time vector to obtain a refresh time vector, wherein the register parameter comprises a candidate refresh time value, and the candidate refresh time value is determined based on a memory capacity; writing second test data into the memory under test based on the refresh time vector; reading the written second test data from the memory under test as second readout data; adjusting the currently configured candidate refresh time value, and determining data read / write results corresponding to different candidate refresh time values; and determining a target refresh time value based on the candidate refresh time value under which the second readout data is consistent with the second test data. 5.The method of claim 4, wherein the writing second test data into the memory under test based on the refresh time vector comprises: sending an activation command based on the refresh time vector, and sending a data write command after a first time interval; sending the second test data to the memory under test, and writing the second test data into specific locations in the memory under test one by one after a second time interval; and sending a pre-charge command and a refresh command in response to a write completion event of a current bank in the memory under test. 6.The method of claim 4, wherein the reading the written second test data from the memory under test as second readout data comprises: sending an activation command based on the refresh time vector, and sending a data read command after a first time interval; reading the written second test data from a current data row in the memory under test after a third time interval; and obtaining the second readout data in response to a read completion event of all data rows in the memory under test; and sending a pre-charge command after a fourth time interval. 7.The method of claim 1, wherein the second memory parameter comprises an instruction response interval time, and the determining the second memory parameter based on the data read / write operation on the memory under test comprises: obtaining an initial response interval time vector, and writing a register parameter in the initial response interval time vector to obtain a response interval time vector, wherein the register parameter comprises a response interval time value. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ writing third test data into the to-be-detected memory based on the response interval time vector; performing a self-refresh configuration operation based on a clock cycle, and updating a current response interval time value through the self-refresh configuration operation; reading the written third test data from the to-be-detected memory as third readout data by using different response interval time values; determining a target response interval time value according to a response interval time value in which the third readout data is consistent with the third test data.

8. The method of claim 7, wherein the writing third test data into the to-be-detected memory based on the response interval time vector comprises: sending an activate command based on the response interval time vector, and sending a data write command after a first time interval; sending the third test data to the to-be-detected memory, and writing the third test data to specific locations of the to-be-detected memory one by one after a second time interval; sending a pre-charge command and a refresh command in response to a write completion event of all data rows of the to-be-detected memory.

9. The method of claim 7, wherein the reading the written third test data from the to-be-detected memory as third readout data by using different response interval time values comprises: sending an activate command based on the response interval time vector, and sending a data read command after a first time interval; reading the written third test data from a current data row of the to-be-detected memory after a third time interval; obtaining the third readout data in response to a read completion event of all data rows of the to-be-detected memory, and sending a pre-charge command.

10. The method of claim 1, wherein the method further comprises: if the comparison result is that the chip-recorded parameter is inconsistent with the memory parameter, determining that the chip-recorded parameter is not a real memory parameter, and sending the determined memory parameter to a corresponding input-output system chip of the to-be-detected memory; if the comparison result is that the chip-recorded parameter is consistent with the memory parameter, determining that the chip-recorded parameter is a real memory parameter, and starting a system board to run based on the chip-recorded parameter.

11. An information detection apparatus, comprising: a memory parameter determination module configured to determine a memory parameter corresponding to a to-be-detected memory; the memory parameter is determined based on at least one of an operation code and a test vector; a chip parameter acquisition module configured to acquire a chip-recorded parameter from a detection chip corresponding to the to-be-detected memory; a parameter comparison module configured to compare the memory parameter and the chip-recorded parameter for consistency, and obtain a comparison result, so as to determine the authenticity of the chip-recorded parameter according to the comparison result; wherein the memory parameter comprises a first memory parameter, and the determination of the memory parameter corresponding to the to-be-detected memory comprises: detecting a power-on state of a system board of a detection device; generating the operation code in response to detecting that the power-on state is a powered-on state. ​ ​ ​ ​ reading the first memory parameter from the to-be-detected memory through the operation code; the first memory parameter comprises manufacturer information and capacity information of the to-be-detected memory; The memory parameter further comprises a second memory parameter, and determining the memory parameter corresponding to the to-be-detected memory comprises: generating a test vector for obtaining the memory parameter; performing data read-write operation on the to-be-detected memory based on the test vector, and determining the second memory parameter according to a data read-write result; The second memory parameter comprises a working frequency, and the operation of determining the second memory parameter according to the data read-write result based on the test vector comprises: obtaining an initial working frequency vector, writing a register parameter into the initial working frequency vector to obtain a working frequency vector; the register parameter comprises a candidate working frequency of the to-be-detected memory; writing first test data into the to-be-detected memory based on the working frequency vector; reading the written first test data from the to-be-detected memory as first read-out data based on a candidate working frequency corresponding to the data write operation; taking the candidate working frequency, at which the first read-out data is consistent with the first test data, as a target working frequency.

12. An electronic device, characterized in that it comprises: a processor; and a memory having computer readable instructions stored thereon, the computer readable instructions, when executed by the processor, implement the information detection method according to any one of claims 1 to 10. ​ ​

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