Trimming method and bonding method

Abstract

The present application provides a trimming method and a bonding method, which are applied to multi-layer bonded wafers and include: providing a multi-layer bonded wafer, the multi-layer bonded wafer including an active area and a trimming area located outside the active area; removing a portion of the trimming area from the multi-layer bonded wafer, wherein the trimming area is an area extending outward from the edge of the active area by a specific width; and removing the remaining trimming area from the multi-layer bonded wafer. The trimming method and bonding method of the technical solution of the present application can solve the problem of defects in the bonding interface when removing the carrier wafer, facilitating subsequent processes and improving product yield.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a trimming method and a bonding method. Background Art

[0002] In existing multi-layer wafer stack bonding processes, both the front and back sides of the stack wafer need to be bonded. Therefore, a carrier wafer is required to assist with flipping and thinning the stack wafer. After bonding the stack wafer to the bottom wafer, the carrier wafer must be completely removed.

[0003] During the carrier wafer removal process, mechanical grinding is first used to remove most of the carrier wafer, and then acid is used to etch the remaining small amount of carrier wafer to reduce potential damage to the stacked wafers caused by mechanical forces. However, it should be noted that acid is isotropic during etching. While it has a high etching rate for the carrier wafer, it also has a certain etching rate for the remaining film layers. This can easily etch gaps at the bonding interface, affecting subsequent processes and yield. Summary of the Invention

[0004] The technical problem to be solved by this application is that the bonding interface will be damaged when removing the carrier wafer, affecting the subsequent process and product yield.

[0005] In order to solve the above technical problems, the present application provides a trimming method applied to a multi-layer bonded wafer, comprising: providing a multi-layer bonded wafer, wherein the multi-layer bonded wafer includes an effective area and a trimming area located outside the effective area; removing part of the multi-layer bonded wafer from the trimming area, wherein part of the trimming area is an area extending outward from the edge of the effective area to a specific width; and removing the remaining trimming area from the multi-layer bonded wafer.

[0006] In an embodiment of the present application, the multi-layer bonded wafer includes a bottom wafer and a plurality of bonded wafers located on the bottom wafer and stacked and distributed, and the edge of the multi-layer bonded wafer is stepped.

[0007] In an embodiment of the present application, the bottom wafer includes: a bottom bare wafer, the bottom bare wafer including a first surface; a first oxide layer, located on the first surface of the bottom bare wafer; a first nitride layer, located on the surface of the first oxide layer, serving as a bonding surface; the bottom bare wafer, the first oxide layer and the first nitride layer have the same width.

[0008] In an embodiment of the present application, the bonded wafer includes: a bonded bare wafer, the bonded bare wafer including a first surface and a second surface relative to each other; a second oxide layer, located on the first surface of the bonded bare wafer, serving as a first bonding surface; a third oxide layer, located on the second surface of the bonded bare wafer; a second nitride layer, located on the surface of the third oxide layer, serving as a second bonding surface; in the same bonded wafer, the widths of the bonded bare wafer, the second oxide layer, the third oxide layer and the second nitride layer are the same.

[0009] In the embodiment of the present application, the width of the trimming area increases sequentially from the top bonded wafer to the bottom wafer.

[0010] In an embodiment of the present application, the difference between the radius of the top bonded wafer and the bottom wafer is 2.5 mm-3 mm, the width of the trimming area of ​​the bottom wafer is 3.5 mm-4 mm, and the specific width is 2.9 mm-3.1 mm.

[0011] In the embodiment of the present application, the depth of the trimming area of ​​the bottom bare wafer is 45 μm-55 μm.

[0012] In an embodiment of the present application, a cutting process is used to remove the multi-layer bonded wafer in the trimming area.

[0013] In an embodiment of the present application, the blade width of the cutting process is equal to the specific width.

[0014] The present application also provides a bonding method, including: providing a bottom wafer and multiple bonding wafers, and each bonding wafer is bonded to a corresponding carrier wafer; with the help of the carrier wafer, the bonding wafers are bonded to the bottom wafer in sequence, wherein each time a bonding operation of a bonding wafer is completed, the corresponding carrier wafer is removed, and the next bonding operation is performed to form a multi-layer bonded wafer, the multi-layer bonded wafer includes an effective area and a trimming area located outside the effective area; the multi-layer bonded wafer is processed using the above-mentioned trimming method.

[0015] Compared with the prior art, the trimming method and bonding method of the technical solution of the present application have the following beneficial effects:

[0016] The trimming method of the technical solution of the present application is applied to a multi-layer bonded wafer, wherein the multi-layer bonded wafer includes an effective area and a trimming area located outside the effective area, wherein the bonding interface of the multi-layer bonded wafer located in the trimming area has a long strip-shaped gap caused by wet etching. By first removing the multi-layer bonded wafer in an area extending outward from the edge of the effective area with a specific width, and then removing the multi-layer bonded wafer in the remaining trimming areas, the electrical risks caused by the existence of the long strip-shaped gaps can be effectively solved, and the occurrence of fragmentation can be reduced, the risk of breakage can be reduced, and the subsequent process can be carried out, which greatly improves the product yield. The trimming method is simple to operate and easy to control the process.

[0017] The bonding method of the technical solution of the present application adds a trimming process for the multi-layer bonded wafer after forming the multi-layer bonded wafer, thereby greatly improving the bonding quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The following figures describe in detail exemplary embodiments disclosed in this application. Identical reference numerals denote similar structures in several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the same inventive intent as described in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0019] Figures 1 to 6 It is a structural schematic diagram of each step of a method for manufacturing a multi-layer bonded wafer;

[0020] Figure 7 A schematic flow chart of a trimming method according to an embodiment of the present application;

[0021] Figures 8 to 14 This is a structural schematic diagram of each step of the bonding method according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0023] refer to Figure 1A method for manufacturing a multi-layer bonded wafer includes: bonding a bonded wafer to a carrier wafer, wherein the bonded wafer includes a bonded bare wafer 20, the bonded bare wafer 20 includes a crystal face and a crystal back, a bonding layer 21 is formed on the crystal face, and the bonding layer 21 can be a multi-layer structure, which is not particularly limited here; the carrier wafer includes a carrier bare wafer 10 and a bonding layer 11 located on the surface of the carrier bare wafer 10, and bonding marks (not shown in the figure) are formed in the bonding layer 21 and the bonding layer 11 for alignment during bonding. Before bonding the carrier wafer and the bonded wafer, the bonded wafer is subjected to a first trimming process to reduce the probability of defects on the edge of the bonded wafer during bonding.

[0024] refer to Figure 2 and Figure 3 The bonded bare wafer 20 is thinned on its back side, and a bonding layer 22 is formed on the back surface of the thinned bonded bare wafer 20. A mark for bonding alignment may also be formed in the bonding layer 22. The bonded wafer is then subjected to a second trimming process. The second trimming process trims the carrier wafer to facilitate subsequent removal of the carrier wafer.

[0025] refer to Figure 4 Then, the bonded wafer with the carrier wafer is bonded to the bottom wafer. The bottom wafer includes a bottom bare wafer 30, a bonding layer 31 is formed on the surface of the bottom bare wafer 30, and a bonding mark may also be formed in the bonding layer 31.

[0026] refer to Figure 5 and Figure 6 , the carrier wafer is removed by mechanical grinding and wet etching. First, most of the carrier bare wafer 10 is removed by mechanical grinding, and then the remaining carrier bare wafer 10 and the bonding layer 11 are removed by a wet etching process. The surface of the exposed bonding layer 21 is used as the bonding surface of the bonding wafer for the next bonding. Because the etching solvent will gather at the right-angle step at position A when the carrier wafer is removed by the wet etching process, and will etch along the bonding interface to form long strip-shaped gaps, which greatly reduces the yield of the product. If position A is trimmed before removing the carrier wafer to remove the right-angle step and prevent the etching solvent from gathering at the step, although it can have a certain effect, it is necessary to add multiple trimming processes for forming a multi-layer bonded wafer, which increases the complexity of the process and makes the final trimming width larger, wasting wafer space.

[0027] Based on this, the technical solution of the present application provides a trimming method and a bonding method. After forming a multi-layer bonded wafer, a third trimming process is performed to remove long strip gaps. In order to further reduce the fragmentation phenomenon caused by the trimming process, the multi-layer bonded wafer in part of the trimming area adjacent to the effective area is first removed, and then the multi-layer bonded wafer in the remaining trimming area is removed, which can effectively reduce the risk of fragmentation.

[0028] The trimming method and bonding method of the technical solution of the present application are described in detail below through specific embodiments and drawings.

[0029] The bonding method of an embodiment of the present application includes:

[0030] Step S1: providing a bottom wafer and a plurality of bonding wafers, wherein each bonding wafer is bonded to a corresponding carrier wafer;

[0031] Step S2: using the carrier wafer, sequentially bonding the bonding wafer to the bottom wafer, wherein each time a bonding operation of a bonding wafer is completed, the corresponding carrier wafer is removed, and the next bonding operation is performed to form a multi-layer bonded wafer, wherein the multi-layer bonded wafer includes an active area and a trimming area located outside the active area;

[0032] Step S3: Processing the multi-layer bonded wafer using the trimming method of an embodiment of the present application.

[0033] refer to Figure 7 , the trimming method of the embodiment of the present application includes:

[0034] Step S31: providing a multi-layer bonded wafer, wherein the multi-layer bonded wafer includes an active area and a trimming area located outside the active area;

[0035] Step S32: removing a portion of the trimmed area of ​​the multi-layer bonded wafer, where the trimmed area is a region extending outward from the edge of the active area to a specific width;

[0036] Step S33: removing the multi-layer bonded wafer from the remaining trimming areas.

[0037] refer to Figure 8 and Figure 9, providing a bottom wafer 300 and a plurality of bonding wafers 200. The bottom wafer 300 includes a bottom bare wafer 310, a first oxide layer 320 and a first nitride layer 330, the bottom bare wafer 310 includes a first surface, the first oxide layer 320 is located on the first surface of the bottom bare wafer 310, the first nitride layer 330 is located on the surface of the first oxide layer 320, wherein the first nitride layer 330 serves as a bonding surface. The material of the first oxide layer 320 may include silicon oxide, such as TEOS, and the material of the first nitride layer 330 may include silicon nitride. A bonding mark may be formed in the first oxide layer 320, for example, a metal bonding mark may be formed. In an embodiment of the present application, the bottom bare wafer 310, the first oxide layer 320 and the first nitride layer 330 have the same width.

[0038] The bonded wafer 200 includes a bonded bare wafer 210, a second oxide layer 220, a third oxide layer 230, and a second nitride layer 240. The bonded bare wafer 210 includes a first surface and a second surface relative to each other. The second oxide layer 220 is located on the first surface of the bonded bare wafer 210 and serves as a first bonding surface. The first bonding surface is used to bond with the bottom wafer 300. In an embodiment of the present application, a groove is further formed in the second oxide layer 220, and the groove serves as a bonding mark. The third oxide layer 230 is located on the second surface of the bonded bare wafer 210. A metal bonding mark may be formed in the third oxide layer 230. The second nitride layer 240 is located on the surface of the third oxide layer 230 and serves as a second bonding surface. The second bonding surface serves as the bonding surface when the bonded wafer 200 is bonded to the carrier wafer 300. The materials of the second oxide layer 220 and the third oxide layer 230 may include silicon oxide, such as TEOS, and the material of the second nitride layer 240 may include silicon nitride. The bonded bare wafer 210 , the second oxide layer 220 , the third oxide layer 230 , and the second nitride layer 240 have the same width.

[0039] Continue to refer to Figure 9 , each bonded wafer 200 is bonded to a corresponding carrier wafer 100. In the embodiment of the present application, the carrier wafer 100 includes a carrier bare wafer 110 and an oxide layer 120 located on the surface of the carrier bare wafer 110, and the oxide layer 120 serves as a bonding layer. The material of the oxide layer 120 can be the same as that of the second oxide layer 220 and the third oxide layer 230. The width of the bonded wafer 200, the oxide layer 120, and part of the carrier bare wafer 110 is the same, and is smaller than the width of the remaining part of the carrier bare wafer 110, forming a step shape.

[0040] refer to Figure 10Using the carrier wafer 100, one of the bonding wafers 200 is first bonded to the bottom wafer 300. During bonding, the bonding wafer 200 is placed on top and the bottom wafer 300 is placed on the bottom. The grooves in the second oxide layer 220 are aligned with the metal bonding marks in the third oxide layer 230. The bonding wafer 200 and the bottom wafer 300 are then bonded together via the second oxide layer 220 of the bonding wafer 200 and the first nitride layer 330 of the bottom wafer 300.

[0041] refer to Figure 11 After bonding the bonding wafer 200 to the bottom wafer 300, the carrier wafer 100 needs to be removed. Specifically, a portion of the carrier bare wafer 110 can be removed by mechanical grinding, and then the remaining carrier bare wafer 110 and oxide layer 120 can be removed by wet etching. During the wet etching process, the etching solution will accumulate on the step at position a and corrode the bonding interface to form a long strip-shaped gap.

[0042] refer to Figure 12 , repeat the aforementioned bonding method to bond the remaining bonded wafers 200 on the bottom wafer 300 in sequence. It should be noted that each time a bonding operation of a bonded wafer is completed, the corresponding carrier wafer needs to be removed before the next bonding operation is performed to form a multi-layer bonded wafer. Due to the aforementioned wet etching process, long strip-shaped gaps appear on the bonding interface of each layer of the bonded wafer 200. Therefore, the multi-layer bonded wafer can be divided into an effective area B and a trimming area C located outside the effective area B. The effective area B refers to the area required for manufacturing the device, and the trimming area C refers to the area that needs to be removed due to defects or other reasons when manufacturing the device. The bottom wafer 300 has the largest width, and the width of each bonded wafer 200 gradually decreases from bottom to top, so that the edge of the multi-layer bonded wafer is stepped. This is formed by the trimming process of the bonded wafer 200 and will not be repeated here. In order to ensure that the long strip-shaped gaps can be completely removed, the width of the trimming area C of the bottom wafer 300 is 3.5mm-4mm. In the embodiment of the present application, three bonded wafers 200 are bonded as an example for illustration. In other embodiments, four bonded wafers 200 or more bonded wafers can also be bonded. Due to the width variation law of each bonded wafer and the bottom wafer, the width of the trimming area C increases sequentially from the top bonded wafer to the bottom wafer 300. In some embodiments, the difference between the radius of the top bonded wafer and the bottom wafer 300 is 2.5mm-3mm.

[0043] After forming the multi-layer bonded wafer, a third trimming process is performed, wherein the third trimming process adopts the trimming method of the embodiment of the present application.

[0044] Continue to refer Figure 12 , providing a multi-layer bonded wafer, that is, providing the multi-layer bonded wafer manufactured as described above. The multi-layer bonded wafer includes an active area B and a trimming area C located outside the active area B.

[0045] refer to Figure 13 , remove part of the multi-layer bonded wafer in the trimming area, and for convenience, the part of the trimming area will be referred to as the first part C1 of the trimming area. It should be noted that the first part C1 of the trimming area is an area that extends outward from the edge of the effective area B to a specific width, rather than an area that extends inward from the edge of the trimming area to a specific width. This is because, if the multi-layer bonded wafer that extends inward from the edge of the trimming area to a specific width is removed first, and then the multi-layer bonded wafer in the remaining trimming areas is removed, defects such as fragments and cracks are very likely to occur, increasing the process risk. If the area that extends outward from the edge of the effective area B to a specific width is removed first, and then the remaining trimming areas are removed, this will not only reduce the generation of large-sized fragments, but also successfully remove the long strip-shaped gaps at the bonding interface.

[0046] The specific width is related to the removal process. In the embodiment of the present application, the process for removing the first portion C1 of the trimming area is a cutting process, and the blade width of the cutting process is equal to the specific width, and the blade width can be between 2.9 mm and 3.1 mm, for example, the blade width is 3 mm.

[0047] Next, the multi-layer bonded wafer in the remaining trimming area is removed in the same manner as the removal of the first portion C1 of the trimming area, which will not be described in detail here.

[0048] refer to Figure 14 , which shows the structure of the multi-layer bonded wafer after trimming. During trimming, the first oxide layer 320 and the first nitride layer 330 of all bonded wafers 200 and the bottom wafer 300 are penetrated in the depth direction, but the bottom bare wafer 310 is not penetrated. In some embodiments, the trimming depth of the bottom bare wafer 310 is 45μm-55μm to ensure that the long strip gaps are completely removed.

[0049] The trimming and bonding methods of the present invention address the problem of long, strip-shaped gaps at the bonding interface of multi-layer bonded wafers, effectively eliminating the electrical risks associated with these gap defects. Furthermore, the trimming method not only completely removes these long, strip-shaped gaps, but also reduces the generation of debris, lowering the risk of breakage and adverse effects on subsequent processes, significantly improving product yield.

[0050] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0051] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may also be present.

[0052] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, the term "directly" indicates that there are no intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0053] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0054] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A trimming method, applied to a multi-layer bonded wafer, characterized in that: include: A multi-layer bonded wafer is provided, the multi-layer bonded wafer comprising an active area and a trimming area located outside the active area, the multi-layer bonded wafer comprising a bottom wafer and at least two bonded wafers located on the bottom wafer and stacked, the edges of any adjacent bonded wafers in the multi-layer bonded wafer and the edges of the bottom wafer and adjacent bonded wafers all being stepped, and the width of the trimming area increases sequentially from the top bonded wafer to the bottom wafer; Removing a portion of the trimmed area of ​​the multi-layer bonded wafer, wherein the trimmed area is a region extending outward from an edge of the active area to a specific width; The multi-layer bonded wafer is then removed from the remaining trimmed area.

2. The trimming method according to claim 1, characterized in that: The bottom wafer includes: a bottom bare wafer, the bottom bare wafer including a first surface; a first oxide layer, located on a first surface of the bottom bare wafer; a first nitride layer, located on a surface of the first oxide layer and serving as a bonding surface; The bottom bare wafer, the first oxide layer, and the first nitride layer have the same width.

3. The trimming method according to claim 2, characterized in that: The bonded wafer includes: a bonded bare wafer, the bonded bare wafer including a first surface and a second surface opposite to each other; a second oxide layer, located on the first surface of the bonded bare wafer, serving as a first bonding surface; a third oxide layer, located on the second surface of the bonded bare wafer; a second nitride layer, located on a surface of the third oxide layer, serving as a second bonding surface; In the same bonded wafer, the bonded bare wafer, the second oxide layer, the third oxide layer and the second nitride layer have the same width.

4. The trimming method according to claim 1, characterized in that: The difference between the radius of the top bonding wafer and the bottom wafer is 2.5 mm to 3 mm, the width of the trimming area of ​​the bottom wafer is 3.5 mm to 4 mm, and the specific width is 2.9 mm to 3.1 mm.

5. The trimming method according to claim 2, characterized in that: The depth of the trimming area of ​​the bottom bare wafer is 45 μm-55 μm.

6. The trimming method according to claim 1, characterized in that: The multi-layer bonded wafer in the trimming area is removed by a cutting process.

7. The trimming method according to claim 6, characterized in that: The blade width of the cutting process is equal to the specific width.

8. A bonding method, characterized in that: include: Providing a bottom wafer and a plurality of bonding wafers, wherein each bonding wafer is bonded to a corresponding carrier wafer; The bonding wafers are sequentially bonded to the bottom wafer using the carrier wafer, wherein each time a bonding operation of a bonding wafer is completed, the corresponding carrier wafer is removed and the next bonding operation is performed to form a multi-layer bonded wafer, wherein the multi-layer bonded wafer includes an active area and a trimming area located outside the active area; The multi-layer bonded wafer is processed using the trimming method described in any one of claims 1 to 7.

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