Method for preparing a semiconductor device

Abstract

The present invention discloses a method for preparing a semiconductor device, comprising: providing a substrate, the substrate comprising a substrate layer on which a gate structure and an active structure are arranged; depositing a first dielectric layer on the substrate; forming a connecting member, comprising: opening a one-time opening penetrating the first dielectric layer for exposing the gate structure and / or the active structure, depositing a conductive material in the opening to form a connecting member connecting the gate structure and / or the active structure; forming a metal layer on the first dielectric layer and the connecting member, the metal layer being connected to the gate structure and / or the active structure via the connecting member. The present invention can save a large number of photomasks, save the middle process in the traditional method, shorten the process flow, and use a single connecting member to avoid the problem of misalignment.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a method for preparing a semiconductor device. Background Art

[0002] With the miniaturization and high integration of semiconductor devices, problems such as small processing windows, control of critical dimension uniformity (CDU), control of overlap deviation (OVL), and the use of too many masks have gradually become bottlenecks in mass production.

[0003] In the prior art, the connection structure of semiconductor devices generally involves connecting the substrate layer to the metal layer above it via a contact structure, and forming a connection between the substrate and the metal layer via a conductive structure. In particular, in high-volume semiconductor manufacturing, the structural design involved includes metal conductors (MD) connecting the active area, metal conductors (MP) connecting the gate area, via-contact connections (VC), and spacers (CMD).

[0004] Combine Figure 1 , the existing method for preparing semiconductor devices is,

[0005] S101. Provide a substrate, the substrate specifically comprising: a substrate layer 11', a barrier layer 14', a dielectric layer 15', and a termination layer 16'. An active structure 12' and a gate structure 13' are provided on the substrate layer 11'. The barrier layer 14' abuts against sidewalls of the gate structure 13' and covers the upper surface of a portion of the substrate layer 11' located between the gate structures 13' and the upper surface of the active structure 12'. The barrier layer 14' is flush with the gate structures 13' and is recessed inwardly to form a groove located between the gate structures 13'. The dielectric layer 15' fills the groove and is flush with the gate structures 13'. The termination layer 16' covers the gate structure 13', the barrier layer 14', and the dielectric layer 15'.

[0006] S102, depositing a dielectric layer 21' on the substrate;

[0007] S103 , forming contact holes 30 ′ through the dielectric layer 21 ′, the stopper layer 16 ′, and / or the dielectric layer 15 ′ and the barrier layer 14 ′. Specifically, first forming a first type of contact hole exposing a predetermined area of ​​the active structure 12 ; then forming a second type of contact hole exposing a predetermined area of ​​the gate structure 13 .

[0008] S104 , filling the contact hole 30 ′ and planarizing the hole to form a contact structure 31 ′ including a liner layer and a contact.

[0009] S105 , depositing a stop layer 212 ′ on the dielectric layer 21 ′ and the contact structure 31 ′, and then depositing a dielectric layer 22 ′ on the stop layer 212 ′.

[0010] S6. Using a dual damascene process, first, a trench 50' is etched on the dielectric layer 22', and then a through hole 50' is formed penetrating the stop layer 212' and the dielectric layer 22'. Metal material is filled in the through hole 50' and the trench and then planarized to form a conductive member 5' and a metal layer 4'.

[0011] The above-mentioned fabrication method has drawbacks: it requires at least three types of photomasks, and the formation of contact holes, vias, and metal trenches requires at least two photolithography steps and multiple etching steps, making the process cumbersome. Furthermore, the contact and via components are prone to misalignment, a problem that is becoming increasingly serious with the current trend toward miniaturization. This misalignment can lead to deviations and poor uniformity in the critical dimensions of the resulting device and also creates significant parasitic capacitance. Summary of the Invention

[0012] The technical problem to be solved by the present invention is to provide a method for preparing a semiconductor device in view of the defects of the prior art in that the preparation process is complicated and misalignment of contact components and conducting components is likely to occur.

[0013] The technical solution adopted by the present invention to solve the technical problem is to construct a method for preparing a semiconductor device, the method comprising:

[0014] Step 1: providing a substrate, wherein the substrate includes a substrate layer on which a gate structure and an active structure are arranged;

[0015] Step 2: depositing a first dielectric layer on the substrate;

[0016] Step three, forming a connecting member, including: opening a first opening penetrating through the first dielectric layer to expose the gate structure and / or the active structure, and depositing a conductive material in the opening to form a connecting member connecting the gate structure and / or the active structure;

[0017] In step four, a metal layer is formed above the first dielectric layer and the connecting member, and the gate structure and / or active structure that need to be connected to the metal layer are connected to the metal layer via the connecting member.

[0018] Preferably, the method further includes: in step three, for the gate structure and active structure that need to be connected to the metal layer, an opening is opened once for them to pass through the first dielectric layer, and a conductive material is deposited in the opening to form a connecting component connecting the gate structure and / or the active structure.

[0019] Preferably, the first dielectric layer includes a lower interlayer dielectric layer and an upper interlayer dielectric layer, and the step 2 specifically includes: depositing the lower interlayer dielectric layer on the substrate, and depositing the upper interlayer dielectric layer on the lower interlayer dielectric layer;

[0020] The method further includes: after forming the lower interlayer dielectric layer in step 2, for a portion of the gate structures or / and active structures that need to be connected to the metal layer, openings penetrating the lower interlayer dielectric layer are opened for them, and conductive material is deposited in the openings to form contact members; in step 3, for the remaining portion of the gate structures or / and active structures that need to be connected to the metal layer, openings penetrating the lower interlayer dielectric layer and the upper interlayer dielectric layer are opened at once, and conductive material is deposited in the openings to form connecting members; and, a conducting member penetrating the upper interlayer dielectric layer for connecting to the contact member is formed.

[0021] Preferably, the depositing of the conductive material in the opening includes: first depositing a layer of conductive material on the entire bottom surface and part / entire side surface of the opening to form a liner layer, and then depositing the conductive material in the opening until the entire opening is filled.

[0022] Preferably, the method further includes: when forming the connecting member, filling the openings opened along the depth direction of the first dielectric layer in batches to form at least two layers of connecting structures stacked along the depth direction of the first dielectric layer, first forming the bottommost layer of connecting structure abutting the gate structure and / or active structure, and finally forming the topmost layer of connecting structure abutting the metal layer.

[0023] Preferably, the batch filling to form at least two layers of connection structures stacked along the depth direction of the first dielectric layer includes:

[0024] The non-top connection structure forming step includes: depositing a preliminary liner layer having a groove along the bottom and sidewalls of the opening by atomic layer deposition, and filling the groove with a dummy part; etching the preliminary liner layer and the dummy part to a desired height; removing the dummy part to expose the groove, and filling the groove with a metal material; etching the metal material to a desired height to obtain a layer of connection structure; if a non-top connection structure is to be formed next, the non-top connection structure forming step is performed again; otherwise, the top connection structure forming step is performed as follows:

[0025] The step of forming a top connection structure is as follows: depositing the materials of the liner layer and the connection member in sequence in the opening provided with the connection structure and on the surface of the first dielectric layer, and then removing the excess material by planarization to expose the surface of the first dielectric layer and form the topmost connection structure in the opening.

[0026] Preferably, step four specifically includes: forming a continuous stop layer above the first dielectric layer and the connecting member; etching the stop layer, filling and forming a metal layer that penetrates the stop layer, and the gate structure and / or active structure that needs to be connected to the metal layer are connected to the metal layer via the connecting member.

[0027] Preferably, the etching stop layer is filled to form a metal layer that penetrates the stop layer, specifically including: etching a groove that penetrates the stop layer in a continuous stop layer through photolithography to expose a connecting component that needs to be connected to the metal layer to form a patterned stop layer; depositing continuous metal in and above the groove of the patterned stop layer, and exposing the patterned stop layer through planarization to form a patterned metal layer.

[0028] Preferably, in step three, when forming the opening, the opening exposing the predetermined area of ​​the active structure is formed first, and then the opening exposing the predetermined area of ​​the gate structure is formed.

[0029] Preferably, the substrate further comprises a barrier layer, a second dielectric layer and a termination layer; the barrier layer abuts against the sidewalls of the gate structure and covers the upper surface of the portion of the substrate layer located between the gate structures and the upper surface of the active structure, the barrier layer is flush with the gate structure, and the barrier layer is recessed inward to form a groove located between the gate structures; the second dielectric layer fills the groove and is flush with the gate structure; the termination layer covers the gate structure, the barrier layer and the second dielectric layer;

[0030] The forming of the opening to expose the predetermined area of ​​the active structure includes: opening an opening through the first dielectric layer, the stop layer, the second dielectric layer, and the barrier layer to expose the predetermined area of ​​the active structure;

[0031] The forming of the opening to expose the predetermined region of the gate structure includes: opening an opening penetrating through the first dielectric layer and the termination layer to expose the predetermined region of the gate structure.

[0032] The semiconductor device fabrication method of the present invention has the following advantageous effects: the present invention only requires two types of photomasks. Accordingly, the present invention can save a large number of photomasks in the manufacturing process when applied to a production line. In the prior art, a dual damascene process is used to form the conductive member and the metal layer, which is a cumbersome process and easily causes device defects. For example, after first forming the trench, the photoresist required for forming the via hole easily accumulates in the trench. In contrast, the present invention uses a single damascene process to form the connecting member and the metal layer, which has high process stability. The present invention eliminates the middle-of-line (MEOL) process in the conventional method, shortens the process flow, and significantly reduces the production cycle. Furthermore, semiconductor devices formed by the prior art fabrication method are prone to misalignment between the contact member and the conductive member, which seriously affects device formation. In contrast, the present invention uses a single connecting member to connect the metal layer to the gate structure / active structure, reducing the possibility of misalignment. Because the mid-of-line process often requires the use of a large number of photomasks, it is prone to multiple misalignment problems and has a small process window. Each photomask saved can avoid one misalignment problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only embodiments of the present invention. Those skilled in the art can also derive other drawings based on the provided drawings without inventive work.

[0034] Figure 1 It is a schematic diagram of the existing semiconductor device preparation process;

[0035] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

[0036] Figure 3 is a cross-sectional view of the substrate provided in step S101 in Example 1;

[0037] Figure 4 This is a schematic diagram after the first dielectric layer is formed in step S102 in embodiment 1;

[0038] Figure 5 is a schematic diagram of the opening opened in step S1031 in Example 1;

[0039] Figure 6 This is a schematic diagram after the connecting member is formed in step S1032 in the first embodiment;

[0040] Figure 7 is a schematic diagram of the second form of connecting member;

[0041] Figure 8is a schematic diagram of the third form of connecting member;

[0042] Figure 9 is a schematic diagram of the fourth form of connecting member;

[0043] Figure 10 is a schematic diagram of the metal layer formed after steps S104 and S105 in Example 1;

[0044] Figure 11 It is a cross-sectional view of the semiconductor device finally manufactured in Example 2. DETAILED DESCRIPTION

[0045] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The drawings illustrate exemplary embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present invention.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. It should be noted that the terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only.

[0047] As used in this specification, terms containing ordinal numbers such as "first" and "second" may be used to describe various components, but these components are not limited by these terms. The purpose of using these terms is only to distinguish one component from other components. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0048] The general idea of ​​the present invention is: after depositing a first dielectric layer on a substrate, a separate connecting member is designed, which directly penetrates the first dielectric layer and connects to the gate structure and / or the active structure. A single connecting member is used to connect the metal layer with the gate structure and the active structure, which can reduce the use of a large number of masks and save the middle of line (MEOL) process in traditional methods, shortening the process flow and greatly reducing the production cycle. In addition, the semiconductor device obtained by this method can greatly reduce the occurrence of misalignment.

[0049] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the drawings and specific implementation methods of the specification. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations on the technical solution of the present application. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0050] Example 1

[0051] This example is to prepare Figure 10 The semiconductor device shown includes a substrate, a first dielectric layer, a connecting member 3, a stop layer 4, and a metal layer 41. The substrate serves as the first layer, the first dielectric layer serves as the second layer, and the stop layer 4 and metal layer 41 serve as the third layer. Connecting member 3 is a conductive member that penetrates the second layer to connect the structures that need to be connected between the first and third layers.

[0052] The semiconductor device manufacturing method of this embodiment includes:

[0053] S101: Provide a substrate.

[0054] like Figure 3 The substrate includes a base layer 11 , a barrier layer 14 , a second dielectric layer 15 and a termination layer 16 .

[0055] A gate structure 13 and an active structure 12 are provided on the substrate layer 11. The active structure 12 includes source and drain structures. The present invention primarily improves the connection between the gate structure 13 and the active structure 12 in the first layer and the metal layer 41 in the third layer. The gate structure 13 and the active structure 12 are common knowledge in the art and will not be further described here.

[0056] The barrier layer 14 abuts the sidewalls of the gate structure 13 and covers the upper surface of the portion of the substrate layer 11 located between the gate structures 13 and the upper surface of the active structure 12. The barrier layer 14 is flush with the gate structure 13 and is recessed inward to form a groove located between the gate structures 13.

[0057] The second dielectric layer 15 fills the groove of the barrier layer 14 and is flush with the gate structure 13 .

[0058] The termination layer 16 covers the gate structure 13 , the barrier layer 14 , and the second dielectric layer 15 .

[0059] S102: depositing a first dielectric layer on the substrate.

[0060] refer to Figure 4 The first dielectric layer includes a lower interlayer dielectric layer 21 and an upper interlayer dielectric layer 22. This step mainly includes:

[0061] S1021, forming a lower interlayer dielectric layer 21 by deposition on the substrate, wherein the lower interlayer dielectric layer 21 is made of a low-K dielectric material;

[0062] S1022 , forming an upper interlayer dielectric layer 22 by deposition on the lower interlayer dielectric layer 21 , wherein the upper interlayer dielectric layer 22 is made of an extremely low-K (ELK) dielectric material, such as a dielectric material having a K value (ie, a dielectric constant value) less than 2.9.

[0063] S103, forming a connecting member 3, including:

[0064] S1031, open an opening 30 penetrating the upper interlayer dielectric layer 22 and the lower interlayer dielectric layer 21 to expose the gate structure 13 and / or the active structure 12. Figure 5 When forming the opening 30, the opening 30 is first formed through the upper interlayer dielectric layer 22, the lower interlayer dielectric layer 21, the termination layer 16, the second dielectric layer 15, and the barrier layer 14 to expose a predetermined area of ​​the active structure 12, and then the opening 30 is formed through the upper interlayer dielectric layer 22, the lower interlayer dielectric layer 21, and the termination layer 16 to expose a predetermined area of ​​the gate structure 13.

[0065] The so-called one-time penetration means that the opening is opened once. In the prior art, the openings of the contact components and the conductive components are opened in steps. However, in the present invention, after forming the upper interlayer dielectric layer 22 and the lower interlayer dielectric layer 21, the opening can be opened in one step without the need for opening in batches.

[0066] It should be noted that in the prior art, because the contact component and the conductive component are formed in two steps, the corresponding first dielectric layer in the prior art must be formed twice. Although the first dielectric layer in the present invention is formed in two steps in this embodiment, it is actually also possible to use a dielectric layer formed in one step.

[0067] It is understandable that the connecting member 3 can also connect the gate structure 13 and the active structure 12 at the same time. This structure is an adjacent structure, for example Figure 6 In the figure, the gate structure 13 and the active structure 12 on the left are connected to the metal layer 41 through independent connecting members 3, while the gate structure 13 and the active structure 12 on the right are connected to the metal layer 41 through the same connecting member 3. The connecting member 3 on the right realizes the function of the adjacent structure, and the corresponding opening is Figure 5 The opening on the right side of the middle is also opened by first opening the portion exposing the predetermined area of ​​the active structure 12 and then opening the portion exposing the predetermined area of ​​the gate structure 13.

[0068] Furthermore, the opening forming the connecting member 3 gradually increases in diameter from bottom to top. Accordingly, the peripheral wall of the connecting member 3 forms an acute angle with the horizontal plane of the substrate. For example, in this embodiment, the angle between the peripheral wall of the connecting member 3 and the horizontal plane of the substrate is 65° to 90°. In the prior art, the peripheral wall of the contact member forms a rounded or chamfered corner with the bottom surface of the metal layer 41. However, in the present invention, the connecting member 3 forms a turning angle with the bottom surface of the metal layer 41.

[0069] S1032, depositing a conductive material in the opening 30 and planarizing the material to form a connecting member 3 connecting the gate structure 13 and / or the active structure 12, as shown in FIG. Figure 6 shown.

[0070] The conductive material is tungsten, copper, cobalt, rubidium, molybdenum, or an alloy of the above components.

[0071] In this embodiment, the connecting member 3 is actually a separate exposed connecting member without a lining layer. Figure 7 The connection member 3 may also be composed of a connection member 32 and a liner layer 31 covering the bottom and sidewalls of the connection member 32. Accordingly, the method of the present invention further comprises: first depositing a layer of conductive material on the entire bottom surface and part / the entire side surface of the opening to form the liner layer 31, and then depositing conductive material in the opening until the entire opening is filled to form the connection member 32. The liner layer 31 and the connection member 32 together constitute the connection member 3.

[0072] The material of the liner layer 31 is at least one of a single metal, a metal alloy, a metal nitride, and a metal silicide, such as titanium, titanium nitride, or a copper-manganese compound. Depending on the silicon material in the dielectric layer, a metal silicide, such as a titanium-silicon compound or a manganese-silicon compound, can also be selectively grown. For example, in step S1032, before filling the entire opening with the conductive material, a selective growth process for a titanium-silicon compound can be added. Titanium is deposited in the opening and, under high temperature conditions, forms a titanium-silicon compound (liner layer) with the silicon in the dielectric layer to reduce the resistance of the device.

[0073] Figure 7 The lining layer 31 covers the bottom and side walls of the entire coupling 32. Figure 8 In other embodiments, only the bottom and part of the sidewall of the connector 32 may be covered. The liner layer 31 serves to act as an adhesive, improving the bonding force between the connector 32 and the dielectric layer, while preventing or slowing down the diffusion of elements in the connector 32.

[0074] Considering that during the production process of the connecting member 3, it is necessary to open holes in the depth direction of the upper interlayer dielectric layer 22 and the lower interlayer dielectric layer 21, so the depth of the opening is deep, and it is easy to cause problems such as filling gaps when filling metal materials in the later stage. Figure 9 , the manufacturing process of the connection member 3 can be optimized. Specifically, the method further includes: when forming the connection member 3, the opening 30 opened along the depth direction of the first dielectric layer is filled in batches to form at least two layers of connection structures stacked along the depth direction of the first dielectric layer, first forming the bottom layer of connection structure abutting the gate structure 13 and / or the active structure 12, and finally forming the top layer of connection structure abutting the metal layer 41. For example, Figure 9 Taking the three-layer connection structure as an example, the manufacturing process of the three-layer connection structure is:

[0075] First, a bottom layer of connection structure is produced: a preliminary liner layer with a groove is deposited along the bottom and sidewalls of the opening by atomic layer deposition, and a dummy part is filled in the groove; a first liner layer is formed by etching the preliminary liner layer and the dummy part to a desired height; the dummy part is removed to expose the groove, and a metal material is filled in the groove; the metal material is etched to a desired height to form a bottom layer of connection structure.

[0076] Then, a middle layer of connection structure is made: in the opening provided with the bottommost connection structure, a preliminary liner layer with a groove is deposited along the bottom and sidewalls of the opening by atomic layer deposition, and a dummy part is filled in the groove; a second liner layer is formed by etching the preliminary liner layer and the dummy part to a desired height; the dummy part is removed to expose the groove, and a metal material is filled in the groove; the metal material is etched to a desired height to form a middle layer of connection structure.

[0077] Finally, the topmost connection structure is produced: the materials of the liner layer and the connection member are sequentially deposited in the opening provided with the intermediate connection structure and on the surface of the upper interlayer dielectric layer 22, and the excess material is removed by chemical mechanical planarization to expose the surface of the upper interlayer dielectric layer 22 and form the topmost connection structure in the opening.

[0078] In this way, the connection member 3 is split into a multi-layer connection structure to achieve this. The use of a multi-layer connection structure can avoid problems such as filling gaps caused by an excessively large aspect ratio of the opening, thereby improving the filling quality.

[0079] S104 , forming a metal layer 41 above the first dielectric layer and the connecting member 3 , and the gate structure 13 and / or the active structure 12 that need to be connected to the metal layer 41 are connected to the metal layer 41 via the connecting member 3 .

[0080] Specifically, a continuous stop layer 4 is formed above the upper interlayer dielectric layer 22 and the connecting member 3. By photolithography, a groove penetrating the stop layer 4 is etched in the continuous stop layer 4 to expose the connecting member 3 that needs to be connected to the metal layer 41, thereby forming a patterned stop layer 4. A continuous metal is deposited in and above the groove of the patterned stop layer 4, and planarization is performed to expose the patterned stop layer 4 and form a patterned metal layer 41. The semiconductor device finally obtained in this embodiment is as follows: Figure 10 shown.

[0081] It should be noted that the method of forming the metal layer is not limited to the method of this embodiment. In this embodiment, because the aspect ratio of the opening corresponding to the connecting component is too high, from the perspective of process efficiency and operability, the above method is most likely to be adopted. In fact, other methods can also be used as long as a patterned metal layer can be formed. For example, referring to the formation process of the conductive component, through openings and grooves can be formed on the first dielectric layer, and the openings and grooves are filled to form the connecting component and the metal layer.

[0082] Example 2

[0083] In the aforementioned first embodiment, in step S103, for the gate structure 13 and the active structure 12 that need to be connected to the metal layer 41, an opening 30 is opened that penetrates the first dielectric layer. A conductive material is deposited in the opening 30 to form a connecting member 3 connecting the gate structure 13 and / or the active structure 12. That is, the connecting member 3 is applied to the connection between the gate structure 13 and the metal layer 41, and the connection between the active structure 12 and the metal layer 41. It is understandable that the connecting member 3 involved does not necessarily need to be applied to connect the gate structure 13 and the active structure 12 at the same time. It can be applied to only one of the gate structure 13 and the active structure 12 and the metal layer 41, while the other maintains the original contact member and conductive member connection scheme, specifically designed according to the device requirements. Therefore, in other embodiments, the gate structure 13 and the active structure 12 in the semiconductor device that need to be connected to the metal layer 41 can be partially connected to the metal layer 41 through the corresponding connecting member 3, and the rest can be connected to the metal layer 41 through the contact member and conductive member. The second embodiment is for preparing such a semiconductor device.

[0084] The main differences between this embodiment and the first embodiment are:

[0085] 1) After forming the lower interlayer dielectric layer 21 in step S102 of the first embodiment, for the gate structure 13 and / or the active structure 12 that need to be connected to the metal layer 41, an opening is opened through the lower interlayer dielectric layer 21, and a conductive material is deposited in the opening to form a contact member.

[0086] 2) In step S103 of the first embodiment, for the remaining gate structures 13 and / or active structures 12 that need to be connected to the metal layer 41, an opening is opened that penetrates the upper interlayer dielectric layer 22 and the lower interlayer dielectric layer 21 at one time, and conductive materials are deposited in the openings to form connecting members 3; and a conducting member is formed that penetrates the upper interlayer dielectric layer 22 and is connected to the contact member.

[0087] refer to Figure 11 The following describes a specific preparation method of this embodiment, taking the solution of retaining the contact member connected to the active structure 12 as an example. The method specifically includes the following steps:

[0088] S201: providing a substrate. For details of the substrate, refer to step S101 of the first embodiment and will not be described again here.

[0089] S202: forming a lower interlayer dielectric layer 21 by deposition on the substrate.

[0090] S203: Forming a contact member for the active structure 12, specifically comprising: creating an opening through the lower interlayer dielectric layer 21, the stopper layer 16, the second dielectric layer 15, and the barrier layer 14 to expose a predetermined area of ​​the active structure 12, and depositing a conductive material in the opening to form the contact member. Of course, the specific manufacturing process of the contact member can also refer to the manufacturing process of the connecting member 3 of this embodiment.

[0091] S204 : forming an upper interlayer dielectric layer 22 by deposition on the lower interlayer dielectric layer 21 and the contact structure.

[0092] S205: Forming a conductive member of the active structure 12, specifically: forming a cavity above the contact member through the upper interlayer dielectric layer 22, and filling the cavity to form a conductive member connected to the contact member. The specific manufacturing process of the conductive member can refer to the specific manufacturing process of the contact member.

[0093] S206: Forming the connecting member 3 of the gate structure 13, specifically comprising: opening through the first dielectric layer and the termination layer 16 to expose a predetermined area of ​​the gate structure 13, depositing a conductive material in the opening and planarizing the material, thereby forming the connecting member 3 connected to the gate structure 13. Of course, the specific method for manufacturing the connecting member 3 can be referred to step S103 of the first embodiment, and will not be repeated here.

[0094] S207 : forming a continuous stop layer 4 on the upper interlayer dielectric layer 22 , the connecting member 3 , and the conductive member.

[0095] S208: etching the stop layer 4 and filling the metal layer 41 to penetrate the stop layer 4 and communicate with the connecting member 3 and the conducting member. For details, please refer to step S105 of the first embodiment and will not be repeated here.

[0096] It is understood that not all coupling members 3 and conductive members need to be connected to the metal layer 41. The specific pattern of the metal layer 41 can be designed based on the positions of the coupling members 3 and conductive members that need to be connected to the metal layer 41. In addition, the pattern of the metal layer 41 can be divided into multiple independent sub-patterns, each of which is connected to a different coupling member 3 or conductive member.

[0097] It should be noted that in the prior art, the formation of contact members and conductive members connecting the gate, and the formation of contact members and conductive members connecting the source and drain electrodes are often carried out in separate steps. One reason is that the depths of the two contact members are inconsistent. If they are completed in one step, it is difficult to ensure the accuracy of the two types of contact holes formed. The second reason is that due to factors such as diffraction of the light source, the patterned photoresist layer formed during the photolithography process is prone to dimensional deviation. As devices become smaller, the clearance between these two types of contact holes and even their corresponding two types of through holes is too low, and the space provided for optical proximity correction is insufficient. Therefore, a more accurate size can only be achieved by using a separate step process. Therefore, even if the second embodiment of the present invention is adopted, some photomasks (for example, photomasks for connecting the gate structure) can still be saved.

[0098] In summary, the semiconductor device preparation method of the present invention has the following beneficial effects: the present invention only requires two types of photomasks (i.e., photomasks corresponding to forming connecting components and photomasks corresponding to forming metal layers). Accordingly, the present invention is applied to the production line, which can save a large number of photomasks in the process. In the prior art, the dual damascene process is used to form the conductive components and the metal layer, which is a cumbersome process and easily causes device defects. For example, after the groove is formed first, the photoresist required in the process of forming the conductive hole is easily accumulated in the groove. The present invention adopts a single damascene process to form the connecting components and the metal layer, and the process stability is improved. High; the present invention saves the middle-of-line (MEOL) process in traditional methods, shortens the process flow, and greatly reduces the production cycle; moreover, semiconductor devices formed by the preparation methods in the prior art are prone to misalignment of contact components and conductive components, which seriously affects device formation. In the present invention, a single connecting component is used to connect the metal layer and the gate structure / active structure, reducing the possibility of misalignment. Because the middle-of-line process often requires the use of a large number of photomasks, multiple misalignment problems are prone to occur, and the process window is small, each time a photomask is saved, one misalignment problem can be avoided.

[0099] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: The method comprises: Step 1: providing a substrate, wherein the substrate includes a substrate layer on which a gate structure and an active structure are arranged, and the active structure includes a source electrode and a drain electrode structure; Step 2: depositing a first dielectric layer on the substrate; Step three, forming a connecting member, including: opening a first opening penetrating through the first dielectric layer to expose the gate structure and / or the active structure, and depositing a conductive material in the opening to form a connecting member connecting the gate structure and / or the active structure; Step 4: forming a metal layer above the first dielectric layer and the connecting member, and the gate structure and / or active structure that need to be connected to the metal layer are connected to the metal layer via the connecting member; The diameter of the opening forming the connecting member gradually increases from bottom to top, and the peripheral wall of the connecting member forms an acute angle with the horizontal plane of the base, and the angle between the peripheral wall of the connecting member and the horizontal plane of the base is 65° to 90°; The method further includes: when forming the connecting member, filling the openings opened along the depth direction of the first dielectric layer in batches to form at least two layers of connecting structures stacked along the depth direction of the first dielectric layer, first forming a bottommost connecting structure abutting the gate structure and / or active structure, and finally forming a topmost connecting structure abutting the metal layer; The step of filling in batches to form at least two layers of connection structures stacked along the depth direction of the first dielectric layer comprises: The non-top connection structure forming step comprises: depositing a preliminary liner layer having a groove along the bottom and sidewalls of the opening by atomic layer deposition, and filling the groove with a dummy part; etching the preliminary liner layer and the dummy part to a desired height; removing the dummy part to expose the groove, and filling the groove with a metal material; etching the metal material to a desired height to obtain a layer of connection structure; if a non-top connection structure is to be formed next, performing the non-top connection structure forming step again; otherwise, performing the following top connection structure forming step: depositing a liner layer and a connection part material in sequence in the opening provided with the connection structure and on the surface of the first dielectric layer, and then removing excess material by planarization to expose the surface of the first dielectric layer and form a top connection structure layer in the opening; The first dielectric layer includes a lower interlayer dielectric layer and an upper interlayer dielectric layer, and the K value of the material of the upper interlayer dielectric layer is lower than the K value of the material of the lower interlayer dielectric layer; The method further includes: after forming the lower interlayer dielectric layer in step 2, for a portion of the gate structures or / and active structures that need to be connected to the metal layer, openings are opened through the lower interlayer dielectric layer, and conductive material is deposited in the openings to form contact members; in step 3, for the remaining portion of the gate structures or / and active structures that need to be connected to the metal layer, openings are opened through the lower interlayer dielectric layer and the upper interlayer dielectric layer at one time, and conductive material is deposited in the openings to form connecting members; and, a conductive member is formed through the upper interlayer dielectric layer for connecting to the contact member, wherein a side surface of the conductive member contacts a side surface of the contact member.

2. The method for preparing a semiconductor device according to claim 1, wherein: The step four specifically includes: forming a continuous stop layer above the first dielectric layer and the connecting member; etching the stop layer, filling and forming a metal layer that penetrates the stop layer, and the gate structure and / or active structure that need to be connected to the metal layer are connected to the metal layer via the connecting member.

3. The method for preparing a semiconductor device according to claim 2, wherein: The etching stop layer is filled to form a metal layer that penetrates the stop layer, specifically including: etching a groove that penetrates the stop layer in a continuous stop layer through photolithography to expose a connecting component that needs to be connected to the metal layer to form a patterned stop layer; depositing continuous metal in and above the groove of the patterned stop layer, and exposing the patterned stop layer through planarization to form a patterned metal layer.

4. The method for preparing a semiconductor device according to claim 1, wherein: In the step three, when forming the opening, the opening exposing the predetermined area of ​​the active structure is formed first, and then the opening exposing the predetermined area of ​​the gate structure is formed.

5. The method for preparing a semiconductor device according to claim 4, wherein: The substrate further includes a barrier layer, a second dielectric layer, and a termination layer; the barrier layer abuts against the sidewalls of the gate structure and covers the upper surface of the portion of the substrate layer located between the gate structures and the upper surface of the active structure, the barrier layer is flush with the gate structure, and the barrier layer is recessed inward to form a groove located between the gate structures; the second dielectric layer fills the groove and is flush with the gate structure; The termination layer covers the gate structure, the barrier layer, and the second dielectric layer; The forming of the opening to expose the predetermined area of ​​the active structure includes: opening an opening through the first dielectric layer, the stop layer, the second dielectric layer, and the barrier layer to expose the predetermined area of ​​the active structure; The forming of the opening to expose the predetermined region of the gate structure includes: opening an opening penetrating through the first dielectric layer and the termination layer to expose the predetermined region of the gate structure.

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