Method of manufacturing a semiconductor device and semiconductor device

Abstract

The application discloses a semiconductor device manufacturing method and a semiconductor device. The manufacturing method comprises the following steps: providing a device intermediate body, wherein the device intermediate body comprises a substrate, an active structure formed in the substrate, a gate structure formed above the substrate, and a first dielectric layer formed between two adjacent gate structures; wherein the gate structure comprises a dummy gate and a gate sidewall abutting both sides of the dummy gate, the gate sidewall comprises a dummy sidewall and a preset first sidewall abutting both sides of the dummy sidewall, and the upper surface of the dummy sidewall is higher than the upper surface of the preset first sidewall; removing the dummy sidewall to form a first opening and expose the inner wall of the preset first sidewall; and forming a sidewall cap above the preset first sidewall and the first opening to cover the first opening and form an air spacing layer, wherein the upper surfaces of the sidewall cap, the dummy gate and the first dielectric layer are on the same horizontal plane.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a method for manufacturing a semiconductor device and a semiconductor device. Background Technology

[0002] In existing Complementary Metal-Oxide-Semiconductor (CMOS) processes, dielectric material sidewalls are typically formed on the sidewalls of the gate. However, the various dielectric materials between the contact member 110 and the gate structure can easily generate high capacitance, leading to problems such as circuit delay, increased power consumption, or series noise, thus affecting the performance of the semiconductor device.

[0003] To address the aforementioned issues, existing CMOS devices typically incorporate an air spacer layer 103 between the contact member 110 and the gate structure, utilizing the low dielectric constant of air to reduce high capacitance. Figures 1 and 2 illustrate two existing methods for forming the air spacer layer 103. Method 1: Referring to Figure 1, the air spacer layer 103 is fabricated as follows: first, a pseudo-sidewall 114' is pre-formed, then the replacement metal gate 109 and the air spacer layer 103 are formed sequentially. The specific steps are as follows:

[0004] S100. Referring to FIG1(a), a substrate 101 is provided, and a dummy gate 104 is provided on the substrate 101.

[0005] S110, a first inner sidewall 105a', a pseudo sidewall 114', and a first outer sidewall 105b' are sequentially formed on the side of the dummy gate 104. The specific process includes the following steps:

[0006] S111. Referring to Figure 1(b), a first inner sidewall layer 105a is deposited on the substrate 101 and the dummy gate 104, and on the side of the dummy gate 104. The first inner sidewall layer 105a is then etched to expose the substrate 101 and the dummy gate 104, so as to form a first inner sidewall 105a' on the side of the dummy gate 104.

[0007] S112. Referring to FIG1(c), a pseudo sidewall layer 114 is deposited over the substrate 101, the pseudo gate 104 and the first inner sidewall 105a' and on the side of the first inner sidewall 105a', and the pseudo sidewall layer 114 is etched to expose the substrate 101, the pseudo gate 104 and the first inner sidewall 105a', so as to form the pseudo sidewall 114' on the side of the first inner sidewall 105a'.

[0008] S113. Referring to Figure 1(d), a first outer wall layer 105b is deposited on the substrate 101, the dummy gate 104, the first inner sidewall 105a' and the dummy sidewall 114', and on the side of the dummy sidewall 114'. The first outer wall layer 105b is etched to expose the substrate 101, the dummy gate 104, the first inner sidewall 105a' and the dummy sidewall 114', so as to form the first outer wall 105b' on the side of the dummy sidewall 114'.

[0009] S120. Referring to Figure 1(e), an active structure 102 (i.e., source and drain) is formed in the substrate 101 by epitaxial growth.

[0010] S130, Referring to Figure 1(f), a first dielectric layer 117 is formed above the substrate 101, abutting against two adjacent first outer walls 105b'. Of course, an additional step can be added between steps S130 and S140, namely, forming a cap. The specific process includes: referring to Figure 1(g), removing a portion of the first dielectric layer 117 by etching back to form a first trench; referring to Figure 1(h), depositing a cap layer 118 in the first trench, with the cap layer 118 covering the entire device, and planarizing the cap layer 118 (CMP, planarization) to expose the dummy gate 104.

[0011] S140. Referring to Figure 1(i), replace the dummy gate 104 with the metal gate 109 (RMG, replacement metalgate).

[0012] S150, forming an air gap layer 103, specifically includes the following steps:

[0013] S151. Referring to Figure 1(j), the pseudo sidewall 114' is removed by etching to form a first opening 107 between the first inner sidewall 105a' and the first outer sidewall 105b'.

[0014] S152. Referring to Figure 1(k), a barrier layer 120 and a second dielectric layer 119 are sequentially deposited over the entire device to form an air gap layer 103 between the first inner wall 105a' and the first outer wall 105b'.

[0015] S160. Referring to Figure 1(l), a contact member 110 is formed between the metal gates 109.

[0016] Option 2: An air gap layer 103 is formed on the side wall of the contact member 110. Referring to Figure 2, the steps are as follows:

[0017] S200. Referring to FIG1(a), a substrate 101 is provided, and a dummy gate 104 is provided above the substrate 101.

[0018] S210. Referring to FIG2(a), dummy gate sidewalls 106 are formed on both sides of the dummy gate 104, and an active structure 102 (including a source and a drain) is epitaxially grown in the substrate 101. A first dielectric layer 117 material (e.g., silicon oxide) is filled above the substrate 101 and between two adjacent dummy gate sidewalls 106, and then planarized by chemical mechanical polishing to expose both the dummy gate sidewalls 106 and the dummy gate 104, thereby forming a first dielectric layer 117 abutting against two adjacent dummy gate sidewalls 106 above the substrate 101.

[0019] S220. Referring to Figure 2(b), the dummy gate 104 is replaced with a metal gate 109, and a barrier layer 120 is deposited over the metal gate 109, the dummy gate sidewall 106 and the first dielectric layer 117.

[0020] S230, The process of forming the pseudo sidewall 114' of the contact member 110 includes the following steps:

[0021] S231. Referring to Figure 2(c), a second dielectric layer 119 is deposited over the barrier layer 120, and a third opening 113 is formed by etching in the first dielectric layer 117, the barrier layer 120 and the second dielectric layer 119 to form a filling space for the subsequent contact member 110.

[0022] S232. Referring to Figure 2(d), a pseudo sidewall layer 114 is deposited on the inner wall and bottom of the third opening 113 and above the second dielectric layer 119, and planarization is performed to expose the second dielectric layer 119 and the bottom of the third opening 113, as well as the pseudo sidewall layer 114 remaining in the third opening 113 as a pseudo sidewall 114'.

[0023] S240, Referring to Figure 2(e), a contact member 110 is further formed within the third opening 113, including a metal spacer 111a (barrier) and a contact member 111b.

[0024] S250. Referring to Figure 2(f), remove the pseudo sidewall 114' to form an air gap layer 103.

[0025] In the first solution of the prior art, the cap is only formed on the first dielectric layer 117 and there is no cap on the metal gate 109. Therefore, during the formation of the air spacer layer 103, it is easy to cause partial missing parts on the top of the metal gate 109. Moreover, when the contact member 110 is offset, metal is easily filled into the air spacer layer 103.

[0026] In the second prior art solution, if the pseudo-sidewall layer 114 is not excessively etched back during the formation of the pseudo-sidewall 114', material from the pseudo-sidewall 114' can easily remain on the upper surface of the substrate 101, affecting the contact between the contact member 110 and the active structure 102, thereby significantly increasing the resistance of the contact window. If the pseudo-sidewall layer 114 is excessively etched back to ensure the exposure of the substrate 101, the etching depth can easily extend to the active structure 102 of the substrate 101, damaging the active structure 102. Moreover, during the process of etching back to form the pseudo-sidewall 114', it is also easy to cause partial material loss at the top of the contact member 110, affecting the subsequent connection of the contact member 110.

[0027] Therefore, a method is needed to solve the above problems. Summary of the Invention

[0028] The main objective of this application is to provide a method for fabricating a semiconductor device, which aims to form a sidewall cap above an air spacer layer and ensure that the formed preset first sidewall and air spacer layer are linear or near-linear structures, so that when the contact member is offset toward the gate structure, the sidewall cap, the preset first sidewall and air spacer layer can prevent the contact member from offset toward the gate structure.

[0029] To achieve the above objectives, this application proposes a method for fabricating a semiconductor device, the method comprising:

[0030] A device intermediate is provided, the device intermediate comprising: a substrate, an active structure formed in the substrate, a gate structure formed above the substrate, and a first dielectric layer formed between two adjacent gate structures;

[0031] The gate structure includes a dummy gate and gate sidewalls abutting both sides of the dummy gate. The gate sidewalls include a dummy sidewall and a preset first sidewall abutting both sides of the dummy sidewall. The upper surface of the dummy sidewall is higher than the upper surface of the preset first sidewall.

[0032] Remove the false sidewall to form a first opening and expose the inner wall of the preset first sidewall;

[0033] A sidewall cap is formed above the preset first sidewall and the first opening to cover the first opening and form an air gap layer.

[0034] In this embodiment, by forming an air gap layer by forming a sidewall cap on the first opening and ensuring that the formed preset first sidewall and air gap layer are linear or near-linear structures, the sidewall cap, preset first sidewall and air gap layer can prevent the contact member from shifting toward the gate structure when the contact member shifts toward the gate structure.

[0035] In one embodiment, the manufacturing method further includes:

[0036] The dummy gate is replaced with a metal gate, and a second dielectric layer is formed over the sidewall cap, the metal gate, and the first dielectric layer.

[0037] A cavity is formed along the upper surface of the second dielectric layer into the first dielectric layer;

[0038] A contact member is formed in the cavity.

[0039] In one embodiment, the formation of the device intermediate includes the following steps:

[0040] The active structure, the dummy gate, and dummy gate sidewalls abutting both sides of the dummy gate are formed on the substrate.

[0041] A first dielectric layer is formed above the substrate to abut against two adjacent dummy gate sidewalls;

[0042] At least partially remove the dummy gate sidewall to form a second opening over the substrate;

[0043] A first sidewall layer is deposited on the inner wall and bottom of the second opening, as well as above the first dielectric layer and the dummy gate, and a dummy sidewall layer is deposited again above the first sidewall layer and inside the second opening.

[0044] The pseudo sidewall layer and the first sidewall layer are processed to form the gate structure.

[0045] In one embodiment, the processing of the pseudo sidewall layer and the first sidewall layer includes:

[0046] Remove the pseudo sidewall layer formed over the first dielectric layer and the pseudo gate to expose the first sidewall layer and partially remove the pseudo sidewall layer formed in the second opening so that the remaining pseudo sidewall layer in the second opening serves as a pseudo sidewall.

[0047] Remove the first sidewall layer formed above the first dielectric layer and the dummy gate, and partially remove the first sidewall layer formed in the second opening, so that the remaining first sidewall layer in the second opening serves as the preset first sidewall.

[0048] In one embodiment, the processing of the pseudo sidewall layer and the first sidewall layer includes:

[0049] Remove the pseudo sidewall layer that forms above the first dielectric layer and the pseudo gate;

[0050] Remove the first sidewall layer formed above the first dielectric layer and the dummy gate, and partially remove the first sidewall layer and the dummy sidewall layer formed in the second opening, so that the remaining first sidewall layer and dummy sidewall layer in the second opening serve as the preset first sidewall and the dummy sidewall, respectively.

[0051] In one embodiment, the processing of the pseudo sidewall layer and the first sidewall layer includes:

[0052] Remove the dummy sidewall layer and the first sidewall layer formed over the first dielectric layer and the dummy gate to expose the first dielectric layer and the dummy gate;

[0053] Partial removal of the first sidewall layer and the pseudo sidewall layer formed within the second opening, so that the remaining first sidewall layer and the pseudo sidewall layer within the second opening serve as the preset first sidewall and the pseudo sidewall, respectively.

[0054] In one embodiment, forming a sidewall cap above the predetermined first sidewall and the first opening includes:

[0055] A hard mask layer is deposited over the four pre-defined elements: the first sidewall, the first opening, the dummy gate, and the first dielectric layer.

[0056] Remove the hard mask layer deposited over the first dielectric layer and the dummy gate to form the sidewall cap over the preset first sidewall and the first opening.

[0057] In one embodiment, the formation of the device intermediate includes the following steps:

[0058] The dummy gate is formed above the substrate, and a first inner sidewall, a dummy sidewall, and a first outer sidewall are formed sequentially to abut against both sides of the dummy gate.

[0059] The active structure is formed in the substrate;

[0060] A first dielectric layer is formed above the substrate, abutting against two adjacent first outer walls;

[0061] Remove portions of the first inner wall, the pseudo side wall, and the first outer wall, so that the remaining first inner wall, pseudo side wall, and first outer wall serve as the preset first inner wall, the pseudo side wall, and the preset first outer wall, respectively, and the preset first inner wall and the preset first outer wall form the preset first side wall.

[0062] In one embodiment, during the removal of the first sidewall layer, the etch selectivity ratio of the first sidewall layer to the pseudo sidewall layer is not less than 10; during the removal of the pseudo sidewall layer, the etch selectivity ratio of the pseudo sidewall layer to the first sidewall layer is not less than 120.

[0063] In one embodiment, the material of the first sidewall layer is at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide, and the material of the pseudo sidewall layer is at least one of silicon dioxide, bottom antireflective layer, and silicon nitride.

[0064] When the material of the first sidewall layer is silicon nitride and the material of the pseudo sidewall layer is silicon dioxide, isotropic dry etching is used to remove the first sidewall layer and isotropic dry etching is used to remove the pseudo sidewall layer; or,

[0065] When the material of the first sidewall layer is silicon nitride and the material of the pseudo sidewall layer is the bottom anti-reflective layer, the first sidewall layer is removed by isotropic dry etching and the pseudo sidewall layer is removed by plasma etching; or...

[0066] When the material of the first sidewall layer is silicon dioxide and the material of the pseudo sidewall layer is silicon nitride, isotropic dry etching is used to remove the first sidewall layer and isotropic dry etching is used to remove the pseudo sidewall layer; or,

[0067] When the material of the first sidewall layer is silicon dioxide and the material of the pseudo sidewall layer is the bottom anti-reflective layer, the first sidewall layer is removed by isotropic dry etching and the pseudo sidewall layer is removed by plasma etching.

[0068] This application also provides a semiconductor device, the semiconductor device comprising:

[0069] Substrate, active structure formed on said substrate, and alternative gate structure;

[0070] The alternative gate structure includes an alternative gate, a preset first sidewall abutting both sides of the alternative gate and having a first opening therein, and a sidewall cap formed on the preset first sidewall and the first opening, wherein the preset first sidewall, the first opening and the sidewall cap surround to form an air gap layer;

[0071] A dielectric layer is formed above the substrate and partially abuts the alternative gate structure;

[0072] Contact members are formed above the substrate and embedded in the dielectric layer.

[0073] This application also provides a semiconductor device manufactured using the method described above. Attached Figure Description

[0074] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0075] Figure 1(a)-1(l) This is a schematic diagram of the formation of an air gap layer according to an embodiment of the prior art;

[0076] Figures 2(a)-2(f) This is a schematic diagram illustrating the formation of an air gap layer according to another embodiment of the prior art;

[0077] Figures 3(a)-3(l) A schematic diagram of a method for fabricating a semiconductor device according to Embodiment 1 of this application is shown;

[0078] Figure 4 A schematic diagram of the cap formation in another technical solution is shown;

[0079] Figures 5(a)-5(c) A schematic diagram of a method for fabricating a semiconductor device according to Embodiment 2 of this application is shown;

[0080] Figure 6(a) shows a schematic diagram of the flow of metallic material into the air spacer layer during the formation of the contact member in the prior art;

[0081] Figure 6(b) shows a schematic diagram of the metal material being blocked from flowing into the air spacer layer during the formation of the contact member in Embodiment 1 of this application.

[0082] Explanation of icon numbers:

[0083] label name label name 100 semiconductor devices 111a Metal spacers 101 substrate 111b Contact 102 Active structure 112 Second opening 103 Air gap 113 Third opening 104 pseudo gate 114 False sidewall layer 105 First side wall 114’ False sidewall 105’ First side wall layer 105a First inner wall layer 106 Pseudo-gate sidewall 105a’ First inner wall 107 First opening 105b First outer wall layer 108 Side wall cap 105b’ First outer wall 109 Metal gate 116 Pre-set first side wall 110 Contact components 117 First dielectric layer 118 Cap layer 119 Second dielectric layer 120 Barrier layer 121 Hard mask layer

[0084] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0085] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0086] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0087] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0088] In view of this, Figures 3(a)-3(l) A schematic diagram of a method for fabricating a semiconductor device according to Embodiment 1 of this application is shown.

[0089] Reference Figures 3(a)-3(l) In the first embodiment, an air spacer layer 103 is first formed, and then a metal gate 109 is formed. The specific steps are as follows:

[0090] S300. Referring to FIG1(a), a substrate 101 is provided, and a dummy gate 104 is provided above the substrate 101.

[0091] S310. Referring to Figure 2(a), pseudo-gate sidewalls 106 are formed on both sides of the pseudo-gate 104, and an active structure 102 (including source and drain) is epitaxially grown in the substrate 101.

[0092] S320. Referring to FIG2(a), a first dielectric layer 117 material (e.g., silicon oxide) is filled above the substrate 101 and between two adjacent dummy gate sidewalls 106. Then, planarization is performed by chemical mechanical polishing to expose the dummy gate sidewalls 106 and the dummy gate 104 simultaneously, thereby forming a first dielectric layer 117 abutting against the two adjacent dummy gate sidewalls 106 above the substrate 101.

[0093] S330, forming a preset first sidewall 116 and a pseudo sidewall 114', the specific process includes the following steps:

[0094] S331. Referring to Figure 3(a), remove the dummy gate sidewall 106 to form a second opening 112 above the substrate 101, between the dummy gate 104 and the first dielectric layer 117. The dummy gate sidewall 106 can be removed by dry etching to expose the substrate 101.

[0095] S332, Referring to Figure 3(b), a first sidewall layer 105' is deposited on the inner wall and bottom of the second opening 112, as well as above the first dielectric layer and the dummy gate 104. The deposition can be any of chemical vapor deposition, atomic layer deposition, etc. The material of the first sidewall layer 105' can be at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide.

[0096] S333. Referring to Figure 3(c), deposit another pseudo-sidewall layer 114 above the first sidewall layer 105' and inside the second opening 112 to fill the second opening 112 and cover the first sidewall layer 105'. This deposition can be performed using any of the following methods: chemical vapor deposition, atomic layer deposition, coating, etc.

[0097] S334. Remove part of the pseudo sidewall layer 114 and the first sidewall layer 105' to form the pseudo sidewall 114' and the preset first sidewall 116 respectively.

[0098] In this application, if the pseudo sidewall 114' is not formed, and instead the first sidewall layer 105' is formed directly followed by etching back to form the predetermined first sidewall 116, it will be difficult to form a regular air gap layer 103. This is because if dry etching is used, the etching gas will directly reach the bottom of the opening and partially or completely remove the first sidewall layer 105', which may damage the substrate; if wet etching is used, the solution will also flow into the second opening 112, which may damage the substrate. These etching methods will directly destroy the overall size and structure of the first sidewall 105, so it is essential to have a pseudo sidewall 114'.

[0099] S334 includes three schemes; the first scheme is as follows:

[0100] Referring to FIG3(d), the dummy sidewall layer 114 formed above the first dielectric layer 117 and the dummy gate 104 is removed by back etching to expose the first sidewall layer 105' and partially remove the dummy sidewall layer 114 formed in the second opening 112 so that the remaining dummy sidewall layer 114 in the second opening 112 serves as the dummy sidewall 114'.

[0101] The first sidewall layer 105' formed above the first dielectric layer 117 and the dummy gate 104 is removed by etchback, and the first sidewall layer 105' formed in the second opening 112 is partially removed, so that the remaining first sidewall layer 105' in the second opening 112 serves as the preset first sidewall 116.

[0102] In the first approach, the etch-back process of the first sidewall layer 105' is carried out by chemical dry etching, which can reduce the wear of the first dielectric layer 117 and avoid additional loss of gate structure height. However, it is necessary to precisely control the etch-back depth of the pseudo sidewall layer 114.

[0103] The second option includes the following:

[0104] Referring to Figure 3(e), the dummy sidewall layer 114 formed above the first sidewall layer 105' is removed using a planarization technique to expose the first sidewall layer 105'. The first sidewall layer 105' formed above the first dielectric layer 117 and the dummy gate 104 is removed, and the first sidewall layer 105' and the dummy sidewall layer 114 formed within the second opening 112 are partially removed, so that the remaining first sidewall layer 105' and dummy sidewall layer 114 within the second opening 112 serve as the preset first sidewall 116 and dummy sidewall 114', respectively. It should be noted that "partially removing the dummy sidewall layer" is used here because when partially removing the first sidewall layer, a portion of the dummy sidewall layer 114 may also be removed simultaneously.

[0105] In the second approach, since the pseudo sidewall layer 114 formed above the first sidewall layer 105' is removed by planarization technology, the pseudo sidewall layer 114 does not need to be etched back on the first sidewall layer 105', which can reduce the loss of the first dielectric layer and avoid additional loss of gate height.

[0106] Furthermore, since the thickness of the pseudo sidewall layer 114 is typically less than 3 nm, it is difficult to remove the pseudo sidewall layer 114 from the first dielectric layer 117 using chemical mechanical polishing (CMP) and stop at the first sidewall layer 105' (i.e., the first sidewall layer 105' is not removed). Because CMP is used, the material of the pseudo sidewall layer 114 can only be the dielectric layer material, which makes it impossible to use materials with flowability (such as anti-reflective layers). Therefore, the materials that can be used in the second approach are relatively limited.

[0107] The third option includes the following:

[0108] Referring to FIG3(f), the pseudo sidewall layer 114 and the first sidewall layer 105' formed above the first dielectric layer 117 and the pseudo gate 104 are removed by planarization technology to expose the first dielectric layer 117 and the pseudo gate 104.

[0109] Partial removal of the first sidewall layer 105' and pseudo sidewall layer 114 formed in the second opening 112, so that the remaining first sidewall layer 105' and pseudo sidewall layer 114 in the second opening 112 serve as the preset first sidewall 116 and pseudo sidewall 114', respectively.

[0110] In the third approach, since the pseudo-sidewall layer 114 and the first sidewall layer 105' formed above the first dielectric layer 117 and the pseudo gate 104 are removed using planarization technology, etch-back of the pseudo-sidewall layer 114 is unnecessary. However, because chemical mechanical polishing is used, the material of the pseudo-sidewall layer 114 can only be the dielectric layer material, making it impossible to use flowable materials (such as anti-reflection layers). Therefore, the materials that can be used in the second approach are relatively limited. Moreover, chemical mechanical polishing can easily damage the first dielectric layer 117 and cause additional loss of gate height.

[0111] S340. Referring to Figure 3(g), remove the pseudo sidewall 114' in the second opening 112 to form the first opening 107 and expose the inner wall of the preset first sidewall 116.

[0112] It is particularly important to note that the material of the pseudo sidewall layer 114 must meet the following requirements:

[0113] 1) Under certain specific conditions, the material of the pseudo sidewall layer 114 has a high etch selectivity ratio with the material of the first sidewall layer 105', that is, the material of the pseudo sidewall layer 114 has a faster etch rate, so as to achieve: a) in the first scheme of step S334, the pseudo sidewall layer 114 is partially removed inside the second opening 112 to precisely control the etch-back depth of the pseudo sidewall layer and ensure that the remaining pseudo sidewall layer 114 in the second opening 112 serves as the pseudo sidewall 114'; b) in step S340, the pseudo sidewall 114' inside the second opening 112 is removed with high quality based on the preset first sidewall to form the first opening 107.

[0114] 2) Under certain conditions, the material of the first sidewall layer 105' has a high etch selectivity ratio with the material of the pseudo sidewall layer 114, that is, the material of the first sidewall layer 105' has a faster etch rate, so as to achieve partial removal of the first sidewall layer formed in the second opening 112 in step S334, so as to form the preset first sidewall 116 with high quality.

[0115] To meet the above requirements, it is necessary to consider various factors, including the process and the materials of the dummy sidewall layer 114 and the first sidewall layer 105'. During the etching of the first sidewall layer 105', the etching selectivity ratio between the first sidewall layer 105' and the dummy sidewall layer 114 should be no less than 10. During the etching of the dummy sidewall layer 114, the etching selectivity ratio between the dummy sidewall layer 114 and the first sidewall layer 105' should be no less than 120.

[0116] Specifically, the materials of the pseudo sidewall layer 114 and the first sidewall layer 105' are not limited to a single combination, but they must be matched together, and the two materials must exhibit significant differences in their gas response during the etching process. Several preferred combinations are listed in Table 1 below:

[0117] Table 1

[0118]

[0119]

[0120] It should be noted that the bottom anti-reflective coating (BARC) refers to the bottom anti-reflective material used in semiconductor manufacturing to effectively eliminate light reflection and the formation of interference standing waves. It is typically an organic material, with main components including cross-linkable resins, thermogenic acid generators, surfactants, and solvents. Furthermore, among the four feasible options provided, Options 1 and 2 better meet the various etching selectivity requirements in the manufacturing process and have high process adaptability.

[0121] S350. A sidewall cap 108 is formed above the preset first sidewall 116 and the first opening 107 to cover the air gap layer 103 formed by the first opening 107, wherein the upper surfaces of the sidewall cap 108, the dummy gate 104, and the first dielectric layer 117 are on the same horizontal plane. Specifically, forming the sidewall cap 108 includes the following steps:

[0122] S351. Referring to Figure 3(h), a hard mask layer 121 is deposited over the four pre-defined first sidewall 116, first opening 107, dummy gate 104 and first dielectric layer 117 to form an air gap layer 103.

[0123] S352. Referring to Figure 3(i), the hard mask layer 121 deposited above the first dielectric layer 117 and the dummy gate 104 is removed by planarization technology to expose the dummy gate 104 and the first dielectric layer 117, so that the remaining hard mask layer 121 forms a sidewall cap 108 above the preset first sidewall 116 and the first opening 107.

[0124] The material of the hard mask layer 121 is at least one of silicon oxide and silicon nitride.

[0125] The sidewall cap 108 of this application is formed by self-alignment, thus avoiding the problems of high cost caused by using a photomask and the inaccuracy of cap position due to photomask misalignment. For example: Figure 4 A schematic diagram of the cap formation using another technique is shown. (Refer to...) Figure 4 After forming the first sidewall layer 105', planarization is performed to expose the gate structure and dielectric layer. Then, a sidewall cap 108 is formed on the planarized first sidewall layer 105' using a photomask via photolithography. This process is prone to cap misalignment, and the problem becomes increasingly severe as semiconductor device dimensions shrink. The sidewall cap 108 of this application overcomes the problems of the prior art through a self-alignment method.

[0126] S360. Referring to Figure 3(j), replace the dummy gate 104 with the metal gate 109.

[0127] S370, Referring to Figure 3(k), a barrier layer 120 and a second dielectric layer 119 are sequentially formed above the sidewall cap 108, the metal gate 109 and the first dielectric layer 117.

[0128] S380, Referring to Figure 3(l), a cavity is formed along the upper surface of the second dielectric layer 119 into the first dielectric layer 117; a contact member 110 is formed in the cavity.

[0129] In the first embodiment of this application, by first forming a second opening 112 and then sequentially depositing a first sidewall layer 105' and a pseudo sidewall layer 114 in the second opening 112, and then removing the pseudo sidewall layer / pseudo sidewall by etching, it can be ensured that the final formed preset first sidewall 116 and air gap layer 103 are linear or near-linear structures. When a contact member shift occurs, it can block the metal material of the contact member from flowing into the air gap layer 103 to a certain extent.

[0130] Figure 5 shows a schematic diagram of the method for fabricating a semiconductor device according to Embodiment 2 of this application.

[0131] Referring to Figures 5(a)-(c), the formation of the device intermediate includes the following steps:

[0132] S500: A dummy gate 104 is formed above the substrate 101, and a first inner sidewall 105a', a dummy sidewall 114', and a first outer sidewall 105b' are sequentially formed abutting both sides of the dummy gate 104. The specific process includes the following steps:

[0133] S501. Referring to FIG1(a), a substrate 101 is provided, and a dummy gate 104 is provided above the substrate 101.

[0134] S502. Referring to FIG1(b), a first inner sidewall layer 105a is deposited on the substrate 101 and the dummy gate 104, and on the side of the dummy gate 104, and the first inner sidewall layer 105a is etched to expose the substrate 101 and the dummy gate 104, so as to form a first inner sidewall 105a' on the side of the dummy gate 104.

[0135] S503. Referring to FIG1(c), a pseudo sidewall layer 114 is deposited over the substrate 101, the pseudo gate 104 and the first inner sidewall 105a' and on the side of the first inner sidewall 105a', and the pseudo sidewall layer 114 is etched to expose the substrate 101, the pseudo gate 104 and the first inner sidewall 105a', so as to form the pseudo sidewall 114' on the side of the first inner sidewall 105a'.

[0136] S504. Referring to FIG1(d), a first outer wall layer 105b is deposited on the substrate 101, the dummy gate 104, the first inner sidewall 105a' and the dummy sidewall 114', and on the side of the dummy sidewall 114'. The first outer wall layer 105b is etched to expose the substrate 101, the dummy gate 104, the first inner sidewall 105a' and the dummy sidewall 114', so as to form the first outer wall 105b' on the side of the dummy sidewall 114'.

[0137] S510. Referring to Figure 1(e), an active structure 102 is formed in the substrate 101.

[0138] S520, Referring to Figure 1(f), a first dielectric layer 117 is formed above the substrate 101 to abut against two adjacent first outer walls 105b'.

[0139] S530. Referring to FIG5(a), a portion of the first inner wall 105a' and the first outer wall 105b' are removed by etching, so that the remaining first inner wall 105a' and the first outer wall 105b' serve as the preset first inner wall and the preset first outer wall, respectively, and the preset first inner wall and the preset first outer wall form the preset first side wall 116.

[0140] In this embodiment, since multiple deposition and planarization steps are used to form the first inner sidewall 105a', pseudo sidewall 114', and first outer sidewall 105b' with substantially flush upper surfaces, there is no need to perform back etching of the pseudo sidewall 114'. However, forming the pseudo sidewall 114' requires multiple thin film deposition and etching processes, which is cumbersome and prone to damaging the substrate. If the pseudo sidewall 114' is formed after the active structure 102 is formed, the active structure 102 is easily damaged during the etching process. If the pseudo sidewall 114' is formed before the active structure 102 is formed, the substrate 101 will show depressions because forming the pseudo sidewall 114' requires multiple thin film deposition and etching processes.

[0141] S540. Referring to Figure 5(b), remove the pseudo sidewall 114' to form the first opening 107 and expose the inner wall of the preset first sidewall 116.

[0142] S550, Referring to Figure 5(c), a sidewall cap 108 is formed above the preset first sidewall 116 and the first opening 107 to cover the first opening 107 to form an air gap layer 103, wherein the upper surfaces of the sidewall cap 108, the dummy gate 104 and the first dielectric layer 117 are on the same horizontal plane.

[0143] S560. Referring to Figure 3(i), replace the dummy gate 104 with the metal gate 109.

[0144] S570, Referring to Figure 3(k), a barrier layer 120 and a second dielectric layer 119 are sequentially formed above the sidewall cap 108, the metal gate 109 and the first dielectric layer 117.

[0145] S580, Referring to Figure 3(l), a cavity is formed along the upper surface of the second dielectric layer 119 into the first dielectric layer 117; a contact member 110 is formed in the cavity.

[0146] Ideally, the contact members involved in this application should be formed such that the contact holes extending into the dielectric layer fall perfectly between the gate structures without any dimensional deviations (see Figure 1(l)). However, as the critical dimensions (CD) of semiconductor devices gradually shrink, the requirements for photolithography become increasingly stringent, further compressing the space between the gate structure and the contact members. Moreover, as the node size decreases, contact members may be formed in batches. Therefore, in actual production processes, it is normal for the contact members to shift towards the gate.

[0147] In the first solution of the prior art, as shown in Figure 6(a), when etching the cavity to accommodate the contact member, it is easy to cause the sidewall to be broken during etching, resulting in the metal material of the contact member flowing into the air spacer layer.

[0148] Conversely, referring to FIG6(b), the semiconductor device involved in this application forms a sidewall cap above the air spacer layer in the device. The sidewall cap material is difficult to etch. When the contact member is offset, it can prevent the contact member from partially overlapping with the preset first sidewall and the air spacer layer, and can effectively block the metal material in the contact member from flowing into the air spacer layer.

[0149] The above description is merely an optional embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The manufacturing method comprises: providing a device intermediate, the device intermediate comprising: a substrate, an active structure formed in the substrate, a gate structure formed above the substrate, and a first dielectric layer formed between two adjacent gate structures; wherein the gate structure comprises a dummy gate and a gate sidewall abutting two sides of the dummy gate, the gate sidewall comprising: a dummy sidewall and a preset first sidewall abutting two sides of the dummy sidewall, an upper surface of the dummy sidewall being higher than an upper surface of the preset first sidewall; removing the dummy sidewall to form a first opening and expose an inner wall of the preset first sidewall; a top surface of the preset first sidewall being lower than a top surface of the dummy gate, and being between the dummy gate and the first dielectric layer, and a corresponding space being formed above the preset first sidewall, the space being used to accommodate a barrier layer when the barrier layer is deposited; forming a sidewall cap above the preset first sidewall and the first opening to cover the first opening and form an air gap layer; a material of the sidewall cap being at least one of silicon oxide and silicon nitride.

2. The production method according to claim 1, characterized by, The manufacturing method further comprises: replacing the dummy gate with a metal gate, and forming a second dielectric layer above the sidewall cap, the metal gate, and the first dielectric layer; forming a cavity in the first dielectric layer along an upper surface of the second dielectric layer; forming a contact member in the cavity.

3. The method of making of claim 1, wherein, The device intermediate is formed by the following steps: forming the active structure, the dummy gate, and a dummy gate sidewall abutting two sides of the dummy gate on the substrate; forming a first dielectric layer abutting two adjacent dummy gate sidewalls above the substrate; at least partially removing the dummy gate sidewall to form a second opening above the substrate; depositing a first sidewall layer on an inner wall, a bottom of the second opening, and above the first dielectric layer and the dummy gate, and re-depositing a dummy sidewall layer above the first sidewall layer and in the second opening; processing the dummy sidewall layer and the first sidewall layer to form the gate structure.

4. The method of manufacturing according to claim 3, wherein, The processing of the dummy sidewall layer and the first sidewall layer comprises: removing the dummy sidewall layer formed above the first dielectric layer and the dummy gate to expose the first sidewall layer, and partially removing the dummy sidewall layer formed in the second opening so that the remaining dummy sidewall layer in the second opening serves as the dummy sidewall; removing the first sidewall layer formed above the first dielectric layer and the dummy gate, and partially removing the first sidewall layer formed in the second opening so that the remaining first sidewall layer in the second opening serves as the preset first sidewall.

5. The method of manufacturing according to claim 3, wherein, The processing of the dummy sidewall layer and the first sidewall layer comprises: removing the dummy sidewall layer formed above the first dielectric layer and the dummy gate to expose the first sidewall layer; removing the first sidewall layer formed above the first dielectric layer and the dummy gate, and partially removing the first sidewall layer and the dummy sidewall layer formed in the second opening so that the remaining first sidewall layer and the dummy sidewall layer in the second opening respectively serve as the preset first sidewall and the dummy sidewall.

6. The method of manufacturing according to claim 3, wherein, The processing of the dummy side wall layer and the first side wall layer comprises: removing the dummy side wall layer and the first side wall layer formed above the first dielectric layer and the dummy gate to expose the first dielectric layer and the dummy gate; partially removing the first side wall layer and the dummy side wall layer formed in the second opening to leave the first side wall layer and the dummy side wall layer remaining in the second opening as the preset first side wall and the dummy side wall respectively.

7. The method of making according to any one of claims 1-6, wherein, The forming of the side wall cap above the preset first side wall and the first opening comprises: depositing a hard mask layer above the preset first side wall, the first opening, the dummy gate and the first dielectric layer; removing the hard mask layer deposited above the first dielectric layer and the dummy gate to form the side wall cap above the preset first side wall and the first opening.

8. The method of making of claim 1, wherein, The forming of the device intermediate comprises the following steps: forming the dummy gate above the substrate and sequentially forming a first inner side wall, a dummy side wall and a first outer side wall abutting two sides of the dummy gate; forming the active structure in the substrate; forming a first dielectric layer above the substrate abutting two adjacent first outer side walls; partially removing the first inner side wall, the dummy side wall and the first outer side wall to leave the remaining first inner side wall, dummy side wall and first outer side wall as a preset first inner side wall, the dummy side wall and a preset first outer side wall respectively, the preset first inner side wall and the preset first outer side wall forming the preset first side wall.

9. The method of making according to any one of claims 4-6, wherein, In the process of removing the first side wall layer, the etching selectivity ratio of the first side wall layer to the dummy side wall layer is not less than 10; in the process of removing the dummy side wall layer, the etching selectivity ratio of the dummy side wall layer to the first side wall layer is not less than 120.

10. The method of manufacturing according to claim 9, wherein, The material of the first side wall layer is at least one of silicon oxide, silicon nitride, silicon oxynitride and silicon oxycarbide, and the material of the dummy side wall layer is at least one of silicon dioxide, bottom anti-reflective layer and silicon nitride; when the material of the first side wall layer is silicon nitride and the material of the dummy side wall layer is silicon dioxide, the first side wall layer is removed by isotropic dry etching and the dummy side wall layer is removed by isotropic dry etching; or when the material of the first side wall layer is silicon nitride and the material of the dummy side wall layer is bottom anti-reflective layer, the first side wall layer is removed by isotropic dry etching and the dummy side wall layer is removed by plasma etching; or when the material of the first side wall layer is silicon dioxide and the material of the dummy side wall layer is silicon nitride, the first side wall layer is removed by isotropic dry etching and the dummy side wall layer is removed by isotropic dry etching; or when the material of the first side wall layer is silicon dioxide and the material of the dummy side wall layer is bottom anti-reflective layer, the first side wall layer is removed by isotropic dry etching and the dummy side wall layer is removed by plasma etching.

11. A semiconductor device, characterized by comprising: The semiconductor device comprises: a substrate, an active structure and a gate structure formed on the substrate; the gate structure comprises a dummy gate, a preset first side wall abutting two sides of the dummy gate and a side wall cap, wherein the preset first side wall and the side wall cap enclose an air spacing layer; The medium layer comprises a first medium layer formed between two adjacent gate structures; a top surface of the preset first sidewall is lower than a top surface of the dummy gate, and is between the dummy gate and the first medium layer, and a corresponding space is formed above the preset first sidewall, the space being used for accommodating the sidewall cap, the sidewall cap being made of at least one of silicon oxide and silicon nitride; A contact member is formed above the substrate and embedded in the medium layer.

12. A semiconductor device, characterized by comprising: The semiconductor device is manufactured by the manufacturing method according to any one of claims 1-10.

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