Semiconductor structure, method of fabricating the same, and memory system
By forming multiple grooves in the dynamic random access memory and filling them with conductive material, the risk of electrode collapse is eliminated, thereby improving the stability of the capacitor and the manufacturing quality of the memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2022-07-22
- Publication Date
- 2026-05-22
Smart Images
Figure CN115223951B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method, and a memory system. Background Technology
[0002] The memory array architecture of Dynamic Random Access Memory (DRAM) consists of an array of memory cells (i.e., 1T1C memory cells) each containing one transistor and one capacitor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
[0003] As the size of dynamic random access memory (DRAM) continues to shrink, the size of capacitors also shrinks. Ensuring the performance of capacitors in DRAM has become a pressing issue.
[0004] Public content
[0005] In view of this, the present disclosure provides a semiconductor structure and a method for fabricating the same.
[0006] According to one aspect of this disclosure, a method for fabricating a semiconductor structure is provided, comprising:
[0007] A first insulating layer is provided, and a plurality of sacrificial material pillars are formed in the first insulating layer;
[0008] The top portion of each of the sacrificial material columns is removed to form a plurality of first grooves;
[0009] The plurality of first grooves are enlarged to form a plurality of second grooves;
[0010] Remove the remaining portion of the sacrificial material column to form multiple third grooves;
[0011] The second groove is filled with a first conductive material, and the third groove is filled with a second conductive material, wherein the first conductive material at the top of each second groove is in contact with a portion of the first conductive material at the top of at least one adjacent second groove;
[0012] Remove the first insulating layer;
[0013] Remove the first conductive material, and use the second conductive material to form the first electrode of the storage structure.
[0014] In the above scheme, the plurality of sacrificial material pillars are arranged in an array along the first direction and the second direction, the first direction and the second direction intersect and are both perpendicular to the direction of the thickness of the first insulating layer;
[0015] The first conductive material at the top of each second groove is in partial contact with the first conductive material at the top of the two adjacent second grooves along the first direction, and is also in partial contact with the first conductive material at the top of the two adjacent second grooves along the second direction.
[0016] In the above scheme, the first conductive material and the second conductive material are made of the same material.
[0017] In the above scheme, after forming multiple second grooves, there is also a portion of a first insulating layer between the second grooves, and the first insulating layer has an exposed top surface.
[0018] In the above solution, filling the second groove with a first conductive material includes:
[0019] The second groove and the top surface of the first insulating layer are filled with a first conductive material;
[0020] The method further includes:
[0021] After filling with the first conductive material, a portion of the first conductive material is removed by a chemical mechanical polishing (CMP) process, exposing the top surface of the first insulating layer.
[0022] In the above solution, removing the first insulating layer includes:
[0023] Remove the first insulating layer between the plurality of second grooves and the first insulating layer between the plurality of third grooves from the exposed top surface of the first insulating layer.
[0024] In the above scheme, forming a plurality of sacrificial material pillars in the first insulating layer includes:
[0025] Multiple sacrificial material pillars with a circular or elliptical projected shape are formed on the surface of the first insulating layer.
[0026] In the above scheme, a first filling area is formed when the first insulating layer is removed;
[0027] The method further includes:
[0028] The first filling region is sequentially filled with a dielectric material and a third conductive material;
[0029] The removal of the first conductive material includes:
[0030] The first conductive material is removed, along with the dielectric material and the third conductive material surrounding the first conductive material. The remaining dielectric material and the third conductive material are used to form the dielectric layer and the second electrode of the storage structure, respectively.
[0031] The method in the above scheme further includes:
[0032] After forming the first electrode, the dielectric layer, and the second electrode, a second insulating layer is formed in the gap between two adjacent second electrodes.
[0033] The method in the above scheme further includes:
[0034] Multiple transistor units are formed; the transistor units are coupled to the first electrode.
[0035] In the above scheme, the transistor forming unit includes:
[0036] A semiconductor layer is provided, wherein the semiconductor layer is stacked with the first insulating layer;
[0037] A first transistor and a second transistor are formed in the semiconductor layer in a symmetrical arrangement along a third direction; each of the first transistor and the second transistor includes a source, a drain, a channel region, a gate, and a gate oxide layer; the extension direction of the channel region of the first transistor and the second transistor is perpendicular to the third direction, and the first transistor and the second transistor share a source or a drain; the third direction is parallel to the thickness direction of the first insulating layer; the first electrode is coupled to one of the source and drain of the transistor unit.
[0038] The method in the above scheme further includes:
[0039] Multiple bit lines are formed; each bit line is coupled to another of the source and drain of the transistor cell.
[0040] In the above scheme, the semiconductor structure includes a dynamic random access memory.
[0041] According to another aspect of this disclosure, a semiconductor structure is provided, formed using the method described in any of the above embodiments.
[0042] According to another aspect of this disclosure, a memory system is provided, comprising:
[0043] One or more semiconductor structures as described in the above scheme; and
[0044] A memory controller that is coupled to and controls the semiconductor structure.
[0045] This disclosure provides a semiconductor structure and a method for fabricating the same. The method includes: providing a first insulating layer and forming a plurality of sacrificial material pillars in the first insulating layer; removing the top portion of each sacrificial material pillar to form a plurality of first grooves; enlarging the plurality of first grooves to form a plurality of second grooves; removing the remaining portion of the sacrificial material pillars to form a plurality of third grooves; filling the second grooves with a first conductive material and filling the third grooves with a second conductive material, wherein the top portion of the first conductive material in each second groove is in contact with a portion of the top portion of the first conductive material in at least one adjacent second groove; removing the first insulating layer; removing the first conductive material, wherein the second conductive material is used to form a first electrode of a memory structure. In this embodiment of the disclosure, a second groove is obtained by enlarging the first groove, such that the first conductive material at the top of each second groove is in contact with the first conductive material at the top of at least one adjacent second groove. That is, the first conductive material in the second groove can form a support layer to support the second conductive material, thereby improving the collapse problem when forming the first electrode. In addition, since the first conductive material at the top of each second groove is in contact with the first conductive material at the top of at least one adjacent second groove, there is a first insulating layer between the first conductive material at the top of each second groove and the first conductive material at the top of the adjacent second groove, making it easier to remove the first insulating layer. Attached Figure Description
[0046] Figure 1 This is a schematic diagram of the circuit connection of a DRAM transistor provided in an embodiment of this disclosure;
[0047] Figures 2-5 A cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of this disclosure;
[0048] Figure 6 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;
[0049] Figures 7-20 A cross-sectional schematic diagram of the fabrication process of a semiconductor structure provided in an embodiment of this disclosure;
[0050] Figures 21 to 29 This is a three-dimensional structural diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation
[0051] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.
[0052] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0053] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0054] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.
[0055] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.
[0056] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.
[0057] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0058] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only.
[0059] However, it should be noted that the following description of dynamic random access memory is only for illustrating this disclosure and is not intended to limit the scope of this disclosure.
[0060] In some embodiments of this disclosure, the dynamic random access memory is composed of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, the dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.
[0061] Figure 1 This is a circuit connection diagram of a 1T1C architecture provided in an embodiment of this disclosure; as shown... Figure 1 As shown, the drain of transistor T is electrically connected to the bit line (BL), and the source of transistor T is electrically connected to one of the electrode plates of capacitor C. The other electrode plate of capacitor C can be connected to a reference voltage, which can be ground or other voltages. The gate of transistor T is connected to the word line (WL). The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on.
[0062] As memory technology advances, the size of dynamic random access memory (DRAM) continues to shrink, while the storage capacity of memory continues to increase, making the process of forming capacitors increasingly difficult.
[0063] This disclosure provides a method for fabricating a semiconductor structure, the method comprising: firstly, as... Figure 2 As shown, a fifth groove 117 is formed in the first insulating layer 101, wherein the aspect ratio of the fifth groove 117 is approximately 50:1; as Figure 3 As shown, conductive material is filled into the fifth groove 117 to form a first electrode 106, which is the lower electrode of the capacitor; as Figure 4 As shown, the first insulating layer 101 surrounding the first electrode 106 is removed using a wet etching process; next, as... Figure 5 As shown, a dielectric layer 108 is formed around the first electrode 106, and a second electrode 109 is formed around the dielectric layer 108. The dielectric layer 108 serves as the dielectric of the capacitor, and the second electrode 109 serves as the upper electrode of the capacitor. The dielectric layer 108, the first electrode 106, and the second electrode 109 together constitute the capacitor.
[0064] Research has found that in the semiconductor structure fabrication method provided in the above embodiments, during the process of removing the first insulating layer 101 surrounding the first electrode 106 to form the first electrode 106 using a wet etching process, the wet etching solution is adsorbed on the surface of the first electrode 106. Due to the surface tension of the wet etching solution, adjacent first electrodes 106 tend to tilt and approach each other or even connect together. In addition, due to the large aspect ratio of the first electrode 106, the first electrode 106 is at risk of collapse.
[0065] Therefore, in order to solve the above problems, this disclosure provides another method for fabricating a semiconductor structure, which can improve the collapse problem. Figure 6 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 6 As shown, the method for fabricating a semiconductor structure provided in this embodiment includes the following steps:
[0066] S100: Provide a first insulating layer, in which a plurality of sacrificial material pillars are formed;
[0067] S200: Remove the top portion of each of the sacrificial material columns to form a plurality of first grooves;
[0068] S300: The plurality of first grooves are enlarged to form a plurality of second grooves;
[0069] S400: Remove the remaining portion of the sacrificial material column to form a plurality of third grooves;
[0070] S500: The second groove is filled with a first conductive material, and the third groove is filled with a second conductive material, wherein the first conductive material at the top of each second groove is in contact with a portion of the first conductive material at the top of at least one adjacent second groove;
[0071] S600: Remove the first insulating layer;
[0072] S700: Remove the first conductive material, and the second conductive material is used to form the first electrode of the storage structure.
[0073] It should be understood that Figure 6 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 6 The steps shown can be adjusted in order according to actual needs. Figures 7 to 20 A cross-sectional schematic diagram of the fabrication process of a semiconductor structure provided in an embodiment of this disclosure; Figures 21 to 29 This is a three-dimensional structural diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this disclosure. It should be noted that... Figures 7 to 20 This is a schematic diagram illustrating the entire process of manufacturing a semiconductor structure. Some parts not marked in the accompanying drawings can be shared with each other. Figures 21 to 29 This is a schematic diagram illustrating the complete manufacturing process of a semiconductor structure. Unmarked parts in some of the accompanying drawings can be shared. The following section combines... Figure 2 , Figures 7 to 20 , Figures 21 to 29 The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail.
[0074] In step S100, as Figures 7 to 9 as well as Figures 21 to 22 As shown, multiple sacrificial material pillars 102 are mainly formed in the first insulating layer 101.
[0075] here, Figure 8 It shows in Figure 9 A cross-sectional view of position AA'. In some specific examples, the material of the first insulating layer 101 includes, but is not limited to, silicon nitride and silicon oxide.
[0076] In some specific examples, the methods for forming the first insulating layer 101 include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and other processes.
[0077] In some specific examples, the process of forming the sacrificial material pillar 102 includes: forming a fourth groove 116 in the first insulating layer 101; filling the fourth groove 116 with sacrificial material to form the sacrificial material pillar 102.
[0078] In some specific examples, when the sacrificial material is filled in the fourth groove 116, the top surface of the first insulating layer 101 is also filled with sacrificial material. After the sacrificial material is filled, the sacrificial material is planarized to expose the top surface of the first insulating layer 101.
[0079] In some specific examples, the planarization process includes, but is not limited to, CMP.
[0080] In some specific examples, the method for forming the fourth groove 116 includes, but is not limited to, dry etching process, specifically dry plasma etching process.
[0081] In some specific examples, the methods for filling the sacrificial material include, but are not limited to, PVD, CVD, and ALD.
[0082] Here, regarding the selection of the sacrificial material, on the one hand, it is necessary to consider that the sacrificial material has a certain etching selectivity relative to the first insulating layer 101, so as to reduce the impact on the first insulating layer 101 when removing the sacrificial material; on the other hand, the sacrificial material needs to be easy to remove in subsequent processes.
[0083] In some specific examples, the material of the sacrificial material column 102 includes, but is not limited to, carbon.
[0084] In some embodiments, such as Figure 21 As shown, the plurality of sacrificial material pillars 102 are arranged in an array along a first direction and a second direction, the first direction and the second direction intersect and are both perpendicular to the direction of the thickness of the first insulating layer 101.
[0085] Here, the first direction intersects with the second direction, which can be understood as the angle between the first direction and the second direction being 0-90 degrees.
[0086] To clearly describe this disclosure, the following embodiments are illustrated using the example of a first direction being perpendicular to a second direction. For example, the first direction is... Figure 21 The X-axis direction shown in the figure; the second direction is Figure 21 The Y-axis direction is shown in the figure; the third direction in the following text is... Figure 21 The Z-axis direction is shown in the figure. However, it should be noted that the description of the direction in the following embodiments is for illustrative purposes only and is not intended to limit the scope of this disclosure.
[0087] In some embodiments, forming a plurality of sacrificial material pillars 102 in the first insulating layer 101 includes:
[0088] Multiple sacrificial material pillars 102, which are circular or elliptical in shape, are formed on the surface of the first insulating layer 101.
[0089] It should be noted that the shape of the projection of the sacrificial material pillar 102 onto the surface of the first insulating layer 101 in the above embodiments is merely an exemplary demonstration and is not intended to limit the shape of the projection of the sacrificial material pillar 102 onto the surface of the first insulating layer 101 in this disclosure. The shape of the projection of the sacrificial material pillar 102 onto the surface of the first insulating layer 101 includes, but is not limited to, a circle, an ellipse, and a rectangle. In this embodiment, a circle is used as an example for illustrative explanation.
[0090] It is understandable that when the projection of the sacrificial material column 102 onto the surface of the first insulating layer 101 is circular, the process is easier to control, so that the first conductive material at the top of each second groove formed in the subsequent process is in partial contact with the first conductive material at the top of the two adjacent second grooves along the first direction, and is in partial contact with the first conductive material at the top of the two adjacent second grooves 104 along the second direction, thereby achieving a better support for the second conductive material filled in the third groove in the subsequent process.
[0091] Figure 9 A top view schematic diagram of the semiconductor structure is shown when the sacrificial material pillar 102 is cylindrical. (See diagram below.) Figure 9 As shown, the sacrificial material pillars 102 are arranged in an array along the first and second directions, and a first insulating layer 101 is formed between the sacrificial material pillars 102.
[0092] In some embodiments, such as Figure 7 As shown, the method further includes:
[0093] Multiple transistor units 10 are formed; the transistor units 10 are coupled to the first electrode 106 (in Figure 7 The first electrode 106 has not yet been formed, and the transistor unit 10 is coupled to the first electrode 106. Figure 20 (as shown in the image).
[0094] The first electrode 106 here is the lower electrode of a storage structure such as a capacitor.
[0095] It should be noted that the order in which the transistor unit 10 and the memory structure are formed is not limited. The transistor unit 10 can be formed after the memory structure is formed or before the memory structure is formed. In this embodiment, the transistor unit 10 is formed first and then the memory structure is formed as an example for illustrative explanation.
[0096] In some embodiments, the transistor forming unit 10 includes:
[0097] A semiconductor layer 111 is provided, which is stacked with the first insulating layer 101;
[0098] A first transistor 1001 and a second transistor 1002 are formed in the semiconductor layer 111 in a symmetrical arrangement along a third direction. Each of the first transistor 1001 and the second transistor 1002 includes a source 112, a drain 113, a channel region, a gate 114, and a gate oxide layer 115. The extension direction of the channel region of the first transistor 1001 and the second transistor 1002 is perpendicular to the third direction, and the first transistor 1001 and the second transistor 1002 share a source 112 or a drain 113. The third direction is parallel to the thickness direction of the first insulating layer 101. The first electrode 106 is coupled to one of the source 112 and the drain 113 of the transistor unit 10.
[0099] Here, the positional relationship between the storage structure and the transistor cell 10 is not limited to that in this disclosure. Figure 7 As shown, in practical applications, the storage structure can be located above or below the transistor cell 10. For example, when the semiconductor layer 111 is above the first insulating layer 101, the storage structure is located below the transistor cell 10; when the semiconductor layer 111 is below the first insulating layer 101, the storage structure is located above the transistor cell 10.
[0100] It should be noted that, Figure 7 The diagram only shows the case where the first transistor 1001 and the second transistor 1002 share the drain 113. Figure 7 The above is merely an exemplary demonstration and is not intended to limit the embodiments disclosed herein. The first transistor 1001 and the second transistor 1002 may also share the source 112.
[0101] It should be noted that the structural limitations of the transistors in the above embodiments are merely illustrative examples and are not intended to limit the structure of the transistors in this disclosure. In practical applications, the structure of the transistors coupled to the storage structure is not limited to these.
[0102] In some specific examples, the semiconductor layer 111 may include a substrate, which may include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.
[0103] Here, the gate oxide layer is located between the gate 114 and the channel region to electrically isolate the channel region and the gate 114, thereby reducing the hot carrier effect of the transistor.
[0104] In some specific examples, the material of gate 114 includes, but is not limited to, polysilicon, conductive metal, or conductive alloy. Conductive metal may include tungsten or copper, etc.
[0105] In some specific examples, the methods for forming the gate oxide layer 115 include, but are not limited to, PCD, CVD, and ALD.
[0106] In some specific examples, the gate oxide layer 115 includes, but is not limited to, silicon oxide.
[0107] In some specific examples, the methods for forming the source 112 and drain 113 include, but are not limited to, doping and diffusion processes. In some specific examples, the first transistor 1001 and the second transistor 1002 can be N-type transistors or P-type transistors.
[0108] In an N-type transistor, both the source 112 and the drain 113 are N-type doped; in a P-type transistor, both the source 112 and the drain 113 are P-type doped. For example, when the doping type is P-type, the P-type impurity source can be boron (B), aluminum (Al), etc., and is not limited to these; when the doping type is N-type, the N-type impurity source can be phosphorus (P), arsenic (As), etc., and is not limited to these.
[0109] Here, the first transistor 1001 and the second transistor 1002 are symmetrically distributed along the third direction, which can be referred to as... Figure 7 To understand: Both the first transistor 1001 and the second transistor 1002 include a source 112, a drain 113, a channel region, a gate 114, and a gate oxide layer 115. The gate 114 of both the first transistor 1001 and the second transistor 1002 is located on the gate oxide layer 115. The source 112 and drain 113 of the transistor are formed in the semiconductor layer 111. The first transistor 1001 and the second transistor 1002 in a transistor unit 10 can share either the source 112 or the drain 113. The choice can be made based on actual needs.
[0110] In some specific examples, such as Figure 7 As shown, a third insulating layer 118 is also formed on the semiconductor layer 111, and the gate oxide layer 115, the gate 114, the lead of the source 112, and the lead of the drain 113 of the transistor unit 10 are formed in the third insulating layer 118.
[0111] In some specific examples, the material of the third insulating layer 118 includes, but is not limited to, silicon oxide and silicon nitride.
[0112] In some specific examples, the methods for forming the third insulating layer 118 include, but are not limited to, PVD, CVD, and ALD.
[0113] In step S200, the main task is to form a plurality of first grooves 103.
[0114] like Figure 10 as well as Figure 23 As shown, the top portion of the sacrificial material column 102 is removed to form the first groove 103.
[0115] In some specific examples, the methods for removing the top portion of the sacrificial material pillar 102 include, but are not limited to, dry etching and wet etching processes. For example, the removal of only the top portion of the sacrificial material pillar 102 can be achieved by controlling the time of wet etching and dry etching.
[0116] In step S300, as Figures 11 to 13 as well as Figure 24 The main process involves enlarging the first groove 103 to form the second groove 104.
[0117] It should be noted that, Figure 11 as well as Figure 12 It shows in Figure 13 A cross-sectional view of position AA'.
[0118] In some specific examples, the methods for enlarging the first groove 103 include, but are not limited to, dry etching.
[0119] After the first groove 103 is enlarged, the tops of the second grooves 104 are interconnected, and a portion of the first insulating layer 101 is formed between the tops of the second grooves 104.
[0120] like Figure 11 As shown, a cross-sectional view of a second groove 104 is presented, from... Figure 11 As can be seen, the cross-sectional shape of the second groove 104 is funnel-shaped. In other specific examples, the shape of the second groove 104 can also be as follows: Figure 12 The cylindrical shape shown. Figure 11 as well as Figure 12The image shows two second grooves, from... Figure 11 as well as Figure 12 It can be seen that the two second grooves are interconnected. To more clearly illustrate the situation of the formed second groove 104, Figure 13 A top view is shown after the second groove 104 has been formed. Figure 13 It can be seen that after the first groove 103 is enlarged, the second groove 104 formed is interconnected with the adjacent second groove 104, forming a connected filling area.
[0121] It should be noted that only two cross-sectional views of the second groove are shown here. In practical applications, the cross-sectional views of the second groove are not limited to these. The cross-sectional shape of the second groove is related to the adjustment of process parameters during manufacturing and the shape of the sacrificial material column, etc.
[0122] In step S400, as Figure 14 as well as Figure 25 As shown, the main process involves removing the remaining portion of the sacrificial material column 102 to form multiple third grooves 105 (e.g., Figure 14 (The part within the dashed box).
[0123] In some specific examples, the methods for removing the sacrificial material pillar 102 include, but are not limited to, wet etching and dry etching processes.
[0124] In step S500, as Figure 15 , Figure 16 as well as Figure 26 As shown, the second groove 104 is filled with a first conductive material 106-1, and the third groove 105 is filled with a second conductive material 106-2. The first conductive material 106-1 at the top of each second groove 104 is in contact with the first conductive material 106-1 at the top of at least one adjacent second groove 104.
[0125] It should be noted that, Figure 15 It shows in Figure 16 A cross-sectional view of position AA'.
[0126] Here, the first conductive material 106-1 at the top of each second groove 104 is in partial contact with the first conductive material 106-1 at the top of at least one adjacent second groove 104. This can be understood as the first conductive material at the top of each second groove being interconnected with the first conductive material at the top of the adjacent second groove. This prevents the second conductive material formed in each third groove from forming independent, large-diameter columnar bodies after the first insulating layer is completely removed, thus avoiding collapse. In other words, in this embodiment, the first conductive material at the top of the second groove constitutes a top support layer, thereby mitigating the collapse problem. Furthermore, the first conductive material 106-1 at the top of each second groove 104 is in partial contact with the first conductive material 106-1 at the top of at least one adjacent second groove 104, and a first insulating layer 101 exists between the first conductive material 106-1 at the top of each second groove 104 and the first conductive material 106-1 at the top of the adjacent second groove 104, making it easier to remove the first insulating layer 101 in subsequent processes.
[0127] Here, a first insulating layer 101 exists between the first conductive material 106-1 at the top of each second groove 104 and the first conductive material 106-1 at the top of the adjacent second groove 104, which can be referenced. Figure 13 To understand this, each second groove 104 is not in complete contact with the adjacent second groove 104, as shown in... Figure 13 There are gaps between the four second grooves 104 shown in the dashed box, in which the first insulating layer 101 is retained. The top surface of the first insulating layer 101 retained between the second grooves 104 is exposed, so that the first insulating layer 101 can be removed from the exposed top surface of the first insulating layer 101 in subsequent processes.
[0128] It should be noted that, in addition to the top portion, the first conductive material 106-1 in the second groove 104 may also have partial contact in the middle and bottom portions. This is related to the shape of the formed second groove 104. Figure 12 The cross-sectional view of the second groove 104 shown in the figure is similar to that shown in the figure. Figure 24 The three-dimensional structural diagram of the second groove 104 shown corresponds to the shape of the second groove 104. Figure 12 as well as Figure 24 When the shape shown is such that the first conductive material 106-1 at the top, middle and bottom of the second groove 104 is also in partial contact, this makes the support effect better.
[0129] In some embodiments, the first conductive material 106-1 at the top of each second groove 104 is in partial contact with the first conductive material 106-1 at the top of the two adjacent second grooves 104 along the first direction, and is also in partial contact with the first conductive material 106-1 at the top of the two adjacent second grooves 104 along the second direction.
[0130] It is understood that when the first conductive material 106-1 at the top of each second groove 104 is in partial contact with the first conductive material 106-1 at the top of the two adjacent second grooves 104 along the first direction, and is in partial contact with the first conductive material 106-1 at the top of the two adjacent second grooves 104 along the second direction, the first conductive material in each second groove is supported on all four sides, thereby improving the support effect.
[0131] In some embodiments, the first conductive material 106-1 and the second conductive material 106-2 are made of the same material.
[0132] In some specific examples, the first conductive material 106-1 and the second conductive material 106-2 can be filled simultaneously.
[0133] In some specific examples, the first conductive material 106-1 and the second conductive material 106-2 may include, but are not limited to, titanium nitride (TiN).
[0134] In some specific examples, the methods for filling the first conductive material 106-1 and the second conductive material 106-2 include, but are not limited to, PVD, CVD, and ALD.
[0135] In some embodiments, after forming a plurality of second grooves 104, a portion of a first insulating layer 101 is also present between the second grooves 104, the first insulating layer 101 having an exposed top surface.
[0136] In some embodiments, filling the second groove 104 with the first conductive material 106-1 includes:
[0137] The second groove 104 and the top surface of the first insulating layer 101 are filled with a first conductive material 106-1;
[0138] The method further includes:
[0139] After filling with the first conductive material 106-1, a portion of the first conductive material 106-1 is removed by a chemical mechanical polishing process, thereby exposing the top surface of the first insulating layer 101.
[0140] Understandably, the first insulating layer is exposed here primarily to allow it to be removed from its top surface in subsequent processes. If the top surface of the first insulating layer is completely covered by the first conductive material, it would be difficult to remove the first insulating layer to form the subsequent dielectric layer and second electrode.
[0141] In step S600, as Figure 17 as well as Figure 27 As shown, the main process involves removing the first insulating layer 101 to form the first filling region 107.
[0142] In some specific examples, the methods for removing the first insulating layer 101 include, but are not limited to, wet etching processes.
[0143] It is understandable that when the wet etching process is used to remove the first insulating layer 101, although the etching solution causes the surfaces of the first conductive material 106-1 and the second conductive material 106-2 to have a certain surface tension, the first conductive material 106-1 formed in the second groove 104 constitutes the top support layer, thereby making it difficult for the second conductive material 106-2 in the third groove 105 to collapse.
[0144] In some embodiments, removing the first insulating layer 101 includes:
[0145] Remove the first insulating layer 101 between the plurality of second grooves 104 and between the plurality of third grooves 105 from the exposed top surface of the first insulating layer 101.
[0146] In some embodiments, such as Figure 17 as well as Figure 27 As shown, when the first insulating layer 101 is removed, a first filling region 107 is formed;
[0147] like Figure 18 as well as Figure 28 As shown, the method further includes:
[0148] The first filling region 107 is sequentially filled with dielectric material 108-1 and third conductive material 109-1.
[0149] In some specific examples, the dielectric material 108-1 includes a high-k dielectric material, which generally refers to a material with a dielectric constant higher than 3.9, and is usually significantly higher than that value. In some specific examples, the dielectric material 108-1 may include, but is not limited to, alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc.
[0150] In some specific examples, the third conductive material 109-1 may include, but is not limited to, titanium nitride.
[0151] Here, the methods for filling the dielectric material 108-1 and the third conductive material 109-1 include, but are not limited to, processes such as PVD, CVD, and ALD.
[0152] In step S700, as Figure 19 as well as Figure 29 As shown, the main process involves removing the first conductive material 106-1 and the second conductive material 106-2, which are used to form the first electrode 106 of the storage structure.
[0153] In some embodiments, removing the first conductive material 106-1 includes:
[0154] The first conductive material 106-1 is removed, and the dielectric material 108-1 and the third conductive material 109-1 surrounding the first conductive material 106-1 are also removed. The remaining dielectric material 108-1 and the third conductive material 109-1 are used to form the dielectric layer 108 and the second electrode 109 of the storage structure, respectively.
[0155] Here, the first electrode 106, the dielectric layer 108, and the second electrode 109 together constitute a storage structure. The first electrode 106 is used as the lower electrode of the capacitor; the dielectric layer 108 is used as the dielectric of the capacitor; and the second electrode 109 is used as the upper electrode of the capacitor.
[0156] In some embodiments, such as Figure 20 As shown, the method further includes:
[0157] After forming the first electrode 106, the dielectric layer 108, and the second electrode 109, a second insulating layer 110 is formed in the gap between two adjacent second electrodes 109.
[0158] Here, the material of the second insulating layer 110 includes, but is not limited to, silicon nitride and silicon oxide.
[0159] Here, the second insulating layer 110 can be used to isolate multiple capacitors and improve mutual interference between them.
[0160] In some embodiments, the method further includes:
[0161] Multiple bit lines are formed; the bit lines are coupled to another of the source 112 and drain 113 of the transistor unit 10.
[0162] It is understood that the bit line BL is used to perform read or write operations on the transistor when the transistor is turned on.
[0163] In some specific examples, bit lines are formed by forming metal lines at predetermined bit line locations. These metal lines include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or any combination thereof.
[0164] In some embodiments, the semiconductor structure includes dynamic random access memory.
[0165] The embodiments disclosed herein merely exemplify some common memories, and the scope of protection of this disclosure is not limited thereto. Any memory containing the semiconductor structure provided in the embodiments of this disclosure falls within the scope of protection of this invention.
[0166] It is understood that, in this embodiment of the present disclosure, on the one hand, in the process of forming the first electrode 106, the first conductive material 106-1 in the second groove 104 is used as a support layer, which can improve the collapse problem in the process of forming the first electrode 106. On the other hand, in the process of forming the first electrode 106, the second conductive material 106-2 is filled at the same time as the first conductive material 106-1 is filled, and the first conductive material 106-1 is directly used as a support layer, without the need to use other materials to form a separate support layer. The process is simple and can save process costs.
[0167] This disclosure provides a semiconductor structure and a method for fabricating the same. The method includes: providing a first insulating layer 101; forming a plurality of sacrificial material pillars 102 in the first insulating layer 101; removing the top portion of each sacrificial material pillar 102 to form a plurality of first grooves 103; enlarging the plurality of first grooves 103 to form a plurality of second grooves 104; removing the remaining portion of the sacrificial material pillars 102 to form a plurality of third grooves 105; filling the second grooves 104 with a first conductive material 106-1 and filling the third grooves 105 with a second conductive material 106-2, wherein the top of the first conductive material 106-1 in each second groove 104 is in partial contact with the top of at least one adjacent second groove 104; removing the first insulating layer 101; removing the first conductive material 106-1; and using the second conductive material 106-2 to form a first electrode 106 of a memory structure. In this embodiment, a second groove 104 is obtained by enlarging the first groove 103, such that the first conductive material 106-1 at the top of each second groove 104 is in partial contact with the first conductive material 106-1 at the top of at least one adjacent second groove 104. That is, the first conductive material 106-1 in the second groove 104 can form a support layer to support the second conductive material 106-2, thereby improving the collapse problem when forming the first electrode 106. In addition, since the first conductive material 106-1 at the top of each second groove 104 is in partial contact with the first conductive material 106-1 at the top of at least one adjacent second groove 104, there is a first insulating layer 101 between the first conductive material 106-1 at the top of each second groove 104 and the first conductive material 106-1 at the top of the adjacent second groove 104, making it easier to remove the first insulating layer 101.
[0168] According to another aspect of this disclosure, embodiments of this disclosure also provide a semiconductor structure formed using a semiconductor structure fabrication method as described in any of the above embodiments.
[0169] The semiconductor structure provided in the above embodiments has been described in detail in the method section and will not be repeated here.
[0170] According to another aspect of this disclosure, embodiments of this disclosure also provide a memory system, including:
[0171] One or more semiconductor structures as described in the above embodiments; and
[0172] A memory controller that is coupled to and controls the semiconductor structure.
[0173] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form a final device structure. Here, the final device may include a memory.
[0174] In some specific examples, the memory system includes a memory card or a solid-state drive.
[0175] In some specific examples, the memory controller is coupled to the memory and the host and is configured to control the memory. The memory controller can manage the data stored in the memory and communicate with the host. In some implementations, the memory controller is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some implementations, the memory controller is designed to operate in high-duty-cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which serve as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.
[0176] A memory controller and one or more memories can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system can be implemented and packaged into different types of end electronic products. For example, a memory controller and a single memory can be integrated into a memory card. Memory cards can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card connector that couples the memory card to the host. For example, a memory controller and multiple memories can be integrated into an SSD. The SSD may also include an SSD connector that couples the SSD to the host.
[0177] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.
[0178] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.
[0179] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A first insulating layer is provided, and a plurality of sacrificial material pillars are formed in the first insulating layer; The top portion of each of the sacrificial material columns is removed to form a plurality of first grooves; The plurality of first grooves are enlarged to form a plurality of second grooves; Remove the remaining portion of the sacrificial material column to form multiple third grooves; The second groove is filled with a first conductive material, and the third groove is filled with a second conductive material, wherein the first conductive material at the top of each second groove is in contact with a portion of the first conductive material at the top of at least one adjacent second groove; Remove the first insulating layer; Remove the first conductive material, and use the second conductive material to form the first electrode of the storage structure.
2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The plurality of sacrificial material pillars are arranged in an array along a first direction and a second direction, the first direction and the second direction intersect and are both perpendicular to the direction of the thickness of the first insulating layer; the first conductive material at the top of each second groove is in partial contact with the first conductive material at the top of the two adjacent second grooves along the first direction, and is also in partial contact with the first conductive material at the top of the two adjacent second grooves along the second direction.
3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The first conductive material and the second conductive material are made of the same material.
4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, After forming multiple second grooves, a portion of a first insulating layer is present between the second grooves, the first insulating layer having an exposed top surface.
5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The step of filling the second groove with a first conductive material includes: The second groove and the top surface of the first insulating layer are filled with a first conductive material; The method further includes: After filling with the first conductive material, a portion of the first conductive material is removed by a chemical mechanical polishing process, thereby exposing the top surface of the first insulating layer.
6. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The removal of the first insulating layer includes: Remove the first insulating layer between the plurality of second grooves and the first insulating layer between the plurality of third grooves from the exposed top surface of the first insulating layer.
7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The formation of a plurality of sacrificial material pillars in the first insulating layer includes: Multiple sacrificial material pillars with a circular or elliptical projected shape are formed on the surface of the first insulating layer.
8. The method for fabricating a semiconductor structure according to claim 1, characterized in that, When the first insulating layer is removed, a first filling region is formed; The method further includes: The first filling region is sequentially filled with a dielectric material and a third conductive material; The removal of the first conductive material includes: The first conductive material is removed, along with the dielectric material and the third conductive material surrounding the first conductive material. The remaining dielectric material and the third conductive material are used to form the dielectric layer and the second electrode of the storage structure, respectively.
9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The method further includes: After forming the first electrode, the dielectric layer, and the second electrode, a second insulating layer is formed in the gap between two adjacent second electrodes.
10. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The method further includes: Multiple transistor units are formed; the transistor units are coupled to the first electrode.
11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, The transistor forming unit includes: A semiconductor layer is provided, wherein the semiconductor layer is stacked with the first insulating layer; A first transistor and a second transistor are formed in the semiconductor layer in a symmetrical arrangement along a third direction; each of the first transistor and the second transistor includes a source, a drain, a channel region, a gate, and a gate oxide layer; the extension direction of the channel region of the first transistor and the second transistor is perpendicular to the third direction, and the first transistor and the second transistor share a source or a drain; the third direction is parallel to the thickness direction of the first insulating layer; the first electrode is coupled to one of the source and drain of the transistor unit.
12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The method further includes: Multiple bit lines are formed; each bit line is coupled to another of the source and drain of the transistor cell.
13. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes dynamic random access memory.
14. A semiconductor structure, characterized in that, Formed using the method described in any one of claims 1-13.
15. A memory system, characterized in that, include: One or more semiconductor structures as described in claim 14; as well as A memory controller that is coupled to and controls the semiconductor structure.