A display panel, a manufacturing method of the display panel, and a display device

Abstract

This invention discloses a display panel, a method for manufacturing the display panel, and a display device. The display panel includes a substrate; at least two source electrodes, a drain electrode, at least two active layers corresponding to the source electrodes, an insulating layer, and a gate electrode disposed on the substrate; the source electrodes are correspondingly connected to the active layers; the drain electrodes are respectively connected to each active layer; an insulating layer is disposed between the gate electrode and the source electrodes; the orthographic projection of the gate electrode onto the substrate at least partially overlaps with the orthographic projection of each active layer onto the substrate. The technical solution provided by the embodiments of this invention improves the uniformity of brightness of the display panel when displaying low grayscale images, thereby improving the display effect of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel, a method for manufacturing the display panel, and a display device. Background Technology

[0002] With the development of display technology, people's requirements for display technology are also getting higher and higher. The driving current of the pixel driving circuit in the display panel is getting smaller and smaller, which makes the current control of the display panel less precise, resulting in poor uniformity of display brightness and affecting the display effect. Summary of the Invention

[0003] This invention provides a display panel, a method for manufacturing the display panel, and a display device to solve the problem that insufficient current control in the display panel leads to poor uniformity of display brightness and affects the display effect.

[0004] According to one aspect of the present invention, a display panel is provided, comprising:

[0005] substrate;

[0006] At least two source electrodes, a drain electrode, at least two active layers corresponding to the source electrodes, an insulating layer and a gate electrode are disposed on the substrate;

[0007] The source electrode is connected to the corresponding active layer; the drain electrode is connected to each active layer respectively.

[0008] An insulating layer is provided between the gate and the source;

[0009] The orthographic projection of the gate onto the substrate at least partially overlaps with the orthographic projection of each active layer onto the substrate.

[0010] Optionally, when at least two active layers are located on opposite sides of the gate along the thickness direction perpendicular to the substrate, the orthographic projection of the active layer located on the side of the gate closer to the substrate onto the substrate and the orthographic projection of the active layer located on the side of the gate farther from the substrate onto the substrate at least partially overlap.

[0011] Optionally, the active layer includes a first active layer and a second active layer; the source includes a first source and a second source; the first source is connected to the first active layer, and the second source is connected to the second active layer;

[0012] The first active layer is disposed on the side of the gate closest to the substrate; the second active layer is disposed on the side of the gate away from the substrate;

[0013] Preferably, the insulating layer includes a first gate insulating layer and a second gate insulating layer; the first gate insulating layer is disposed between the first active layer and the gate; and the second gate insulating layer is disposed between the second active layer and the gate.

[0014] Optionally, when at least two active layers are located on the same side of the gate along a direction perpendicular to the substrate thickness, the orthogonal projections of each active layer onto the substrate do not overlap.

[0015] Optionally, at least two active layers are disposed on the side of the gate closest to the substrate;

[0016] Preferably, at least two active layers are set on the same layer.

[0017] Optionally, the display panel further includes:

[0018] At least two power lines are provided corresponding to the source electrode, and the power lines are respectively connected to the source electrode. The power lines are used to transmit electrical signals to the source electrode.

[0019] Preferably, the electrical signals transmitted by each of the power lines are the same.

[0020] Optionally, the display panel may also include: light-emitting devices;

[0021] The light-emitting device is connected to the drain, and the drain is used to transmit a driving current signal to the light-emitting device; wherein, the current signal transmitted by the drain is equal to the sum of the current signals transmitted by each source.

[0022] Optionally, the source and drain can be configured to correspond one-to-one;

[0023] The power cords are configured to correspond one-to-one with the source terminals.

[0024] Secondly, embodiments of the present invention provide a method for manufacturing a display panel, comprising:

[0025] Provide substrate;

[0026] At least two sources, at least two drains, at least two active layers corresponding to the sources, an insulating layer, and a gate are disposed on a substrate; wherein the sources are connected to the active layers respectively; the drains are connected to each active layer respectively; the insulating layer is disposed between the gate and the source; the orthographic projection of the gate on the substrate at least partially overlaps with the orthographic projection of each active layer on the substrate.

[0027] Optionally, after forming at least two source electrodes, a drain electrode, at least two active layers corresponding to the source electrodes, an insulating layer, and a gate electrode on the substrate, the method further includes:

[0028] At least two power lines are provided on the substrate, corresponding to the source electrode, wherein the power lines are respectively connected to the source electrode and are used to transmit electrical signals to the source electrode.

[0029] Thirdly, embodiments of the present invention provide a display device, comprising: a display panel as described in any of the first aspects.

[0030] The technical solution of this invention involves configuring a display panel including at least two sources, at least two active layers corresponding to the sources, a drain, and a gate. Each source is connected to an active layer, and each drain is connected to an active layer. An insulating layer is disposed between the gate and the sources. The orthographic projection of the gate onto the substrate at least partially overlaps with the orthographic projection of each active layer onto the substrate. This configuration allows for a larger allowable voltage fluctuation range for each source, making it less likely for the drain current of the driving transistor to enter the subthreshold region. When displaying low grayscale images, the driving transistor can more precisely control the drain current, preventing small source voltage fluctuations from causing the drain current of the driving transistor to change by more than one grayscale level. This improves the uniformity of brightness in low grayscale display and thus improves the display effect.

[0031] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0034] Figure 1a This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0035] Figure 2 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0038] Figure 5 This is a graph showing the source-drain current of a driving transistor in a display panel as a function of the gate-source voltage, according to an embodiment of the present invention.

[0039] Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0040] Figure 7 This is an embodiment of the present invention providing a display panel edge Figure 1a A cross-sectional view along the AA' direction;

[0041] Figure 8 This is an embodiment of the present invention providing a display panel edge Figure 1a A cross-sectional view along the BB' direction;

[0042] Figure 9 This is a schematic diagram of the structure of a driving circuit for a display panel provided in another embodiment of the present invention;

[0043] Figure 10 This is a schematic diagram of the structure of a driving circuit for a display panel provided in another embodiment of the present invention;

[0044] Figure 11 This is a flowchart of a method for manufacturing a display panel according to an embodiment of the present invention;

[0045] Figure 12 This is a flowchart of another method for manufacturing a display panel provided in an embodiment of the present invention;

[0046] Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0047] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0048] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0049] As mentioned in the background section, the decreasing drive current of the pixel driving circuit in the display panel leads to inaccurate current control of the light-emitting devices, resulting in poor brightness uniformity and affecting the display effect. Through long-term research, the inventors discovered that when displaying low grayscale images, the drive current is relatively small. Under this low drive current, the driving transistor operates in the subthreshold region. Because the driving transistor operates in the subthreshold region, even small fluctuations in the source-drain voltage can cause large changes in current. This results in inaccurate current control of the driving transistor operating in the subthreshold region. Furthermore, even small fluctuations in the source voltage of the driving transistor can cause current changes exceeding one grayscale level, leading to poor brightness uniformity when displaying low grayscale images, and consequently, display murmurs.

[0050] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 1a This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 5 This is a graph showing the source-drain current of a driving transistor in a display panel as a function of the gate-source voltage, according to an embodiment of the present invention. (Combined with...) Figures 1 to 5 The display panel provided by the present invention includes a substrate 1, at least two source electrodes S, a drain electrode D, at least two active layers 10 corresponding to the source electrodes S, an insulating layer 2, and a gate electrode G disposed on the substrate 1; each source electrode S is correspondingly connected to an active layer 10; each drain electrode D is connected to each active layer 10; an insulating layer 2 is disposed between the gate electrode G and the source electrode S. The orthographic projection of the gate electrode G on the substrate 1 at least partially overlaps with the orthographic projection of each active layer 10 on the substrate 1.

[0051] Specifically, by connecting the source S to the active layer 10 and the drain D to each active layer 10, each source S is connected to one active layer 10. The orthographic projection of the gate G onto the substrate 1 at least partially overlaps with the orthographic projection of each active layer 10 onto the substrate 1, so that the source S and the corresponding connected active layer 10 form a branch. The number of branches can be equal to the number of sources S.

[0052] For example, Figure 1 and Figure 1aAn exemplary illustration shows a display panel comprising two sources S and two active layers 10. The sources S include a first source S1 and a second source S2, and the active layers 10 include a first active layer A1 and a second active layer A2. See also... Figure 1a The first source S1 is connected to the first active layer A1, and the orthographic projection of the gate G on the substrate 1 at least partially overlaps with the orthographic projection of the first active layer A1 on the substrate 1, so that the first source S1 and the first active layer A1 form a first branch. By connecting the second source S2 to the second active layer A2, the orthographic projection of the gate G on the substrate 1 at least partially overlaps with the orthographic projection of the second active layer A2 on the substrate 1, so that the second source S2 and the second active layer A2 form a second branch.

[0053] For example, Figure 2 An exemplary illustration shows a display panel comprising three sources S and three active layers 10. The sources S include a first source S1, a second source S2, and a third source S3, and the active layers 10 include a first active layer A1, a second active layer A2, and a third active layer A3. See also... Figure 3 The first source S1 is connected to the first active layer A1. The orthographic projection of the gate G onto the substrate 1 at least partially overlaps with the orthographic projection of the first active layer A1 onto the substrate 1, thus forming a first branch. The second source S2 is connected to the second active layer A2. The orthographic projection of the gate G onto the substrate 1 at least partially overlaps with the orthographic projection of the second active layer A2 onto the substrate 1, thus forming a second branch. The third source S3 is connected to the third active layer A3. The orthographic projection of the gate G onto the substrate 1 at least partially overlaps with the orthographic projection of the third active layer A3 onto the substrate 1, thus forming a third branch. It should be noted that the number of active layers 10 can be set as needed, and no limitation is made here.

[0054] Along a direction Y perpendicular to the thickness of the substrate 1, at least two active layers 10 are located on the same side or opposite sides of the gate G. For example, combined with... Figure 1 and Figure 2 Along the direction Y perpendicular to the thickness of substrate 1, the first active layer A1 and the second active layer A2 are located on the same side or opposite side of the gate G. This arrangement allows the first active layer A1 and the second active layer A2 to share the same gate G. It should be noted that... Figure 1 An exemplary illustration shows a case where the first active layer A1 and the second active layer A2 are located on opposite sides of the gate G along a direction Y perpendicular to the substrate 1, without any limitation. Figure 2 An exemplary illustration shows the case where the first active layer A1, the second active layer A2, and the third active layer A3 are located on the same side of the gate G along a direction Y perpendicular to the substrate 1, without any limitation. Figure 3 and Figure 4 An exemplary illustration shows a case in which the first active layer A1 and the third active layer A3 are located on the same side of the gate G along the direction Y perpendicular to the substrate 1, and the second active layer A2 and the first active layer A1 are located on opposite sides of the gate G, without any limitation.

[0055] The drain D is connected to each active layer 10, thus creating multiple branches formed by each source S and its corresponding active layer 10. These multiple branches are connected in parallel through the drain D, so that the current flowing through the driving transistor used to drive the light-emitting device comes from the smaller current of each branch. Since the current in each branch is less than the current of the driving transistor used to drive the light-emitting device, the source-drain voltage D of each branch is relatively small.

[0056] For example, see Figure 1 The drain D is connected to the first source S1 and the second source S2, respectively. This configuration ensures that the first branch formed by the first source S1 and the first active layer A1, and the second branch formed by the second source S2 and the second active layer A2, are connected in parallel through the drain D. This allows the current flowing through the driving transistor used to drive the light-emitting device to come from two smaller currents in the first and second branches. Since the current in the first branch is less than the current in the driving transistor used to drive the light-emitting device, and the current in the second branch is also less than the current in the driving transistor used to drive the light-emitting device, the source-drain voltage D in both the first and second branches is relatively small.

[0057] For example, Figure 5 An exemplary diagram is shown, illustrating the variation of source-drain current of the driving transistors in a display panel with gate-source voltage. Figure 5 This includes curves showing the source-drain current versus gate-source voltage for a driving transistor with a source-drain voltage VDS of -1.1V, -2.1V, and -10.1V. Figure 1 and Figure 5 The curve following the small current flowing through the first active layer A1 can be set to reflect the change in source-drain current of the driving transistor as a function of the gate-source voltage when the source-drain voltage VDS is equal to -2.1V. Similarly, the curve following the small current flowing through the second active layer A2 can be set to reflect the change in source-drain current of the driving transistor as a function of the gate-source voltage when the source-drain voltage VDS is equal to -1.1V.

[0058] When the brightness of a light-emitting device is low, the voltage difference between the anode and cathode is small, resulting in a larger source-drain voltage VDS of the driving transistor. Since the drain current of the driving transistor exhibits a significant drain voltage dependence, it increases with increasing drain voltage. For the same change in drain current Ids, a driving transistor with a larger source-drain voltage VDS allows for a smaller range of variation in its gate-source voltage Vgs, while a driving transistor with a smaller source-drain voltage VDS allows for a larger range of variation in its gate-source voltage Vgs.

[0059] The first branch with a smaller source-drain voltage VDS allows for larger voltage fluctuations between the first source S1 and the gate G, while the second branch with a smaller source-drain voltage allows for larger voltage fluctuations between the second source S2 and the gate G. In other words, even if the data voltage fluctuation range transmitted across the first source S1 is large, the current change in the first branch with a smaller source-drain voltage VDS is smaller, and this smaller current change is less likely to cause gray-scale transitions. Similarly, even if the data voltage fluctuation range transmitted across the second source S2 is large, the current change in the second branch with a smaller source-drain voltage VDS is smaller, and this smaller current change is less likely to cause gray-scale transitions.

[0060] This configuration allows for a larger allowable voltage fluctuation range between each source (S) and gate (G), making it less likely for the drain current (D) of the driving transistor to enter the subthreshold region. This configuration enables more precise control of the source and drain currents of the driving transistors when displaying low grayscale images, preventing small source voltage fluctuations from causing drain current changes exceeding one grayscale level. This improves the uniformity of brightness in low grayscale displays, thereby enhancing the overall display performance.

[0061] The technical solution provided in this embodiment involves setting a display panel including at least two sources S, at least two active layers 10 corresponding to the sources S, a drain D, and a gate G. Each source S is connected to an active layer 10, and each drain D is connected to an active layer 10. An insulating layer 2 is disposed between the gate G and the sources S. The orthographic projection of the gate G onto the substrate 1 at least partially overlaps with the orthographic projection of each active layer 10 onto the substrate 1. This configuration allows for a larger allowable voltage fluctuation range for each source S, making it less likely for the drain current of the driving transistor to enter the subthreshold region. When displaying low grayscale images, the driving transistor can more precisely control the drain current, preventing small source voltage fluctuations from causing the drain current of the driving transistor to change by more than one grayscale level. This improves the uniformity of brightness in low grayscale display and thus improves the display effect of the display panel.

[0062] It should be noted that each active layer 10 provided in this embodiment can be one or more of amorphous silicon, polycrystalline silicon, oxide semiconductor, etc. Each active layer 10 can be simultaneously a P-type channel, simultaneously a N-type channel, or at least one can be an N-type channel and at least one a P-type channel; no limitations are made here. Optionally, based on the above embodiments, see further... Figure 1 In the display panel provided in this embodiment, when at least two active layers 10 are located on opposite sides of the gate G along the direction Y perpendicular to the thickness of the substrate 1, the orthographic projection of the active layer 10 located on the side of the gate G closer to the substrate 1 on the substrate 1 at least partially overlaps with the orthographic projection of the active layer 10 located on the side of the gate G away from the substrate 1 on the substrate 1.

[0063] Specifically, the orthographic projection of the active layer 10 on the side of the gate G near the substrate 1 onto the substrate 1 is at least partially overlapped with the orthographic projection of the active layer 10 on the side of the gate G away from the substrate 1 onto the substrate 1. This results in at least partial overlap between the active layers 10 on the side of the gate G near the substrate 1 and the active layers 10 on the side of the gate G away from the substrate 1, reducing the area of ​​the driving transistor perpendicular to the substrate 1. Preferably, the active layers 10 on the side of the gate G away from the substrate 1 and the active layers 10 on the side of the gate G near the substrate 1 can be completely aligned, further reducing the area of ​​the driving transistor perpendicular to the substrate 1 and saving space occupied by the driving transistor in the display panel.

[0064] Optionally, based on the above embodiments, see also... Figure 1 The active layer 10 of the display panel provided in this embodiment includes a first active layer A1 and a second active layer A2; the source S includes a first source S1 and a second source S2; the first source S1 is connected to the first active layer A1, and the second source S1 is connected to the second active layer A2; the first active layer A1 is disposed on the side of the gate G close to the substrate 1; the second active layer A2 is disposed on the side of the gate G away from the substrate 1.

[0065] Specifically, the first active layer A1 is disposed on the side of the gate G closest to the substrate 1, and the second active layer A2 is disposed on the side of the gate G away from the substrate 1, so that the gate G can be disposed between the first active layer A1 and the second active layer A2, so that the gate G can be made smaller. By transmitting an electrical signal to the gate G, the first source S1 is connected to the drain D through the first active layer A1, and the second source S2 is connected to the drain D through the second active layer A2.

[0066] Preferred, Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Based on the above embodiments, see... Figure 6The insulating layer 2 may include a first gate insulating layer 231 and a second gate insulating layer 232. The first gate insulating layer 231 is disposed between the first active layer A1 and the gate G; the second gate insulating layer 232 is disposed between the second active layer A2 and the gate G. This arrangement effectively insulates the gate G from the first active layer A1 through the first gate insulating layer 231 and from the second active layer A2 through the second gate insulating layer 232, preventing short circuits between the gate G and either the first or second active layer A1, and improving the reliability of the driving transistor. Optionally, the materials of the first gate insulating layer 231 and the second gate insulating layer 232 may be the same or different, and no limitation is made here.

[0067] Optionally, based on the above embodiments, see also... Figure 2 In the display panel provided in this embodiment, when at least two active layers 10 are located on the same side of the gate G along the direction perpendicular to the thickness of the substrate 1, the orthogonal projections of each active layer 10 on the substrate 1 do not overlap.

[0068] Specifically, this arrangement can better stagger the active layers 10, thereby making the gate G large enough to facilitate the co-fabrication of the source electrodes S, reducing the thickness of the display panel, and thus helping to thin the display panel.

[0069] Optional, Figure 7 This is an embodiment of the present invention providing a display panel edge Figure 1a A cross-sectional view along the AA' direction. Figure 8 This is an embodiment of the present invention providing a display panel edge Figure 1a A cross-sectional view along the BB' direction. Based on the above embodiments, combined with... Figure 7 and Figure 8 In this embodiment, at least two active layers 10 of the display panel are disposed on the side of the gate G near the substrate 1; preferably, at least two active layers 10 are disposed on the same layer.

[0070] Specifically, this configuration allows for larger voltage fluctuation ranges at the first source S1, second source S2, and third source S3, making it less likely for the drain current of the driving transistor to enter the subthreshold region. When displaying low grayscale images, the display panel can more precisely control the source and drain currents of the driving transistor, improving the uniformity of brightness when displaying low grayscale images. Furthermore, this configuration allows for further reduction in the thickness of the display panel, contributing to its thinner and lighter design.

[0071] Optional, Figure 9 This is a schematic diagram of the structure of a driving circuit for a display panel provided in an embodiment of the present invention. Figure 10This is a schematic diagram of the driving circuit for another display panel provided in an embodiment of the present invention. Based on the above embodiments, combined with... Figure 1 , Figure 1a , Figure 2 , Figure 5 , Figure 9 and Figure 10 The display panel may further include at least two power lines corresponding to the source terminal S, each power line being connected to the source terminal S and used to transmit electrical signals to the source terminal S. Preferably, the electrical signals transmitted by each power line are the same. Optionally, the source terminal S and the drain terminal D are configured in a one-to-one correspondence; the power lines are configured in a one-to-one correspondence with the source terminal S. Figure 9 An example is shown where the display panel may include: a first power line VDD1 and a second power line VDD2; the first power line VDD1 is used to transmit an electrical signal to the first source S1, and the second power line VDD2 is used to transmit an electrical signal to the second source S2. Figure 10 An exemplary illustration shows that the display panel may include: a first power line VDD1, a second power line VDD2, and a third power line VDD3; the first power line VDD1 is used to transmit an electrical signal to the first source S1, the second power line VDD2 is used to transmit an electrical signal to the second source S2, and the third power line VDD3 is used to transmit an electrical signal to the third source S3.

[0072] Specifically, in combination Figure 1 , Figure 1a and Figure 9 The first power line VDD1 is used to transmit an electrical signal to the first source S1. By adjusting the magnitude of the electrical signal transmitted through the first power line VDD1, the voltage signal received by the first source S1 can be adjusted, resulting in a larger voltage between the first source and the gate, and a smaller voltage between the first source S1 and the drain D. This, in turn, controls the current flowing through the first source S1 and the first active layer A1 to be smaller. This configuration allows for a larger allowable voltage fluctuation range for the first source S1, enabling more precise control of the drain current by the driving transistor. It prevents small source voltage fluctuations from causing changes in the drain current of the driving transistor exceeding one gray level, further improving the uniformity of brightness in low gray levels of the display panel, and thus improving the display effect of the display panel.

[0073] The second power line VDD2 is used to transmit electrical signals to the second source S2. By adjusting the magnitude of the electrical signal transmitted through the second power line VDD2, the voltage signal received by the second source S2 can be adjusted, resulting in a larger voltage between the second source and the gate, and a smaller voltage between the second source S2 and the drain D. This, in turn, controls the current flowing through the second source S2 and the second active layer A2 to be smaller. This configuration allows for a wider range of voltage fluctuations at the second source S2, enabling more precise control of the drain current by the driving transistor. It prevents small source voltage fluctuations from causing changes in the drain current of the driving transistor exceeding one gray level, further improving the uniformity of brightness in low gray levels of the display panel, and thus improving the display effect.

[0074] Because the current flowing through the second source S2 and the second active layer A2 is relatively small, the current signals of the first active layer A1 and the second active layer A2 converge at the drain D. This results in a smaller voltage between the first source S1 and the drain D, and a smaller voltage between the second source S2 and the drain D. Consequently, the characteristic that the current change rate with the gate-source voltage decreases near the subthreshold region of the driving transistor's source-drain D is reduced, thus achieving precise control of the grayscale voltage.

[0075] Preferably, the electrical signals transmitted on the first power line VDD1 and the second power line VDD2 are the same. This configuration allows for simultaneous adjustment of the electrical signals transmitted on both the first power line VDD1 and the second power line VDD2, reducing debugging difficulty and cost.

[0076] Optionally, based on the above embodiments, see also... Figure 9 The display panel provided in this embodiment may further include: a light-emitting device D1; the light-emitting device D1 is connected to a drain D, and the drain D is used to transmit a driving current signal to the light-emitting device D1; wherein, the current signal transmitted by the drain D is equal to the sum of the current signals transmitted by each source S1.

[0077] Specifically, the anode and drain D of the light-emitting device D1 are connected. When the voltage between the gate G of the driving transistor and the first source S1 is greater than the threshold voltage, the first source S1 and drain D of the driving transistor are turned on. When the voltage between the gate G of the driving transistor and the second source S2 is greater than the threshold voltage, the second source S2 and drain D are turned on. The current signals transmitted through the first source S1 and the second source S2 are both transmitted to the drain D, and then output to the anode of the light-emitting device D1. The current signal received by the anode of the light-emitting device D1 is equal to the sum of the current signal transmitted through the first source S1 through the first active layer A1 and the current signal transmitted through the second source S2 through the second active layer A2. This configuration ensures the brightness of the light-emitting device D1 while minimizing the current flowing through the first active layer A1 and the second active layer A2, resulting in a smaller slope for the voltage curves between the first source S1 and drain D, and a smaller slope for the voltage curves between the second source S2 and drain D. This allows for a wider voltage fluctuation range for both the first source S1 and the second source S2 while ensuring the brightness of the light-emitting device. This improves the accuracy of current control in the display panel and further enhances the display uniformity.

[0078] For example, see [link to example]. Figure 9 , Figure 9 An exemplary schematic diagram of a pixel driving circuit using a 9T2C driving transistor as described in any of the above embodiments is shown. The pixel driving circuit includes: a driving transistor T1 as described in any of the above embodiments; a first switch T2, a second switch T3, a third switch T4, a fourth switch T5, a fifth switch T6, a sixth switch T7, a seventh switch T8, and an eighth switch T9; a first capacitor C1; a second capacitor C2; and a light-emitting device D1. A first power line VDD1 is connected to the first source S1 of the driving transistor T1 via the first switch T2. A second power line VDD2 is connected to the second source S2 of the driving transistor T1 via the seventh switch T8. A second switch T3 is connected between the drain D of the driving transistor T1 and the anode of the light-emitting device D1. The gates of the first switch T2, the seventh switch T8, and the second switch T3 are connected to a light-emitting control line EM, and the first switch T2, the seventh switch T8, and the second switch T3 are used to conduct according to the light-emitting control signal transmitted via the light-emitting control line EM.

[0079] The first capacitor C1 is connected between the first power supply line VDD1 and the gate G of the driving transistor T1, and the second capacitor C2 is connected between the second power supply line VDD2 and the gate G of the driving transistor T1.

[0080] The third switch T4 is connected between the data line VData and the second source S2 of the driving transistor T1. The eighth switch T9 is connected between the first source S1 and the second source S2 of the driving transistor T1. The fourth switch T5 is connected between the gate G and the drain D of the driving transistor T1. The fifth switch T6 is connected between the initialization line and the gate G of the driving transistor T1. The sixth switch T7 is connected between the initialization line and the anode of the light-emitting device. The cathode of the light-emitting device is electrically connected to the third power line VSS.

[0081] See also Figure 9 The exemplary operation of the 9T2C drive circuit is divided into three stages:

[0082] Phase 1: Initialization phase. The fifth switch T6 and the sixth switch T7 are turned on to reset the anode of the light-emitting device D1 and the lower plates of the first capacitor C1 and the second capacitor C2.

[0083] Second stage: Data writing stage, the third switch T4, the eighth switch T9 and the fifth switch T5 are turned on, and the data voltage of the data line VData is written to the gate G of the driving transistor T1.

[0084] Third stage: Light emission stage. The first switch T2, the second switch T3 and the seventh switch T8 are turned on. The potentials of the first power line VDD1 and the second power line VDD2 are applied to the first source S1 and the second source S2 of the driving transistor T1, and the light emission device D1 emits light.

[0085] Combination Figure 2 and Figure 10 , Figure 10 An exemplary display panel may further include: a ninth switch T10, a tenth switch T11, and a third capacitor C3. A third power supply line VDD3 is connected to the third source S3 of the driving transistor T1 via the ninth switch T10. A second switch T3 is connected between the drain D of the driving transistor T1 and the anode of the light-emitting device D1. The gates of the first switch T2, the seventh switch T8, the second switch T3, and the ninth switch T10 are connected to the light-emitting control line EM, and the first switch T2, the seventh switch T8, the second switch T3, and the ninth switch T10 are used to conduct according to the light-emitting control signal transmitted by the light-emitting control line EM. The third capacitor C3 is connected between the third power supply line VDD3 and the gate G of the driving transistor T1. The tenth switch T11 is connected between the third source S3 of the driving transistor T1 and the first source S1 of the driving transistor T1.

[0086] See also Figure 10 The exemplary operation of the 11T3C drive circuit is divided into three stages:

[0087] Phase 1: Initialization phase. The fifth switch T6 and the sixth switch T7 are turned on to reset the anode of the light-emitting device D1 and the lower plates of the first capacitor C1 and the second capacitor C2.

[0088] Second stage: Data writing stage, the third switch T4, the eighth switch T9, the tenth switch T11 and the fifth switch T5 are turned on, and the data voltage of the data line VData is written to the gate G of the driving transistor T1.

[0089] Third stage: Light emission stage. The first switch T2, the second switch T3, the ninth switch T10 and the seventh switch T8 are turned on. The potentials of the first power line VDD1, the second power line VDD2 and the third power line VDD3 are applied to the first source S1, the second source S2 and the third source S3 of the driving transistor T1, and the light emission device D1 emits light.

[0090] Figure 11 This is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present invention. Based on the above embodiment, see... Figure 11 This embodiment of the invention provides a method for manufacturing a display panel, including:

[0091] S801, provides a substrate;

[0092] S802. At least two source electrodes, a drain electrode, at least two active layers corresponding to the source electrodes, an insulating layer, and a gate electrode are disposed on the substrate; wherein, the source electrodes are connected to the active layers respectively; the drain electrodes are connected to each of the active layers respectively; the insulating layer is disposed between the gate electrode and the source electrode; the orthographic projection of the gate electrode on the substrate at least partially overlaps with the orthographic projection of each of the active layers on the substrate.

[0093] The technical solution provided in this embodiment involves setting the display panel to include at least two sources, at least two active layers corresponding to the sources, a drain, and a gate. Each source is connected to an active layer, and each drain is connected to an active layer. An insulating layer is provided between the gate and the sources. The orthographic projection of the gate onto the substrate at least partially overlaps with the orthographic projection of each active layer onto the substrate. This arrangement allows for a larger allowable voltage fluctuation range for each source, making it less likely for the drain current of the driving transistor to enter the subthreshold region. When displaying low grayscale images, the driving transistor can more precisely control the drain current, preventing small source voltage fluctuations from causing the drain current of the driving transistor to change by more than one grayscale level. This improves the uniformity of brightness in low grayscale display and thus improves the display effect of the display panel.

[0094] Optional, Figure 12This is a flowchart illustrating another method for manufacturing a display panel according to an embodiment of the present invention. Based on the above embodiments, see... Figure 12 This embodiment of the invention provides a method for manufacturing a display panel, including:

[0095] S801, provides a substrate;

[0096] S802. At least two source electrodes, a drain electrode, at least two active layers corresponding to the source electrodes, an insulating layer, and a gate electrode are disposed on the substrate; wherein, the source electrodes are connected to the active layers respectively; the drain electrodes are connected to each of the active layers respectively; the insulating layer is disposed between the gate electrode and the source electrode; the orthographic projection of the gate electrode on the substrate at least partially overlaps with the orthographic projection of each of the active layers on the substrate.

[0097] S901. At least two power lines are provided on the substrate corresponding to the source electrode, wherein the power lines are respectively connected to the source electrode and are used to transmit electrical signals to the source electrode.

[0098] Specifically, in combination Figure 9 and Figure 11 By dynamically adjusting the data voltage VData and the first and second power supply voltages transmitted on the first and second power supply lines, in conjunction with adjusting the third power supply voltage VSS transmitted on the third power supply line, the voltage between the source and drain of the driving transistor at low grayscale levels is reduced, and the allowable fluctuation range of the gate-source voltage Vgs of the driving transistor is increased. This alters the operating curve of the driving transistor, moving its smaller current operating region away from the subthreshold region. Without changing the grayscale current of the light-emitting device, the sensitivity of the drain current of the driving transistor to fluctuations in the gate-source voltage Vgs is reduced, thus achieving precise control of the drain current in the display panel at low grayscale levels. This further improves the display uniformity of the display panel.

[0099] Figure 13 This is a schematic diagram of a display device provided in an embodiment of the present invention. Based on the above embodiment, see [link to previous section]. Figure 13 The display device 200 provided in this embodiment of the invention includes the display panel 100 proposed in any of the above embodiments, and has the beneficial effects of the display panel 100 proposed in any of the above embodiments, which will not be described again here. The display device 200 provided in this embodiment of the invention may include terminals such as mobile phones, tablet computers, and wearable devices.

[0100] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0101] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, The display panel includes: substrate; At least two source electrodes, a drain electrode, at least two active layers corresponding to the source electrodes, an insulating layer, and a gate electrode are disposed on the substrate; The source electrode is connected to the corresponding active layer; the drain electrode is connected to each of the active layers respectively; An insulating layer is disposed between the gate electrode and the source electrode; The orthographic projection of the gate onto the substrate at least partially overlaps with the orthographic projection of each of the active layers onto the substrate; the source is correspondingly connected to the active layer to form at least two branches, and the at least two branches are connected in parallel through the drain; current flows through the two branches simultaneously, and the current flowing through the driving transistor for driving the light-emitting device of the display panel comes from two smaller currents from the at least two branches, and the current in each branch is less than the current in the driving transistor for driving the light-emitting device.

2. The display panel according to claim 1, characterized in that, When at least two of the active layers are located on opposite sides of the gate along a thickness direction perpendicular to the substrate, the orthographic projection of the active layer located on the side of the gate closer to the substrate on the substrate at least partially overlaps with the orthographic projection of the active layer located on the side of the gate farther from the substrate on the substrate.

3. The display panel according to claim 2, characterized in that, The active layer includes a first active layer and a second active layer; the source includes a first source and a second source; the first source is connected to the first active layer, and the second source is connected to the second active layer; The first active layer is disposed on the side of the gate closest to the substrate; the second active layer is disposed on the side of the gate away from the substrate.

4. The display panel according to claim 3, characterized in that, The insulating layer includes a first gate insulating layer and a second gate insulating layer; the first gate insulating layer is disposed between the first active layer and the gate; the second gate insulating layer is disposed between the second active layer and the gate.

5. The display panel according to claim 1, characterized in that, When at least two active layers are located on the same side of the gate along a direction perpendicular to the thickness of the substrate, the orthogonal projections of each active layer onto the substrate do not overlap.

6. The display panel according to claim 5, characterized in that, At least two of the active layers are disposed on the side of the gate near the substrate.

7. The display panel according to claim 6, wherein at least two of the active layers are disposed on the same layer.

8. The display panel according to claim 1, characterized in that, The display panel further includes: At least two power lines are provided corresponding to the source electrode, and the power lines are respectively connected to the source electrode. The power lines are used to transmit electrical signals to the source electrode.

9. The display panel according to claim 8, characterized in that, The electrical signals transmitted by each of the power lines are the same.

10. The display panel according to claim 1, characterized in that, The display panel further includes: A light-emitting device is connected to a drain, and the drain is used to transmit a driving current signal to the light-emitting device; wherein the current signal transmitted by the drain is equal to the sum of the current signals transmitted by each of the sources.

11. A method for manufacturing a display panel, characterized in that, include: Provide substrate; At least two source electrodes, a drain electrode, at least two active layers corresponding to the source electrodes, an insulating layer, and a gate electrode are disposed on the substrate. The source electrode is connected to the active layer. The drain is connected to each of the active layers respectively; an insulating layer is disposed between the gate and the source; the orthographic projection of the gate on the substrate and the orthographic projection of each of the active layers on the substrate at least partially overlap; the source is correspondingly connected to the active layer to form at least two branches, and the at least two branches are connected in parallel through the drain; current flows through the two branches simultaneously, and the current flowing through the driving transistor for driving the light-emitting device of the display panel comes from two smaller currents of the at least two branches, and the current of each branch is less than the current of the driving transistor for driving the light-emitting device.

12. The method for manufacturing a display panel according to claim 11, characterized in that, After at least two source electrodes, a drain electrode, at least two active layers corresponding to the source electrodes, an insulating layer, and a gate electrode are disposed on the substrate, the substrate further includes: At least two power lines are provided on the substrate, corresponding to the source electrode; wherein the power lines are respectively connected to the source electrode, and the power lines are used to transmit electrical signals to the source electrode.

13. A display device, characterized in that, include: The display panel according to any one of claims 1-10.

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