A display panel and its manufacturing method, and an electronic device thereof.

Abstract

This disclosure provides a display panel and its fabrication method, as well as an electronic device. The display panel includes: a substrate; a thin-film transistor layer; and an insulating layer. The insulating layer includes multiple arrayed light-emitting regions and non-light-emitting regions located between adjacent light-emitting regions. A light-emitting unit is disposed on the surface of each light-emitting region away from the thin-film transistor layer. At least one eaves structure is disposed in the non-light-emitting region. Each light-emitting unit includes at least an anode layer, a light-emitting layer, a functional layer, and a cathode layer sequentially disposed on the surface of the light-emitting region away from the thin-film transistor layer. An auxiliary electrode layer is covered on the surface of the eaves structure, and the cathode layer is electrically connected to the auxiliary electrode layer. This disclosure utilizes the eaves structure to disconnect the functional layer during fabrication, allowing the cathode layer and auxiliary electrode layer to be electrically connected at the eaves structure during installation. This reduces the overall cathode resistance using the auxiliary electrode layer, thereby improving the display effect of the display panel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel and its manufacturing method, and an electronic device. Background Technology

[0002] With technological advancements, OLED (Organic Light-Emitting Diode) light-emitting devices are increasingly being used in display devices. They are generally classified into top-emitting and bottom-emitting structures based on their light emission direction. For top-emitting display devices, to ensure optimal display quality on the light-emitting side, the electrode (usually the cathode) on that side is typically made very thin to increase its transmittance. However, when the electrode thickness is low, its resistance increases accordingly. A high cathode resistance can lead to an IR drop, causing uneven display and affecting the overall display quality, especially in large-size displays. Summary of the Invention

[0003] The purpose of this disclosure is to provide a display panel and its manufacturing method, as well as an electronic device, to solve the problems of increased resistance and uneven display effect caused by increasing electrode transmittance in the prior art.

[0004] The embodiments of this disclosure adopt the following technical solution: a display panel, comprising: a substrate; a thin-film transistor layer disposed on one side surface of the substrate; an insulating layer disposed on the side surface of the thin-film transistor layer away from the substrate, the insulating layer comprising a plurality of light-emitting regions arranged in an array and non-light-emitting regions located between adjacent light-emitting regions, a light-emitting unit disposed on the side surface of each light-emitting region away from the thin-film transistor layer, and at least one eaves structure disposed in the non-light-emitting region; the light-emitting unit comprises at least an anode layer, a light-emitting layer, a functional layer and a cathode layer sequentially disposed on the side surface of the light-emitting region away from the thin-film transistor layer; the surface of the eaves structure is covered with an auxiliary electrode layer, and the cathode layer is electrically connected to the auxiliary electrode layer.

[0005] In some embodiments, the auxiliary electrode layer is fabricated in the same layer as the anode layer.

[0006] In some embodiments, the insulating layer includes at least a planarization layer and a passivation layer sequentially disposed on the surface of the thin-film transistor layer away from the substrate; wherein the planarization layer located in the non-light-emitting region includes at least one recessed structure, the passivation layer covers a first surface of the planarization layer, and the orthographic projection of the first surface on the substrate is completely covered by the orthographic projection of the passivation layer on the substrate, so that the eaves structure is formed between the passivation layer and the planarization layer; the first surface is the remaining portion of the surface of the planarization layer located in the non-light-emitting region on the side away from the thin-film transistor layer, excluding the recessed structure.

[0007] In some embodiments, the shape of the orthographic projection of the recessed structure onto the substrate is one of the following shapes: circular, elliptical, rectangular, triangular, hexagonal, or linear.

[0008] In some embodiments, the non-light-emitting area is a grid-like area surrounding a plurality of light-emitting areas; wherein, the non-light-emitting area includes at least a wiring area and a non-wiring area, and the eaves structure is disposed in the non-wiring area; the wiring area is disposed between two adjacent rows of light-emitting areas, and a first auxiliary wiring layer is disposed on the surface of the insulating layer in the wiring area, and the first auxiliary wiring layer is electrically connected to the auxiliary electrode layer in the non-light-emitting area.

[0009] In some embodiments, the non-light-emitting region is an island-like region disposed between adjacent light-emitting regions, and a second auxiliary wiring layer is disposed in the flat layer between adjacent light-emitting regions, the second auxiliary wiring layer being electrically connected to the auxiliary electrode layer in the non-light-emitting region.

[0010] In some embodiments, overlapping holes are formed on the planarization layer and the passivation layer between adjacent light-emitting regions, so that the auxiliary electrode layer is electrically connected to the second auxiliary wiring layer based on the overlapping holes.

[0011] In some embodiments, the auxiliary electrode layer is connected to the cathode driving voltage of the peripheral region of the display panel.

[0012] This disclosure also provides a method for fabricating a display panel, comprising: fabricating a thin-film transistor layer on one side surface of a substrate; fabricating an insulating layer on the side of the thin-film transistor layer away from the substrate, wherein the insulating layer includes a plurality of light-emitting regions arranged in an array and non-light-emitting regions located between adjacent light-emitting regions; fabricating a light-emitting unit on the side of each light-emitting region away from the thin-film transistor layer, the light-emitting unit including at least an anode layer, a light-emitting layer, a functional layer and a cathode layer sequentially disposed on the side of the light-emitting region away from the thin-film transistor layer; and providing at least one eaves structure in the non-light-emitting region, the surface of the eaves structure being covered with an auxiliary electrode layer, the cathode layer being electrically connected to the auxiliary electrode layer.

[0013] This disclosure also provides an electronic device, which includes at least the display panel described above.

[0014] The beneficial effects of this embodiment are as follows: by setting the eaves structure, the functional layer is disconnected at the eaves structure during the manufacturing process, so that the cathode layer and the auxiliary electrode layer are electrically connected at the eaves structure during the laying process. This reduces the overall resistance of the cathode by using the auxiliary electrode layer, making the display screen of the display panel more uniform and improving the display effect of the display panel. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the hierarchical structure of the display panel in the first embodiment of this disclosure;

[0017] Figure 2 for Figure 1 A magnified view of a portion of the non-luminescent region;

[0018] Figure 3 This is a partial top view of the non-light-emitting area when the recessed structure is circular in the first embodiment of this disclosure;

[0019] Figure 4 This is a top view of the display panel in the first embodiment of this disclosure;

[0020] Figure 5 for Figure 4 A schematic diagram of the cross-section of BB';

[0021] Figure 6This is another top view of the display panel in the first embodiment of this disclosure;

[0022] Figure 7 for Figure 6 A schematic diagram of the cross-section of CC';

[0023] Figure 8 for Figure 6 Another cross-sectional schematic diagram of CC'. Detailed Implementation

[0024] Various embodiments and features of this disclosure are described herein with reference to the accompanying drawings.

[0025] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this disclosure will be apparent to those skilled in the art.

[0026] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present disclosure and, together with the general description of the disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the disclosure.

[0027] These and other features of this disclosure will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.

[0028] It should also be understood that although this disclosure has been described with reference to some specific examples, many other equivalent forms of this disclosure can be definitively implemented by those skilled in the art, which have the features of the claims and are therefore within the scope of protection defined herein.

[0029] The above and other aspects, features and advantages of this disclosure will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.

[0030] Specific embodiments of this disclosure are described thereafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of this disclosure, which may be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure this disclosure. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely to serve as the basis and representative basis for the claims to teach those skilled in the art to use this disclosure in a variety of substantially any suitable detailed structures.

[0031] This specification may use the phrases “in one embodiment,” “in another embodiment,” “in yet another embodiment,” or “in still another embodiment,” all of which may refer to one or more of the same or different embodiments according to this disclosure.

[0032] With technological advancements, OLED light-emitting devices are increasingly being used in display devices. They are generally categorized into top-emitting and bottom-emitting structures based on their light emission direction. For top-emitting displays, to ensure optimal display quality on the emitting side, the electrode (usually the cathode) on that side is typically made very thin to increase transmittance. However, a thinner electrode results in increased resistance. Generally, the cathode of an OLED display panel is a surface electrode, meaning all light-emitting units (pixels) within the display area share a single cathode. Therefore, this cathode only needs to be connected to the cathode driving voltage of the surrounding area. During cathode driving, the current driving the cathode decreases with increasing distance, causing an IR drop. Pixels closer to the center of the display panel may experience reduced brightness. Higher cathode resistance can lead to uneven display, affecting the overall display quality, especially in large-size displays.

[0033] To address the aforementioned issues, the first embodiment of this disclosure provides a display panel, specifically an OLED display panel. This display panel is divided into a display area and a peripheral area surrounding the display area. The display area is primarily used to house light-emitting units (pixels) and control circuits to display the image, while the peripheral area is primarily used to arrange wiring to drive the light-emitting units and control circuits.

[0034] Figure 1 This embodiment illustrates a hierarchical structure of the display panel. For example... Figure 1 As shown, the display panel mainly includes a substrate 10, a thin-film transistor layer 20, an insulating layer 30, a light-emitting unit 40, and a roof structure 50 disposed in the insulating layer 30. The substrate 10 is mainly used to support the display panel and is typically made of an insulating material composed of polymer resins (polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof).

[0035] The thin-film transistor layer 20 corresponds to the pixel circuit that controls the illumination of the light-emitting unit. Each light-emitting unit corresponds to one pixel circuit, and the illumination and extinguishing of the light-emitting unit are controlled by controlling the pixel circuit. Generally, each pixel circuit includes at least two TFT structures and one capacitor structure. The TFT structure mainly includes a gate layer, an active layer, source and drain electrodes, and buffer layers and dielectric layers disposed between the above layers. Its actual layer structure can be directly fabricated using existing technologies and materials, and will not be described in detail in this embodiment. In actual pixel circuit implementation, more TFT structures and capacitor structures can be set according to control requirements. It should be noted that... Figure 1 The thin-film transistor layer 20 shown includes multiple layers, which can directly correspond to the gate layer, active layer, source and drain, and buffer layer and dielectric layer disposed between the above layers in the prior art. The structure, number, size and other parameters of the above layers can also be adjusted according to actual needs, as long as the function can be realized. This embodiment does not limit its specific preparation method and materials.

[0036] On the surface of the thin-film transistor layer 20 away from the substrate 10 (i.e. Figure 1 An insulating layer 30 is provided on the upper surface of the thin-film transistor layer 20. This insulating layer typically consists of a planarization layer 31 near the thin-film transistor layer 20 and a passivation layer 32 on the surface of the planarization layer 31 away from the thin-film transistor layer 20. Its main function is to flatten the surface of the thin-film transistor layer 20 to facilitate the placement of the light-emitting units 40. In this embodiment, the insulating layer 30 is divided into light-emitting regions arranged in an array and non-light-emitting regions located between adjacent light-emitting regions. The light-emitting regions are the pixel areas used for setting the light-emitting units 40, and are generally arranged in an array according to the resolution and size requirements of the display panel. The non-light-emitting regions are mainly used for corresponding traces or other necessary structures in the display panel, generally corresponding to the non-light-emitting positions between adjacent light-emitting regions.

[0037] like Figure 1As shown, a light-emitting unit 40 is disposed on the surface of the insulating layer 30 corresponding to the light-emitting region, away from the thin-film transistor layer 20. This region also corresponds to the TFT structure in the thin-film transistor layer 20. The light-emitting unit 40 mainly includes an anode layer 41, a light-emitting layer 42, a functional layer 43, and a cathode layer 44 sequentially disposed on the surface of the light-emitting region away from the thin-film transistor layer. The anode layer 41 is connected to the source or drain of its corresponding TFT structure through vias or other means to realize the control of the light-emitting unit based on the TFT structure. The functional layer 43 is mainly an electron injection layer. Functional layers such as electron transport layers and hole blocking layers are generally fabricated by vapor deposition. The cathode 44 is usually made of a low work function metal, such as lithium (Li), calcium (Ca), lithium fluoride / calcium (LiF / Ca), lithium fluoride / aluminum (LiF / Al), aluminum (Al), magnesium (Mg), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), gold (Au), neodymium (Nd), iridium (Ir), chromium (Cr), barium fluoride (BaF), barium (Ba), or their compounds or mixtures, such as a mixture of Ag and Mg.

[0038] In the non-light-emitting area, at least one eaves structure 50 is provided in the insulating layer 30. By laying an auxiliary electrode layer 51 on the exposed surface of the eaves structure 50, the cathode layer 44 is electrically connected to the auxiliary electrode layer 51 at the eaves structure 50. At the same time, the auxiliary electrode layer 51 extends to the surrounding area and is also connected to the cathode driving voltage, so as to reduce the cathode IR drop and improve the uniformity of the display panel.

[0039] Figure 2 for Figure 1 A magnified schematic diagram of a portion of the non-luminescent area. In this embodiment, the eaves structure 50 can be formed by etching grooves or protrusions on the insulating layer 30, and by utilizing the different etching rates of the planarization layer 31 and the passivation layer 32. Specifically, the planarization layer 31 is mainly made of one or more organic insulating materials selected from polyimide, polyamide, acrylic resin, BCB, and phenolic resin, while the passivation layer 32 is mainly made of single or stacked inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, hafnium oxide, and zirconium oxide. By utilizing the different etching rates of the organic and inorganic materials, the planarization layer 31 is etched to form grooves or protrusions. Figure 2The inverted trapezoidal recessed structure 311 shown has a passivation layer 32 covering the first surface of the planarization layer 31. The orthogonal projection of the first surface onto the substrate 10 is completely covered by the orthogonal projection of the passivation layer 32 onto the substrate. That is, the opening of the passivation layer 32 at the recessed structure is smaller than the opening of the recessed structure 311 itself at the planarization layer 31, thereby forming an eaves structure 50 at the recessed structure 311 by the passivation layer 32 and the planarization layer 31. The first surface is the remaining part of the surface of the planarization layer 31 on the side away from the thin film transistor layer 20, excluding all recessed structures, but should not include the part exposed after the recessed structure is opened. In fact, the first surface only includes the part in contact between the planarization layer 31 and the passivation layer 32.

[0040] It should be noted that the number of recessed structures 311 can be adjusted according to the size of the non-light-emitting area, the shape and size of the recessed structures 311, etc. In actual implementation, the more recessed structures 311, the better. Increasing the number of recessed structures 311 increases the number of eaves structures 50, and the contact area between the auxiliary electrode layer 51 and the cathode layer 44 will also increase accordingly when they are electrically connected later, so as to achieve a better electrical connection effect. In addition, the orthographic projection shape of the recessed structure 311 on the substrate 10 can be any shape such as circle, ellipse, rectangle, triangle, hexagon or line. Figure 3 A partial top view of the non-light-emitting area is shown when the orthographic projection shape of the recessed structure 311 is circular. Each circle in the figure represents a recessed structure 311. By setting a larger number of recessed structures, the overall number of eaves structures is increased, thereby increasing the contact area between the cathode layer and the auxiliary electrode layer, which is more conducive to reducing the voltage drop.

[0041] In the actual fabrication of the display panel, the light-emitting unit 40 is fabricated only after the roof structure 50 is formed. Therefore, the auxiliary electrode layer 51 laid on the roof structure 50 and the anode layer 41 in the light-emitting unit 40 can be fabricated in the same layer using the same materials and fabrication methods. However, it is necessary to ensure that the anode layer 41 and the auxiliary electrode layer 51 are not connected to each other so as to ensure that they each achieve different functions. In this embodiment, both the anode layer 41 and the auxiliary electrode layer 51 can be fabricated using physical vapor deposition (PVD) or chemical vapor deposition (CVD). The deposition direction is relatively dispersed, allowing the auxiliary electrode layer 51 to achieve good film formation even at the roof structure 50. Subsequently, the light-emitting layer 42 is prepared within the light-emitting area. The preparation method and materials can be directly applied using existing technologies, and will not be described in this embodiment. After the light-emitting layer 42 is prepared, the functional layer 43 is vapor-deposited. Because the vapor-deposited beam is concentrated in the vertical direction, the functional layer 43 cannot form a continuous film at the roof structure 50; it can only form a film on the surface of the passivation layer 32, the bottom of the recessed structure 311, and part of the sidewalls. Later, when preparing the cathode layer 44, PVD or CVD is also used, ensuring that the cathode layer 44 can also achieve a continuous and complete film at the roof structure 50, thereby connecting the cathode layer 44 with the auxiliary electrode layer 51 at the roof structure 55.

[0042] Figure 4 This is a top view of the display panel in this embodiment. Figure 4 As shown, the non-light-emitting area can be a grid-like area surrounding multiple light-emitting areas. The shape and size of the light-emitting areas are set according to the actual pixel arrangement rules of the display panel, and the non-light-emitting areas are correspondingly located in the gaps between adjacent light-emitting areas. In some embodiments, the non-light-emitting area can be further subdivided into wiring areas (such as...). Figure 4 (as shown in the shaded area) and non-trace areas (such as...) Figure 4 (As shown in the shaded area by the vertical line), an eaves structure 50 is set in the non-wiring area to realize the electrical connection between the auxiliary electrode layer 51 and the cathode layer 44 in each pixel. In the wiring area, the eaves structure 50 is not set, but is only used for the design of the first auxiliary wiring layer 52. The first auxiliary wiring layer 52 is set in the same layer as the auxiliary electrode layer 51 and the anode layer 41, and is usually set between two adjacent rows of light-emitting areas. This connects the first auxiliary wiring layer with the auxiliary electrode layer 51 in the adjacent area, so as to shorten the distance between the light-emitting unit 40 and the auxiliary electrode. This allows the cathode driving voltage transmitted through the first auxiliary wiring layer 52 to reach the corresponding light-emitting unit through a shorter path, thereby achieving less attenuation and making the display panel have a more uniform display image.

[0043] Figure 5 A cross-sectional schematic diagram of the wiring area BB' is shown, with the portions containing the light-emitting units 40 shown on both sides. Figure 1 Similarly, without repeating the details, the wiring portion of the non-light-emitting area in the middle can be directly fabricated on the planarization layer 31 to form the first auxiliary wiring layer 52. At the same time, when fabricating the corresponding layers of the light-emitting unit 40, since no roof structure is set here and no electrical connection with the cathode layer 44 is required, the support structure 45 can be set here.

[0044] In some embodiments, the non-light-emitting area may also be an island-like area disposed between adjacent light-emitting areas, such as... Figure 6 As shown, Figure 6 The shaded area corresponds to the non-light-emitting area. At least one eaves structure 50 can be provided within each independent non-light-emitting area to connect the cathode layer 44 of the light-emitting unit adjacent to that non-light-emitting area. At this time, an independent second auxiliary wiring layer 53 is provided in the flat layer 31. Figure 6 (Not shown in the image), it is laid at the bottom of the eaves structure to achieve electrical connection with the auxiliary electrode layer 51 at the bottom of the eaves structure. Figure 7 It shows Figure 6 A schematic diagram of the cross-section of CC', as shown below. Figure 7 As shown, a second auxiliary wiring layer 53 is provided in the region between adjacent light-emitting areas. When forming the recessed structure 311, the bottom of the recessed structure 311 is made to contact the surface of the second auxiliary wiring layer 53, so that when the auxiliary electrode layer 51 is fabricated in the recessed structure, the auxiliary electrode layer 51 is directly connected to the second auxiliary wiring layer 53. It should be noted that in actual fabrication, the thickness of the planarization layer 31 can be increased accordingly, and the planarization layer 31 can be fabricated in two stages so that the second auxiliary wiring layer 53 is fabricated first after the first planarization layer 31a is fabricated. Then, the second planarization layer 31b is covered on the second auxiliary wiring layer 53. Then, the recessed structure 311 is fabricated after the passivation layer 32 is fabricated, so that the bottom of the recessed structure 311 is connected to the surface of the second auxiliary wiring layer 53. Finally, the auxiliary electrode layer 51 and the cathode layer 44 are fabricated and connected when the light-emitting unit 40 is fabricated. In addition, due to the provision of the second auxiliary wiring layer 53, when the anode layer 41 of the corresponding light-emitting unit 40 is connected to the TFT structure, a jumper can also be provided at the same level as the second auxiliary wiring layer 53 to ensure the connection between the anode layer 41 and the source or drain of the TFT structure.

[0045] Figure 8 It shows Figure 6 Another cross-sectional diagram of CC', compared to Figure 7 The structure shown, Figure 8 An overlap hole 312 is formed on the second flat layer 31b to increase the contact area between the auxiliary electrode layer 51 and the second auxiliary wiring layer 53, so that the two have better electrical connection performance.

[0046] This embodiment utilizes the eaves structure to disconnect the functional layer during fabrication, allowing the cathode layer and auxiliary electrode layer to be electrically connected at the eaves structure during installation. This reduces the overall cathode resistance using the auxiliary electrode layer, resulting in a more uniform display image and improved display performance.

[0047] The second embodiment of this disclosure provides a method for manufacturing a display panel according to the first embodiment of this disclosure, which mainly includes the following steps:

[0048] S1, a thin-film transistor layer is prepared on one side surface of the substrate; wherein, the selection of substrate material and the preparation process of thin-film transistor layer can be directly implemented using existing technology, and will not be described in detail in this embodiment.

[0049] S2, An insulating layer is prepared on the surface of the thin-film transistor layer away from the substrate; wherein the insulating layer includes multiple light-emitting regions arranged in an array and non-light-emitting regions located between adjacent light-emitting regions.

[0050] S3, light-emitting units are fabricated on the surface of each light-emitting region away from the thin-film transistor layer. Each light-emitting unit includes at least an anode layer, a light-emitting layer, a functional layer, and a cathode layer sequentially disposed on the surface of the light-emitting region away from the thin-film transistor layer. The fabrication process of the light-emitting units can be directly implemented using existing technologies, and will not be described in detail in this embodiment.

[0051] S4, at least one eaves structure is provided in the non-light-emitting area, the surface of the eaves structure is covered with an auxiliary electrode layer, and the cathode layer is electrically connected to the auxiliary electrode layer; further, both the cathode layer and the auxiliary electrode layer are connected to the cathode driving voltage of the peripheral area of ​​the display panel.

[0052] In some embodiments, the auxiliary electrode layer can be fabricated in the same layer as the anode layer. Both can be reflective layers of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and mixtures thereof, as well as transparent or translucent electrode layers formed on the reflective layer. Alternatively, they can be made of at least one material selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). They can also be multilayer structures similar to ITO / Ag / ITO.

[0053] In some embodiments, the insulating layer includes at least a planarization layer and a passivation layer sequentially disposed on the surface of the thin-film transistor layer away from the substrate; wherein the planarization layer located in the non-light-emitting region includes at least one recessed structure, the passivation layer covers a first surface of the planarization layer, and the orthographic projection of the first surface on the substrate is completely covered by the orthographic projection of the passivation layer on the substrate, so that an eaves structure is formed between the passivation layer and the planarization layer; the first surface is the remaining portion of the surface of the planarization layer located in the non-light-emitting region away from the thin-film transistor layer, excluding the recessed structure. Specifically, the orthographic projection of the recessed structure on the substrate has one of the following shapes: circular, elliptical, rectangular, triangular, hexagonal, or linear.

[0054] In some embodiments, the non-light-emitting area can be a grid-like area surrounding multiple light-emitting areas; wherein, the non-light-emitting area includes at least a wiring area and a non-wiring area, and an eaves structure is provided in the non-wiring area; the wiring area is provided between two adjacent rows of light-emitting areas, and a first auxiliary wiring layer is provided on the surface of the insulating layer in the wiring area, and the first auxiliary wiring layer is electrically connected to the auxiliary electrode layer in the non-light-emitting area.

[0055] In some embodiments, the non-light-emitting region may also be an island-like region disposed between adjacent light-emitting regions. A second auxiliary wiring layer is disposed in the planarization layer between adjacent light-emitting regions, and the second auxiliary wiring layer is electrically connected to the auxiliary electrode layer in the non-light-emitting region. Further, overlapping holes are formed on the planarization layer and passivation layer between adjacent light-emitting regions, so that the auxiliary electrode layer is electrically connected to the second auxiliary wiring layer based on the overlapping holes.

[0056] This embodiment utilizes the eaves structure to disconnect the functional layer during fabrication, allowing the cathode layer and auxiliary electrode layer to be electrically connected at the eaves structure during installation. This reduces the overall cathode resistance using the auxiliary electrode layer, resulting in a more uniform display image and improved display performance.

[0057] The third embodiment of this disclosure provides an electronic device, which can be a display device with display function, especially a smartphone, tablet computer or television with a large screen size, etc., which at least includes the display panel provided in the first embodiment of this disclosure, so as to achieve a more uniform screen display.

[0058] The foregoing has provided a detailed description of several embodiments of this disclosure. However, this disclosure is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications based on the concept of this disclosure, and all such variations and modifications should fall within the scope of protection claimed by this disclosure.

Claims

1. A display panel, characterized in that, include: substrate; A thin-film transistor layer disposed on one side surface of the substrate; An insulating layer is disposed on the surface of the thin-film transistor layer away from the substrate. The insulating layer includes a plurality of light-emitting regions arranged in an array and non-light-emitting regions located between adjacent light-emitting regions. A light-emitting unit is disposed on the surface of each light-emitting region away from the thin-film transistor layer. At least one eaves structure is disposed in the non-light-emitting region. The insulating layer includes at least a planarization layer and a passivation layer disposed sequentially on the surface of the thin-film transistor layer away from the substrate. The eaves structure is formed by etching a groove structure on the insulating layer and utilizing different etching rates of the planarization layer and the passivation layer. The non-luminescent area is a grid-like area arranged around the plurality of luminescent areas; wherein... The non-light-emitting area includes at least a wiring area and a non-wiring area, and the eaves structure is provided in the non-wiring area; the wiring area is located between two adjacent rows of light-emitting areas, and a first auxiliary wiring layer is provided on the surface of the insulating layer in the wiring area, and the first auxiliary wiring layer is electrically connected to the auxiliary electrode layer in the non-light-emitting area. The light-emitting unit includes at least an anode layer, a light-emitting layer, a functional layer, and a cathode layer sequentially disposed on the surface of the light-emitting region away from the thin-film transistor layer; The surface of the eaves structure is covered with an auxiliary electrode layer, and the cathode layer is electrically connected to the auxiliary electrode layer.

2. The display panel according to claim 1, characterized in that, The auxiliary electrode layer is fabricated in the same layer as the anode layer.

3. The display panel according to claim 1, characterized in that, in, The planarization layer located in the non-light-emitting area includes at least one recessed structure, the passivation layer covers a first surface of the planarization layer, and the orthographic projection of the first surface on the substrate is completely covered by the orthographic projection of the passivation layer on the substrate, so that the eaves structure is formed between the passivation layer and the planarization layer; The first surface is the remaining portion of the flat layer located in the non-light-emitting region on the side away from the thin-film transistor layer, excluding the recessed structure.

4. The display panel according to claim 3, characterized in that, The shape of the orthographic projection of the recessed structure onto the substrate is one of the following shapes: Circle, oval, rectangle, triangle, hexagon, and line shape.

5. The display panel according to claim 3, characterized in that, The non-light-emitting area is an island-like area set between adjacent light-emitting areas. A second auxiliary wiring layer is provided in the flat layer between adjacent light-emitting areas. The second auxiliary wiring layer is electrically connected to the auxiliary electrode layer in the non-light-emitting area.

6. The display panel according to claim 5, characterized in that, Overlapping holes are formed on the planarization layer and the passivation layer between adjacent light-emitting regions, so that the auxiliary electrode layer is electrically connected to the second auxiliary wiring layer based on the overlapping holes.

7. The display panel according to any one of claims 1 to 6, characterized in that, The auxiliary electrode layer is connected to the cathode driving voltage of the peripheral area of ​​the display panel.

8. A method for manufacturing a display panel, characterized in that, include: A thin-film transistor layer is fabricated on one side surface of the substrate; An insulating layer is formed on the surface of the thin-film transistor layer away from the substrate. The insulating layer includes a plurality of light-emitting regions arranged in an array and non-light-emitting regions located between adjacent light-emitting regions. The insulating layer also includes at least a planarization layer and a passivation layer sequentially disposed on the surface of the thin-film transistor layer away from the substrate. A light-emitting unit is formed on the surface of each light-emitting region away from the thin-film transistor layer. The light-emitting unit includes at least an anode layer, a light-emitting layer, a functional layer, and a cathode layer sequentially disposed on the surface of the light-emitting region away from the thin-film transistor layer. The non-luminescent area is a grid-like area arranged around the plurality of luminescent areas; wherein... The non-light-emitting area includes at least a wiring area and a non-wiring area. An eaves structure is provided in the non-wiring area. The wiring area is located between two adjacent rows of light-emitting areas. A first auxiliary wiring layer is provided on the surface of the insulating layer in the wiring area. The first auxiliary wiring layer is electrically connected to the auxiliary electrode layer in the non-light-emitting area. At least one eaves structure is provided in the non-light-emitting area. The surface of the eaves structure is covered with an auxiliary electrode layer. The cathode layer is electrically connected to the auxiliary electrode layer. The eaves structure is formed by etching a groove structure on the insulating layer and utilizing different etching rates of the planarization layer and the passivation layer.

9. An electronic device, characterized in that, It includes at least the display panel as described in any one of claims 1 to 7.

Images