Duty cycle adjustment circuit and chip

Abstract

The present application discloses a duty cycle adjustment circuit and chip. The circuit includes a first adjustment circuit and a second adjustment circuit, the first adjustment circuit includes a first path set and a second path set; the second adjustment circuit includes a third path set and a fourth path set; the first path set and the fourth path set respectively receive a first control signal and a second control signal to control the number of first paths that are turned on in the first path set and the number of fourth paths that are turned on in the fourth path set, thereby adjusting the duty cycle of the output clock signal; when the second path set and the third path set are working, the first paths that are turned on in the first path set work in conjunction with the third paths that are turned on in a fixed number in the third path set; the fourth paths that are turned on in the fourth path set work in conjunction with the second paths that are turned on in a fixed number in the second path set, thereby improving the linearity of the output clock signal.

Description

Technical Field

[0001] The present application relates to the field of semiconductor integrated circuits, and in particular to a duty cycle adjustment circuit and chip. Background Art

[0002] As the operating frequency of the circuit increases, high-speed circuits, especially input and output module circuits, are increasingly sensitive to the duty cycle of the clock signal, so a duty cycle adjustment circuit is needed to calibrate the duty cycle of the clock signal. When the traditional duty cycle adjustment circuit adjusts the clock signal, it uses the number of transistors that are turned on to adjust the clock signal to appropriately delay a clock edge to adjust the duty cycle. However, as the number of transistors that are turned on changes, the duty cycle of the clock signal adjustment varies greatly, the linearity is poor, and there is a problem that the required duty cycle value cannot be accurately obtained. Summary of the invention

[0003] The present application proposes a duty cycle adjustment circuit and chip to solve the above-mentioned problem that the clock duty cycle linearity is poor and the required duty cycle value cannot be accurately obtained.

[0004] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a duty cycle adjustment circuit, wherein the duty cycle adjustment circuit includes a first adjustment circuit and a second adjustment circuit.

[0005] The first regulating circuit includes a first path set and a second path set; the second regulating circuit includes a third path set and a fourth path set; wherein the first path set, the second path set, the third path set and the fourth path set respectively include a plurality of conductive paths, and the first path set and the fourth path set respectively receive a first control signal and a second control signal to control the number of conductive first paths in the first path set and the number of conductive fourth paths in the fourth path set, thereby adjusting the duty cycle of the output clock signal;

[0006] When the second path set and the third path set are working, the number of the second paths that are turned on in the second path set and the number of the third paths that are turned on in the third path set are fixed, the first path set and the third path set are in working state in response to the logic low level of the input clock signal, and the first paths that are turned on in the first path set cooperate with the fixed number of the third paths that are turned on in the third path set.

[0007] The third path works; the fourth path set and the second path set are in working state in response to the logic high level of the input clock signal, and the fourth paths turned on in the fourth path set cooperate with the fixed number of second paths turned on in the second path set to improve the linearity of the output clock signal.

[0008] The first path set includes M first paths, the fourth path set includes M fourth paths; the second path set includes N second paths, the third path includes N third paths, M and N are natural numbers, and N is less than M;

[0009] The sum of the number of first paths of the first path set that are turned on in an active state in response to a logic low level of the input clock signal and the number of fourth paths of the fourth path set that are turned on in an active state in response to a logic high level of the input clock signal is M.

[0010] Here, N is equal to M / 2 or a natural number close to M / 2.

[0011] Each first path in the first path set includes a first transistor and a second transistor.

[0012] A first transistor, a first path end of which is connected to a power supply voltage, and a control end of which is used to receive an input clock signal;

[0013] A second transistor, a first channel end of which is connected to the second channel end of the first transistor, a control end of which is used to receive a first control signal, and a second channel end of which is connected to the first output end;

[0014] Wherein, based on the input clock signal received by the first transistor in each first path being at a logic low level, the first path set is in a working state; based on the first control signal received by the second transistor in each first path, the number of first paths that are turned on in the first path set is adjusted.

[0015] Each second path in the second path set includes a third transistor and a fourth transistor.

[0016] A third transistor, a first path end of which is connected to the first output end, and a control end of which is used to receive a first working power supply;

[0017] a fourth transistor, a first channel end of which is connected to the second channel end of the third transistor, a control end of which is used to receive an input clock signal, and a second channel end of which is used to receive a ground voltage;

[0018] Among them, based on the input clock signal received by the fourth transistor in each second path being at a logic high level, the second path set is in a working state; based on the first working power received by the third transistor in each second path, the second paths that are turned on in the working state of the second path set are all the second paths.

[0019] Each third path in the third path set includes a fifth transistor and a sixth transistor.

[0020] a fifth transistor, a first channel terminal of which is connected to a power supply voltage, and a control terminal of which is used to receive an input clock signal;

[0021] a sixth transistor, a first channel end of which is connected to the second channel end of the fifth transistor, a control end of which is used to receive a second working power supply, and a second channel end of which is connected to the second output end;

[0022] Among them, based on the input clock signal received by the fifth transistor in each third path being at a logic low level, the third path set is in a working state; based on the second working power received by the sixth transistor in each third path, the third paths that are turned on in the working state of the third path set are all third paths.

[0023] Each fourth path in the fourth path set includes a seventh transistor and an eighth transistor.

[0024] a seventh transistor, a first channel end of which is connected to the second output end, and a control end of which is used to receive a second control signal;

[0025] an eighth transistor, a first channel end of which is connected to the second channel end of the seventh transistor, a control end of which is used to receive an input clock signal, and a second channel end of which is connected to receive a ground voltage;

[0026] In which, based on the input clock signal received by the eighth transistor in each fourth path being at a logic high level, the fourth path set is in a working state; based on the second control signal received by the seventh transistor in each fourth path, the number of fourth paths that are turned on in the fourth path set is adjusted.

[0027] The first regulating circuit and the second regulating circuit respectively receive input clock signals through buffers and / or output output clock signals through inverters.

[0028] The duty cycle adjustment circuit further includes at least one dummy unit, wherein the duty cycle adjustment circuit changes the initial duty cycle of the output clock signal by changing the number of the dummy units.

[0029] In order to solve the above technical problems, another technical solution adopted in the present application is: to provide a chip, the chip includes any one of the duty cycle adjustment circuits mentioned above.

[0030] The beneficial effect of the present application is as follows: Different from the prior art, the present application adjusts the duty cycle of the input clock signal by setting a first adjustment circuit and a second adjustment circuit, wherein the first adjustment circuit includes a first path set and a second path set, the second adjustment circuit includes a third path set and a fourth path set, each adjustment path set includes multiple conduction paths, and the present application adjusts the duty cycle of the output clock signal by controlling the number of conduction paths of the first path set and the fourth path set, and improves the linearity of the output clock signal by respectively cooperating with the fourth path set and the first path set through the second path set and the third path set with a fixed number of conduction paths, thereby accurately controlling the duty cycle of the output clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the structure of a traditional duty cycle adjustment circuit;

[0032] Figure 2 It is a structural schematic diagram of the first embodiment of the duty cycle adjustment circuit of the present application;

[0033] Figure 3 is a structural schematic diagram of a second embodiment of the duty cycle adjustment circuit of the present application;

[0034] Figure 4 is a schematic structural diagram of a third embodiment of the duty cycle adjustment circuit of the present application;

[0035] Figure 5 It is a schematic diagram comparing the duty cycle adjustment circuit of the present application with the simulation structure of the traditional circuit;

[0036] Figure 6 This is a schematic diagram comparing the duty cycle adjustment step length of the present application's duty cycle adjustment circuit with that of the traditional structure;

[0037] Figure 7 It is a schematic diagram of the structure of a chip embodiment of the present application. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] As the operating frequency of the circuit increases, high-speed circuits, especially input and output module circuits, are becoming more and more sensitive to the duty cycle of the clock signal. Therefore, the duty cycle adjustment circuit is extremely important in high-speed circuits.

[0040] See also Figure 1 , Figure 1 This is a schematic diagram of the traditional duty cycle adjustment circuit structure. Figure 1 As shown, the conventional duty cycle adjustment circuit includes a buffer 1 , an inverter 2 , a first transistor set 3 , a second transistor set 4 , a third transistor set 5 and a fourth transistor set 6 .

[0041] The input clock signal is input to the buffer 1, and the buffer 1 is connected to the first transistor set 3 and the fourth transistor set 6 respectively, and the input clock signal is input to the first transistor set 3 and the fourth transistor set 6 respectively. The first transistor set 3 is in an operating state in response to the logic low level of the input clock signal, and the fourth transistor set 6 is in an operating state in response to the logic high level of the input clock signal.

[0042] The first transistor set 3 includes multiple transistors P, the control end of each transistor P receives an input clock signal, and the first channel end of each transistor P is connected to the power supply voltage VDD. The second transistor set 4 includes multiple transistors PC with the same number as the first transistor set 3. The first channel ends of the transistors PC are connected to the second channel ends of the transistors P in a one-to-one correspondence. The first control signal is connected to the control end of each transistor PC to control the conduction and disconnection of the transistor PC. The second channel end of the transistor PC is the first output end.

[0043] The fourth transistor set 6 also includes a plurality of transistors N of the same number as the first transistor set 3, the first channel end of each transistor N is connected to the ground voltage, and the control end of each transistor N receives an input clock signal. The third transistor set 5 also includes a plurality of transistors NC of the same number as the first transistor set 3, the first channel end of the transistor NC is connected one-to-one with the second channel end of the transistor N, and the second control signal is connected to the control end of each transistor NC, thereby controlling the conduction and disconnection of the transistor NC, and the second channel end of the transistor NC is the second output end.

[0044] The first input terminal and the second input terminal are both connected to the inverter 2, so as to output the adjusted output clock signal.

[0045] The working principle of the conventional duty cycle adjustment circuit is to control the number of transistors of the second transistor set 4 and the third transistor set 5 to be turned on by the first control signal and the second control signal to control the delay time of the clock edge of the input clock signal and thus adjust the duty cycle of the clock signal.

[0046] by Figure 1 In the example, the number of transistors in the first transistor set 3 is 16, the first transistor set 3 is represented by P<15:0>, the second transistor set 4 is represented by PC<15:0>, the third transistor set 5 is represented by NC<15:0>, and the fourth transistor set 6 is represented by N<15:0>.

[0047] By setting the first control signal and the second control signal, the number of transistors turned on in the second transistor set 4 and the third transistor set 5 can be controlled, wherein the sum of the number of transistors PC in the second transistor set 4 and the number of transistors NC in the third transistor set 5 is 16. When 8 transistors PC in the second transistor set 4 and 8 transistors NC in the third transistor set 5 are turned on, the input clock signal has the same ability to change to 0 and 1, and the input and output duty ratios remain unchanged. When the number of transistors PC in the second transistor set 4 and the number of transistors NC in the third transistor set 5 that are turned on are inconsistent, the ability of the clock to change to 0 and 1 is inconsistent. In other words, the rising time and falling time of the clock edge of the input clock signal are inconsistent, which is reflected in the change of the clock duty ratio of the clock signal when it is reflected in the output clock signal. Therefore, the purpose of adjusting the clock duty ratio of the input clock signal can be achieved by adjusting the control signal to adjust the number of transistors turned on in the second transistor set 4 and the third transistor set 5.

[0048] However, when the conventional duty cycle adjustment circuit adjusts the input clock duty cycle, as the control signal changes, the duty cycle adjusted in each step varies greatly, and the linearity of the clock signal is poor. For example, the duty cycle adjusted when the transistor PC in the second transistor set 4 changes from one to two is much greater than the duty cycle adjusted when the transistor PC changes from 15 to 16. Therefore, the conventional duty cycle adjustment circuit has the problem of being unable to accurately obtain the required duty cycle value.

[0049] In order to solve the problems existing in the above-mentioned conventional duty cycle adjustment circuit, the present application proposes a duty cycle adjustment circuit, see Figure 2 , Figure 2 is a schematic diagram of the structure of the first embodiment of the duty cycle adjustment circuit of the present application. Figure 2 As shown, the duty cycle adjustment circuit 100 of this embodiment includes a first adjustment circuit 10 and a second adjustment circuit 20 .

[0050] The first regulation circuit 10 includes a first path set 11 and a second path set 12; the second regulation circuit 20 includes a third path set 21 and a fourth path set 22; wherein, the first path set 11, the second path set 12, the third path set 21 and the fourth path set 22 respectively include multiple conductive paths, and the first path set 11 and the fourth path set 22 respectively receive a first control signal and a second control signal to control the number of conductive first paths in the first path set and the number of conductive fourth paths in the fourth path set, thereby adjusting the duty cycle of the output clock signal.

[0051] When the second path set 12 and the third path set 21 are working, the number of second paths turned on in the second path set 12 and the number of third paths turned on in the third path set 21 are fixed, the first path set 11 and the third path set 21 are in working state in response to the logic low level of the input clock signal, and the first paths turned on in the first path set 11 cooperate with the fixed number of third paths turned on in the third path set 21 to work; the fourth path set and the second path set are in working state in response to the logic high level of the input clock signal, and the fourth paths turned on in the fourth path set 22 cooperate with the fixed number of second paths turned on in the second path set 12 to improve the linearity of the output clock signal.

[0052] The first path set 11, the second path set 12, the third path set 21 and the fourth path set 22 respectively include a plurality of conductive paths. In this embodiment, the first path set 11, the second path set 12, the third path set 21 and the fourth path set 22 may be a plurality of transistors. In other embodiments, the first path set 11, the second path set 12, the third path set 21 and the fourth path set 22 may also be other switch elements, as long as the above conditions are met, and are not limited here.

[0053] Different from the prior art, the present application adjusts the duty cycle of the input clock signal by setting a first adjustment circuit 10 and a second adjustment circuit 20, wherein the first adjustment circuit 10 includes a first path set 11 and a second path set 12, and the second adjustment circuit 20 includes a third path set 21 and a fourth path set 22, each adjustment path set includes multiple conduction paths, and the present application adjusts the duty cycle of the output clock signal by controlling the number of conduction paths of the first path set 11 and the fourth path set 22, and improves the linearity of the output clock signal by fixing the number of conduction paths of the second path set 12 and the third path set 21, respectively cooperating with the fourth path set 22 and the first path set 11, thereby accurately controlling the duty cycle of the output clock signal.

[0054] Optionally, see Figure 3 , Figure 3 Schematic diagram of the structure of the second embodiment of the duty cycle adjustment circuit of the present application. Figure 3 As shown, the first path set 11 includes M first paths, the fourth path set 22 includes M fourth paths; the second path set 12 includes N second paths, the third path 21 includes N third paths, M and N are natural numbers respectively, and N is less than M.

[0055] The sum of the number of first paths that are turned on in the first path set 11 in response to the logic low level of the input clock signal and the number of fourth paths that are turned on in the fourth path set 22 in response to the logic high level of the input clock signal is M.

[0056] Here, N is equal to M / 2 or a natural number close to M / 2.

[0057] When adjusting the duty cycle of the clock signal, the duty cycle adjustment circuit 100 of the present application selects to conduct X number of first paths among M first paths in the first path set 11 through a first control signal, where X is a natural number, X<=M. The number of (MX) fourth paths in the fourth path set 22 is conducted through a second control signal. The present application adjusts the duty cycle of the output clock signal by controlling the number X of first paths in the first path set 11 and the number of fourth paths in the fourth path set 22 that are conducted.

[0058] Taking M equal to 32 as an example, when the number of on-states of the first path of the first path set 11 and the number of on-states of the fourth path of the fourth path set 22 are both 16 on-states, the input clock signal has the same ability to change to 0 and 1, resulting in the input clock signal having the same rise time and fall time after passing through the duty cycle adjustment circuit 100, and the duty cycle of the output clock signal remains unchanged. When the number of on-states of the first path of the first path set 11 and the number of on-states of the fourth path of the fourth path set 22 are inconsistent, the input clock signal has different abilities to change to 0 and 1, resulting in the input clock signal having inconsistent rise time and fall time after passing through the duty cycle adjustment circuit 100, thereby achieving the purpose of adjusting the duty cycle of the clock signal.

[0059] The second path set 12 and the third path set 21 both include N second paths. When the second path set 12 and the third path set 21 are working, the number of second paths conducted in the second path set 12 and the number of third paths conducted in the third path set 21 are fixed, both being N.

[0060] When the input clock signal is at a logic low level, both the first path set 11 and the third path set 21 are in working state, and the X first paths in the first path set 11 cooperate with the N third paths in the third path set 21 to work.

[0061] When the input clock signal is at a logic high level, the second path set 12 and the fourth path set 22 are both in operation, and the (MX) conductive fourth paths in the fourth path set 22 cooperate with the N conductive second paths in the second path set 12 to operate.

[0062] When the number X of the first paths turned on in the first path set 11 and the (MX) fourth paths turned on in the fourth path set 22 change, due to the N second paths turned on in the second path set 12 and the N third paths turned on in the third path set 21, each time X is adjusted, the duty cycle of the clock signal does not differ much. The coordination of the N second paths turned on in the second path set 12 and the N third paths turned on in the third path set 21 enables the final output clock signal to be fitted, so that the duty cycle thereof does not differ much each time X is adjusted, thereby improving the linearity of the output clock signal, thereby significantly improving the achievable resolution of the clock duty cycle.

[0063] Alternatively, if Figure 3 As shown, each first path in the first path set 11 includes a first transistor 111 and a second transistor 112 .

[0064] The first path end of the first transistor 111 is connected to the power supply voltage VDD, and the control end thereof is used to receive the input clock signal; the first path end of the second transistor 112 is connected to the second path end of the first transistor 111, the control end thereof is used to receive the first control signal, and the second path end thereof is connected to the first output end; wherein, based on the input clock signal received by the first transistor 111 in each first path being at a logic low level, the first path set 11 is in a working state; based on the first control signal received by the second transistor 112 in each first path, the number of first paths that are turned on in the first path set 11 is adjusted.

[0065] like Figure 3 As shown, P1 of the first path set 11 <m:1>It indicates that M first transistors 111 are connected in parallel, the first path end of each first transistor 111 is connected to the power supply voltage VDD, and the control end thereof is used to receive the input clock signal. PC1 of the first path set 11 <m:1>It indicates that M second transistors 112 are connected in parallel, wherein the first connection ends of the M second transistors 112 are connected one-to-one with the second connection ends of the M first transistors 111, and the control end of each second transistor 112 receives a first control signal, and the number of first paths that are turned on in the first path set 11 is adjusted by the first control signal.

[0066] In this embodiment, when the first path set 11 is working, the first control signal can be a plurality of pulse signals having the same number as the second transistors 112. When the pulse signal is at a logic low level, the second transistor 112 is in an on state, and at this time, the first path of the first path set 11 is in an on state. When the pulse signal is at a logic high level, the second transistor 112 is in an off state, and at this time, the first path of the first path set 11 is in an off state. In other embodiments, the first control signal can also be a pulse signal, and the on and off of the plurality of second transistors 112 are controlled by a pulse signal.

[0067] In this embodiment, the first transistor 111 and the second transistor 112 may be PMOS transistors. In other embodiments, they may also be other switch elements without limitation.

[0068] Optionally, see Figure 3 , each second path in the second path set 12 includes a third transistor 121 and a fourth transistor 122 .

[0069] The first channel end of the third transistor 121 is connected to the first output end, and the control end thereof is used to receive the first working power supply V1; the first channel end of the fourth transistor 122 is connected to the second channel end of the third transistor 121, the control end thereof is used to receive the input clock signal, and the second channel end thereof is used to receive the ground voltage; wherein, based on the input clock signal received by the fourth transistor 122 in each second path being at a logic high level, the second path set 12 is in a working state; based on the first working power supply received by the third transistor 121 in each second path, the second paths that are turned on in the working state of the second path set 12 are all the second paths.

[0070] like Figure 3 As shown, NC1 of the second path set 12 <n:1>N third transistors 121 are connected in parallel, the first path end of each third transistor 121 is connected to the first output end, and the control end thereof is used to receive the first working power supply V1, and the first working power supply V1 makes the N third transistors 121 all in the conducting state. <m:1>It indicates that N fourth transistors 122 are connected in parallel, wherein the first connection ends of the N fourth transistors 122 are connected one-to-one with the second connection ends of the N third transistors 121, and the control end of each fourth transistor 122 receives an input clock signal. Based on the input clock signal received by each fourth transistor 122 being at a logic high level, the second path set 12 is in a working state. When the second path set 12 is in a working state, the second paths that are turned on are all second paths.

[0071] In this embodiment, the third transistor 121 and the fourth transistor 122 may be NMOS transistors. In other embodiments, they may also be other switch elements which are not limited here.

[0072] Optionally, see Figure 3 , each third path in the third path set 21 includes a fifth transistor 211 and a sixth transistor 212 .

[0073] The first path end of the fifth transistor 211 is connected to the power supply voltage VDD, and the control end thereof is used to receive the input clock signal; the first path end of the sixth transistor 212 is connected to the second path end of the fifth transistor 211, the control end thereof is used to receive the second working power supply V2, and the second path end thereof is connected to the second output end; wherein, based on the input clock signal received by the fifth transistor 211 in each third path being at a logic low level, the third path set 21 is in a working state; based on the second working power supply V2 received by the sixth transistor 212 in each third path, the third paths that are turned on in the working state of the third path set 21 are all the third paths.

[0074] like Figure 3 As shown, P2 of the third path set 21 <n:1>It indicates that N fifth transistors 211 are connected in parallel, and the first path end of each fifth transistor 211 is connected to the power supply voltage VDD, and the control end thereof is used to receive the input clock signal. <n:1>It indicates that N sixth transistors 212 are connected in parallel, wherein the first connection terminals of the N sixth transistors 212 are connected one-to-one with the second connection terminals of the N fifth transistors 211, and the control terminal of each sixth transistor 212 receives the second working power supply V2, and the second working power supply V2 makes the N sixth transistors 212 all in a conducting state. Based on the input clock signal received by each fifth transistor 211 being at a logic low level, the third path set 21 is in a working state, and when the third path set 21 is in a working state, the turned-on third paths are all the third paths.

[0075] The fifth transistor 211 and the sixth transistor 212 may be PMOS transistors in this embodiment, and may be other switch elements in other embodiments without limitation.

[0076] Optionally, see Figure 3 , each fourth path in the fourth path set 22 includes a seventh transistor 221 and an eighth transistor 222 .

[0077] The first channel end of the seventh transistor 221 is connected to the second output end, and the control end thereof is used to receive the second control signal; the first channel end of the eighth transistor 222 is connected to the second channel end of the seventh transistor 221, the control end thereof is used to receive the input clock signal, and the second channel end thereof is connected to receive the ground voltage; wherein, based on the input clock signal received by the eighth transistor 222 in each fourth path being at a logic high level, the fourth path set 22 is in a working state; based on the second control signal received by the seventh transistor 221 in each fourth path, the number of fourth paths that are turned on in the fourth path set 22 is adjusted.

[0078] like Figure 3 As shown, NC2 of the fourth path set 22 <m:1>It indicates that M seventh transistors 221 are connected in parallel, the first path end of each seventh transistor 221 is connected to the second output end, and the control end thereof is used to receive the second control signal. <m:1>It indicates that M eighth transistors 222 are connected in parallel, wherein the first connection ends of the M eighth transistors 222 are connected one-to-one with the second connection ends of the M seventh transistors 221, and the control end of each eighth transistor 222 receives an input clock signal, and the number of conductive fourth paths of the fourth path set 22 is adjusted by the second control signal.

[0079] In this embodiment, when the fourth path set 22 is working, the second control signal can be a plurality of pulse signals of the same number as the seventh transistors 221. When the pulse signal is at a logic high level, the seventh transistor 221 is in an on state, and at this time, the fourth path of the fourth path set 22 is in an on state. When the pulse signal is at a logic low level, the seventh transistor 221 is in an off state, and at this time, the fourth path of the fourth path set 22 is in an off state. In other embodiments, the second control signal can also be a pulse signal, and the on and off of multiple seventh transistors 221 are controlled by a pulse signal. Among them, the first control signal and the second control signal cooperate with each other, and the sum of the number of first paths in the first path set 11 and the number of fourth paths in the fourth path set is M.

[0080] The seventh transistor 221 and the eighth transistor 222 may be NMOS transistors in this embodiment, and may be other switch elements in other embodiments without limitation.

[0081] Optionally, see Figure 3 The duty cycle adjustment circuit 100 of this embodiment includes a buffer 30 and an inverter 40. In this embodiment, the first adjustment circuit 10 and the second adjustment circuit 20 receive input clock signals through the buffer 30 and / or output output clock signals through the inverter 40 respectively.

[0082] The buffer 30 is used to receive the input clock signal, and its main function is to copy, convert the format and level of the clock signal generated by the crystal or crystal oscillator. Selecting a suitable clock buffer 30 can replace the crystal or crystal oscillator and reduce the cost.

[0083] The inverter 40 receives the input clock signal from the first regulating circuit 10 and the second regulating circuit 20 and inverts the phase of the input clock signal by 180 degrees, so that the phase of the output clock signal CLK_OUT is consistent with the phase of CLK_IN.

[0084] Optionally, see Figure 4 , Figure 4 is a schematic diagram of the structure of the third embodiment of the duty cycle adjustment circuit of the present application. Figure 4 As shown, the duty cycle adjustment circuit 100 of this embodiment further includes at least one dummy unit 50, wherein the duty cycle adjustment circuit 100 changes the initial duty cycle of the output clock signal by changing the number of dummy units 50. The duty cycle adjustment circuit 100 can change the initial duty cycle of its own structure by changing the number of dummy units 50 in case a duty cycle other than 50% is required.

[0085] In one application scenario, see Figure 5 , Figure 5 1 is a schematic diagram comparing the duty cycle adjustment circuit of the present application with the traditional circuit simulation structure. In this application scenario, the number of first paths of the first path set 11 and the number of fourth paths of the fourth path set 22 of the duty cycle adjustment circuit 100 are set to 32, and the number of second paths of the second path set 12 and the number of third paths of the third path set 21 are set to 16. Figure 5 The middle line is the simulation result of the duty cycle adjustment circuit 100 of the present application. The upper and lower lines are the simulation results of two duty cycle adjustment circuits with different traditional structures. Figure 5 The vertical axis is the duty cycle, and the horizontal axis is the adjustment gear of the first control signal. The adjustment gear of the first control signal refers to the number of paths that are conducted by the first control signal.

[0086] Compared with the traditional structure duty cycle adjustment circuit, when the number of conduction of the first path of the first path set 11 increases from one to two, the duty cycle adjusted by the first adjustment circuit 10 is relatively large, and the number of conduction of the fourth path in the fourth path set 22 in the second adjustment circuit 20 increases from 31 to 30, and the duty cycle adjusted by the second adjustment circuit 20 is relatively small. Then, the first output end and the second output end of the first adjustment circuit 10 and the second adjustment circuit 20 are fitted, so that the duty cycle adjusted each time the gear is adjusted is not much different, so that the linearity of the output clock signal is better, that is, the resolution of the clock signal duty cycle is significantly improved.

[0087] See also Figure 6 , Figure 6 This is a schematic diagram comparing the duty cycle adjustment steps of the present application's duty cycle adjustment circuit and the traditional structure. Figure 6 The figure shows the change of each adjustment step length of the conventional duty cycle adjustment circuit and the duty cycle adjustment circuit 100 of the present application with the adjustment gear under the clock input of 2400 MHz. The horizontal axis is the adjustment gear, and the vertical axis is the change amount, in picoseconds. It can be seen that the adjustment value of the duty cycle adjustment circuit 100 of the present application has been very stable and maintained at around 2 picoseconds, while the conventional structure exceeds 20 picoseconds at the edge gear.

[0088] Different from the prior art, the present application adjusts the duty cycle of the input clock signal by setting a first adjustment circuit 10 and a second adjustment circuit 20, wherein the first adjustment circuit 10 includes a first path set 11 and a second path set 12, and the second adjustment circuit 20 includes a third path set 21 and a fourth path set 22, each adjustment path set includes multiple conduction paths, and the present application adjusts the duty cycle of the output clock signal by controlling the number of conduction paths of the first path set 11 and the fourth path set 22, and improves the linearity of the output clock signal by fixing the number of conduction paths of the second path set 12 and the third path set 21, respectively cooperating with the fourth path set 22 and the first path set 11, thereby accurately controlling the duty cycle of the output clock signal.

[0089] This application further proposes a chip, see Figure 7 , Figure 7 It is a schematic diagram of the structure of a chip embodiment of the present application, and the chip 200 includes any one of the duty cycle adjustment circuits 100 described above.

[0090] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A duty cycle adjustment circuit, It is characterized in that include: A first regulating circuit includes a first path set and a second path set; A second regulating circuit includes a third path set and a fourth path set; The first path set, the second path set, the third path set and the fourth path set respectively include a plurality of conductive paths, and the first path set and the fourth path set respectively receive a first control signal and a second control signal to control the number of conductive first paths in the first path set and the number of conductive fourth paths in the fourth path set, thereby adjusting the duty cycle of the output clock signal; When the second path set and the third path set are working, the number of second paths turned on in the second path set and the number of third paths turned on in the third path set are fixed, the first path set and the third path set are in working state in response to the logic low level of the input clock signal, and the first paths turned on in the first path set cooperate with the third paths turned on in a fixed number in the third path set; the fourth path set and the second path set are in working state in response to the logic high level of the input clock signal, and the fourth paths turned on in the fourth path set cooperate with the second paths turned on in a fixed number in the second path set, so as to improve the linearity of the output clock signal.

2. The duty cycle adjustment circuit according to claim 1, It is characterized in that include: The first path set includes M first paths, and the fourth path set includes M fourth paths; The second path set includes N second paths, the third path includes N third paths, M and N are natural numbers respectively, and N is less than M; The sum of the number of the first paths of the first path set that are turned on in an operating state in response to a logic low level of the input clock signal and the number of the fourth paths of the fourth path set that are turned on in an operating state in response to a logic high level of the input clock signal is M.

3. The duty cycle adjustment circuit according to claim 2, It is characterized in that N is equal to M / 2 or a natural number close to M / 2.

4. The duty cycle adjustment circuit according to claim 3, It is characterized in that Each of the first paths in the first path set includes: A first transistor, a first channel end of which is connected to a power supply voltage, and a control end of which is used to receive the input clock signal; a second transistor, a first path end of which is connected to the second path end of the first transistor, a control end of which is used to receive the first control signal, and a second path end of which is connected to the first output end; Wherein, based on the input clock signal received by the first transistor in each of the first paths being at a logic low level, the first path set is in a working state; based on the first control signal received by the second transistor in each of the first paths, the number of the first paths that are turned on in the first path set is adjusted.

5. The duty cycle adjustment circuit according to claim 3, It is characterized in that Each of the second paths in the second path set includes: A third transistor, a first path end of which is connected to the first output end, and a control end of which is used to receive a first working power supply; a fourth transistor, a first channel end of which is connected to the second channel end of the third transistor, a control end of which is used to receive the input clock signal, and a second channel end of which is used to receive a ground voltage; Among them, based on the input clock signal received by the fourth transistor in each of the second paths being at a logic high level, the second path set is in a working state; based on the first working power received by the third transistor in each of the second paths, the second paths in the second path set that are turned on in the working state are all the second paths.

6. The duty cycle adjustment circuit according to claim 3, It is characterized in that Each of the third paths in the third path set includes: a fifth transistor, a first channel end of which is connected to a power supply voltage, and a control end of which is used to receive the input clock signal; a sixth transistor, a first channel end of which is connected to the second channel end of the fifth transistor, a control end of which is used to receive a second working power supply, and a second channel end of which is connected to the second output end; Among them, based on the input clock signal received by the fifth transistor in each of the third paths being at a logic low level, the third path set is in a working state; based on the second working power received by the sixth transistor in each of the third paths, the third paths that are turned on in the working state in the third path set are all the third paths.

7. The duty cycle adjustment circuit according to claim 3, It is characterized in that Each of the fourth paths in the fourth path set includes: a seventh transistor, a first channel end of which is connected to the second output end, and a control end of which is used to receive the second control signal; an eighth transistor, a first channel end of which is connected to the second channel end of the seventh transistor, a control end of which is used to receive the input clock signal, and a second channel end of which is connected to receive a ground voltage; Wherein, based on the input clock signal received by the eighth transistor in each of the fourth paths being at a logic high level, the fourth path set is in a working state; based on the second control signal received by the seventh transistor in each of the fourth paths, the number of the fourth paths that are turned on in the fourth path set is adjusted.

8. The duty cycle adjustment circuit according to claim 3, It is characterized in that The first regulating circuit and the second regulating circuit respectively receive the input clock signal through a buffer and / or output the output clock signal through an inverter.

9. The duty cycle adjustment circuit according to claim 3, It is characterized in that Further including: At least one dummy unit, wherein the duty cycle adjustment circuit changes the initial duty cycle of the output clock signal by changing the number of the dummy units.

10. A chip, It is characterized in that Comprising a duty cycle adjustment circuit as described in any one of claims 1-9.

Images