Chip testing equipment and systems

Abstract

The present invention provides a chip testing device and system suitable for testing multiple chips in a chipset group. The chip testing device includes a signal interface and a test design circuit. The signal interface transmits an input signal from a test device and multiple drive signals in parallel to each chip. The test design circuit receives multiple output signals from the chips through the signal interface and serially outputs test data to the test device based on the output signals.

Description

Technical Field

[0001] The present invention relates to a chip testing device and system, and in particular to a chip testing device and system used in a wafer probe (CP) stage. Background Art

[0002] With the continuous advancement of process technology and the development of applications, the capacity of memory products is constantly increasing. As a result, the testing cost required for each memory chip is also increasing. Therefore, how to reduce the testing cost of memory chips has become an increasingly important issue.

[0003] To reduce testing costs, most current memory tests allocate test channels on a test fixture to multiple chips, increasing the number of chips tested in parallel and reducing test time. However, current practices require at least one probe pin on the test fixture to connect to the chip's input / output (IO) pins for each chip to transmit test results. Furthermore, the number of probes on the test fixture must match the number of test pins on the chips being tested in parallel. This limits the number of chips that can be tested in parallel, preventing further reductions in testing costs. Summary of the Invention

[0004] The present invention provides a chip testing device and system, which increase the number of chips tested in parallel by sharing a test interface.

[0005] The chip testing device of the present invention is suitable for testing multiple chips in a chipset group. The chip testing device includes a signal interface and a test design circuit. The signal interface is coupled to the chips in the chipset group. The signal interface transmits an input signal from a test device and multiple drive signals in parallel to each chip. The test design circuit is coupled to the signal interface. The test design circuit receives multiple output signals from the chips via the signal interface and serially outputs test data to the test device based on the output signals.

[0006] The test device system of the present invention includes a chipset group having multiple chips, a test device, and the aforementioned chip test device. The chip test device is coupled to the chipset group and the test device and tests the chips in the chipset group.

[0007] Based on the above, the chip testing device and system of the present invention not only enables the driver pins of each chip under test to share the same driver pads, but also enables the input and output pins of each chip under test to share the same input and output pads. Therefore, the chip testing device and system of the present invention does not require a dedicated probe for each chip's input and output pins. Furthermore, the number of chips that can be tested in parallel is not limited by the number of probes in the test fixture. This allows for the easy expansion of the number of chips tested in parallel, thereby reducing the cost of testing memory chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram showing a chip testing system according to an embodiment of the present invention;

[0009] Figure 2 A circuit diagram showing a chip testing device according to an embodiment of the present invention;

[0010] Figure 3 A signal diagram illustrating a chip testing device according to an embodiment of the present invention;

[0011] Figure 4 FIG. 1 shows a configuration example of a chip testing device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0012] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0013] First reference Figure 1 , Figure 1 A schematic diagram of a chip testing system according to an embodiment of the present invention is shown. In this embodiment, the chip testing system 100 includes a chip testing device 110, a chip group 120, and a testing device 130. The chip group 120 includes four chips 140_1 to 140_4. For example, the chip group 120 can be formed by selecting four chips 140_1 to 140_4 with similar positions from a wafer to be tested. Those skilled in the art can determine the number of chips in the chip group 120 according to their actual needs, and the embodiment of the present invention is not limited to this. The testing device 130, for example, includes testing tools such as probe cards, which can be used to judge the quality of chips during the chip probing (CP) stage.

[0014] The chip testing device 110 is suitable for testing the four chips 140_1 to 140_4 in the chip group 120. The chip testing device 110 includes a signal interface 150 and a test design circuit 160. Figure 1As shown, signal interface 150 is coupled to chips 140_1-140_4 in chipset group 120. When testing chips 140_1-140_4, signal interface 150 transmits an input signal IN from test equipment 130 and three drive signals DS1-DS3 in parallel to each chip 140_1-140_4. Input signal IN, for example, carries test data. Drive signals DS1-DS3 include, for example, clock signals, address signals, and chip control signals.

[0015] The test design circuit 160 is coupled to the signal interface 150. Figure 1 As shown, when testing chips 140_1 to 140_4, test design circuit 160 can receive four output signals OUT1 to OUT4 from chips 140_1 to 140_4 via signal interface 150. Furthermore, test design circuit 160 can serially output test data TS to test equipment 130 via signal interface 150 based on output signals OUT1 to OUT4. Thus, test equipment 130 can determine the quality of chips 140_1 to 140_4 based on test data TS.

[0016] It should be noted that since the signal interface 150 in this case is only composed of lines and buffers, it does not change the logic level of the signal and the value it represents. Figure 1 The same reference numerals are used to represent the signals (input signal IN, drive signals DS1-DS3, output signals OUT1-OUT4 and test data TS) transmitted via the signal interface 150. The detailed circuit structure of the signal interface 150 will be described later.

[0017] The detailed circuit structure of the chip testing device 110 of this embodiment is introduced below. Figure 2 FIG. 1 is a circuit diagram of a chip testing device according to an embodiment of the present invention. Figure 2 In the example, signal interface 150 includes a buffer circuit 200, driver pads PCLK, PDR1, and PDR2, input / output pads PIO, and an operating voltage pad PVCC. Buffer circuit 200 is coupled to each chip 140_1-140_4 and test design circuit 160. Buffer circuit 200 includes driver buffers 220_1-220_4, 230_1-230_4, and 240_1-240_4, a first input buffer 250, second input buffers 260_1-260_4, and output buffers 270_1-270_4.

[0018] Driver pads PCLK, PDR1, and PDR2 are coupled to buffer circuit 200. Specifically, driver buffers 220_1, 230_1, and 240_1 in buffer circuit 200 are coupled to chip 140_1. Driver buffers 220_2, 230_2, and 240_2 in buffer circuit 200 are coupled to chip 140_2. Driver buffers 220_3, 230_3, and 240_3 in buffer circuit 200 are coupled to chip 140_3. Driver buffers 220_4, 230_4, and 240_4 in buffer circuit 200 are coupled to chip 140_4. The input of each driver buffer 220_1-220_4 is coupled to driver pad PCLK. The output of each driver buffer 220_1-220_4 is coupled to driver pin NCLK on the corresponding chip. The input of each driver buffer 230_1-230_4 is coupled to driver pad PDR1. The output of each driver buffer 230_1-230_4 is coupled to a corresponding on-chip drive pin NDR1. The input of each driver buffer 240_1-240_4 is coupled to a drive pad PDR2. The output of each driver buffer 240_1-240_4 is coupled to a corresponding on-chip drive pin NDR2. The drive pads PCLK, PDR1, and PDR2 can respectively receive drive signals DS1-DS3 from the test equipment 130 and transmit the drive signals DS1-DS3 to the drive pins NCLK, NDR1, and NDR2 of each chip 140_1-140_4 via the buffer circuit 200.

[0019] The input / output pad PIO is coupled to the test design circuit 160 and the buffer circuit 200. Specifically, the input end of the first input buffer 250 in the buffer circuit 200 is coupled to the input / output pad PIO. The second input buffers 260_1 through 260_4 in the buffer circuit 200 are coupled to the chips 140_1 through 140_4, respectively. The input end of each second input buffer 260_1 through 260_4 is coupled to the output end of the first input buffer 250. The output end of each second input buffer 260_1 through 260_4 is coupled to the input / output pin NIO on the corresponding chip. The input / output pad PIO receives an input signal IN from the test equipment 130 and transmits the input signal IN to the input / output pin NIO of each chip 140_1 through 140_4 via the buffer circuit 200.

[0020] The operating voltage pad PVCC is coupled to the buffer circuit 200 . The operating voltage pad PVCC receives the operating voltage VCC and transmits the operating voltage VCC to the operating voltage pin NVCC of each chip 140_1 ˜ 140_4 via the buffer circuit 200 .

[0021] In buffer circuit 200, the input terminal of each output buffer 270_1-270_4 is coupled to an input / output pin NIO on the corresponding chip. The control terminals of output buffers 270_1-270_4 are respectively coupled to output enable signals OE1-OE4. The output terminal of each output buffer 270_1-270_4 is coupled to test design circuit 160. In response to output enable signals OE1-OE4, buffer circuit 200 can transmit output signals OUT1-OUT4 from chips 140_1-140_4 in parallel to test design circuit 160. For example, when chips 140_1-140_4 transmit output signals OUT1-OUT4 to output buffers 270_1-270_4, respectively, chips 140_1-140_4 may also transmit output enable signals OE1-OE4 at a high logic level to output buffers 270_1-270_4, respectively. As a result, the output buffers 270_1 - 270_4 can start transmitting the output signals OUT1 - OUT4 in parallel to the test design circuit 160 .

[0022] The test design circuit 160 includes flip-flop circuits 300_1-300_4 and a test buffer 310. The flip-flop circuits 300_1-300_4 are connected in series. The first input of each flip-flop circuit 300_1-300_4 is coupled to the output of the output buffers 270_1-270_4 in the buffer circuit 200. The second input of the first-stage flip-flop circuit 300_1 is coupled to the serial control signal CS. The second input of the flip-flop circuits 300_2-300_4 other than the first stage is coupled to the output of the flip-flop circuit in the previous stage.

[0023] An input terminal of the test buffer 310 is coupled to the output terminal of the last-stage flip-flop circuit 300_4 , a control terminal of the test buffer 310 is coupled to the output enable signal OE4 , and an output terminal of the test buffer 310 is coupled to the input / output pad PIO.

[0024] In this embodiment, the drive signal DS1 can be operated as, for example, a clock signal SCLK. The test design circuit 160 can respond to the clock signal SCLK and sequentially transmit the output signals OUT1-OUT4 as test data TS to the input / output pads PIO. Specifically, after the output buffers 270_1-270_4 transmit the output signals OUT1-OUT4 in parallel to the test design circuit 160, the flip-flop circuits 300_1-300_4 of each stage in the test design circuit 160 can respond to the clock signal SCLK and transmit the received output signals OUT1-OUT4 to the flip-flop circuit of the next stage. This allows the flip-flop circuit 300_4 of the last stage to sequentially output the output signals OUT1-OUT4 as test data TS to the input / output pads PIO via the test buffer 310.

[0025] In terms of the flip-flop circuit structure, flip-flop circuits 300_1-300_4 respectively include AND gates 320_1-320_4 and flip-flops 330_1-330_4. The first input of AND gate 320_1 is coupled to output buffer 270_1 in buffer circuit 200. The second input of AND gate 320_1 is coupled to serial control signal CS. The input of flip-flop 330_1 is coupled to the output of AND gate 320_1. The control terminal of flip-flop 330_1 is coupled to clock signal SCLK. The output of flip-flop 330_1 is coupled to the second input of AND gate 320_2 in the next-stage flip-flop circuit 330_2. The first input of AND gate 320_2 is coupled to output buffer 270_2 in buffer circuit 200. The input of flip-flop 330_2 is coupled to the output of AND gate 320_2. The control terminal of flip-flop 330_2 is coupled to the clock signal SCLK. The output terminal of flip-flop 330_2 is coupled to the second input terminal of AND gate 320_3 in the next-stage flip-flop circuit 330_3. The first input terminal of AND gate 320_3 is coupled to output buffer 270_3 in buffer circuit 200. The input terminal of flip-flop 330_3 is coupled to the output terminal of AND gate 320_3. The control terminal of flip-flop 330_3 is coupled to the clock signal SCLK. The output terminal of flip-flop 330_3 is coupled to the second input terminal of AND gate 320_4 in the next-stage flip-flop circuit 330_4. The first input terminal of AND gate 320_4 is coupled to output buffer 270_4 in buffer circuit 200. The input terminal of flip-flop 330_4 is coupled to the output terminal of AND gate 320_4. The control terminal of flip-flop 330_4 is coupled to the clock signal SCLK. An output terminal of the flip-flop 330_4 is coupled to an input terminal of the test buffer 310 .

[0026] It should be noted that those skilled in the art may, based on their actual needs and referring to the teachings of the embodiments of the present invention, increase the number of buffers in the buffer circuit 200 and the number of flip-flop circuits connected in series to a greater number, and the embodiments of the present invention are not limited thereto.

[0027] Figure 3 A signal diagram of a chip testing device according to an embodiment of the present invention is shown. Figure 3 The signals on the driving pads PCLK, PDR1, PDR2, input / output pads PIO, and the driving pins NCLK, NDR1, NDR2, and input / output pin NIO of each chip 140_1 to 140_4 are shown in FIG. Figure 2 and Figure 3 .

[0028] When testing the chips 140_1 to 140_4, write operations and read operations can be performed on the chips 140_1 to 140_4. When performing a write operation, the driving pads PDR1 and PDR2 receive write commands WCA#1, WCA#2, and WCA#3 from the test equipment 130 via the driving signals DS2 and DS3. Figure 3 As shown, the write commands WCA# 1 , WCA# 2 , and WCA# 3 may be transmitted to the driving pins NDR1 and NDR2 of each chip 140_1 ˜ 140_4 via the buffer circuit 200 .

[0029] Then, the input / output pad PIO can receive the write data WD1-WD4 from the test device 130 via the input signal IN. Figure 3 As shown, the write data WD1 - WD4 may be transmitted to the input / output pin NIO of each chip 140_1 - 140_4 via the buffer circuit 200 .

[0030] When performing a read operation, the driving pads PDR1 and PDR2 may receive the read commands RCA#1, RCA#2, and RCA#3 from the test device 130 via the driving signals DS2 and DS3. Figure 3 As shown, the read commands RCA# 1 , RCA# 2 and RCA# 3 may be transmitted to the driving pins NDR1 and NDR2 of each chip 140_1 ˜ 140_4 via the buffer circuit 200 .

[0031] Then, the input and output pins NIO of each chip 140_1 to 140_4 can generate read data RD1 to RD4 respectively according to the read commands RCA#1, RCA#2 and RCA#3. At this time, the read data RD1 to RD4 can be transmitted in parallel to the test design circuit 160 via the buffer circuit 200. Figure 3As shown, the test design circuit 160 can respond to the clock signal on the driving pad PCLK to serially transmit the read data RD1 - RD4 to the input / output pad PIO in sequence.

[0032] According to the above-described operation method, the chip testing device 110 of this embodiment allows the chips 140_1 to 140_4 to share the same driving pads PCLK, PDR1, PDR2, input / output pads PIO, and operating voltage pads PVCC. Furthermore, through the configuration of the signal interface 150 and the test design circuit 160, more chips can be tested without increasing the test time.

[0033] Figure 4 FIG. 1 shows an example of a configuration of a chip testing device according to an embodiment of the present invention. Figure 4 Figure 4 shows chip groups 400_1 and 400_2 on a wafer. Chip group 400_1 includes multiple chips, such as chips 410_1 to 410_2. Chip group 400_2 includes multiple chips, such as chips 420_1 to 420_2. Chip testing device 430 can be located on scribe line C1 on the wafer containing chip group 400_1, and chip testing device 440 can be located on scribe line C2 on the wafer containing chip group 400_2. Since no circuits are located on scribe lines C1 and C2 on the wafer, placing chip testing devices 430 and 440, used during wafer probing, on scribe lines C1 and C2 can avoid increasing chip size and interfering with other circuits. However, in other embodiments, chip testing devices 430 and 440 can also be located inside the chips of chips groups 400_1 and 400_2, respectively, and the present invention is not limited to this.

[0034] In summary, the chip testing device and system of the present invention can serially transmit output signals from multiple chips in parallel to shared input and output pads within a chip group. Therefore, the number of chips tested in parallel can be easily increased without increasing test time, thereby reducing the test cost of memory chips.

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip testing device, adapted to test multiple chips in a chip group, comprising: a signal interface coupled to the plurality of chips in the chip group and transmitting an input signal from a test device and a plurality of driving signals in parallel to each chip; as well as a test design circuit coupled to the signal interface, receiving a plurality of output signals from the plurality of chips through the signal interface, and serially outputting test data to the test device according to the plurality of output signals; The signal interface includes: a buffer circuit coupling each chip and the test design circuit, The buffer circuit responds to the multiple output enable signals transmitted from the multiple chips and transmits the multiple output signals output from the multiple chips in parallel to the test design circuit. The test design circuit responds to the clock signal in the multiple drive signals and transmits the multiple output signals in sequence as the test data to the input and output pads in series, so as to serially output the test data to the test equipment.

2. The chip testing device according to claim 1, wherein the signal interface further comprises: a plurality of driving pads coupled to the buffer circuit, receiving the plurality of driving signals from the test equipment, and transmitting the plurality of driving signals to each chip via the buffer circuit; as well as The input / output pad is coupled to the test design circuit and the buffer circuit, receives the input signal from the test equipment, and transmits the input signal to each chip via the buffer circuit.

3. The chip testing device according to claim 2, wherein the buffer circuit comprises: A plurality of driving buffers, wherein an input end of each driving buffer is coupled to a corresponding driving pad, and an output end of each driving buffer is coupled to a corresponding driving pin on the chip; A first input buffer, an input terminal of which is coupled to the input-output pad, a plurality of second input buffers, wherein an input end of each second input buffer is coupled to an output end of the first input buffer, and an output end of each second input buffer is coupled to an input / output pin on a corresponding chip; as well as A plurality of output buffers are provided, wherein the input end of each output buffer is coupled to the corresponding input and output pins on the chip, the control end of each output buffer is coupled to the corresponding output enable signal, and the output end of each output buffer is coupled to the test design circuit.

4. The chip testing device according to claim 2, wherein the test design circuit comprises: A plurality of flip-flop circuits are connected in series, wherein a first input terminal of each flip-flop circuit is coupled to the buffer circuit, a second input terminal of a first-stage flip-flop circuit is coupled to a serial control signal, and a second input terminal of flip-flop circuits other than the first-stage flip-flop circuit is coupled to an output terminal of a previous-stage flip-flop circuit; as well as A test buffer, whose input terminal is coupled to the output terminal of the last-stage flip-flop circuit, whose control terminal is coupled to the corresponding output enable signal, and whose output terminal is coupled to the input / output pad. Among them, the flip-flop circuit of each level responds to the clock signal in the multiple driving signals to transmit the received output signal to the flip-flop circuit of the next level, so that the flip-flop circuit of the last level outputs the multiple output signals serially as the test data through the test buffer.

5. The chip testing device according to claim 4 , wherein each flip-flop circuit comprises: an AND gate, a first input terminal of which is coupled to the buffer circuit; as well as A flip-flop, whose input terminal is coupled to the output terminal of the AND gate, whose control terminal is coupled to the clock signal, and whose output terminal is coupled to the second input terminal of the AND gate in the next-stage flip-flop circuit, The second input terminal of the AND gate in the first-stage flip-flop circuit is coupled to the serial control signal, and the output terminal of the flip-flop in the last-stage flip-flop circuit is coupled to the input terminal of the test buffer.

6. The chip testing device according to claim 2, wherein the signal interface further comprises: The operating voltage pad is coupled to the buffer circuit, receives an operating voltage, and transmits the operating voltage to each chip via the buffer circuit. 7 . The chip testing device according to claim 1 , wherein the chip testing device is disposed on a dicing street on a wafer to which the chip group belongs. 8 . The chip testing device according to claim 1 , wherein the chip testing device is disposed inside the chip of the chip group.

9. A chip testing system comprising: Chipset, which has multiple chips; Testing equipment; as well as The chip testing device according to claim 1 is coupled to the chipset group and the testing equipment, and performs testing on the plurality of chips in the chipset group.

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