A DC pulse signal acquisition circuit

Abstract

The present application discloses a DC pulse signal acquisition circuit. It includes a conversion module, a voltage follower module, a comparison module and an FPGA module. The present application is designed with a conversion module, the conversion module has a first input terminal, the first input terminal is configured to receive a first differential pulse signal; the conversion module is configured to convert the first differential pulse signal to obtain a second single-ended signal; the voltage follower module, the voltage follower module is configured to achieve impedance matching between the second single-ended signal and the comparison module input terminal signal to obtain a third single-ended signal; the comparison module, the comparison module is configured to compare a fourth reference signal with the third single-ended signal to obtain a fifth level signal; the FPGA module, the FPGA module has a fifth input terminal and a sixth input terminal, the fifth input terminal and the sixth input terminal are both configured to receive a fifth level signal, and the FPGA module is configured to calculate the number of rising edges and falling edges of the fifth level signal.

Description

Technical Field

[0001] The present disclosure relates to the field of electrical technology, and in particular to a direct current pulse signal acquisition circuit. Background Art

[0002] In the field of control, counting sensors are often needed to count the effective actions of actuators. Currently, counting sensors generally use encoders, displacement sensors and other types of sensors, and their output signals are pulse signals. In order to complete the action counting of the actuator, the pulse signals output by the counting sensors need to be collected and processed.

[0003] In the past, counting and acquisition were usually performed by means of photocoupler and trigger combination, high-speed AD conversion circuit, etc. Among them, although the photocoupler and trigger combination can achieve isolated acquisition, the photocoupler will be mis-conducted for pulse signals with spikes or jitter, affecting the counting accuracy. The high-speed AD conversion circuit has high-speed AD conversion capability, which can complete the real-time acquisition of the pulse signal voltage value and count after judgment by the logic circuit, but this method occupies a large amount of hardware and software processing resources, and isolated acquisition is difficult to implement. Therefore, in order to meet the needs of a certain type of airborne equipment, complete the effective action of the actuator for counting, and comprehensively consider the influence of the external electromagnetic environment, we propose a DC pulse signal acquisition circuit to solve the above problems. Summary of the invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a DC pulse signal acquisition circuit with a simple circuit that can count the effective actions of the actuator.

[0005] In a first aspect, the present application provides a DC pulse signal acquisition circuit, comprising:

[0006] A conversion module, wherein the conversion module has a first input terminal, and the first input terminal is configured to receive a first differential pulse signal; the conversion module is configured to convert the first differential pulse signal to obtain a second single-ended signal;

[0007] A voltage follower module, wherein the voltage follower module has a second input terminal, the second input terminal is configured to receive the second single-ended signal, and the voltage follower module is configured to achieve impedance matching between the second single-ended signal and the input terminal signal of the comparison module to obtain a third single-ended signal;

[0008] a comparison module, the comparison module having a third input terminal and a fourth input terminal, the third input terminal being configured to receive a fourth reference signal, the fourth input terminal being configured to receive the third single-ended signal, the comparison module being configured to compare the fourth reference signal with the third single-ended signal to obtain a fifth level signal;

[0009] An FPGA module, wherein the FPGA module has a fifth input terminal and a sixth input terminal, wherein the fifth input terminal and the sixth input terminal are both configured to receive the fifth level signal, and the FPGA module is configured to calculate the number of rising edges and falling edges of the fifth level signal.

[0010] According to the technical solution provided in the embodiment of the present application, the conversion module includes a voltage dividing unit, a first current limiting unit and a differential amplification unit;

[0011] The voltage divider unit has an input end, which is the same as the first input end and is configured to receive a first differential pulse signal; the voltage divider unit is configured to perform voltage division processing on the first differential pulse signal to obtain a first pulse voltage division signal;

[0012] The first current limiting unit has an input end, and the input end of the first current limiting unit is configured to receive the first pulse voltage division signal; the first current limiting unit is configured to limit the current of the first pulse voltage division signal to obtain the first pulse voltage division signal after current limiting;

[0013] The differential amplifier unit has an input end, and the input end of the differential amplifier unit is configured to receive the first pulse voltage-divided signal after current limiting; the differential amplifier unit is configured to convert the first pulse voltage-divided signal after current limiting to obtain a second single-ended signal.

[0014] According to the technical solution provided in the embodiment of the present application, the voltage following module includes a second current limiting unit and a voltage following unit;

[0015] The second current limiting unit has an input end, the input end of the second current limiting unit is the same as the second input end, and is configured to receive the second single-ended signal; the second current limiting unit is configured to process the second single-ended signal by current limiting to obtain a second single-ended signal after current limiting;

[0016] The voltage follower unit has an input end, and the input end of the voltage follower unit is configured to receive the second single-ended signal after current limiting; the voltage follower unit is configured to achieve impedance matching between the second single-ended signal after current limiting and the input end signal of the comparison module to obtain a third single-ended signal.

[0017] According to the technical solution provided in the embodiment of the present application, the comparison module includes a third current limiting unit and a comparison unit;

[0018] The third current limiting unit has two input terminals, namely the third input terminal and the fourth input terminal, the third input terminal is configured to receive the fourth reference signal, and the fourth input terminal is configured to receive the third single-ended signal; the third current limiting unit is configured to perform current limiting processing on the third single-ended signal and the fourth reference signal to obtain the third single-ended signal after current limiting and the fourth reference signal after current limiting;

[0019] The comparison unit has two input ends, and the two input ends of the comparison unit are respectively configured to receive the third single-ended signal and the fourth reference signal after current limiting; the comparison unit is configured to compare the fourth reference signal after current limiting with the third single-ended signal after current limiting to obtain a fifth level signal.

[0020] According to the technical solution provided by the embodiment of the present application, it also includes: an isolation unit configured to isolate the pulse signal ground GND of the voltage dividing unit from the analog ground AGND of the isolation unit;

[0021] A filter unit configured to filter out common mode interference of an output signal;

[0022] a decoupling unit configured to perform filtering of a connected power source;

[0023] A voltage pull-up unit configured to increase the level and improve the noise margin of the signal and enhance the anti-interference capability.

[0024] According to the technical solution provided in the embodiment of the present application, the voltage dividing unit includes a first resistor R1 and a second resistor R2 connected in series in sequence, the first resistor R1 has a first end and a second end, the first end of the first resistor R1 is configured to receive the first differential pulse signal, the second resistor R2 has a first end and a second end, the first end and the second end of the second resistor R2 are respectively connected to the two ends of the first capacitor C1, the first end of the second resistor R2 is connected to the second end of the first resistor R1, and the second end of the second resistor R2 is configured to be connected to the pulse signal ground GND;

[0025] The first current limiting unit includes a fifth resistor R5, a fourth resistor R4 and a fourth capacitor C4, each of which has a first end and a second end, the first end of the fifth resistor R5 is connected to the first end of the second resistor R2, the second end of the fifth resistor R5 is connected to the first end of the fourth capacitor C4, the second end of the fourth capacitor C4 is connected to the second end of the fourth resistor R4, and the first end of the fourth resistor R4 is connected to the second end of the second resistor R2;

[0026] The differential amplifier unit includes a precision instrument amplifier N1, which has pin 1 RG1, pin 2 IN-, pin 3 IN+, pin 4 VS-, pin 5 REF, pin 6 OUTPUT, pin 7 VS+ and pin 8 RG2; the pin 2 IN- is connected to the second end of the fourth capacitor C4, the pin 3 IN+ is connected to the first end of the fourth capacitor C4, and the pin 1 RG1 and the pin 8 RG2 are set to be suspended.

[0027] According to the technical solution provided in the embodiment of the present application, the second current limiting unit includes a sixth resistor R6, which has a first end and a second end, and the first end of the sixth resistor R6 is connected to the 6-pin OUTPUT;

[0028] The voltage follower unit includes an operational amplifier N2A, which has pins 1, 2, 3, 4 and 8; the pin 3 of the operational amplifier N2A is connected to the second end of the sixth resistor R6.

[0029] According to the technical solution provided in the embodiment of the present application, the third current limiting unit includes a seventh resistor R7 and an eighth resistor R8, each of which has a first end and a second end, the first end of the seventh resistor R7 is configured to receive a fourth reference signal, and the first end of the eighth resistor R8 is connected to pin 1 of the operational amplifier N2A;

[0030] The comparison unit includes a comparator N3A, which has pins 2, 3, 4, 5 and 12; pin 4 of the comparator N3A is connected to the second end of the eighth resistor R8, pin 5 of the comparator N3A is connected to the second end of the seventh resistor R7, and pin 2 of the comparator N3A is respectively connected to the fifth input terminal of the FPGA module.

[0031] According to the technical solution provided in the embodiment of the present application, the isolation unit includes a third resistor R3, which has a first end and a second end, the first end of the third resistor R3 is connected to the second end of the second resistor R2, and the second end of the third resistor R3 is configured to be connected to the analog ground AGND;

[0032] The filtering unit includes a first filtering unit, a second filtering unit and a third filtering unit; the first filtering unit includes a second capacitor C2, the second capacitor C2 has a first end and a second end, the first end of the second capacitor C2 is connected to the second end of the fifth resistor R5, and the second end of the second capacitor C2 is configured to connect to the analog ground AGND; the second filtering unit includes a third capacitor C3, the third capacitor C3 has a first end and a second end, the first end of the third capacitor C3 is connected to the second end of the fourth resistor R4, and the second end of the third capacitor C3 is configured to connect to the analog ground AGND; the third filtering unit includes a ninth capacitor C9, the ninth capacitor C9 has a first end and a second end, the first end of the ninth capacitor C9 is connected to the second end of the seventh resistor R7, the second end of the ninth capacitor C9 is connected to the 12th pin of the comparator N3A, and the second end of the ninth capacitor C9 is configured to connect to the analog ground AGND;

[0033] The decoupling unit includes a first decoupling unit, a second decoupling unit, a third decoupling unit, a fourth decoupling unit and a fifth decoupling unit. The first decoupling unit includes a sixth capacitor C6, which has a first end and a second end. The first end of the sixth capacitor C6 is respectively connected to the 7-pin VS+ and the first external +15V power supply, and the second end of the sixth capacitor C6 is configured to connect to the analog ground AGND; the second decoupling unit includes a fifth capacitor C5, which has a first end and a second end. The first end of the fifth capacitor C5 is connected to the 5-pin REF, and the first end of the fifth capacitor C5 is configured to connect to the analog ground AGND, and the second end of the fifth capacitor C5 is respectively connected to the 4-pin VS- and the first external -15V power supply; the third decoupling unit includes a seventh capacitor C7, which has a first end and a second end. The first end of the seventh capacitor C7 is connected to the second end of the sixth resistor R6, the second end of the seventh capacitor C7 is connected to the 4th pin of the operational amplifier N2A, and the second end of the seventh capacitor C7 is configured to connect to the analog ground AGND; the fourth decoupling unit includes an eighth capacitor C8, which has a first end and a second end, the first end of the eighth capacitor C8 is respectively connected to the 8th pin of the operational amplifier N2A and the second external +15V power supply, and the second end of the eighth capacitor C8 is configured to connect to the analog ground AGND; the fifth decoupling unit includes a tenth capacitor C10, which has a first end and a second end, the first end of the tenth capacitor C10 is respectively connected to the 3rd pin of the comparator N3A and the third external +15V power supply, and the second end of the tenth capacitor C10 is configured to connect to the analog ground AGND;

[0034] The voltage pull-up unit includes a ninth resistor R9, which has a first end and a second end. The first end of the ninth resistor R9 is connected to pin 2 of the comparator N3A, and the second end of the ninth resistor R9 is connected to an external +3.3V power supply.

[0035] In summary, the technical solution specifically discloses a DC pulse signal acquisition circuit. The present application is designed with a conversion module, which has a first input terminal, and the first input terminal is configured to receive a first differential pulse signal; the conversion module is configured to convert the first differential pulse signal to obtain a second single-ended signal; a voltage follower module, the voltage follower module has a second input terminal, and the second input terminal is configured to receive a second single-ended signal, and the voltage follower module is configured to achieve impedance matching between the second single-ended signal and the input terminal signal of the comparison module to obtain a third single-ended signal; a comparison module, the comparison module has a third input terminal and a fourth input terminal, the third input terminal is configured to receive a fourth reference signal, the fourth input terminal is configured to receive a third single-ended signal, and the comparison module is configured to compare the fourth reference signal with the third single-ended signal to obtain a fifth level signal; an FPGA module, the FPGA module has a fifth input terminal and a sixth input terminal, the fifth input terminal and the sixth input terminal are both configured to receive a fifth level signal, and the FPGA module is configured to calculate the number of rising edges and falling edges of the fifth level signal.

[0036] This solution has a simple circuit hierarchy, requires few components in the circuit structure, and has simple calculation of component parameters. It does not require complicated circuits and can effectively filter out abnormal jitter and electromagnetic interference of pulse signals, so as to count the effective actions of the actuator. It is especially suitable for occasions with compact structure space and isolation and anti-electromagnetic interference functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0038] Figure 1 The figure is an application diagram of a DC pulse signal acquisition circuit.

[0039] Figure 2 The figure is a schematic diagram of a conversion module of a DC pulse signal acquisition circuit.

[0040] Figure 3 The figure is a schematic diagram of a voltage follower module of a DC pulse signal acquisition circuit.

[0041] Figure 4 It is a schematic diagram of a comparison module of a DC pulse signal acquisition circuit. DETAILED DESCRIPTION

[0042] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0043] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0044] Embodiment 1

[0045] Please refer to Figure 1 The present application provides a DC pulse signal acquisition circuit, including:

[0046] A conversion module, the conversion module having a first input terminal, the first input terminal being configured to receive a first differential pulse signal; the conversion module is configured to convert the first differential pulse signal to obtain a second single-ended signal;

[0047] A voltage follower module, the voltage follower module having a second input terminal, the second input terminal is configured to receive a second single-ended signal, and the voltage follower module is configured to achieve impedance matching between the second single-ended signal and the input terminal signal of the comparison module to obtain a third single-ended signal;

[0048] A comparison module, the comparison module having a third input terminal and a fourth input terminal, the third input terminal is configured to receive a fourth reference signal, the fourth input terminal is configured to receive a third single-ended signal, and the comparison module is configured to compare the fourth reference signal with the third single-ended signal to obtain a fifth level signal;

[0049] The FPGA module has a fifth input terminal and a sixth input terminal, both of which are configured to receive a fifth level signal, and the FPGA module is configured to calculate the number of rising edges and falling edges of the fifth level signal.

[0050] In this embodiment, the conversion module has a first input terminal, the first input terminal is configured to receive a first differential pulse signal, the first differential pulse signal is a pulse signal Pulse_IN; the conversion module is configured to convert the pulse signal Pulse_IN to obtain a second single-ended signal;

[0051] A voltage follower module, the voltage follower module has a second input terminal, the second input terminal is configured to receive a second single-ended signal, the second single-ended signal is a single-ended signal Vout1, and the voltage follower module is configured to achieve impedance matching between the single-ended signal Vout1 and the input terminal signal of the comparison module to obtain a third single-ended signal;

[0052] a comparison module, the comparison module having a third input terminal and a fourth input terminal, the third input terminal being configured to receive a fourth reference signal, the fourth reference signal being a reference signal Vref, the fourth input terminal being configured to receive a third single-ended signal, the third single-ended signal being a single-ended signal Vout2, the comparison module being configured to compare the reference signal Vref with the single-ended signal Vout2 to obtain a fifth level signal;

[0053] FPGA module, the FPGA module has a fifth input terminal and a sixth input terminal, the fifth input terminal and the sixth input terminal are respectively the IO port channels IO1 and IO2 of the FPGA module, the IO port channels IO1 and IO2 are both configured to receive a fifth level signal, the fifth level signal is a TTL level signal IO_Timer, and the FPGA module is configured to count the number of rising edges and falling edges of the TTL level signal IO_Timer, thereby completing the DC pulse signal acquisition and counting functions.

[0054] like Figure 2 As shown, the conversion module includes a voltage dividing unit, a first current limiting unit and a differential amplification unit;

[0055] The voltage divider unit has an input end, which is the same as the first input end and is configured to receive the pulse signal Pulse_IN; the voltage divider unit is configured to perform voltage division processing on the pulse signal Pulse_IN to obtain a first pulse voltage division signal, and the first pulse voltage division signal is a signal Vout_P;

[0056] The first current limiting unit has an input end, and the input end of the first current limiting unit is configured to receive the differential signal Vout_P; the first current limiting unit is configured to limit the current of the differential signal Vout_P to obtain the differential signal Vout_P after current limiting;

[0057] The differential amplifier unit has an input end, and the input end of the differential amplifier unit is configured to receive the current-limited differential signal Vout_P; the differential amplifier unit is configured to convert the current-limited differential signal Vout_P to obtain a single-ended signal Vout1.

[0058] like Figure 3 As shown, the voltage following module includes a second current limiting unit and a voltage following unit;

[0059] The second current limiting unit has an input end, the input end of the second current limiting unit is the same as the second input end, and is configured to receive the single-ended signal Vout1; the second current limiting unit is configured to process the single-ended signal Vout1 by current limiting to obtain the single-ended signal Vout1 after current limiting;

[0060] The voltage follower unit has an input end, and the input end of the voltage follower unit is configured to receive the single-ended signal Vout1 after current limiting; the voltage follower unit is configured to achieve impedance matching between the single-ended signal Vout1 after current limiting and the input end signal of the comparison module to obtain the single-ended signal Vout2.

[0061] like Figure 4 As shown, the comparison module includes a third current limiting unit and a comparison unit;

[0062] The third current limiting unit has two input terminals, namely, a third input terminal and a fourth input terminal, the third input terminal is configured to receive a reference signal Vref, and the fourth input terminal is configured to receive a single-ended signal Vout2; the third current limiting unit is configured to perform current limiting processing on the single-ended signal Vout2 and the reference signal Vref to obtain the single-ended signal Vout2 after current limiting and the reference signal Vref after current limiting;

[0063] The comparison unit has two input terminals, which are respectively configured to receive the single-ended signal Vout2 and the reference signal Vref after current limiting; the comparison unit is configured to compare the reference signal Vref after current limiting with the single-ended signal Vout2 after current limiting to obtain a TTL level signal IO_Timer.

[0064] like Figure 1-4 As shown, it also includes: an isolation unit configured to isolate the pulse signal ground GND of the voltage dividing unit from the analog ground AGND of the isolation unit;

[0065] A filter unit configured to filter out common mode interference of an output signal;

[0066] a decoupling unit configured to perform filtering of a connected power source;

[0067] A voltage pull-up unit configured to increase the level and improve the noise margin of the signal and enhance the anti-interference capability.

[0068] like Figure 2 As shown, the voltage dividing unit includes a first resistor R1 and a second resistor R2 connected in series in sequence, the first resistor R1 has a first end and a second end, the first end of the first resistor R1 is configured to receive the pulse signal Pulse_IN, the second resistor R2 has a first end and a second end, the first end and the second end of the second resistor R2 are respectively connected to the two ends of the first capacitor C1, the first end of the second resistor R2 is connected to the second end of the first resistor R1, and the second end of the second resistor R2 is configured to be connected to the pulse signal ground GND;

[0069] The isolation unit includes a third resistor R3 having a first end and a second end, the first end of the third resistor R3 is connected to the second end of the second resistor R2, and the second end of the third resistor R3 is configured to be connected to an analog ground AGND;

[0070] The pulse signal Pulse_IN is divided by the first resistor R1 and the second resistor R2 to adjust the voltage of the pulse signal Pulse_IN; then the third resistor R3 is used to isolate the pulse signal ground GND and the analog ground AGND, eliminating the isolation chip and simplifying the acquisition circuit structure;

[0071] Furthermore, the first resistor R1 and the second resistor R2 for voltage division are selected according to the amplitude range of the input pulse signal Pulse_IN, mainly considering the resistance value and power matching. Generally, the voltage of the signal Vout_P after voltage division is less than the input voltage range allowed by the back-end precision instrumentation amplifier N1. The voltage is calculated as the voltage of the signal Vout_P = R1 * the voltage of the pulse signal Pulse_IN.

[0072] / (R1+R2);

[0073] Furthermore, the high pulse amplitude range of the pulse signal Pulse_IN is 16V to 32V, and the first resistor R1 and the second resistor R2 are 100KΩ and 20KΩ respectively. According to the formula: voltage of signal Vout_P = R1*voltage of pulse signal Pulse_IN / (R1+R2), the voltage range of signal Vout_P in high level state is 2.67V to 5.33V, which satisfies the requirement that the voltage of signal Vout_P after voltage division is less than the input voltage range of -15V to +15V allowed by the back-end precision instrumentation amplifier N1;

[0074] Furthermore, the resistance of the third resistor R3 is 1 MΩ;

[0075] The first current limiting unit includes a fifth resistor R5, a fourth resistor R4 and a fourth capacitor C4, each of which has a first end and a second end, the first end of the fifth resistor R5 is connected to the first end of the second resistor R2, the second end of the fifth resistor R5 is connected to the first end of the fourth capacitor C4, the second end of the fourth capacitor C4 is connected to the second end of the fourth resistor R4, and the first end of the fourth resistor R4 is connected to the second end of the second resistor R2;

[0076] The first filtering unit includes a second capacitor C2, the second capacitor C2 has a first end and a second end, the first end of the second capacitor C2 is connected to the second end of the fifth resistor R5, and the second end of the second capacitor C2 is configured to be connected to the analog ground AGND;

[0077] The second filtering unit includes a third capacitor C3, the third capacitor C3 has a first end and a second end, the first end of the third capacitor C3 is connected to the second end of the fourth resistor R4, and the second end of the third capacitor C3 is configured to be connected to the analog ground AGND;

[0078] The signal Vout_P and the pulse signal ground GND are respectively protected by current limiting through the fifth resistor R5 and the fourth resistor R4, the resistance values ​​of the fourth resistor R4 and the fifth resistor R5 are both 10KΩ, the second capacitor C2 and the third capacitor C3 respectively complete the common-mode filtering of the output signal Vout_P and the pulse signal ground GND after voltage division, and the fourth capacitor C4 completes the differential-mode filtering between the signal Vout_P and the pulse signal ground GND;

[0079] Preferably, the resistance of the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 is 1nf;

[0080] The differential amplifier unit includes a precision instrument amplifier N1, which has a pin RG1, a pin 2 IN-, a pin 3 IN+, a pin 4 VS-, a pin 5 REF, a pin 6 OUTPUT, a pin 7 VS+ and a pin 8 RG2; the pin 2 IN- is connected to the second end of the fourth capacitor C4, the pin 3 IN+ is connected to the first end of the fourth capacitor C4, and the pin 1 RG1 and the pin 8 RG2 are suspended;

[0081] The first decoupling unit includes a sixth capacitor C6, which has a first end and a second end, the first end of the sixth capacitor C6 is respectively connected to the 7-pin VS+ and the first external +15V power supply, and the second end of the sixth capacitor C6 is configured to be connected to the analog ground AGND;

[0082] The second decoupling unit includes a fifth capacitor C5, which has a first end and a second end, the first end of the fifth capacitor C5 is connected to the 5-pin REF, and the first end of the fifth capacitor C5 is configured to connect to the analog ground AGND, and the second end of the fifth capacitor C5 is respectively connected to the 4-pin VS- and the first external -15V power supply;

[0083] The precision instrumentation amplifier N1 realizes the conversion of the divided signal Vout_P and the pulse signal ground GND into a single-ended signal Vout1 which is shared with the analog ground AGND, and effectively filters out the common mode interference of the divided signal Vout_P and the pulse signal ground GND; the fifth capacitor C5 and the sixth capacitor C6 respectively realize the filtering of the first -15V power supply and the first +15V power supply;

[0084] Preferably, the resistance values ​​of the fifth capacitor C5 and the sixth capacitor C6 are both 0.1 μF;

[0085] Furthermore, since there is no need to amplify the divided signal Vout_P, there is no need to configure resistors at the gain resistor ends of pins 1 and 8 of the precision instrument amplifier N1, and the gain resistor ends remain in an open circuit state. According to the gain G calculation formula of the precision instrument amplifier N1, G=49.4KΩ / R gain resistor+1, and the open circuit gain resistor end is equivalent to the R gain resistor tending to infinity. Therefore, in this state, the gain G of the precision instrument amplifier N1 is ≈ 1, and there is no amplification effect. It can be considered that Vout1=Vout_P.

[0086] like Figure 3 As shown, the second current limiting unit includes a sixth resistor R6, which has a first end and a second end, and the first end of the sixth resistor R6 is connected to the 6-pin OUTPUT;

[0087] The third decoupling unit includes a seventh capacitor C7, which has a first end and a second end, the first end of the seventh capacitor C7 is connected to the second end of the sixth resistor R6, the second end of the seventh capacitor C7 is connected to the 4th pin of the operational amplifier N2A, and the second end of the seventh capacitor C7 is configured to be connected to the analog ground AGND;

[0088] Further, the pin 4 of the operational amplifier N2A is the negative power supply terminal of the operational amplifier N2A, and the resistance value of the sixth resistor R6 is 5.1KΩ;

[0089] The single-ended signal Vout1 is current-limited by the sixth resistor R6 of the second current-limiting unit, and the seventh capacitor C7 implements filtering of the negative power supply terminal of the operational amplifier N2A;

[0090] The voltage follower unit includes an operational amplifier N2A, which has pins 1, 2, 3, 4 and 8; the pin 3 of the operational amplifier N2A is connected to the second end of the sixth resistor R6;

[0091] The fourth decoupling unit includes an eighth capacitor C8, which has a first end and a second end, the first end of the eighth capacitor C8 is respectively connected to the 8th pin of the operational amplifier N2A and the second external +15V power supply, and the second end of the eighth capacitor C8 is configured to be connected to the analog ground AGND;

[0092] Further, the pin 8 of the operational amplifier N2A is the positive power supply terminal of the operational amplifier N2A;

[0093] The operational amplifier N2A completes the impedance matching of the input single-ended signal Vout1 and the single-ended signal Vout2, reduces the impact of the voltage drop of the acquisition circuit, and the single-ended signal Vout1 does not change. Therefore, Vout2=Vout1, and the line loss is negligible; the eighth capacitor C8 realizes the filtering of the positive power supply terminal of the operational amplifier N2A and the second external +15V power supply.

[0094] like Figure 4 As shown, the third current limiting unit includes a seventh resistor R7 and an eighth resistor R8, each of which has a first end and a second end, the first end of the seventh resistor R7 is configured to receive a reference signal Vref, and the first end of the eighth resistor R8 is connected to pin 1 of the operational amplifier N2A;

[0095] Further, the resistance of the seventh resistor R7 and the eighth resistor R8 is 2KΩ;

[0096] The single-ended signal Vout2 and the reference signal Vref are respectively transmitted to the operational amplifier N2A after being protected by current limiting via the eighth resistor R8 and the seventh resistor R7;

[0097] The comparison unit includes a comparator N3A, which has pins 2, 3, 4, 5 and 12; pin 4 of the comparator N3A is connected to the second end of the eighth resistor R8, pin 5 of the comparator N3A is connected to the second end of the seventh resistor R7, and pin 2 of the comparator N3A is respectively connected to the fifth input terminal of the FPGA module;

[0098] The third filtering unit includes a ninth capacitor C9, the ninth capacitor C9 has a first end and a second end, the first end of the ninth capacitor C9 is connected to the second end of the seventh resistor R7, the second end of the ninth capacitor C9 is connected to the 12th pin of the comparator N3A, and the second end of the ninth capacitor C9 is configured to be connected to the analog ground AGND;

[0099] The fifth decoupling unit includes a tenth capacitor C10, which has a first end and a second end, the first end of the tenth capacitor C10 is respectively connected to the 3rd pin of the comparator N3A and the third external +15V power supply, and the second end of the tenth capacitor C10 is configured to be connected to the analog ground AGND;

[0100] The voltage pull-up unit includes a ninth resistor R9, the ninth resistor R9 has a first end and a second end, the first end of the ninth resistor R9 is connected to the 2nd pin of the comparator N3A, and the second end of the ninth resistor R9 is connected to the external +3.3V power supply;

[0101] Further, the pin 12 of the comparator N3A is the negative power supply terminal of the comparator N3A, the pin 3 of the comparator N3A is the positive power supply terminal of the comparator N3A, and the resistance value of the ninth resistor R is 4.7KΩ;

[0102] The single-ended signal Vout2 after current limiting and the reference signal Vref are compared by the comparator N3A. The voltage range of the high-level state of the calculated signal Vout_P is 2.67V to 5.33V. Since Vout2=Vout_P, the voltage range of the high-level state of the single-ended signal Vout2 is also 2.67V to 5.33V. According to the voltage range of the single-ended signal Vout2, the reference signal Vref=2.5V is taken. When the voltage of the single-ended signal Vout2 output by the voltage follower unit is higher than the voltage of the reference signal Vref input to the third current limiting unit, the TTL level signal IO_Timer output by the comparison unit is low level, otherwise, it is high level. The comparison unit outputs the TTL level signal IO_Timer to the FPGA module for collection and counting processing; the ninth capacitor C9 completes the filtering of the reference signal Vref, and the tenth capacitor C10 realizes the filtering of the positive power supply terminal of the comparator N3A; the ninth resistor R9 is a pull-up resistor, which is used to increase the value of the high level of the output TTL level signal IO_Timer;

[0103] Furthermore, the two IO port channels IO1 and IO2 of the FPGA module simultaneously receive the TTL level signal IO_Timer output by the comparison unit, respectively complete the collection and counting of the rising edge and the falling edge, and eliminate the abnormal counts according to the frequency range of the input pulse signal Pulse_IN, thus completing the pulse signal collection function;

[0104] Furthermore, the FPGA module can be implemented by using CPU chips such as MCU and DSP to capture functions.

[0105] like Figure 1-4 As shown, specifically, the filtering unit includes a first filtering unit, a second filtering unit and a third filtering unit;

[0106] Specifically, the decoupling unit includes a first decoupling unit, a second decoupling unit, a third decoupling unit, a fourth decoupling unit and a fifth decoupling unit.

[0107] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A DC pulse signal acquisition circuit, characterized in that: include: A conversion module, the conversion module having a first input terminal, the first input terminal being configured to receive a first differential pulse signal; The conversion module is configured to convert the first differential pulse signal to obtain a second single-ended signal; A voltage follower module, wherein the voltage follower module has a second input terminal, the second input terminal is configured to receive the second single-ended signal, and the voltage follower module is configured to achieve impedance matching between the second single-ended signal and the input terminal signal of the comparison module to obtain a third single-ended signal; a comparison module, the comparison module having a third input terminal and a fourth input terminal, the third input terminal being configured to receive a fourth reference signal, the fourth input terminal being configured to receive the third single-ended signal, the comparison module being configured to compare the fourth reference signal with the third single-ended signal to obtain a fifth level signal; An FPGA module, wherein the FPGA module has a fifth input terminal and a sixth input terminal, wherein the fifth input terminal and the sixth input terminal are both configured to receive the fifth level signal, and the FPGA module is configured to calculate the number of rising edges and falling edges of the fifth level signal.

2. A DC pulse signal acquisition circuit according to claim 1, characterized in that: The conversion module includes a voltage dividing unit, a first current limiting unit and a differential amplification unit; The voltage divider unit has an input end, which is the same as the first input end and is configured to receive a first differential pulse signal; the voltage divider unit is configured to perform voltage division processing on the first differential pulse signal to obtain a first pulse voltage division signal; The first current limiting unit has an input end, and the input end of the first current limiting unit is configured to receive the first pulse voltage division signal; the first current limiting unit is configured to limit the current of the first pulse voltage division signal to obtain the first pulse voltage division signal after current limiting; The differential amplifier unit has an input end, and the input end of the differential amplifier unit is configured to receive the first pulse voltage-divided signal after current limiting; the differential amplifier unit is configured to convert the first pulse voltage-divided signal after current limiting to obtain a second single-ended signal.

3. A DC pulse signal acquisition circuit according to claim 2, characterized in that: The voltage following module includes a second current limiting unit and a voltage following unit; The second current limiting unit has an input end, the input end of the second current limiting unit is the same as the second input end, and is configured to receive the second single-ended signal; the second current limiting unit is configured to process the second single-ended signal by current limiting to obtain a second single-ended signal after current limiting; The voltage follower unit has an input end, and the input end of the voltage follower unit is configured to receive the second single-ended signal after current limiting; the voltage follower unit is configured to achieve impedance matching between the second single-ended signal after current limiting and the input end signal of the comparison module to obtain a third single-ended signal.

4. A DC pulse signal acquisition circuit according to claim 3, characterized in that: The comparison module includes a third current limiting unit and a comparison unit; The third current limiting unit has two input terminals, namely the third input terminal and the fourth input terminal, the third input terminal is configured to receive the fourth reference signal, and the fourth input terminal is configured to receive the third single-ended signal; the third current limiting unit is configured to perform current limiting processing on the third single-ended signal and the fourth reference signal to obtain the third single-ended signal after current limiting and the fourth reference signal after current limiting; The comparison unit has two input ends, and the two input ends of the comparison unit are respectively configured to receive the third single-ended signal and the fourth reference signal after current limiting; the comparison unit is configured to compare the fourth reference signal after current limiting with the third single-ended signal after current limiting to obtain a fifth level signal.

5. A DC pulse signal acquisition circuit according to claim 4, characterized in that: Also includes: An isolation unit, configured to isolate a pulse signal ground GND of the voltage divider unit from an analog ground AGND of the isolation unit; A filter unit configured to filter out common mode interference of an output signal; a decoupling unit configured to perform filtering of a connected power source; A voltage pull-up unit configured to increase the level and improve the noise margin of the signal and enhance the anti-interference capability.

6. A DC pulse signal acquisition circuit according to claim 5, characterized in that: The voltage dividing unit includes a first resistor R1 and a second resistor R2 connected in series in sequence, the first resistor R1 having a first end and a second end, the first end of the first resistor R1 being configured to receive the first differential pulse signal, the second resistor R2 having a first end and a second end, the first end and the second end of the second resistor R2 being respectively connected to two ends of the first capacitor C1, the first end of the second resistor R2 being connected to the second end of the first resistor R1, and the second end of the second resistor R2 being configured to be connected to a pulse signal ground GND; The first current limiting unit includes a fifth resistor R5, a fourth resistor R4 and a fourth capacitor C4, each of which has a first end and a second end, the first end of the fifth resistor R5 is connected to the first end of the second resistor R2, the second end of the fifth resistor R5 is connected to the first end of the fourth capacitor C4, the second end of the fourth capacitor C4 is connected to the second end of the fourth resistor R4, and the first end of the fourth resistor R4 is connected to the second end of the second resistor R2; The differential amplifier unit includes a precision instrument amplifier N1, which has pin 1 RG1, pin 2 IN-, pin 3 IN+, pin 4 VS-, pin 5 REF, pin 6 OUTPUT, pin 7 VS+ and pin 8 RG2; the pin 2 IN- is connected to the second end of the fourth capacitor C4, the pin 3 IN+ is connected to the first end of the fourth capacitor C4, and the pin 1 RG1 and the pin 8 RG2 are set to be suspended.

7. A DC pulse signal acquisition circuit according to claim 6, characterized in that: The second current limiting unit includes a sixth resistor R6 having a first end and a second end, and the first end of the sixth resistor R6 is connected to the 6-pin OUTPUT; The voltage follower unit includes an operational amplifier N2A, which has pins 1, 2, 3, 4 and 8; the pin 3 of the operational amplifier N2A is connected to the second end of the sixth resistor R6.

8. A DC pulse signal acquisition circuit according to claim 7, characterized in that: The third current limiting unit includes a seventh resistor R7 and an eighth resistor R8, each of which has a first end and a second end, the first end of the seventh resistor R7 is configured to receive a fourth reference signal, and the first end of the eighth resistor R8 is connected to pin 1 of the operational amplifier N2A; The comparison unit includes a comparator N3A, which has pins 2, 3, 4, 5 and 12; pin 4 of the comparator N3A is connected to the second end of the eighth resistor R8, pin 5 of the comparator N3A is connected to the second end of the seventh resistor R7, and pin 2 of the comparator N3A is respectively connected to the fifth input terminal of the FPGA module.

9. A DC pulse signal acquisition circuit according to claim 8, characterized in that: The isolation unit includes a third resistor R3 having a first end and a second end, the first end of the third resistor R3 is connected to the second end of the second resistor R2, and the second end of the third resistor R3 is configured to be connected to an analog ground AGND; The filtering unit includes a first filtering unit, a second filtering unit and a third filtering unit; the first filtering unit includes a second capacitor C2, the second capacitor C2 has a first end and a second end, the first end of the second capacitor C2 is connected to the second end of the fifth resistor R5, and the second end of the second capacitor C2 is configured to connect to the analog ground AGND; the second filtering unit includes a third capacitor C3, the third capacitor C3 has a first end and a second end, the first end of the third capacitor C3 is connected to the second end of the fourth resistor R4, and the second end of the third capacitor C3 is configured to connect to the analog ground AGND; the third filtering unit includes a ninth capacitor C9, the ninth capacitor C9 has a first end and a second end, the first end of the ninth capacitor C9 is connected to the second end of the seventh resistor R7, the second end of the ninth capacitor C9 is connected to the 12th pin of the comparator N3A, and the second end of the ninth capacitor C9 is configured to connect to the analog ground AGND; The decoupling unit includes a first decoupling unit, a second decoupling unit, a third decoupling unit, a fourth decoupling unit and a fifth decoupling unit. The first decoupling unit includes a sixth capacitor C6, which has a first end and a second end. The first end of the sixth capacitor C6 is respectively connected to the 7-pin VS+ and the first external +15V power supply, and the second end of the sixth capacitor C6 is configured to connect to the analog ground AGND; the second decoupling unit includes a fifth capacitor C5, which has a first end and a second end. The first end of the fifth capacitor C5 is connected to the 5-pin REF, and the first end of the fifth capacitor C5 is configured to connect to the analog ground AGND, and the second end of the fifth capacitor C5 is respectively connected to the 4-pin VS- and the first external -15V power supply; the third decoupling unit includes a seventh capacitor C7, which has a first end and a second end. The first end of the seventh capacitor C7 is connected to the second end of the sixth resistor R6, the second end of the seventh capacitor C7 is connected to the 4th pin of the operational amplifier N2A, and the second end of the seventh capacitor C7 is configured to connect to the analog ground AGND; the fourth decoupling unit includes an eighth capacitor C8, which has a first end and a second end, the first end of the eighth capacitor C8 is respectively connected to the 8th pin of the operational amplifier N2A and the second external +15V power supply, and the second end of the eighth capacitor C8 is configured to connect to the analog ground AGND; the fifth decoupling unit includes a tenth capacitor C10, which has a first end and a second end, the first end of the tenth capacitor C10 is respectively connected to the 3rd pin of the comparator N3A and the third external +15V power supply, and the second end of the tenth capacitor C10 is configured to connect to the analog ground AGND; The voltage pull-up unit includes a ninth resistor R9, which has a first end and a second end. The first end of the ninth resistor R9 is connected to pin 2 of the comparator N3A, and the second end of the ninth resistor R9 is connected to an external +3.3V power supply.

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