Test device and test equipment

Abstract

The present application discloses a test device and test equipment that can simplify test operations and improve test efficiency. Specifically, a test device is provided, comprising an interface circuit, a test circuit, and a test interface, wherein the interface circuit, the test circuit, and the test interface are coupled. The test interface is used to connect to a device under test. The test interface is used to receive a test signal from the device under test, the test circuit is used to determine a test result for the device under test based on the test signal, and the interface circuit is used to transmit the test result.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic technology, and in particular to a testing device and testing equipment. Background Art

[0002] With the development of high-speed signal technology, many types of high-speed signals have emerged, such as high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIE) signals, serial attached small computer system interface (SAS) signals, and serial advanced technology attachment (SATA) signals. With the continuous development of high-speed signals, the challenges of high-speed signal link design are increasing, and high-speed signal testing is becoming increasingly important.

[0003] For example, a server motherboard is equipped with a processor and a high-speed serial computer expansion bus slot that are coupled to each other. The link between the processor and the high-speed serial computer expansion bus slot is used to transmit high-speed signals, which require eye diagram and bit error rate testing. However, current testing methods are complex and inefficient. Summary of the Invention

[0004] The embodiments of the present application provide a testing device and a testing apparatus, which can simplify testing operations and improve testing efficiency.

[0005] To achieve the above objectives, the present invention adopts the following technical solutions:

[0006] In a first aspect of an embodiment of the present application, a test device is provided. The test device includes an interface circuit, a test circuit, and a test interface, wherein the interface circuit, the test circuit, and the test interface are coupled. The test interface is configured to connect to a device under test. The test interface is configured to receive a test signal from the device under test, the test circuit is configured to determine a test result for the device under test based on the test signal, and the interface circuit is configured to transmit the test result.

[0007] The test device provided in the embodiment of the present application includes a test circuit and a test interface. The test interface is used to interface with the device to be tested and receive a test signal from the device to be tested via the test interface. The test circuit is used to generate a test result based on the test signal. The test device has a simple structure and a simple testing method. Compared with using an expensive oscilloscope or bit error meter to test and generate test results, the test cost is reduced. At the same time, compared with using an oscilloscope or bit error meter for testing, the test device of this embodiment is directly connected to the device to be tested, and does not need to be connected to the oscilloscope or bit error meter through a coaxial cable connector, nor does it need to change the connection position of the coaxial cable connector multiple times. Therefore, it can simplify the test operation and improve the test efficiency.

[0008] In combination with the first aspect, in a possible implementation, the above-mentioned test signal is a first test code type, and the above-mentioned test result includes eye diagram data and / or eye diagram test conclusion, and the eye diagram test conclusion is used to indicate whether the eye diagram data meets the preset eye diagram test indicators.

[0009] The test device provided in the embodiment of the present application receives a test signal from the device to be tested through a test interface, and generates eye diagram data and / or eye diagram test conclusions through a test circuit. Compared with testing using an oscilloscope, the test device of this embodiment is directly connected to the device to be tested, and does not need to be connected to the oscilloscope through a coaxial cable connector, nor does it need to change the connection position of the coaxial cable connector multiple times. Therefore, it can simplify the test operation, improve the test efficiency, and reduce the test cost.

[0010] In conjunction with the first aspect, in one possible implementation, when the test result is eye diagram data, the test circuit is specifically configured to obtain a synchronization clock signal based on a first test pattern, determine waveform data for multiple clock cycles based on the first test pattern and the synchronization clock signal, and determine eye diagram data based on the waveform data for the multiple clock cycles. Alternatively, when the test result is an eye diagram test conclusion, the test circuit is further configured to determine the eye diagram test conclusion based on the eye diagram data and preset eye diagram test indicators.

[0011] The test device provided in the embodiment of the present application receives a first test code pattern from the device to be tested through a test interface, and generates eye diagram data and / or eye diagram test conclusions through a test circuit. Compared with testing using an oscilloscope, the test device of this embodiment is directly connected to the device to be tested, does not need to be connected to the oscilloscope through a coaxial cable connector, and does not need to change the connection position of the coaxial cable connector multiple times. This can simplify test operations, improve test efficiency, and reduce test costs.

[0012] In conjunction with the first aspect, in one possible implementation, the test signal is a second test pattern, and the test result is bit error information. The interface circuit is further configured to receive a control signal, the test circuit is further configured to generate a third test pattern based on the control signal, and the test interface is further configured to send the third test pattern to the device under test, wherein the second test pattern is obtained by the device under test by converting the third test pattern.

[0013] The test device provided in the embodiment of the present application receives a second test code pattern from the device to be tested through a test interface, and generates bit error information based on the second test code pattern and the third test code pattern through a test circuit. Compared with testing using a bit error meter, the test device of this embodiment is directly connected to the device to be tested, and does not need to be connected to the bit error meter through a coaxial cable connector, nor does it need to change the connection position of the coaxial cable connector multiple times. This can simplify test operations, improve test efficiency, and reduce test costs.

[0014] In combination with the first aspect, in one possible implementation, the above-mentioned test circuit is specifically used to compare the second test code type and the third test code type bit by bit, determine the number of error bits of the second test code type, and determine the error information based on the ratio of the number of error bits to the total number of bits of the third test code type.

[0015] The test device provided in the embodiment of the present application receives a second test code pattern from the device to be tested through a test interface, and generates bit error information based on the second test code pattern and the third test code pattern through a test circuit. Compared with testing using a bit error meter, the test device of this embodiment is directly connected to the device to be tested, and does not need to be connected to the bit error meter through a coaxial cable connector, nor does it need to change the connection position of the coaxial cable connector multiple times. This can simplify test operations, improve test efficiency, and reduce test costs.

[0016] In combination with the first aspect, in a possible implementation, the test circuit includes a test chip, one end of the test chip is coupled to the test interface, and the other end of the test chip is coupled to the interface circuit.

[0017] The test device provided in the embodiments of the present application generates test results based on test signals using a test chip, eliminating the need for expensive oscilloscopes and bit error meters to generate test results, thereby reducing testing costs. Furthermore, compared to testing using an oscilloscope or bit error meter, the test device of this embodiment is directly connected to the device under test, eliminating the need for connection to the oscilloscope or bit error meter via a coaxial cable connector, nor does it require frequent changes in the connection position of the coaxial cable connector. This simplifies testing operations and improves testing efficiency.

[0018] In combination with the first aspect, in a possible implementation, the test chip includes a high-speed clock data recovery chip, a signal driver chip, or a selection chip.

[0019] In combination with the first aspect, in a possible implementation, the test circuit further includes a clock circuit and a reset circuit, and the clock circuit and the reset circuit are respectively coupled to the test chip.

[0020] The test device provided in the embodiment of the present application uses a clock circuit to provide a clock to the test chip, and uses a reset circuit to restore the test chip to its initial state when the test of each channel in the device to be tested is completed. As a result, the test device can complete the test of all channels in the device to be tested without the need for expensive oscilloscopes and bit error meters to generate test results, thereby reducing testing costs. Furthermore, compared to testing using an oscilloscope or bit error meter, the test device of this embodiment is directly connected to the device to be tested, eliminating the need for connecting to the oscilloscope or bit error meter via a coaxial cable connector or repeatedly changing the connection position of the coaxial cable connector. This simplifies testing operations and improves testing efficiency.

[0021] In combination with the first aspect, in a possible implementation, the testing device further includes a power supply circuit, an input end of the power supply circuit is coupled to the test interface, and an output end of the power supply circuit is coupled to the interface circuit and the test circuit.

[0022] The test device provided in the embodiment of the present application processes the power supply voltage received by the test interface through the power supply circuit, thereby being able to provide a stable power supply voltage for the interface circuit and the test circuit.

[0023] In combination with the first aspect, in one possible implementation, the above-mentioned test interface includes a high-speed serial computer expansion bus interface, a serial small computer system interface, a serial advanced technology attachment interface, a card electromechanical interface, a non-volatile memory standard interface or an open core protocol interface.

[0024] The test device provided in the embodiment of the present application can support the test device to test high-speed signals such as high-speed serial computer expansion bus signals, serial connection small computer system interface signals, serial advanced technology attachment signals, and universal serial bus signals by setting different types of test interfaces according to the type of slots in the device to be tested.

[0025] In combination with the first aspect, in a possible implementation, the interface circuit includes an Ethernet interface circuit, a serial communication interface circuit, a universal serial bus interface circuit, or a wireless interface circuit.

[0026] The test device provided in the embodiment of the present application can support different types of control devices by setting the interface circuit to multiple types of interface circuits. For example, the control device can be a personal computer, a tablet computer, a mobile phone, etc.

[0027] In a second aspect of an embodiment of the present application, a test device is provided. The test device is used to test a device to be tested. The test device includes a control device and a test device. One end of the control device is coupled to the test device, and the other end of the control device is used to connect to the device to be tested. The structure of the test device is the structure of the test device described in the first aspect or any possible implementation of the first aspect. The control device is used to send a control signal to the device to be tested, and the test device is used to receive a test signal sent by the device to be tested in response to the control signal, and determine a test result for the device to be tested based on the test signal. The control device is also used to receive the test result.

[0028] The description of the second aspect in this application can refer to the detailed description of the first aspect; and the beneficial effects of the second aspect can refer to the analysis of the beneficial effects of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a structural schematic diagram of a test fixture;

[0030] Figure 2 It is a schematic diagram of an eye diagram curve;

[0031] Figure 3 It is a structural schematic diagram of an eye diagram test circuit;

[0032] Figure 4 It is a structural diagram of a bit error test circuit;

[0033] Figure 5 A schematic diagram of an application scenario of a test device provided in an embodiment of the present application;

[0034] Figure 6 A schematic diagram of another application scenario of the test device provided in an embodiment of the present application;

[0035] Figure 7 A schematic diagram of the structure of a testing device provided in an embodiment of the present application;

[0036] Figure 8 A schematic diagram of an application scenario of a test device provided in an embodiment of the present application;

[0037] Figure 9 A schematic diagram of the structure of a test device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The following sections discuss the making and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided herein can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to implement and use this description and technology and do not limit the scope of this application.

[0039] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0040] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when a specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuitry that performs an operation, etc.

[0041] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be single or multiple. In addition, in the embodiments of the present application, words such as "first" and "second" do not limit the quantity and order.

[0042] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0043] Before introducing the embodiments of the present application, the background technology involved in the present application is first introduced.

[0044] With the continuous development of high-speed signals, the challenges of high-speed signal link design are becoming increasingly greater, and high-speed signal testing is becoming increasingly important. Currently, high-speed signal tests are generally performed using oscilloscopes, bit error meters, and test fixtures, such as eye diagram tests and bit error tests.

[0045] The test fixture is used to provide a test interface to complete high-speed signal testing when the measuring instrument (oscilloscope or bit error tester) cannot be directly coupled to the device to be tested.

[0046] For example, Figure 1 FIG. 1 shows a test fixture 100 including multiple test interfaces 110 and a high-speed serial computer expansion bus interface 120. The high-speed serial computer expansion bus interface 120, also known as a gold finger, is used to couple with a high-speed serial computer expansion bus slot in a device under test. The multiple test interfaces 110 correspond to multiple channels in the high-speed serial computer expansion bus slot and provide a test interface for an oscilloscope or a bit error tester.

[0047] Specifically, the eye diagram test circuit may include an oscilloscope and a test fixture. The oscilloscope may receive a high-speed signal from the device to be tested through the test fixture to generate an eye diagram. Figure 2 The eye diagram shown can be used to analyze the duty cycle, noise, and jitter of high-speed signals. A bit error test circuit can include a bit error tester and a test fixture. The bit error tester can send and receive high-speed signals to or from the device under test through the test fixture. The bit error rate can be calculated based on the errors in the transmitted and received high-speed signals. To ensure stable and repeatable testing, a test pattern is generally used as the high-speed signal for the above-mentioned eye diagram or bit error test.

[0048] For example, Figure 3FIG3 shows a block diagram of an eye diagram test circuit 300, which includes a motherboard 310, a test fixture 320, an oscilloscope 330, and a personal computer (PC) 340. Motherboard 310 is the device to be tested and includes a processor 311 and a high-speed serial computer expansion bus slot 312, which are coupled to each other. Test fixture 320 includes multiple test interfaces 321 and a high-speed serial computer expansion bus interface 322. Personal computer 340 can be coupled to processor 311 in motherboard 310 via a network cable. Personal computer 340 can also be coupled to oscilloscope 330 via a network cable. Oscilloscope 330 is coupled to a test interface 321 in test fixture 320 via a coaxial cable connector 350 (also known as an SMP connector). High-speed serial computer expansion bus interface 322 is coupled to high-speed serial computer expansion bus slot 312. The personal computer 340 is used to generate a control signal, the processor 311 generates a test pattern based on the control signal, and the oscilloscope 330 receives the test pattern through the coaxial cable connector 350 and generates an eye diagram based on the test pattern. The personal computer 340 can then analyze the duty cycle, noise, and jitter of the high-speed signal based on the eye diagram to determine the quality of the transmission (transport x, TX) link between the processor 311 and the oscilloscope 330.

[0049] For another example, Figure 3 The oscilloscope 330 in the embodiment is replaced with the bit error meter 360, and the structure is as follows: Figure 4 The structure of the bit error test circuit 400 is shown. A personal computer 340 can be coupled to a bit error tester 360, which is coupled to two test interfaces 321 in the test fixture 320 via coaxial cable connectors 350 and 370, respectively. The personal computer 340 is configured to generate a control signal, and the bit error tester 360 is configured to generate a first test pattern based on the control signal. The first test pattern is transmitted to the processor 311 via the coaxial cable connector 350. The processor 311 generates a second test pattern based on the first test pattern, and the second test pattern is transmitted to the bit error tester 360 via the coaxial cable connector 370. The bit error tester 360 determines the bit error rate (BER) of the high-speed signal transmitted in the loop between the bit error tester 360 and the processor 311 based on the first and second test patterns. The personal computer 340 can then determine the quality of the receive (RX) link between the bit error tester 360 and the processor 311 based on the BER error rate.

[0050] However, since the link between the processor 311 and the high-speed serial computer expansion bus slot 312 includes multiple channels, and the number of channels of the oscilloscope 330 and the bit error meter 360 is limited, it is necessary to change the connection position of the coaxial cable connector to connect different test interfaces 321 in the test fixture 320 to complete the eye diagram test or bit error test of the above multiple channels. The operation is relatively complicated and the test efficiency is low. Figure 3 and Figure 4 As can be understood, eye diagram testing and bit error testing require different test circuits. Simultaneously performing both eye diagram and bit error testing on multiple channels between processor 311 and high-speed serial computer expansion bus slot 312 requires changing the test circuit structure, making the operation complex, inefficient, and requiring high test operator skills. Furthermore, the oscilloscope 330, bit error meter 360, and test fixture 320 used for high-speed signal testing are expensive, leading to high testing costs.

[0051] In summary, the above Figure 3 or Figure 4 The test circuit shown is complex to operate when testing high-speed signals, has low test efficiency, requires high tester skills, and has high test costs. Therefore, the present application provides a test device that can improve test efficiency and is easy to operate.

[0052] Figure 5 A schematic diagram of an application scenario of a test device 500 provided in an embodiment of the present application, wherein the test device 500 is used to test a signal in a device to be tested 600, and the test device 500 may include an interface circuit 510, a test circuit 520 and a test interface 530, wherein the interface circuit 510, the test circuit 520 and the test interface 530 are coupled.

[0053] In one possible embodiment, Figure 5 As shown, the test device 500 may include an interface circuit 510, a test circuit 520, and a test interface 530 that are coupled in sequence. In other embodiments, the interface circuit 510, the test circuit 520, and the test interface 530 may be coupled in pairs.

[0054] It should be noted that the above Figure 5 The structure of the testing device 500 is for illustrative purposes only and does not limit the embodiments of the present application.

[0055] The test interface 530 is used to receive a test signal from the device under test 600. The test circuit 520 is used to determine a test result of the device under test 600 based on the test signal. The interface circuit 510 is used to send the test result.

[0056] Optionally, the device under test 600 may include a server or a storage device, and the embodiment of the present application does not limit the specific type of the device under test 600. For example, the device under test 600 may be a solid state drive.

[0057] The test device 500 provided in the embodiment of the present application has a simple structure and includes a test circuit 520 and a test interface 530. The test interface 530 is used to interface with the device to be tested 600 and receive a test signal from the device to be tested 600 via the test interface 530. The test circuit 520 is used to generate a test result based on the test signal. The test device 500 has a simple structure and a simple testing method. Compared with using expensive oscilloscopes and bit error meters to test and generate test results, the test cost is reduced and the test efficiency is improved. At the same time, compared with using an oscilloscope or bit error meter for testing, the test device of this embodiment is directly connected to the device to be tested, and does not need to be connected to the oscilloscope or bit error meter through a coaxial cable connector, nor does it need to change the connection position of the coaxial cable connector multiple times. Therefore, it can simplify the test operation and improve the test efficiency.

[0058] Optionally, the test device 500 provided in the embodiment of the present application can be used for high-speed signal testing, or it can be used for low-speed signal testing. The embodiment of the present application does not limit whether the test device 500 is used for high-speed signal testing or low-speed signal testing. The following embodiment uses the test device 500 for high-speed signal testing as an example for illustrative description.

[0059] For example, when the test device 500 is used for high-speed signal testing, the device to be tested 600 may include a slot 610 and a processor 620 coupled to each other, wherein the slot 610 is coupled to the test interface 530, and the test device 500 is used to perform a high-speed signal test on the link between the slot 610 and the processor 620. The slot 610 is a high-speed signal slot.

[0060] Optionally, the above-mentioned test signal can be a test code pattern, which can be used to perform stable and repeatable testing. The test code pattern can include one of the following: pseudo-random binary sequence (PRBS) 31, PRBS7, PRBS9, PRBS11, PRBS15, PRBS20 and PRBS23.

[0061] Optionally, the test device 500 provided in the embodiment of the present application can be used for eye diagram testing, generating an eye diagram and / or an eye diagram test conclusion to determine whether the quality of the transmission link between the processor 620 and the test circuit 520 is qualified. Alternatively, the test device 500 can be used for bit error testing, determining the bit error rate to determine whether the quality of the reception link between the processor 620 and the test circuit 520 is qualified.

[0062] In one possible embodiment, Figure 5 As shown, when the test device 500 is used for eye diagram testing, the above-mentioned test signal can be a first test code type, and the above-mentioned test results include eye diagram data (or can be called an electronic eye diagram) and / or eye diagram test conclusions, and the eye diagram test conclusions are used to indicate whether the eye diagram data meets the preset eye diagram test indicators.

[0063] Optionally, when the test result is eye diagram data, the test circuit 520 is specifically configured to obtain a synchronous clock signal based on the first test pattern, determine waveform data for multiple clock cycles based on the first test pattern and the synchronous clock signal, and determine eye diagram data based on the waveform data for the multiple clock cycles. When the test result is an eye diagram test conclusion, the test circuit 520 is further configured to determine the eye diagram test conclusion based on the eye diagram data and preset eye diagram test indicators.

[0064] It will be appreciated that when the test result is eye diagram data, the control device 700 can receive the eye diagram data sent by the test device 500, analyze and process the eye diagram data to generate an eye diagram test conclusion, and display the eye diagram test conclusion. When the test result is an eye diagram test conclusion, the control device 700 can receive the eye diagram test conclusion without further analysis and processing, and can directly display the eye diagram test conclusion.

[0065] For example, the link between the slot 610 and the processor 620 may include multiple channels, and the slot 610 and the test interface 530 may include the same number of channels. When the test result is eye diagram data, the processor 620 in the device under test 600 may receive a first control signal, generate a first test pattern based on the first control signal, and send the first test pattern through any one of the multiple channels of the slot 610. The test circuit 520 may receive the first test pattern through the corresponding channel in the test interface 530, determine eye diagram data based on the first test pattern, and send the eye diagram data through the interface circuit 510. It will be understood that by receiving different control signals multiple times and generating corresponding test patterns, the processor 620 can complete the eye diagram test of all channels between the slot 610 and the test interface 530.

[0066] When the test result is an eye diagram test conclusion, the test circuit 520 may store preset eye diagram test indicators. The test circuit 520 may determine the eye diagram test conclusion based on the above eye diagram data and the preset eye diagram test indicators, and send the above eye diagram data and / or eye diagram test conclusion through the interface circuit 510.

[0067] It can be understood that when the test device 500 provided in the embodiment of the present application performs an eye diagram test, it receives the test signal generated by the processor 620 through the test interface 530, and the test interface 530 includes multiple channels corresponding to the slot 610. Therefore, during the eye diagram test, the test pattern sent by the processor 620 through different channels can be received by the test circuit 520 through the corresponding channel in the test interface 530, thereby completing the eye diagram test of all channels between the slot 610 and the processor 620 without having to change the connection position of the coaxial cable connector multiple times. Therefore, the operation is simple, the test efficiency can be improved, and the expensive oscilloscope 330 and test fixture 320 are not required, which can reduce costs.

[0068] In another possible embodiment, Figure 6 As shown, when the test device 500 is used for bit error testing, the above-mentioned test signal is the second test code type, the above-mentioned test result is the bit error information (or called bit error rate), the interface circuit 510 is also used to receive the second control signal, the test circuit 520 is used to generate a third test code type according to the second control signal, and the test interface 530 is also used to send the third test code type to the device to be tested 600. The second test code type is sent by the device to be tested 600 based on the received third test code type.

[0069] When the test result is error information, the test circuit 520 is specifically used to compare the second test code type and the third test code type bit by bit, determine the number of error bits in the second test code type, and determine the error information based on the ratio of the number of error bits to the total number of bits of the third test code type, so as to judge whether the quality of the receiving link between the processor 620 and the test circuit 520 is qualified.

[0070] For example, the link between the slot 610 and the processor 620 may include multiple channels, and the slot 610 and the test interface 530 may include the same number of channels. The test circuit 520 in the test device 500 may receive the second control signal, generate a third test pattern based on the second control signal, and send the third test pattern through any channel in the test interface 530. The processor 620 in the device to be tested 600 may receive the third test pattern through the corresponding channel in the slot 610, generate a second test pattern based on the third test pattern, and send the second test pattern through another channel in the slot 610. The test circuit 520 may receive the second test pattern through the corresponding channel in the test interface 530, compare the second test pattern with the third test pattern bit by bit, determine the number of bits of error in the second test pattern, determine error information based on the ratio of the number of bits of error to the total number of bits of the third test pattern, and send the error information through the interface circuit 510. The test circuit 520 generates corresponding test patterns by receiving different control signals multiple times, thereby completing the error code test of all channels between the slot 610 and the test interface 530 .

[0071] It is understandable that when the test device 500 provided in the embodiment of the present application performs a bit error test, the test circuit 520 sends the third test pattern through the test interface 530 and receives the second test pattern generated by the processor 620 through the test interface 530, wherein the test interface 530 includes multiple channels corresponding to the slot 610. Therefore, during the bit error test, the test circuit 520 can send the test pattern to the processor 620 or receive the test pattern generated by the processor 620 through different channels in the test interface 530, thereby completing the bit error test of all channels between the slot 610 and the processor 620 without having to change the connection position of the coaxial cable connector multiple times. Therefore, the operation is simple, the test efficiency can be improved, and the expensive bit error meter 360 and test fixture 320 are not required, which can reduce costs.

[0072] Optional, such as Figure 5 and Figure 6 As shown, the first control signal and the second control signal can be generated by the control device 700. The control device 700 can also be used to receive the eye diagram data and / or eye diagram test conclusion, generate and display the eye diagram and / or eye diagram test conclusion, or receive the bit error data and display the bit error rate. The control device can be an electronic device, such as a personal computer, tablet computer, mobile phone, etc.

[0073] Exemplarily, when the test device 500 is used to perform an eye diagram test on a high-speed signal in the device to be tested 600, the control device 700 can be coupled to the processor 620 and the interface circuit 510 in the device to be tested 600. The control device 700 can be used to generate the first control signal, receive the eye diagram data, generate and display the eye diagram, and further, the control device 700 can store preset eye diagram test indicators. The control device 700 can determine the eye diagram test conclusion based on the eye diagram and the preset eye diagram test indicators. Alternatively, the control device 700 can be used to receive the eye diagram test conclusion and display the eye diagram test conclusion. Alternatively, the control device 700 can be used to receive the eye diagram data and the eye diagram test conclusion, generate and display the eye diagram and the eye diagram test conclusion. When the test device 500 is used to perform a bit error test on a high-speed signal in the device to be tested 600, the control device 700 can be coupled to the interface circuit 510 of the test device 500. The control device 700 can be used to generate the second control signal, receive the bit error information and display the bit error rate.

[0074] Optionally, the control device 700 may include control software, which is used to start, pause, stop testing, collect, analyze test data, and output a test report. For example, the control software can be used to generate control signals such as the above-mentioned first control signal and the second control signal. Specifically. The test operator can select the test to be performed by clicking the virtual button in the control software. For example, the operator can select an eye diagram test, or can select an error code test to control the test device 500 and the device to be tested 600 to execute corresponding instructions to complete test contents such as eye diagram testing or error code testing, receive the test results sent by the test device 500, analyze the test results and generate a test report, thereby completing the test of the device to be tested 600. Furthermore, the tester can also perform parameter deviation and parameter optimization based on the test report generated by the control software, thereby improving the test efficiency.

[0075] Optionally, the interface circuit 510 may be an Ethernet interface circuit, a serial communication interface circuit, a universal serial bus (USB) interface circuit, or a wireless interface circuit. The embodiment of the present application does not limit the specific type of the interface circuit 510 .

[0076] It can be understood that when the interface circuit 510 is a wireless interface circuit, the interface circuit 510 and the control device 700 do not need to be connected wirelessly through a wired connection. Compared with a wired connection, the positions of the control device 700 and the test device 500 are not restricted by cables and are more flexible, and it is more convenient to establish communication between the control device 700 and the test device 500.

[0077] For example, when the interface circuit 510 is an Ethernet interface circuit, the interface circuit 510 may include an Ethernet interface and an Ethernet interface chip; when the interface circuit 510 is a serial communication interface circuit, the interface circuit 510 may include a serial communication interface and a serial communication interface chip; when the interface circuit 510 is a universal serial bus interface circuit, the interface circuit 510 may include a universal serial bus interface and a universal serial bus interface chip; when the interface circuit 510 is a wireless interface circuit, the interface circuit 510 may include a wireless chip.

[0078] For example, when the interface circuit 510 includes an Ethernet interface and an Ethernet interface chip, the Ethernet interface can be a RJ-45 (registered jack 45) interface or an RJ-11 (registered jack 11) interface, and the Ethernet interface chip can be a physical layer (PHY) chip. When the interface circuit 510 includes a serial communication interface and a serial communication chip, the serial communication interface chip can be an RS232 (Recommended Standard 232) serial port chip, where the serial communication interface can be simply referred to as a serial port. When the interface circuit 510 includes a universal serial bus (USB) interface and a USB interface chip, the USB interface can be a USB 2.0 interface or a USB 3.0 interface, and the USB interface chip can be a USB 2.0 interface chip or a USB 3.0 interface chip. When the interface circuit 510 includes a wireless interface chip, the wireless interface chip may be a Bluetooth chip, a wireless fidelity (WIFi) chip, or a Zigbee chip. Figure 5 and Figure 6 In the figure, the interface circuit 510 is a serial communication interface circuit, and the serial communication interface circuit includes a serial port 511 and an RS232 serial port chip 512 as an example for illustration.

[0079] Optional, such as Figure 5 and Figure 6 As shown, the above-mentioned test circuit 520 may include a test chip 521, one end of the test chip 521 is coupled to the interface circuit 510, and the other end of the test chip 521 is coupled to the test interface 530. The test chip 521 is used to determine the test result of the device to be tested 600 according to the test signal.

[0080] Optionally, the test chip 521 includes one of the following: a high-speed clock and data recovery (CDR) chip, a signal driver (retimer) chip, and a switch chip. The embodiment of the present application does not limit the specific type of the test chip 521.

[0081] Optional, such as Figure 5 and Figure 6 As shown, the test circuit 520 may further include a clock circuit 522 and a reset circuit 523, each of which is coupled to the test chip 521. The clock circuit 522 is used to provide a clock for the test chip 521, and the reset circuit 523 is used to restore the test chip 521 to its initial state after testing of each channel in the device under test is completed. This allows the test device 500 to complete testing of all channels in the device under test 600.

[0082] Optionally, the test interface 530 (or referred to as a gold finger) is related to the type of the slot 610 in the device to be tested 600. The test interface 530 can be designed as a different type of interface according to the type of the slot 610. The test interface 530 can include one of the following: a high-speed serial computer expansion bus interface, a serial connection small computer system interface, a serial advanced technology attachment interface, a card electromechanical (CEM) interface, a non-volatile memory express (NVME) interface, and an open core protocol (OCP) interface. This allows the test device 500 to test high-speed signals such as high-speed serial computer expansion bus signals, serial connection small computer system interface signals, serial advanced technology attachment signals, and universal serial bus signals.

[0083] Exemplarily, when the slot 610 is a high-speed serial computer expansion bus slot, the test interface 530 may be a high-speed serial computer expansion bus interface.

[0084] Optionally, when the test interface 530 is a high-speed serial computer expansion bus interface, the high-speed serial computer expansion bus interface may include 16 channels, 8 channels, 4 channels or 1 channel, or may include more channels. The embodiment of the present application does not limit the specific number of channels included in the high-speed serial computer expansion bus interface.

[0085] Optionally, the test device 500 provided in the embodiment of the present application can be set to different forms according to the type of test interface, so that it can be more conveniently used to test the device to be tested 600. The form of the test device 500 may include one of the following: a high-speed serial computer expansion bus board, an interface and open core protocol board, a 2.5-inch hard drive, a 3.5-inch hard drive or a USB flash drive, etc.

[0086] The test device 500 provided in the embodiment of the present application receives a test signal sent by the device under test 600 via a test interface 530, or receives a test signal sent by the device under test 600 via the test interface 530. The test interface 530 includes multiple channels corresponding to the slots 610 in the device under test 600. Therefore, during the test process, there is no need to repeatedly change the structure of the test circuit. The test circuit 520 can receive a test signal sent by any of the multiple channels and determine the test result of the device under test 600 based on the test signal. Therefore, the test process is simple to operate, which can improve test efficiency. At the same time, there is no need to use an expensive oscilloscope 330, bit error meter 360, and test fixture 320, which can reduce costs.

[0087] In one possible embodiment, Figure 7 As shown, the test device 500 may further include a power supply circuit 540 , an input end of the power supply circuit 540 is coupled to the test interface 530 , and an output end of the power supply circuit 540 is coupled to the interface circuit 510 and the test interface 530 .

[0088] It should be noted that the above Figure 7 The structure of the testing device 500 is for illustrative purposes only and does not limit the embodiments of the present application.

[0089] The power supply circuit 540 is used to supply power to the interface circuit 510 and the test circuit 520 .

[0090] Specifically, the power supply circuit 540 is used to receive the power supply voltage from the test interface 530. When the power supply voltage is different from the power supply voltage required by the interface circuit 510 and the test circuit 520, the received power supply voltage can be converted to generate the power supply voltage required by the interface circuit 510 and the test circuit 520.

[0091] Optionally, the power supply voltages required by the interface circuit 510 and the test circuit 520 may be the same, or the required power supply voltages may be different. The embodiments of the present application do not limit this. The following embodiments are illustrative using the example where the power supply voltages required by the interface circuit 510 and the test circuit 520 are different.

[0092] For example, combined with Figure 7When the interface circuit 510 and the test circuit 520 require different power supply voltages, the first output terminal of the power supply circuit 540 is coupled to the RS232 serial port chip in the interface circuit 510, and the second output terminal of the power supply circuit 540 is coupled to the test chip 521. For example, if the power supply circuit 540 receives a 12V power supply voltage from the device under test 600 via the test interface 530, and the RS232 serial port chip in the interface circuit 510 requires a 1.8V power supply voltage, while the test chip 521 requires a 3.3V power supply voltage, the power supply circuit 540 can generate the 1.8V power supply voltage required by the RS232 serial port chip in the interface circuit 510 and the 3.3V power supply voltage required by the test chip 521 based on the 12V power supply voltage.

[0093] The test device 500 provided in the embodiment of the present application processes the power supply voltage received by the test interface 530 through the power supply circuit 540 , thereby being able to provide a stable power supply voltage for the interface circuit 510 and the test circuit 520 .

[0094] In other embodiments, the power supply circuit 540 can be coupled to the interface circuit 510, and the interface circuit 510 can receive a power supply voltage from the control device 700. When the power supply voltage is different from the power supply voltage required by the interface circuit 510 and the test circuit 520, the received power supply voltage can be converted to generate the power supply voltage required by the interface circuit 510 and the test circuit 520.

[0095] In other embodiments, the power supply circuit 540 may only provide a stable power supply voltage to the interface circuit 510, or the power supply circuit 540 may only provide a stable power supply voltage to the test circuit 520. Figure 8 As shown, the embodiment of the present application further provides a test device 800, which is used to test a device to be tested 900. The test device 800 includes a control device 810 and a test device 820 coupled to each other. The control device 810 and the test device 820 are respectively coupled to the device to be tested 900. The structure of the test device 820 can be as follows: Figure 5 、 Figure 6 and Figure 7 The structure of the testing device 500 is shown.

[0096] It should be noted that the above Figure 8 The structure of the testing device 800 is for illustrative purposes only and does not limit the embodiments of the present application.

[0097] The control device 810 is used to send a control signal, the device under test 900 is used to send a test signal according to the control signal, the test device 820 is used to determine the test result of the device under test 900 according to the test signal, and the control device 810 is also used to receive the test result.

[0098] Optionally, the test device 800 provided in the embodiment of the present application can be used for high-speed signal testing, or can be used for low-speed signal testing. The embodiment of the present application does not limit whether the test device 800 is used for high-speed signal testing or low-speed signal testing.

[0099] Optionally, the test device 800 provided in the embodiment of the present application can be used for eye diagram testing, generating an eye diagram and / or eye diagram test conclusion to determine the quality of the sending link of the device to be tested 900, and the above test results are eye diagrams and / or eye diagram test conclusions; or, it can be used for bit error testing, determining bit error information (bit error rate) to judge the quality of the receiving link of the device to be tested 900, and the above test results are bit error information.

[0100] Optionally, the control device 810 may include control software, which is used to start, pause, stop testing, collect, analyze test data, and output a test report. For example, the control software can be used to generate control signals such as the above-mentioned first control signal and the second control signal. Specifically. The test operator can select the test to be performed by clicking the virtual button in the control software. For example, the operator can select an eye diagram test, or can select an error code test to control the test device 820 and the device to be tested 900 to execute corresponding instructions to complete test contents such as eye diagram testing or error code testing, receive the test results sent by the test device 820, analyze the test results and generate a test report, thereby completing the test of the device to be tested 900. Furthermore, the tester can also perform parameter deviation and parameter optimization based on the test report generated by the control software, thereby improving the test efficiency.

[0101] Exemplarily, the control device 810 can adjust pre-emphasis based on the eye diagram and / or eye diagram test conclusions, as well as the bit error rate, to improve the quality of high-speed signal transmission by the device under test 900. Pre-emphasis refers to a signal processing method that compensates for the high-frequency components of a high-speed signal when the signal is transmitted. By adjusting pre-emphasis, losses in the high-speed signal during transmission can be compensated, thereby improving the quality of the high-speed signal.

[0102] Optionally, the control device 810 is an electronic device, such as a personal computer, a tablet computer, a mobile phone, etc.

[0103] Optionally, the device to be tested 900 may include a mainboard 910 , on which a processor 911 and a slot 912 may be provided.

[0104] The test device 820 includes a test interface 821 , which is used to couple with the slot 912 in the device to be tested 900 .

[0105] Optionally, the test interface 821 may include one of the following: a high-speed serial computer expansion bus interface, a serial small computer system interface, a serial advanced technology attachment interface, a card electromechanical interface, a non-volatile memory standard interface, and an open core protocol interface. This allows the test device 900 to test high-speed signals such as high-speed serial computer expansion bus signals, serial small computer system interface signals, serial advanced technology attachment signals, and universal serial bus signals.

[0106] Optionally, the test signal is a test pattern, and stable and repeatable testing can be performed using the test pattern. The test pattern may include one of the following: PRBS31, PRBS7, PRBS9, PRBS11, PRBS15, PRBS20, and PRBS23.

[0107] In one possible embodiment, Figure 9 As shown, the above-mentioned control device 810 can be integrated into the test device 820, and the test device 800 can also include a human-computer interaction interface 830, which is coupled with the control device 810. The test operator can control the test device to test the device to be tested 900 by clicking the virtual button in the human-computer interaction interface 830. The human-computer interaction interface 830 can also be used to display the test results.

[0108] The test device 800 provided in the embodiment of the present application determines the test result of the device under test 900 based on the test signal through the test device 820. The test device 820 is coupled to the device under test 900 via a test interface 821 and a slot 912. The test interface 821 includes multiple channels corresponding to the slots 912. Therefore, during the test process, there is no need to repeatedly change the structure of the test circuit. The test device 820 can receive the test signal from the device under test 900 and determine the test result based on the test signal. The control device 810 can display the test result eye diagram and / or eye diagram test conclusion based on the test result, or display the bit error rate, thereby determining the quality of the transmitting link and receiving link of the device under test 900. Compared with the prior art, during the test process, there is no need to repeatedly change the connection position of the coaxial cable connector, thereby simplifying the operation and improving the test efficiency. At the same time, there is no need to use an expensive oscilloscope 330, bit error meter 360, and test fixture 320, thereby reducing costs. It should be noted that the relevant descriptions of the testing device 500 in the above device embodiment can be correspondingly referenced in the embodiment of the testing device 800, and the embodiments of the present application will not be repeated here.

[0109] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A testing device, characterized in that: The test device is used for eye diagram testing or bit error testing, and includes: an interface circuit, a test circuit, and a test interface, wherein the interface circuit, the test circuit, and the test interface are coupled, wherein: The test interface is used to connect to a slot in a device to be tested, the test interface includes a plurality of channels corresponding to the slots, and the device to be tested includes a server or a storage device; The test interface is used to receive a test signal from the device to be tested; The test circuit is configured to determine a test result of the device to be tested based on the test signal, wherein the test result includes eye diagram data and / or an eye diagram test conclusion, wherein the eye diagram test conclusion is configured to indicate whether the eye diagram data meets a preset eye diagram test indicator, or the test result includes bit error information; The interface circuit is used to send the test result.

2. The testing device according to claim 1, wherein: The test signal is a first test pattern, and when the test result is the eye diagram data, the test circuit is specifically configured to obtain a synchronous clock signal according to the first test pattern, determine waveform data of a plurality of clock cycles according to the first test pattern and the synchronous clock signal, and determine the eye diagram data according to the waveform data of the plurality of clock cycles; Alternatively, when the test result is the eye diagram test conclusion, the test circuit is further configured to determine the eye diagram test conclusion based on the eye diagram data and the preset eye diagram test indicator.

3. The testing device according to claim 1, wherein: The test signal is a second test pattern, and the test result is the bit error information; The interface circuit is further configured to receive a control signal; The test circuit is further configured to generate a third test pattern according to the control signal; The test interface is further configured to send the third test code pattern to the device under test, and the second test code pattern is obtained by the device under test by converting the third test code pattern.

4. The testing device according to claim 3, characterized in that: The test circuit is specifically used to compare the second test code type and the third test code type bit by bit, determine the number of bits of the second test code type, and determine the error information based on the ratio of the number of bits of the error code to the total number of bits of the third test code type.

5. The testing device according to claim 1, wherein: The test circuit includes a test chip, one end of the test chip is coupled to the test interface, and the other end of the test chip is coupled to the interface circuit.

6. The testing device according to claim 5, characterized in that: The test chip includes a high-speed clock data recovery chip, a signal driver chip or a selection chip.

7. The testing device according to claim 5 or 6, characterized in that: The test circuit further includes a clock circuit and a reset circuit, and the clock circuit and the reset circuit are respectively coupled to the test chip.

8. The testing device according to claim 1, wherein: The testing device further includes a power supply circuit; An input end of the power supply circuit is coupled to the test interface, and an output end of the power supply circuit is coupled to the interface circuit and the test circuit.

9. A testing device, characterized in that: The testing device is used to test the device to be tested, the testing device comprises a control device and a testing device coupled to each other, and the testing device is the testing device according to any one of claims 1 to 8; The control device is used to send a control signal to the device to be tested; The testing device is configured to receive a test signal sent by the device to be tested according to a control signal, and determine a test result of the device to be tested according to the test signal; The control device is further configured to receive the test result.

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