A dynamic memory operation method

Abstract

The present invention discloses a dynamic memory operation method, comprising the following steps: performing a refresh operation on the dynamic memory according to a preset interval time T, and receiving an operation instruction in real time at the same time; when receiving the operation instruction, performing a read operation on the selected storage unit according to the position information of the selected storage unit in the operation instruction, and temporarily storing the state data read in the read operation in a read buffer, wherein the interval time T is less than the time t required for the voltage value of the capacitor in the storage unit to drop to the critical capacitor voltage value for correctly reading the state data of the storage unit in the read operation during the write operation; and then performing a corresponding operation on the selected storage unit according to the operation instruction type information in the operation instruction, wherein a refresh operation execution step is required after each read operation. The present invention can effectively ensure the normal operation of the storage unit in the read and write operations even when the capacitor in the selected storage unit leaks.

Description

Technical Field

[0001] The present invention belongs to the technical field of memory, and more specifically, relates to a dynamic memory operation method. Background Art

[0002] In the computer structure of the von Neumann system, DRAM (dynamic random access memory) plays a connecting role between external memory and CPU, and plays a very important role in the stability of the computer system. DRAM adopts a 1T1C structure, that is, it is composed of a transistor and a storage unit in series. Since the transistor is a three-port device, its peripheral control circuit needs to consume a large area, and the three-port device is not suitable for three-dimensional stacking, making it difficult for DRAM to achieve high-density storage through three-dimensional integration. This is also the most critical factor restricting DRAM performance.

[0003] In order to solve the problem of low DRAM storage density, the academic and industrial circles in the field of memory have explored many new types of memory that may replace DRAM. Among them, the storage unit (1S1C unit) composed of an OTS selection tube and a capacitor connected in series mentioned in Chinese invention patent CN202111280349.1 is comparable to DRAM in terms of read and write speed and power consumption. It is a new storage technology that is very likely to replace DRAM. However, there is no research on the reading and writing scheme of its array in detail. In addition, this type of memory is a dynamic memory, and the charge stored in its capacitor will gradually be lost due to the leakage effect, affecting the read and write operations of the storage unit. Summary of the invention

[0004] In view of the defects of the prior art, the object of the present invention is to provide a dynamic memory operation method, which can effectively ensure the normal operation of the read and write operations of the memory cell even when the capacitor in the selected memory cell leaks.

[0005] To achieve the above object, the present invention provides a method for operating a dynamic memory, wherein the dynamic memory comprises word lines and bit lines arranged vertically to each other and memory cells arranged in an array between the word lines and the bit lines, wherein the memory cells comprise a capacitor connected in series and a two-terminal gating device, wherein the two-terminal gating device has a bidirectional conduction characteristic and a conduction threshold voltage V TH and holding voltage Vhold, the method comprises the following steps:

[0006] (1) performing a refresh operation on the dynamic memory at a preset interval time T, and receiving an operation instruction in real time, performing a read operation on the selected storage unit according to the position information of the selected storage unit in the operation instruction when the operation instruction is received, and temporarily storing the state data read in the read operation; wherein the interval time T is less than the time t required for the voltage value of the capacitor in the storage unit during the write operation to drop to the critical capacitor voltage value for correctly reading the state data of the storage unit during the read operation;

[0007] (2) performing a corresponding operation on the selected storage unit according to the operation instruction type information in the operation instruction. If the received operation instruction type is a read operation, the temporarily stored data is output to the corresponding I / O port, and then step (3) is executed; if the received operation instruction type is a refresh operation, step (3) is executed; if the received operation instruction type is a write operation, step (4) is executed;

[0008] (3) writing state 1 to the selected storage unit, and then judging the data of the temporarily stored selected storage unit. If the temporarily stored data is state 1, the operation is terminated. If the temporarily stored data is state 0, writing state 0 to the selected storage unit again.

[0009] (4) Obtaining and, based on the operation information of the write operation, performing a write state 1 or state 0 operation on the selected storage unit.

[0010] The dynamic memory operation method provided by the present invention sets a refresh operation on the selected storage unit according to an interval time T, and the interval time T is less than the time t required for the voltage value of the capacitor in the storage unit during the write operation to drop to the critical capacitor voltage value for the read operation to correctly read the state data of the storage unit. Even if the capacitor in the storage unit leaks, it can effectively ensure that the read operation can always correctly read the state data of the storage unit. In addition, it is set to immediately perform a read operation on the selected storage unit and temporarily store the state data when an operation instruction is received, and the execution step of the refresh operation is performed after each read operation (rewriting the temporarily stored data into the storage unit), which can effectively ensure that the state data of the storage unit is correctly written in the subsequent write operation.

[0011] In one embodiment, in step (1), the step of performing a read operation on the selected storage unit and temporarily storing the status data read in the read operation is specifically:

[0012] (a) Apply a bit line voltage V to the bit line connected to the selected memory cell. BLread , a word line voltage V is applied to the word line connected to the selected memory cell. Wlread , thus generating a voltage of V at both ends of the storage cell to be read. read The read voltage Vread Used to keep the two-terminal gating device in the selected storage unit in state 0 open, and to open the two-terminal gating device in the selected storage unit in state 1, so that the state changes from state 1 to state 0, and to generate a read current;

[0013] (b) detecting whether there is a read current on the bit line connected to the selected memory cell; if there is a read current, determining that the selected memory cell is in state 1 and outputting a state 1 signal; otherwise determining that the selected memory cell is in state 0 and outputting a state 0 signal;

[0014] (c) Send the output status signal to the read buffer for temporary data storage.

[0015] In one embodiment, in step (a), the read voltage V read Satisfies the following relationship: V read -V C1 >V TH , V read -V C0 <V TH , where V C1 is the capacitor voltage when the storage cell is in state 1, V C0 is the capacitor voltage when the memory cell is in state 0.

[0016] In one embodiment, the write state 1 operation is performed on the selected memory cell by applying a voltage V to the word line connected to the selected memory cell. WL1 , apply a voltage V to the bit line connected to the selected memory cell BL1 , thus forming V at both ends of the selected storage cell IN1 The write state 0 operation to the selected storage cell is performed by applying a voltage V to the word line connected to the selected storage cell. WL0 , apply a voltage V to the bit line connected to the selected memory cell BL0 , thus forming V at both ends of the selected storage cell IN0 The pressure difference is achieved;

[0017] Pressure difference V IN1 and the voltage difference V IN0 Satisfies the following relationship:

[0018] V IN1 =V BL1 –V WL1 , V IN0 =V BL0 –V WL0

[0019] |V IN1 |=|V IN0 |

[0020] V TH <|V IN1 |=|V IN0 |<V TH +V Hold

[0021] |V IN1 |-V Hold +|V BL1 |<V TH

[0022] |V IN1 |-V Hold +|V WL1 |<V TH

[0023] |V IN1 |-V Hold +|V BL0 |<V TH

[0024] |V IN1 |-V Hold +|V WL0 |<V TH

[0025] |V IN1 |-V Hold +|V BLread |<V TH

[0026] |V IN1 |-V Hold +|V WLread |<V TH .

[0027] In one embodiment, the interval time T is less than the voltage of the capacitor in the storage unit from ||V IN |-V Hold |Decrease to V read –V TH The time required t, |V IN |=|V IN1 |=|V IN0 |.

[0028] In one embodiment, step (4) is specifically:

[0029] When the operation information of the write operation is write state 1, the write state 1 operation is directly performed on the selected storage unit; when the operation information of the write operation is write state 0, the write state 1 operation is first performed on the selected storage unit, and then the write state 0 operation is performed on the selected storage unit.

[0030] In one embodiment, the position information of the selected storage unit in the operation instruction includes bitwise, whole row, whole column or matrix position information. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of a flow chart of a dynamic memory operation method provided by an embodiment of the present invention

[0032] Figure 2 and Figure 3 Corresponding to this is a principle block diagram of a bit-by-bit operation method of a dynamic memory and a whole-row operation method of a dynamic memory provided by an embodiment of the present invention;

[0033] Figure 4 and Figure 5 Corresponding to a diagram of applying a 4.5V read voltage to selected memory cells in state 1 and state 0 provided by a specific embodiment of the present invention;

[0034] Figure 6 A diagram of applying a -4.5V write 1 voltage to a selected memory cell in state 0 provided by a specific embodiment of the present invention;

[0035] Figure 7 A diagram of applying a 4.5V write-0 voltage to a selected memory cell in state 1 provided by a specific embodiment of the present invention;

[0036] Figure 8 1 is a voltage diagram of a refresh operation on a selected memory cell in state 0 provided by a specific embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0038] In order to ensure that the read and write operations of the storage unit are not affected by the leakage of the capacitor in the storage unit, the present invention provides a dynamic memory operation method, the applicable dynamic memory includes word lines and bit lines arranged vertically to each other and storage units arranged in an array between the word lines and the bit lines, wherein the storage unit includes a capacitor connected in series and a two-terminal gating device, the two-terminal gating device has a bidirectional conduction characteristic and a conduction threshold voltage V TH and holding voltage Vhold.

[0039] Figure 1 is a flow chart of a dynamic memory operation method provided by an embodiment of the present invention. Figure 1 As shown, the method includes steps S10 to S40, which are described in detail as follows:

[0040] S10, refreshing the dynamic memory at a preset interval T, and receiving an operation instruction in real time, when receiving the operation instruction, performing a read operation on the selected storage unit according to the position information of the selected storage unit in the operation instruction, and temporarily storing the read state data. Specifically, the data can be temporarily stored in a read buffer.

[0041] In step S10, the interval time T is less than the time t required for the voltage value of the capacitor in the storage unit during the write operation to drop to the critical capacitor voltage value for correctly reading the state data of the storage unit in the read operation. Since the voltage of the capacitor in the storage unit will gradually drop due to the leakage effect, when the voltage value of the capacitor drops to the critical capacitor voltage value for correctly reading the state data at this time during the read operation, it will cause subsequent read and write errors. For example, the current write state of the storage unit is 1, and the voltage value of the capacitor in the storage unit is V1 at this time. If the capacitor in the storage unit leaks at this time, the voltage of the capacitor will gradually drop from V1, and the voltage of the capacitor needs to be between V2 and V3 (V3 is greater than V2) when the read operation correctly reads state 1. Therefore, it is necessary to refresh the storage unit before the capacitor voltage drops from V1 to V2 to ensure that the subsequent read operation reads the state data incorrectly. Similarly, it can be known that the situation when the storage unit is written to state 0 is not repeated in this embodiment.

[0042] The operation instruction provided in this embodiment includes the position information of the selected storage unit and the type of operation instruction, and the type of operation instruction includes read operation, write operation and refresh operation. The position information of the selected storage unit includes the position information of the bit, the whole row, the whole column or the matrix, that is, the word line and the bit line position information of the selected storage unit, which is used to perform read and write operations on the storage unit in the dynamic memory in a corresponding bit, the whole row, the whole column or the matrix. For example, when it is necessary to perform a read and write operation on the storage unit in the dynamic memory in a bit-by-bit manner, it is only necessary to obtain the information of the storage unit to be operated, that is, the word line and the bit line information of the storage unit, and then perform the corresponding operation according to the operation method provided in this embodiment according to the information; when it is necessary to perform a read and write operation on the storage unit in the dynamic memory in a whole row, it is only necessary to obtain the word line and the bit line information of the storage unit in the row, and then perform the corresponding operation according to the operation method provided in this embodiment according to the information. Similarly, it can be known that the implementation method of the read and write operation of the whole column and the matrix is ​​not repeated in this embodiment.

[0043] In this embodiment, the dynamic memory will work only after receiving the operation instruction, and after receiving the operation instruction, it will immediately perform a read operation on the selected storage unit, and then send the current state data of the selected storage unit to the read buffer for temporary storage, so that in the subsequent write operation, the storage unit can be correctly written through the state data temporarily stored in the read buffer. After the data is temporarily stored, the next step is performed according to the operation instruction type in the operation instruction, as shown in step S20.

[0044] S20, perform corresponding operations on the selected storage unit according to the operation instruction type information in the operation instruction. If the received operation instruction type is a read operation, the data temporarily stored in the read buffer is output to the corresponding I / O port, and then execute step S30; if the received operation instruction type is a refresh operation, execute step S30; if the received operation instruction type is a write operation, execute step S40.

[0045] S30, write state 1 operation to the selected storage unit, and then judge the data of the selected storage unit temporarily stored in the read buffer. If the temporarily stored data is state 1, end the operation; if the temporarily stored data is state 0, write state 0 operation to the selected storage unit again.

[0046] In steps S20 and S30, after each read operation, a refresh operation execution step is performed. Since the refresh operation execution step is essentially to rewrite the data of the selected storage unit temporarily stored in the read buffer, it is convenient for subsequent write operations to correctly write the storage unit through the status data temporarily stored in the read buffer.

[0047] S40, obtaining and, according to the operation information of the write operation, correspondingly performing a write state 1 or a write state 0 operation on the selected storage unit. The operation information of the write operation includes a write state 1 operation and a write state 0 operation. When the operation information of the write operation is a write state 1, the write state 1 operation can be directly performed on the selected storage unit; when the operation information of the write operation is a write state 0, the write state 1 operation can be first performed on the selected storage unit, and then the write state 0 operation can be performed on the selected storage unit.

[0048] The dynamic memory operation method provided in the present embodiment is set to perform interval refresh operation on the selected storage unit according to the time T, and the interval time T is less than the time t required for the voltage value of the capacitor in the storage unit during the write operation to drop to the critical capacitor voltage value for correctly reading the state data of the storage unit during the read operation. Even if the capacitor in the storage unit leaks, it can effectively ensure that the read operation can always correctly read the state data of the storage unit. In addition, it is set to immediately perform a read operation on the selected storage unit and temporarily store the state data when an operation instruction is received, and the execution step of the refresh operation is performed after each read operation (rewriting the temporarily stored data into the storage unit), which can effectively ensure that the state data of the storage unit is correctly written in the subsequent write operation.

[0049] In one embodiment, the implementation method of the read operation provided in this embodiment can be completed by applying specific voltages to the word line and the bit line connected to the selected memory cell respectively, and the specific steps are as follows:

[0050] Step 1: Apply a bit line voltage V to the bit line connected to the selected memory cell. BLread , a word line voltage V is applied to the word line connected to the selected memory cell. Wlread , thus generating a voltage of V at both ends of the storage cell to be read. read The read voltage V read It is used to keep the two-terminal gating device in the selected storage unit in state 0 open, and to open the two-terminal gating device in the selected storage unit in state 1, so that it changes from state 1 to state 0, and generates a read current, that is, a read voltage V read The following relationship must be satisfied: V read -V C1 >V TH , V read -V C0 <V TH , where V C1 is the capacitor voltage when the storage cell is in state 1, V C0 is the capacitor voltage when the memory cell is in state 0.

[0051] Step 2: Detect whether there is a read current on the bit line connected to the selected memory cell. If there is a read current, the selected memory cell is judged to be in state 1 and a state 1 signal is output. Otherwise, the selected memory cell is judged to be in state 0 and a state 0 signal is output. After the read operation, the selected memory cells are all in state 0, and then the next operation is performed according to the type of operation instruction received, such as the above step S20.

[0052] Step 3: Send the output status signal to the read buffer for temporary data storage.

[0053] In one embodiment, the write state 1 operation to the selected memory cell can be performed by applying a voltage V to the word line connected to the selected memory cell. WL1 , apply a voltage V to the bit line connected to the selected memory cell BL1 , thus forming V at both ends of the selected storage cell IN1 =V BL1 –V WL1 The write state 0 operation to the selected memory cell can be achieved by applying a voltage V on the word line connected to the selected memory cell. WL0 , apply a voltage V to the bit line connected to the selected memory cell BL0 , thus forming V at both ends of the selected storage cell IN0 =V BL0 –V WL0 pressure difference to achieve.

[0054] Among them, V IN1 and V IN0 are two voltage pulses with the same amplitude and opposite polarity, that is, |V IN1 |=|V IN0 |, in order to write data normally, the following relationship needs to be satisfied: V TH <|V IN1 |=|V IN0 |<V TH +V Hold The principle is as follows: a voltage with an amplitude between V TH With V TH +V Hold The operating voltage pulse between V IN1 When the gate tube is initially in high impedance state, the voltage on the capacitor is 0V, and the applied voltage pulse V IN1 Fully applied to the gate tube, and the amplitude is greater than V TH , so that the gate tube is switched from high impedance to low impedance, and the capacitor is quickly charged. As the capacitor voltage rises, the voltage across the gate tube drops. When the voltage across the gate tube drops to less than V Hold When the gate tube switches from low resistance state to high resistance state, the capacitor voltage is maintained at V IN1 -V Hold , operating voltage V IN1 After the action, the capacitor voltage V IN1 -V Hold Less than V TH , the gate tube is maintained in a high impedance state, and the capacitor voltage is maintained at V IN1 -V Hold, the writing of the logic state "1" is completed. The writing principle of the logic state 0 can refer to the writing principle of the logic state "1" mentioned above, and this embodiment will not be repeated in detail. The difference between the two is that the operating voltage pulse V IN0 With V IN1 The amplitude is the same, the polarity is opposite, and the capacitor voltage is also the same as the capacitor voltage of the logic state "0" with the opposite polarity, which is -||V IN0 |-V Hold |.

[0055] According to the principle of writing state 1 and writing state 0 of the storage unit provided in this embodiment, it can be known that no matter writing state 1 or writing state 0, the voltage value across the capacitor in the storage unit is ||V IN |-V Hold |,|V IN |=|V IN1 |=|V IN0 |. Therefore, in this write operation mode, the interval time T of the refresh operation provided by the present invention should be less than the time for the capacitor voltage in the storage unit to change from ||V IN |-V Hold |Decrease to V read –V TH The time required is t.

[0056] At the same time, in order to ensure that the voltage applied to the word line and bit line will not affect the storage state of the semi-selected cell (the storage cell that shares the same word line or bit line with the selected storage cell) and the unselected storage cell (the storage cell that neither shares a word line nor a bit line with the selected storage cell) when the selected storage cell is read or written, it is necessary to obtain V BL1 、V WL1 、V BL0 、V WL0 The following relationship needs to be satisfied:

[0057] |V IN1 |-V Hold +|V BL1 |<V TH

[0058] |V IN1 |-V Hold +|V WL1 |<V TH

[0059] |V IN1 |-V Hold +|V BL0 |<V TH

[0060] |V IN1 |-V Hold +|VWL0 |<V TH

[0061] |V IN1 |-V Hold +|V BLread |<V TH

[0062] |V IN1 |-V Hold +|V WLread |<V TH

[0063] Among them, V TH Represents the conduction threshold voltage of the two-terminal gate device in the dynamic memory; V Hold Indicates the holding voltage of the two-terminal gate device in the dynamic memory; V BL1 Indicates the voltage applied to the bit line connected to the selected memory cell when writing state 1; V WL1 Indicates the voltage applied to the word line connected to the selected memory cell when writing state 1; V BL0 Indicates the voltage applied to the bit line connected to the selected memory cell when writing state 0; V WL0 Represents the voltage applied to the word line connected to the selected memory cell when writing state 0; V BLread Represents the voltage applied to the bit line connected to the selected memory cell during a read operation; V WLread Represents the voltage applied to the word line connected to the selected memory cell during the read operation; the capacitor voltage fluctuation range in the selected memory cell in state 1 is: -||V IN1 |-V Hold |~V read –V TH ; The capacitor voltage of the selected storage cell in state 0 is: V read –V TH ~||V IN1 |-V Hold |.

[0064] |V IN1 |-V Hold is the voltage amplitude of the capacitor after the state is written. Because the capacitor has leakage, the capacitor voltage will gradually decrease over time after the state is written. Therefore, the maximum voltage across the capacitor is |V IN1 |-V Hold Therefore, it is only necessary to ensure that when the storage unit is read or written, the capacitor voltage is |V IN1 |-V Hold The half-selected unit is not affected, that is, the voltage across the gate tube corresponding to the half-selected unit is always less than the threshold voltage V TH , that is, VBL1 、V WL1 、V BL0 、V WL0 、V BLread 、V WLread Add |V IN1 |-V Hold Less than V TH .

[0065] In order to explain the present invention more clearly, the present invention is described below in conjunction with specific embodiments:

[0066] A 1S1C memory, in which the selected gate threshold voltage V th is 4V, maintain voltage V hold is 3V.

[0067] V IN1 =-4.5V, V BL1 = -2.5V, V WL1 =2V

[0068] V IN0 =4.5V, V BL0 =2.5V, V WL0 = -2V

[0069] V read =4.5V, V BLread =2.5V, V WLread = -2V

[0070] The capacitor voltage in state 1 is: -1.5V~0.5V; the capacitor voltage in state 0 is: 0.5V~1.5V.

[0071] like Figure 2 As shown, for a dynamic memory bitwise operation method:

[0072] When an operation instruction is received, a read operation is immediately performed on the selected storage cell, that is, V is applied to the selected storage cell. read =4.5V, for the selected storage cell in state 1, such as Figure 4 As shown, applying the bit line voltage (see Figure 4 The word line voltage (see Figure 4 The voltage across the gate device in the storage unit is greater than 4V, and the gate device is turned on to generate a read current (see Figure 4 No. 34), capacitor voltage (see Figure 4 The voltage of the selected storage unit in state 0 is changed from -1V to 1.5V. Figure 5 As shown, applying the bit line voltage (see Figure 5The word line voltage (see Figure 5 The middle label number 42) is -2V, so that the voltage across the gate device is less than 4V, the gate is closed, and no read current is generated (see Figure 5 No. 44), capacitor voltage (see Figure 5 The voltage of the memory cell is maintained at 1.4V by monitoring whether a read current is generated in the bit line. The data obtained after reading will be temporarily stored in the read buffer. After the read operation, the memory cell is in state 0.

[0073] If the received operation instruction type is a refresh operation, V is applied to the storage unit. IN1 = -4.5V, such as Figure 6 As shown, applying the bit line voltage (see Figure 6 The word line voltage (see Figure 6 The voltage of the capacitor in the storage unit (see Figure 51) is 2V. Since the storage unit is currently in state 0, the voltage across the gate tube is greater than 4V, and the gate tube will be turned on. Figure 6 The voltage of the memory cell is changed to -1.5V, and the writing of state 1 is completed. At this time, the data state in the read buffer is judged. If it is state 1, the operation is completed. If it is state 0, V is applied to the memory cell again. IN0 =4.5V, such as Figure 7 As shown, applying the bit line voltage (see Figure 7 The word line voltage (see Figure 7 The middle label number 62) is -2V, because the current storage unit is in state 1, the voltage across the gate tube is greater than 4V, the gate tube will be turned on, and the storage unit capacitor voltage (see Figure 7 The voltage 63 in the middle becomes 1.5V, the writing of state 0 is completed, and the operation ends.

[0074] If the received operation instruction is a read operation, the data temporarily stored in the read buffer is output to the I / O port, and then a refresh operation is performed to complete the write back of the storage unit data.

[0075] If the received operation instruction is a write 1 operation, V is applied to the storage unit. IN1 = -4.5V, such as Figure 6 As shown, applying the bit line voltage (see Figure 6 The word line voltage (see Figure 6 The voltage of the storage unit capacitor (see Figure 51) is 2V, because the current storage unit is in state 0, the voltage across the gate tube is greater than 4V, the gate tube will be turned on, and the storage unit capacitor voltage ... Figure 6 The voltage 53 in the middle becomes -1.5V, completing the writing of state 1.

[0076] If the received operation instruction is a write 0 operation, V is first applied to the storage unit. IN1 = -4.5V, such as Figure 6 As shown, applying the bit line voltage (see Figure 6 The word line voltage (see Figure 6 The middle label number 51) is 2V. Because the current storage unit is in state 0, the voltage across the gate tube is greater than 4V, the gate tube will be turned on, and the storage unit capacitor voltage 53 becomes -1.5V, completing the writing of state 1. Then V is applied to the storage unit. IN0 =4.5V, such as Figure 7 As shown, applying the bit line voltage (see Figure 7 The word line voltage (see Figure 7 The middle label number 62) is -2V, because the current storage unit is in state 1, the voltage across the gate tube is greater than 4V, the gate tube will be turned on, and the storage unit capacitor voltage (see Figure 7 The voltage 63 in the middle becomes 1.5V, the writing of state 0 is completed, and the operation ends.

[0077] like Figure 3 As shown, a method for operating a whole row of a dynamic memory is as follows:

[0078] When an operation instruction is received, V is applied to the entire row of storage cells. read =4.5V, that is, a voltage V is applied to the word line shared by the entire row of memory cells. WLread = -2V, and a voltage V is applied to the bit line connected to each memory cell. BLread =2.5V, for a storage cell in state 1, Figure 4 As shown, the voltage across the gate tube is greater than 4V, the gate tube is turned on, and a read current is generated (see Figure 4 No. 34), capacitor voltage (see Figure 4 The voltage of the memory cell in state 0 is 1.5V. Figure 5 As shown, the voltage across the gate tube is less than 4V, the gate tube is closed, and no read current is generated (see Figure 5 No. 44), capacitor voltage (see Figure 5 The state of the corresponding storage cell can be determined by monitoring whether a read current is generated in the bit line. The data obtained after reading will be temporarily stored in the entire row read buffer. After the read operation, the entire row of storage cells is in state 0.

[0079] If the received operation instruction is a refresh operation, V is applied to the entire row of storage cells. IN1 = -4.5V, such as Figure 6 As shown, a voltage V is applied to the word line shared by the entire row of memory cells.WL1 =2V, and a voltage V is applied to the bit line connected to each memory cell BL1 = -2.5V, because the entire row of storage cells is currently in state 0, the voltage across the gate tube is greater than 4V, the gate tube will be turned on, making the entire row of storage cells in state 1, and then determine whether each bit of data temporarily stored in the row read buffer is in state 1 or state 0. If it is state 1, the operation can be terminated. If it is state 0, V is applied to the corresponding storage cell again. IN0 =4.5V, such as Figure 7 As shown, a voltage V is applied to the word line shared by the entire row of memory cells. WL0 = -2V, apply voltage V to the bit line connected to the memory cell that needs to write 0 BL0 =2.5V, the voltage across the corresponding storage unit's gate tube is greater than 4V, the gate tube will open, and the writing of state 0 will be completed.

[0080] If the received operation instruction is a write operation, V is applied to the entire row of storage cells. IN1 = -4.5V, such as Figure 6 As shown, a voltage V is applied to the word line shared by the entire row of memory cells. WL1 =2V, and a voltage V is applied to the bit line connected to each memory cell BL1 = -2.5V, because the entire row of storage cells are currently in state 0, the voltage across the gate tube is greater than 4V, the gate tube will be turned on, making the entire row of storage cells in state 1, and then determine which storage cells need to be written to state 0 according to the operation instructions, and then apply V to the corresponding storage cells. IN0 =4.5V, such as Figure 7 As shown, a voltage V is applied to the word line shared by the entire row of memory cells. WL0 = -2V, apply voltage V to the bit line connected to the memory cell that needs to write 0 BL0 =2.5V, the voltage across the corresponding storage unit's gate tube is greater than 4V, the gate tube will open, and the writing of state 0 will be completed.

[0081] like Figure 8 As shown, the memory cell is written to the logic state "0" and a write pulse V is applied. IN0=4.5V. It can be seen that after the writing is completed, the capacitor voltage is maintained at around 1.5V. Thereafter, due to the leakage of the capacitor, the capacitor voltage gradually decreases from 1.5V over time, and drops to 0.5V at time t. The capacitor voltage corresponding to the logic state "0" is: 0.5V~1.5V. If it continues to decrease, the logic state stored in the storage unit will change from "0" to "1", that is, the stored data is wrong. Therefore, it is necessary to refresh the storage unit and rewrite the data before the capacitor voltage drops to 0.5V. Therefore, it is necessary to refresh the data stored in the storage unit at intervals T. The interval time T is less than the time t required for the capacitor voltage in the storage unit to drop from the highest value to the lowest value due to leakage, that is, less than the time t required for the voltage value of the capacitor in the storage unit during the write operation to drop to the critical capacitor voltage value for the read operation to correctly read the state data of the storage unit.

[0082] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A dynamic memory operation method, characterized in that: The dynamic memory comprises word lines and bit lines arranged vertically to each other and memory cells arranged in an array between the word lines and the bit lines. The memory cells comprise a capacitor connected in series and a two-terminal gating device. The two-terminal gating device has a bidirectional conduction characteristic and a conduction threshold voltage V TH and holding voltage Vhold, the method comprises the following steps: (1) performing a refresh operation on the dynamic memory at a preset interval time T, and receiving an operation instruction in real time, performing a read operation on the selected storage unit according to the position information of the selected storage unit in the operation instruction when the operation instruction is received, and temporarily storing the state data read in the read operation; wherein the interval time T is less than the time t required for the voltage value of the capacitor in the storage unit during the write operation to drop to the critical capacitor voltage value for correctly reading the state data of the storage unit during the read operation; (2) performing a corresponding operation on the selected storage unit according to the operation instruction type information in the operation instruction. If the received operation instruction type is a read operation, the temporarily stored data is output to the corresponding I / O port, and then step (3) is executed; if the received operation instruction type is a refresh operation, step (3) is executed; if the received operation instruction type is a write operation, step (4) is executed; (3) writing state 1 to the selected storage unit, and then judging the data of the temporarily stored selected storage unit. If the temporarily stored data is state 1, the operation is terminated. If the temporarily stored data is state 0, writing state 0 to the selected storage unit again. (4) obtaining and, based on the operation information of the write operation, performing a write state 1 or a write state 0 operation on the selected storage unit; In step (1), the step of performing a read operation on the selected storage unit and temporarily storing the status data read in the read operation is specifically as follows: (a) Apply a bit line voltage V to the bit line connected to the selected memory cell. BLread , a word line voltage V is applied to the word line connected to the selected memory cell. Wlread , thus generating a voltage of V at both ends of the storage cell to be read. read The read voltage V read Used to keep the two-terminal gating device in the selected storage unit in state 0 open, and to open the two-terminal gating device in the selected storage unit in state 1, so that the state changes from state 1 to state 0, and to generate a read current; (b) detecting whether there is a read current on the bit line connected to the selected memory cell; if there is a read current, determining that the selected memory cell is in state 1 and outputting a state 1 signal; otherwise determining that the selected memory cell is in state 0 and outputting a state 0 signal; (c) sending the output status signal to the read buffer for temporary data storage; In step (a), the read voltage V read Satisfies the following relationship: V read -V C1 >V TH , V read -V C0 <V TH , where V C1 is the capacitor voltage when the storage cell is in state 1, V C0 is the capacitor voltage when the memory cell is in state 0.

2. The dynamic memory operation method according to claim 1, characterized in that: The write state 1 operation to the selected memory cell is performed by applying a voltage V to the word line connected to the selected memory cell. WL1 , apply a voltage V to the bit line connected to the selected memory cell BL1 , thus forming V at both ends of the selected storage cell IN1 The write state 0 operation to the selected storage cell is performed by applying a voltage V to the word line connected to the selected storage cell. WL0 , apply a voltage V to the bit line connected to the selected memory cell BL0 , thus forming V at both ends of the selected storage cell IN0 The pressure difference is achieved; Pressure difference V IN1 and the voltage difference V IN0 Satisfies the following relationship: V IN1 =V BL1 -V WL1 ,V IN0 =V BL0 -V WL0 |V IN1 |=|V IN0 | V TH <|V IN1 |=|V IN0 |<V TH +V Hold |V IN1 |-V Hold +|V BL1 |<V TH |V IN1 |-V Hold +|V WL1 |<V TH |V IN1 |-V Hold +|V BL0 |<V TH |V IN1 |-V Hold +|V WL0 |<V TH |V IN1 |-V Hold +|V BLread |<V TH |V IN1 |-V Hold +|V WLread |<V TH 。 3. The dynamic memory operation method according to claim 2, characterized in that: The interval time T is less than the voltage of the capacitor in the storage unit from ||V IN |-V Hold |Decrease to V read -V TH The time required t, |V IN |=|V IN1 |=|V IN0 |.

4. The dynamic memory operation method according to claim 1, characterized in that: Step (4) is specifically as follows: When the operation information of the write operation is write state 1, the write state 1 operation is directly performed on the selected storage unit; when the operation information of the write operation is write state 0, the write state 1 operation is first performed on the selected storage unit, and then the write state 0 operation is performed on the selected storage unit.

5. The dynamic memory operation method according to claim 1, characterized in that: The position information of the selected storage unit in the operation instruction includes bitwise, whole row, whole column or matrix position information.

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