Electrostatic discharge (ESD) devices with improved turn-on voltage

Abstract

The present invention relates to electrostatic discharge (ESD) devices with improved turn-on voltage. The present disclosure relates to semiconductor structures, and more particularly to electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a bipolar transistor device including a base region having a base contact region located in a first well of a first conductivity type, a collector region having a collector contact region located in a second well of a second conductivity type, and an emitter region having an emitter contact region located in the first well between the base contact region and the second well; and a second conductivity type of a reverse-doped resistive well located in the first well of the first conductivity type between the base contact region and the emitter contact region and configured to reduce a turn-on voltage of the bipolar transistor device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor structures, and more particularly to electrostatic discharge (ESD) devices with improved turn-on voltage and methods of fabrication. BACKGROUND

[0002] To protect semiconductor circuits, features are often provided to prevent electrostatic discharge (ESD), which is a sudden transient flow of electrical charge that can cause electrical shorts or dielectric breakdown. In fact, ESD events can cause failure of solid state electronic components on such integrated circuit chips. For example, ESD events can cause core circuit damage, resulting in gate oxide layer pinholes, junction damage, metal damage, and surface charge accumulation. In addition, ESD events can cause latching, which can cause permanent damage to the circuit.

[0003] To prevent such problems, ESD devices can be integrated directly into integrated circuit (IC) chips. Such ESD devices can protect circuit elements in the IC chip during fabrication and / or operation of the circuit in the IC chip. For example, an ESD device can be designed to be triggered, i.e., switched from an "off' state to an "on' state, when exposed to an ESD event, effectively acting as a clamp to protect the circuit in the IC chip. Under normal operation, the ESD device is in its "off' state.

[0004] In conventional ESD devices, the trigger voltage at which a high voltage ESD device is turned on under ESD stress is significantly higher than the DC breakdown voltage of the device. This results in late turn-on, reducing the effectiveness of the ESD device. To address this problem, ESD devices have external base resistance regions and diodes to increase resistance. However, such external devices significantly increase the size of the overall ESD circuit. Other methods have used substrate current injection and current coupling effects through capacitors, but these require additional elements that increase complexity, size, and cost. SUMMARY

[0005] In one aspect of the present disclosure, a structure includes a bipolar transistor device including a base region having a base contact region located in a first well of a first conductivity type, a collector region having a collector contact region located in a second well of a second conductivity type, and an emitter region having an emitter contact region located in the first well between the base contact region and the second well, and a reverse doped resistive well of the second conductivity type located in the first well of the first conductivity type between the base contact region and the emitter contact region and configured to reduce a turn-on voltage of the bipolar transistor device.

[0006] In an aspect of the disclosure, a bipolar transistor device includes a substrate having a first conductivity type; an isolation region located in the substrate, wherein the isolation region has a second conductivity type; a base region including a base contact region located in a first well of the first conductivity type over a first portion of the isolation region; a collector region including a collector contact region located in a second well of the second conductivity type over a second portion of the isolation region; an emitter region having an emitter contact region located in the first well between the base contact region and the second well; and a reverse-doped resistive element including a third well having the second conductivity type in the first well of the first conductivity type between the base contact region and the emitter contact region.

[0007] In an aspect of the disclosure, a method includes forming a bipolar transistor device including a base region having a base contact region located in a first well of a first conductivity type, a collector region having a collector contact region located in a second well of a second conductivity type, and an emitter region having an emitter contact region located in the first well between the base contact region and the second well; and forming a reverse-doped resistive well of the second conductivity type in the first well of the first conductivity type between the base contact region and the emitter contact region and configured to reduce an on-voltage of the bipolar transistor device. BRIEF DESCRIPTION OF DRAWINGS

[0008] In the following detailed description, the disclosure is described by way of non-limiting examples of illustrative embodiments of the present disclosure with reference to the figures mentioned.

[0009] Figures 1A-1D Different manufacturing stages of an electrostatic discharge (ESD) device according to some aspects of the present disclosure are shown.

[0010] Figures 2-5 An electrostatic discharge (ESD) device according to other aspects of the present disclosure is shown.

[0011] Figures 6A-6B Figures 7A-7B show a top view and a cross-sectional view, respectively, of an electrostatic discharge (ESD) device according to other aspects of the present disclosure.

[0012] Figure 8 A cross-sectional view of an electrostatic discharge (ESD) device having a multi-fingered collector and emitter structure according to other aspects of the present disclosure is shown.

[0013] Figures 9A-9B Figures 8A-8B show a graph and a table, respectively, comparing an ESD device of the present disclosure to an ESD device without a resistive well arrangement according to some aspects of the present disclosure. DETAILED DESCRIPTION

[0014] The present disclosure relates to semiconductor structures, and more particularly to electrostatic discharge (ESD) devices with improved turn-on voltage and methods of manufacture. In more particular embodiments, the ESD devices include a reverse-doped resistive well in a base well to improve turn-on voltage. More particularly, the present disclosure relates to ESD bipolar devices that use a reverse-doped resistive well in a base well of an NPN ESD device and / or a PNP ESD device to provide a resistive region. Advantageously, the present disclosure provides ESD performance improvements in ESD device technology, such as fast turn-on time and lower trigger voltage, while effectively saving area compared to conventional device structures.

[0015] In embodiments, the ESD device can be an NPN or PNP bipolar device formed using a CMOS process to include a base well and a collector well formed adjacent to each other above a buried isolation region in a semiconductor substrate. A high-impurity base contact region and an emitter contact region can both be formed in the base well, and a high-impurity collector contact region can be formed in the adjacent collector well. In this arrangement, the base contact region and the emitter contact region can both be coupled to a ground voltage. The collector contact region can be connected to receive any ESD surge voltage that occurs to turn on the ESD device to avoid damage to a protected circuit from the ESD surge voltage. When no ESD event is occurring, the ESD device is normally turned off. Additionally, the collector contact region can be optionally coupled to a collector bias voltage.

[0016] In embodiments, a resistive region disposed in the base well increases the internal resistance on the ESD device, thereby bringing the trigger voltage of the device closer to the breakdown voltage of the device. In embodiments, the resistive region can be a well with a reverse-doped resistance in the base well between the base contact region and the emitter contact region. For example, if the base well is a P-well formed above an N-type isolation region in a P-type substrate, the reverse-doped well can be an N-well formed in the P-type base well between the base contact region and the emitter contact region. The upper surface of the reverse-doped resistive well can be exposed to the upper surface of the device, and can be floating (i.e., no electrical connection to an external voltage), or can be connected to a collector bias voltage applied to the collector contact region. Alternatively, the reverse-doped resistive well can be a buried well formed below a shallow trench isolation region formed in the upper surface of the substrate between the base contact region and the emitter contact region.

[0017] In embodiments, the concentration density of the reverse-doped resistive well can be higher at its upper portion than at its lower portion. This can be achieved by providing a high-impurity upper region in a lower region of lower impurities.

[0018] ESD devices of the present disclosure can be fabricated using a variety of different tools, in a variety of ways. Generally, however, methods and tools are used to form structures having micron and nanometer scale dimensions. Methods (i.e., techniques) for fabricating ESD devices of the present disclosure have been adopted from integrated circuit (IC) technology. For example, these structures are built on wafers and realized in material films that are patterned on top of the wafers by means of photolithographic processes. In particular, fabrication of ESD devices uses three basic building blocks: (i) deposition of thin films of material on a substrate; (ii) application of a patterned mask on top of the film by photolithographic imaging; and (iii) etching of the film selectively to the mask.

[0019] Figure 1A Starting structures and corresponding fabrication processes according to some aspects of the present disclosure are shown. More specifically, Figure 1A ESD device 10 includes a substrate 12 composed of any suitable semiconductor material including, but not limited to, Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. Substrate 12 can include any suitable crystal orientation (e.g., (100), (110), (111), or (001) crystal orientation). Substrate 12 can be a single semiconductive material, such as bulk silicon, or can be composed of semiconductor-on-insulator (SOI) technology. In embodiments, substrate 12 is a P-type substrate.

[0020] Still referring to Figure 1A Substrate 12 includes an isolation region 14 formed as a buried layer in substrate 12. In NPN bipolar applications where substrate 12 is P-type, isolation region 14 includes an N-type region. In PNP bipolar applications where substrate 12 is N-type, isolation region 14 can be P-type. Isolation region 14 can be formed by introducing a different dopant type into substrate 12 with, for example, an ion implantation process. For example, isolation region 14 can be doped with a p-type dopant, such as boron (B), if it is P-type, or an n-type dopant, such as arsenic (As), phosphorus (P), and antimony (Sb), if it is N-type, among other suitable examples. Alternatively, isolation region 14 can be formed in an epitaxial region formed over substrate 12 using conventional epitaxial deposition techniques.

[0021] In an ion implantation process, a patterned implantation mask 15 can be used to define one or more selected regions exposed for implantation. The implantation mask 15 used to select the exposed regions of the isolation regions 14 is stripped after implantation. The implantation mask 15 can include a layer of photo-sensitive material (e.g., organic photoresist) applied by a spin-on process, then pre-baked, exposed to light projected through a photomask, post-exposure baked, and developed with a chemical developer. The implantation mask 15 has a thickness and resistivity sufficient to block the masked regions from receiving a dose of implantation ions. For purposes of example only, the isolation regions 14 can be doped to a concentration of 1 x 1015 18 to 5 x 1016 19 cm -3 .

[0022] In Figure 1B , after the implantation process, an epitaxial region 13 can be formed over the isolation regions 14 using conventional epitaxial deposition techniques. In this manner, the isolation regions 14 can now be buried within the substrate 12. The epitaxial region 13 can be a semiconductor material formed on the substrate 12 using conventional epitaxial growth processes, and therefore need not be further explained herein to fully understand the present disclosure. In embodiments, the epitaxial region 13 can be the same semiconductor material as the substrate 12, and can be used as a substrate for forming base, emitter, collector, and resistor regions, as described below. In alternative embodiments, the p-substrate 12 can be used for the base, emitter, collector, and resistor regions.

[0023] Still referring to Figure 1B , a plurality of shallow trench isolation structures 16 can be formed in the epitaxial region 13 of the substrate 12. The shallow trench isolation structures 16 can be formed by conventional photolithography, etching, and deposition methods known to those skilled in the art. For example, a resist formed on the substrate 12 (e.g., the epitaxial region 13) is exposed to energy (light) to form a pattern (opening). An etching process (e.g., RIE) with a selective chemical action will serve to form one or more trenches in the substrate 12 through the opening in the resist. After the resist is removed by a conventional oxygen ashing process or other known stripper, an insulator material can be deposited by any conventional deposition process (e.g., a CVD process) to form the shallow trench isolation structures 16.

[0024] Still referring to Figure 1B , in embodiments, the substrate 12 includes a base well 18, and optionally a low-impurity concentration collector well 24 formed in the epitaxial region 13 over the isolation regions 14. In NPN bipolar applications, the base well 18 is a P-type region, and the low-impurity concentration collector well 24 is an N-type region. In PNP bipolar applications, the base well 18 is an N-type region, and the low-impurity concentration collector well 24 is a P-type region.

[0025] Wells 18 and 24 can be formed by introducing different dopant types into epitaxial region 13 with, for example, an ion implantation process using, for example, the patterned implantation mask used to form isolation regions 14 as described above. For example, in addition to other suitable examples, if well 18 or 24 is to be P-type, it can be doped with a p-type dopant such as boron (B), and if it is to be N-type, it can be doped with an n-type dopant such as arsenic (As), phosphorus (P), and antimony (Sb). For purposes of example only, wells 18 and 24 can be doped to a level of 1 x 1016 16 to 1 x 1018 18 cm -3 .

[0026] Referring Figure 1C , the plurality of shallow trench isolation structures 16 formed in epitaxial region 13 of substrate 12 can be used to separate elements in base region 17, collector region 22, emitter region 30, and resistive region 34 from one another. In Figure 1C , high impurity concentration collector well 26 can be formed to overlap low impurity concentration collector well 24, and resistive well 36 can be formed as a counter-doped resistive region in base well 18.

[0027] As will be discussed with respect to Figure 9A and 9B , well 36 has an impurity concentration of opposite type doping from base well 18. For example, if base well 18 is a P-type well above an N-type isolation region 14 in a P-type substrate 12, resistive well 36 can be an N-type well formed in P-type base well 18 between base contact region 20 and emitter contact region 32. This increases the resistance of base well 18 without the need for an external resistive element, allowing the trigger voltage for turning on ESD device 10 to be closer to the DC breakdown voltage of the ESD device. This will effectively avoid the hysteresis turn-on of the ESD device that would result in ineffective protection of the IC internal elements that ESD device 10 is protecting from the inrush current, as will be discussed later with respect to Figure 9A and 9B .

[0028] Wells 26 and 36 are formed, for example, using ion implantation techniques such as those described above for wells 18 and 24. As previously mentioned, well 24 is optional, and high impurity concentration collector well 26 can be formed directly in epitaxial region 13 above isolation region 14. Wells 26 and 36 can be formed simultaneously to have the same impurity concentration, or can be formed in separate ion implantation operations to have different impurity concentrations. In NPN bipolar applications, wells 26 and 36 are N-type regions. In PNP bipolar applications where the substrate is N-type, wells 26 and 36 are P-type regions. For purposes of non-limiting example only, wells 26 and 36 can be doped to a level of 1 x 1016 17 to 5 x 101818 cm -3 horizontal doping between 5 x 1018

[0029] Still referring to Figure 1C In embodiments, the epitaxial region 13 also includes a collector contact region 28 formed in the high impurity concentration collector well 26, an emitter contact region 32 formed in the base well 18, and a resistor contact region 38 formed in the resistor well 36. These contact regions 28, 32, and 38 can be formed using, for example, the ion implantation techniques described above for the wells 18 and 24. The contact regions 28, 32, and 38 can be formed simultaneously to have the same impurity concentration, or can be formed in separate ion implantation operations to have different impurity concentrations.

[0030] In NPN bipolar applications, the contact regions 28, 32, and 38 are N-type regions. In PNP bipolar applications, the contact regions 28, 32, and 38 are P-type regions. For purposes of example only, the contact regions 28, 32, and 38 can be doped to a horizontal doping between 5 x 1018 19 and 5 x 1019 21 cm -3 Thus, these contact regions can be high impurity regions having an N++ or P++ impurity concentration that is higher than the impurity concentration of the collector well 26, the base well 18, and the resistor well 36, respectively, in which they are formed.

[0031] Still referring to Figure 1C In embodiments, the epitaxial region 13 also includes a base contact region 20 formed in the base well 18. This base contact region 20 can be formed using, for example, the ion implantation techniques described above for the wells 18 and 24. The base contact region 20 can be formed before or after the contact regions 28, 32, and 38, and has the opposite conductivity type as the contact regions 28, 32, and 38. In NPN bipolar applications, the base contact region 20 can be a P-type region; while in PNP bipolar applications, the base contact region 20 can be an N-type region. For purposes of example only, the base contact region 20 can be doped to a horizontal doping between 5 x 1018 19 and 5 x 1019 21 cm -3 Thus, the base contact region 20 can be a high impurity region having an N++ or P++ impurity concentration that is higher than the impurity concentration of the base well 18 in which it is formed.

[0032] In Figure 1DIn the illustrated embodiment, contacts 40b, 40c, 40e, and 40r are provided on base contact region 20, collector contact region 28, emitter contact region 30, and resistive contact region 38, respectively, for applying voltages to these contact regions. Contacts 40b, 40c, 40e, and 40r can be formed using a silicide process. For example, as will be understood by those skilled in the art, contacts 40b, 40c, 40e, and 40r can be formed by a silicide process using a silicide block (SBLK) 39 on the upper surface of ESD device 10 where silicide processing is not desired, such as over high impurity concentration collector well 26. A thin layer of a transition metal, such as nickel, cobalt, or titanium, is deposited over the fully formed and patterned semiconductor device. After the material is deposited, the structure is heated, allowing the transition metal to react with exposed silicon (or other semiconductor material as described herein) in base contact region 20, collector contact region 28, emitter contact region 32, and resistive contact region 38, forming a low resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving a silicide contact on base contact region 20, collector contact region 28, emitter contact region 32, and resistive contact region 38 in the illustrated ESD device 10. Mask 39 can then be removed. Thereafter, contacts 40b, 40c, 40e, and 40r to the silicided regions are formed using conventional CMOS processes known to those of ordinary skill in the art, and therefore need not be further explained herein to fully understand the present disclosure. Figure 1D In the illustrated arrangement, base contact region 20 and emitter contact region 32 are both coupled to ground voltage by contacts 40b and 40e, respectively. Collector contact region 28 can be connected by contact 40c to receive any ESD surge voltage that occurs, thereby turning on the ESD device to avoid damage to the protected circuitry from the ESD surge voltage. When no ESD event is occurring, the ESD device is normally turned off. In addition, collector contact region 28 can be optionally coupled to a collector bias voltage by contact 40c. Resistive well 36 can be connected to a bias voltage by contact 40r. It is noted that the illustrated contact 40r for resistive contact region 38 is optional and can be omitted if no bias voltage is to be provided to resistive well 36.

[0033] In the illustrated embodiment, contacts 40b, 40c, 40e, and 40r are provided on base contact region 20, collector contact region 28, emitter contact region 30, and resistive contact region 38, respectively, for applying voltages to these contact regions. Contacts 40b, 40c, 40e, and 40r can be formed using a silicide process. For example, as will be understood by those skilled in the art, contacts 40b, 40c, 40e, and 40r can be formed by a silicide process using a silicide block (SBLK) 39 on the upper surface of ESD device 10 where silicide processing is not desired, such as over high impurity concentration collector well 26. A thin layer of a transition metal, such as nickel, cobalt, or titanium, is deposited over the fully formed and patterned semiconductor device. After the material is deposited, the structure is heated, allowing the transition metal to react with exposed silicon (or other semiconductor material as described herein) in base contact region 20, collector contact region 28, emitter contact region 32, and resistive contact region 38, forming a low resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving a silicide contact on base contact region 20, collector contact region 28, emitter contact region 32, and resistive contact region 38 in the illustrated ESD device 10. Mask 39 can then be removed. Thereafter, contacts 40b, 40c, 40e, and 40r to the silicided regions are formed using conventional CMOS processes known to those of ordinary skill in the art, and therefore need not be further explained herein to fully understand the present disclosure. Figure 1D In the illustrated arrangement, base contact region 20 and emitter contact region 32 are both coupled to ground voltage by contacts 40b and 40e, respectively. Collector contact region 28 can be connected by contact 40c to receive any ESD surge voltage that occurs, thereby turning on the ESD device to avoid damage to the protected circuitry from the ESD surge voltage. When no ESD event is occurring, the ESD device is normally turned off. In addition, collector contact region 28 can be optionally coupled to a collector bias voltage by contact 40c. Resistive well 36 can be connected to a bias voltage by contact 40r. It is noted that the illustrated contact 40r for resistive contact region 38 is optional and can be omitted if no bias voltage is to be provided to resistive well 36.

[0034] Figures 2-5 An electrostatic discharge (ESD) device according to other aspects of the present disclosure is illustrated. For example, Figure 2 An ESD device 10a is illustrated that includes a collector voltage contact 42 on resistive contact region 38, rather than Figure 1DThe contact 40r shown is connected to a bias voltage other than the collector bias voltage applied to contact 40c. This allows the collector voltage applied to contact 40c on collector contact region 28 to also be applied to resistor well contact region 38 and resistor well 36 via collector voltage contact 42.

[0035] Figure 3 ESD device 10b is shown, which includes a polysilicon layer 44 (which can be connected to the emitter contact 32 via contacts and metal) located between the emitter contact region 32 and the well 26 for forming a gate structure. This allows the NPN and / or PNP devices discussed herein to be formed using standard CMOS processing to provide an ESD device.

[0036] exist Figure 1D , 2 In the ESD structures 10, 10a, and 10b shown in Figures 3 and 4, the upper surface of the inversion-doped resistive well 36 can be exposed to the upper surface of the device and can be floating (i.e., without electrical connection to an external voltage), as shown in Figure 5. Figure 1D As shown, it can also be connected to the collector bias voltage applied to the collector contact region 28 via contact 42. Alternatively, the inversion-doped resistive well can be a buried inversion-doped resistive well 36' formed below one of the shallow trench isolation regions 16, which are formed in the upper surface of the substrate 12 between the base contact region 20 and the emitter contact region 32, as for Figure 4 The ESD device 10c is shown in the figure.

[0037] Figure 5 A structure 10d is shown including a floating buried inversion-doped resistive well 36” with variable impurity concentration, wherein the concentration density of the inversion-doped resistive well 36” is higher at its upper part than at its lower part. This can be achieved by providing a high-impurity upper region 36a and a low-impurity lower region 36b in the well 36”. This is for non-limiting illustrative purposes only. Figure 5 The inversion-doped resistive trap 36” shown has an in the high-impurity upper region 36a with an inductance of approximately 1 × 10⁻⁶. 18 cm -3 Horizontal doping, and in the lower impurity region 36b at approximately 1 × 10 17 cm -3 Horizontal doping.

[0038] Alternatively, for the purpose of merely being a non-limiting example, the impurity concentration density of the inversion-doped resistive well 36” can be from approximately 1 × 10⁻⁶ at the top of the inversion-doped resistive well 36”. 18 cm -3 The higher impurity concentration gradually changes to approximately 1×10⁻⁶ at the bottom of the inversion-doped resistive well 36”. 17 cm -3The concentration of impurities is relatively low. It should be noted that... Figure 1D , 2 The impurity concentration density of the inversion-doped resistor well 36 in the structure shown in Figure 3 can gradually change from the higher impurity concentration at the top of the inversion-doped resistor well 36 to the lower impurity concentration at the bottom of the inversion-doped resistor well 36.

[0039] Figure 6A and 6B They are shown respectively Figure 2 The diagram shows a top view and a cross-sectional view of an electrostatic discharge (ESD) device. Figure 2 Lines are provided between the top view and the cross-sectional view of the structure shown to illustrate the relationship between structures such as collector contact 40c, base contact 40b, resistor contact 42, emitter contact 40e, silicide barrier layer 39, and collector contact 40c exposed from silicide barrier layer 39.

[0040] Figure 7A and 7B They are shown respectively Figure 2 The diagram shows a top view and a cross-sectional view of an electrostatic discharge (ESD) device, but with the discontinuous resistive contact region 42' used instead. Figure 6A and 6B The continuous resistive contact area 42 is shown. In other words, Figure 7A The resistor contact arrangement provided in the structure can be multiple spaced resistor contacts 42', rather than... Figure 6A The single continuous resistive contact 42 is shown. In ( Figure 2 Lines are provided between the top view and cross-sectional view of the structure shown to illustrate the relationship between structures such as collector contact region 28, base contact 40b, discontinuous resistance contact 42', emitter contact 40e, silicide barrier layer 39, and collector contact 40c exposed from silicide barrier layer 39.

[0041] Figure 8 A cross-sectional view of an electrostatic discharge (ESD) device having a multi-finger collector and emitter structure according to other aspects of this disclosure is shown. Figure 8 The structure shown is similar to multiple adjacent Figure 1D The structure shown is now labeled 10, 10'. Specifically, in Figure 8 In this configuration, the two adjacent collector regions 22 and 22' of the corresponding adjacent ESD devices 10 and 10' are separated by a central emitter contact region 32, and two parallel ESD devices 10, 10' are provided in a mirror-image arrangement (i.e., a two-finger ESD arrangement). Due to the presence of two ESD devices 10, 10', the combination of ESD devices can handle higher ESD surges. Of course, Figure 8The illustration of two side-by-side parallel ESD devices 10, 10' in FIG. 1 is for example purposes only, and the number of ESD devices referred to can vary depending on the ESD level requirements.

[0042] It should now be appreciated that in this layout, the increase of the resistive region 34 in the base well 18 ensures that all ESD devices in the multi-finger ESD arrangement will be triggered at a voltage closer to the DC breakdown voltage of the ESD device compared to ESD devices without the resistive region 34, as discussed below with respect to Figure 9A and 9B It should be appreciated that these resistance values are exemplary, and such resistance values can be increased or decreased based on different variables (e.g., material type and doping profile).

[0043] Figure 9A and 9B respectively show graphs and tables comparing the ESD devices of the present disclosure with ESD devices that do not have a resistive region 34 as discussed with respect to Figure 1D and 2 -8. The graphs in FIG. 8 are TCAD simulations showing a comparison between the ESD device 10 (device “B”) described in Figure 9A Figure 1D Figure 2 The graphs in FIG. 8 are TCAD simulations showing a comparison between the ESD device 10 (device “B”) described in

[0044] As shown in Figure 9A and 9B Device “A” represented by line “A” has a trigger voltage of 42.07 V and a breakdown voltage of 33.4 V. There is a voltage difference of 8.67 V between the trigger voltage and the breakdown voltage. Device “B” represented by line “B” such as shown in Figure 1D has a trigger voltage of 37.00 V and a breakdown voltage of 33.3 V. There is a voltage difference of only 3.7 V between the trigger voltage and the breakdown voltage. Similarly, device “C” represented by line “C” such as shown in Figure 2 has a trigger voltage of 36.47 V and a breakdown voltage of 33.0 V. There is a voltage difference of only 3.47 V between the trigger voltage and the breakdown voltage.

[0045] Thus, as shown in Figure 9A and 9B devices such as Figure 1D and 2 ​​The lower trigger voltage (shown at -8) is closer to the DC breakdown voltage compared to an ESD device without the inversion doped resistive well 36 in the base well 18. This helps prevent turn-on hysteresis and significantly improves the protection capability of the ESD device using the inversion doped resistive well 36 in the base well region 18.

[0046] These ESD devices can be utilized in system-on-a-chip (SoC) technology. Those skilled in the art will appreciate that an SoC is an integrated circuit (also referred to as a “chip”) that integrates all components of an electronic system onto a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0047] The above-described methods are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricant as raw chips, i.e., as a single wafer having many unpackaged chips, as bare chips, or in packages. In the latter case the chips are mounted in single chip packages (e.g., plastic carriers, with leads that are affixed to a motherboard or other higher level carrier) or in multi-chip packages (e.g., ceramic carriers that have surfaces that interconnect and / or mask the leads). In any case the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of the product being fabricated (for example a motherboard). The product so

[0048] The description of various embodiments of the present disclosure has been presented for purposes of illustration but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The embodiments were chosen and described in order to best explain the principles of the embodiments, the practical application, and to enable others skilled in the art to understand the disclosure with various embodiments disclosed herein. The selection of the terms used herein are intended to best explain the principles of the embodiments, the practical application, or the technical improvements found in the technology as it is found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: Bipolar transistor devices, including: The base region includes a base contact region located in a first well of a first conductivity type; The collector region includes a collector contact region located in a second well of the second conductivity type; and An emitter region, comprising an emitter contact region in the first well located between the base contact region and the second well; and The second conductivity type inversion-doped resistive well is located in the first well of the first conductivity type between the base contact region and the emitter contact region, and is configured to reduce the turn-on voltage of the bipolar transistor device, wherein the inversion-doped resistive well is separated from the emitter region.

2. The semiconductor structure according to claim 1, wherein, The base contact area and the emitter contact area are connected to each other and to ground.

3. The semiconductor structure according to claim 1, wherein, The upper surface of the inverted doped resistive well is located on the upper surface of the substrate.

4. The semiconductor structure of claim 3 further includes a contact configured to apply a voltage to the upper surface of the inversion-doped resistive well.

5. The semiconductor structure according to claim 4, wherein, The contact is connected to the current collector contact area.

6. The semiconductor structure according to claim 1, wherein, The inverse-doped resistive well includes a floating well.

7. The semiconductor structure of claim 6 further includes a shallow trench isolation region above the inversion-doped resistive well in the region between the base contact region and the emitter contact region.

8. The semiconductor structure according to claim 1, wherein, The inverse-doped resistive well has a higher concentration density at its upper part than at its lower part.

9. The semiconductor structure according to claim 1 further includes a polycrystalline silicon region formed on the upper surface of the substrate between the emitter contact region and the collector contact region.

10. The semiconductor structure of claim 1, further comprising an isolation region in a substrate located below the first well, the second well, and the inversion-doped resistive well.

11. The semiconductor structure according to claim 1, further comprising a resistor well contact region located in the inversion-doped resistor well, a resistor well contact located on the resistor well contact region, a collector contact located on the collector contact region, a base contact located on the base contact region, and an emitter contact located on the emitter contact region.

12. The semiconductor structure according to claim 11, wherein, When the structure is viewed from a top view, the resistive trap contact comprises a continuous ring.

13. The semiconductor structure according to claim 11, wherein, When the structure is viewed from a top view, the resistor trap contact comprises a plurality of separate, individual contact areas spaced apart from each other on the resistor trap contact area.

14. A bipolar transistor device, comprising: Substrate having a first conductivity type; An isolation region of the second conductivity type located in the substrate; The base contact region of the first conductivity type in the first well located above the first portion of the isolation region; The collector contact area of ​​the second well of the second conductivity type is located above the second portion of the isolation region; The emitter contact region is located in the first well and between the base contact region and the second well; as well as An inversion-doped resistor element comprising a third well of a second conductivity type located in a first well of a first conductivity type between the base contact region and the emitter contact region, wherein the inversion-doped resistor element is separated from the emitter contact region.

15. The bipolar transistor device according to claim 14, wherein, The base contact area and the emitter contact area are connected to each other and to ground.

16. The bipolar transistor device according to claim 14, wherein, The upper surface of the third well is located at the upper surface of the substrate.

17. The bipolar transistor device of claim 16, further comprising a contact that applies a voltage to the upper surface of the third well.

18. The bipolar transistor device according to claim 17, wherein, The contact is connected to the current collector contact area.

19. The bipolar transistor device according to claim 14, wherein, The third trap includes a floating trap.

20. A method for manufacturing a semiconductor structure, comprising: A bipolar transistor device is formed, the bipolar transistor device including a base region having a base contact region located in a first well of a first conductivity type, a collector region having a collector contact region located in a second well of a second conductivity type, and an emitter region having an emitter contact region located in the first well between the base contact region and the second well; as well as An inverse-doped resistive well of the second conductivity type is formed, the inverse-doped resistive well being located in the first well of the first conductivity type between the base contact region and the emitter contact region and being configured to reduce the turn-on voltage of the bipolar transistor device, wherein the inverse-doped resistive well is separated from the emitter region.

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