semiconductor element

Abstract

This invention discloses a semiconductor device. The semiconductor device includes: a fin structure extending along a first direction on a substrate, the fin structure including a first portion and a second portion; a shallow trench isolation surrounding the fin structure; a first monodiffusion isolation structure extending along a second direction different from the first direction between the first portion and the second portion; and at least one second monodiffusion isolation structure extending within the shallow trench isolation and disposed beside the fin structure.

Description

[0001] This application is a divisional application of Chinese invention patent application (application number: 201710160665.2, application date: March 17, 2017, invention title: semiconductor element and method of manufacturing thereof). Technical Field

[0002] This invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming a single diffusion break (SDB) structure within a shallow trench isolation adjacent to a fin structure. Background Technology

[0003] In recent years, with the continuous shrinking of field-effect transistor (FET) device dimensions, the development of existing planar FET devices has reached the limits of fabrication technology. To overcome these limitations, replacing planar FET devices with non-planar FET devices, such as fin field-effect transistors (Fin FETs), has become the mainstream development trend. Because the three-dimensional structure of Fin FETs increases the contact area between the gate and the fin structure, it further enhances the gate's control over the carrier channel region, thereby reducing the drain-induced barrier lowering (DIBL) effect faced by small-sized devices and suppressing the short-channel effect (SCE). Furthermore, since Fin FETs have a wider channel width for the same gate length, they can achieve double the drain drive current. Moreover, the threshold voltage of the transistor device can be controlled by adjusting the work function of the gate.

[0004] In current fin field-effect transistor (FET) fabrication processes, the fin structure is typically divided and then filled with insulating material to form shallow trenches. However, the shallow trenches between the divided fin structures often develop flares due to fabrication process factors, affecting the subsequent gate structure configuration. Therefore, improving existing fin field-effect transistor fabrication processes and architectures is a crucial issue. Summary of the Invention

[0005] This invention discloses a method for fabricating a semiconductor device. First, a fin-like structure is formed on a substrate. Then, a shallow trench isolation is formed around the fin-like structure. Part of the fin-like structure and part of the shallow trench isolation are removed to form a first groove. At the same time, part of the shallow trench isolation next to the fin-like structure is removed to form a second groove. Then, a dielectric layer is formed in the first groove and the second groove to form a first monodiffusion isolation structure and a second monodiffusion isolation structure.

[0006] Another embodiment of the present invention discloses a semiconductor device, which mainly includes: a fin structure extending in a first direction on a substrate, the fin structure including a first portion and a second portion; a shallow trench isolation surrounding the fin structure; a first monodiffusion isolation structure extending in a second direction between the first portion and the second portion; and a second monodiffusion isolation structure extending in a second direction within the shallow trench isolation and disposed beside the fin structure.

[0007] Another embodiment of the present invention discloses a semiconductor device, which mainly includes: a fin structure extending in a first direction on a substrate, the fin structure including a first portion and a second portion; a shallow trench isolation surrounding the fin structure; and a first monodiffusion isolation structure extending in a second direction between the first portion and the second portion, wherein the lower surface of the first monodiffusion isolation structure includes a wavy surface. Attached Figure Description

[0008] Figure 1 A top view of a semiconductor element fabricated for the present invention;

[0009] Figure 2 for Figure 1 A schematic cross-section along the tangent AA';

[0010] Figure 3 for Figure 2 A schematic cross-sectional view along the tangent BB'.

[0011] Figure 4 To continue Figure 2 A cross-sectional schematic diagram;

[0012] Figure 5 To continue Figure 3 A cross-sectional schematic diagram;

[0013] Figure 6 To continue Figure 4 A cross-sectional schematic diagram;

[0014] Figure 7 To continue Figure 5 A cross-sectional schematic diagram;

[0015] Figure 8 To continue Figure 6 A cross-sectional schematic diagram;

[0016] Figure 9 To continue Figure 7 A cross-sectional schematic diagram.

[0017] Explanation of main component symbols

[0018] 12 Base 14 First Region

[0019] 16 Second Region 18 Fin-like Structure

[0020] 22 Shallow trench isolation 24 Patterned hard mask

[0021] 26 Organic dielectric layer 28 Silicon-containing hard mask and anti-reflective layer

[0022] 30 Patterned photoresist 32 First groove

[0023] 34 Second groove 36 Dielectric material

[0024] 38 Buffer layer 40 Part 1

[0025] 42 Part Two 44 Wavy Surface

[0026] 46 Flat surface 48 Curved surface

[0027] 50 Arc Surface 52 Dielectric Layer

[0028] 54 First monodiffusion isolation structure 56 Second monodiffusion isolation structure Detailed Implementation

[0029] Please refer to Figure 1 as well as Figures 2 to 9 ,in Figure 1 This is a top view of a semiconductor device according to a preferred embodiment of the present invention. Figure 2 , Figure 4 , Figure 6 , Figure 8 for Figure 1 A cross-sectional view of a semiconductor device fabricated along the tangent AA' direction. Figure 3 , Figure 5 , Figure 7 , Figure 9 Then it is Figure 1 A schematic cross-sectional view along the tangent BB'. (See diagram below.) Figures 2 to 3As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. Then, a first region 14 and an adjacent second region 16 are defined on the substrate 12. The first region 14 preferably includes fin structures 18 and a portion of shallow trench isolation 22 surrounding the fin structures 18. The second region 16 is preferably the area of ​​shallow trench isolation 22 surrounding the first region 14, and at this stage, the second region 16 only includes shallow trench isolation 22 and has no fin structures. In this embodiment, although four fin structures 18 are used as an example, their number can be adjusted arbitrarily according to product requirements and is not limited to this.

[0030] According to a preferred embodiment of the present invention, the fin structure 18 is preferably fabricated using techniques such as sidewall image transfer (SIT). The procedure generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equally wide patterned sacrificial layers are formed on the substrate using photolithography and etching processes, giving each layer a strip-like appearance. Then, deposition and etching processes are sequentially performed to form spacers on the sidewalls of the patterned sacrificial layers. The patterned sacrificial layers are then removed, and etching is performed under the cover of the spacers, transferring the pattern formed by the spacers into the substrate. Finally, a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0031] In addition, the formation of the fin structure 18 may also include first forming a patterned mask (not shown) on the substrate 12, and then transferring the pattern of the patterned mask to the substrate 12 through an etching process to form the fin structure 18. Alternatively, the fin structure 18 may be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial fabrication process to grow a semiconductor layer, such as silicon-germanium, on the substrate 12 exposed above the patterned hard mask layer. This semiconductor layer can then serve as the corresponding fin structure 18. These embodiments of forming the fin structure 18 are all within the scope of this invention.

[0032] Then, a shallow trench isolation (STI) 22 is formed around the fin structure 18. In this embodiment, the shallow trench isolation 22 is formed by first using a flowable chemical vapor deposition (FCVD) process to form a silicon monoxide layer on the substrate 12 that completely covers the fin structure 18. Then, a portion of the silicon oxide layer is removed using an etching or chemical mechanical polishing (CMP) process, leaving the remaining silicon oxide layer flush with or slightly above the surface of the fin structure 18 to form the shallow trench isolation 22.

[0033] Next, an ion implantation process can be performed to implant the desired N-type or P-type dopant into the fin structure 18, accompanied by a thermal processing step to diffuse the implanted dopant to form the well region (not shown) required for the subsequent fabrication of the semiconductor device.

[0034] Please refer to the following: Figure 4 and Figure 5 , Figure 4 To continue Figure 2 Cross-sectional schematic diagram Figure 5 This is a continuation. Figure 3 A cross-sectional schematic diagram. For example... Figure 4 and Figure 5 As shown, a buffer layer 38 is first applied to the fin structure 18 and the shallow trench isolation 22, and then a mask layer is formed. For example, an organic dielectric layer (ODL) 26, a silicon-containing hard mask bottom anti-reflective coating (SHB) layer 28, and a patterned photoresist 30 are sequentially formed on the buffer layer 38. In this embodiment, the buffer layer 38 preferably contains an oxide such as silicon dioxide, but is not limited thereto.

[0035] Please refer to the following: Figure 6 and Figure 7 , Figure 6 To continue Figure 4 Cross-sectional schematic diagram Figure 7 This is a continuation. Figure 5 A cross-sectional schematic diagram. For example... Figure 6 and Figure 7As shown, subsequently, a portion of the fin-like structures 18 and a portion of the shallow groove isolation 22 within the first region 14 are removed to form a first groove 32, and simultaneously, a portion of the shallow groove isolation 22 beside the fin-like structures 18 or within the second region 16 is removed to form a second groove 34. Preferably, the first groove 32 within the first region 14 divides each fin-like structure 18 into a first part 40 and a second part 42 and is used to define the position of the subsequently formed first single-diffusion isolation structure, such as... Figure 1 As shown, the second groove 34 is used to define the position of the second monodiffusion isolation structure that will be formed subsequently.

[0036] More specifically, the steps for forming the first groove 32 and the second groove 34 mainly include performing a first etching process to remove part of the shallow trench isolation 22, and then performing a second etching process to remove part of the fin structure 18 and the remaining shallow trench isolation 22 to form the first groove 32 and the second groove 34.

[0037] In detail, the first etching process preferably removes a portion of the shallow trench isolation 18 and makes the upper surface of the shallow trench isolation 22 slightly lower than the upper surface of the fin structure 18. Since the second region 16 does not have the fin structure 18, the first etching process performed at this stage preferably removes a portion of the shallow trench isolation 22 in the first region 14 and makes the upper surface of the shallow trench isolation 22 slightly lower than the upper surface of the fin structure 18, but only removes a portion of the shallow trench isolation 22 in the second region 16. In this embodiment, the first etching process may use carbon tetrafluoride (CF4), trifluoromethane (CHF3), or a combination thereof to remove a portion of the shallow trench isolation 22 and a smaller portion of the fin structure 18. In this embodiment, during the first etching process, the etching selectivity ratio between silicon and silicon oxide is preferably adjusted to about 0.9 to 1, so that more of the shallow trench isolation 22 composed of silicon oxide and less of the fin structure 18 composed of silicon can be removed, and the remaining upper surface of the shallow trench isolation 22 is slightly lower than the upper surface of the fin structure 18.

[0038] The second etching process employs, for example, hydrogen bromide (HBr), CF4, or a combination thereof, to simultaneously remove more of the fin structures 18 and the remaining shallow trench isolation 22. Since the upper surface of the remaining shallow trench isolation 22 in the first region 14 is slightly lower than the upper surface of the fin structures 18 during the first etching process, the present invention preferably adjusts the silicon-to-silicon oxide etching selectivity ratio to approximately 2:1 at this stage, thereby removing more of the silicon-based fin structures 18 and less of the silicon-based shallow trench isolation 22. Similar to the first etching process, since the second region 16 only has shallow trench isolation 22, the second etching process also removes only a portion of the shallow trench isolation 22 within the second region 16.

[0039] According to a preferred embodiment of the present invention, since the first region 14 is provided with both the fin structure 18 and the shallow trench isolation 22, while the second region 16 only has the shallow trench isolation 22, the lower surface of the first groove 32 formed after the above-described first etching process and second etching process preferably has an uneven surface or more specifically a wavy surface 44, while the lower surface of the second groove 34 includes a flat surface 46. It should be noted that since the second etching process has a much higher etching selectivity for silicon than for silicon oxide, the bottom of the wavy surface or arc surface 48 formed at the bottom of the first groove 32 due to the removal of the fin structure 18 is preferably lower than the bottom of the adjacent arc surface 50 formed due to the removal of the shallow trench isolation 22.

[0040] Please refer to the following: Figure 8 and Figure 9 , Figure 8 To continue Figure 6 Cross-sectional schematic diagram Figure 9 This is a continuation. Figure 7 A cross-sectional schematic diagram. For example... Figure 8 and Figure 9 As shown, a dielectric layer 52 is then formed and filled in the first groove 32 and the second groove 34. Next, a planarization process, such as etch-back or chemical mechanical polishing, is used to remove a portion of the dielectric layer 52, aligning the remaining dielectric layer 52 with the upper surface of the buffer layer 38 to form a first single-diffusion isolation structure 54 and a second single-diffusion isolation structure 56. Furthermore, according to one embodiment of the invention, the remaining buffer layer 38 can be removed simultaneously with the removal of the portion of the dielectric layer 52, aligning the upper surface of the remaining dielectric layer 52 with the upper surface of the shallow trench isolation 22. In this embodiment, the dielectric layer 52 and the shallow trench isolation 22 preferably contain different materials; for example, the dielectric layer 52 filling the first groove 32 and the second groove 34 preferably contains silicon nitride, while the shallow trench isolation 22 contains silicon oxide, but this is not a limitation.

[0041] Subsequently, depending on the fabrication process requirements, subsequent fabrication processes, such as those for fin structure transistors, can be performed. For example, gate structures (not shown) spanning the fin structure 18 can be formed on the first portion 40 and the second portion 42 of the fin structure 18 within the first region 14, spacers can be formed around the gate structures, and source / drain regions can be formed on both sides of the spacers, for example, within the first portion 40 and the second portion 42. Since the fabrication of fin structure transistors is a well-known technique in the art, it will not be described in detail here.

[0042] Please refer to the following at the same time: Figure 1 and Figures 8 to 9 The invention further discloses a semiconductor device structure according to an embodiment of the present invention. For example... Figure 1 and Figure 8As shown, the semiconductor device of the present invention mainly includes fin structures 18 extending in a first direction (e.g., the X direction) on a substrate 12, and each fin structure 18 includes a first portion 40 and a second portion 42, a shallow trench isolation 22 surrounding the fin structure 18, a first monodiffusion isolation structure 54 extending in a second direction (e.g., the Y direction) between the first portion 40 and the second portion 42, and a second monodiffusion isolation structure 56 extending in a second direction within the shallow trench isolation 22 and disposed beside the fin structure 18.

[0043] More specifically, a first region 14 and a second region 16 are defined on the substrate 12. The first region 14 contains at least one fin-like structure 18, a first monodiffusion isolation structure 54, and a shallow trench isolation 22 surrounding the fin-like structure 18. The second region 16 contains only a second monodiffusion isolation structure 56 and a shallow trench isolation 22, but no fin-like structure. In this embodiment, the first monodiffusion isolation structure 54 and the shallow trench isolation 22 preferably contain different materials, and the second monodiffusion isolation structure 56 and the shallow trench isolation 22 preferably contain the same material. The shallow trench isolation 22 contains silicon dioxide, while both the first monodiffusion isolation structure 54 and the second monodiffusion isolation structure 56 contain silicon nitride.

[0044] It should also be noted that although the first single-diffusion isolation structure 54 and the second single-diffusion isolation structure 56 are arranged in parallel within the first region 14 and the second region 16, and the upper and lower surfaces of the first single-diffusion isolation structure 54 are aligned with the upper and lower surfaces of the second single-diffusion isolation structure 56, this arrangement is not limited to this. The present invention can also adjust the number, length and position of the second single-diffusion isolation structure 56 according to product requirements. For example, multiple second single-diffusion isolation structures 56 can be set to extend along the Y direction within the shallow trench isolation 22 of the second region 16, and each second single-diffusion isolation structure 56 can have the same or different lengths as the first single-diffusion isolation structure 54.

[0045] In addition, in this embodiment, particularly as Figure 8 and Figure 9 As shown in the cross-sectional structure, the lower surface of the first monodiffusion isolation structure 54 in the first region 14 preferably includes a wavy surface 44, while the second monodiffusion isolation structure 56 in the second region 16 includes a flat surface 46. The wavy surface 44 preferably includes multiple arc surfaces 48 and arc surfaces 50 with different curvatures or depths. Since the wavy surface 44 is located between the first monodiffusion isolation structure 54 and the substrate 12, from another perspective, in addition to the wavy surface on the lower surface of the first monodiffusion isolation structure 54, the surface of the substrate 12 also has a wavy surface.

[0046] Generally, the fabrication of a single-diffusion isolation structure mainly involves first using etching to divide at least one fin-like structure into two parts to form a groove, and then filling the groove with a dielectric material such as silicon nitride to form a single-diffusion isolation structure. However, due to etching technology considerations, the formed single-diffusion isolation structure often shrinks inward, preventing the fin-like structure from being completely separated, resulting in the phenomenon known as etching bias. In view of this, the present invention mainly forms one or more dummy single-diffusion isolation structures (i.e., the second single-diffusion isolation structure 56 in the above embodiment) within the shallow trench isolation around the fin-like structure while fabricating a general single-diffusion isolation structure (i.e., the first single-diffusion isolation structure 54 in the above embodiment), and improves the above-mentioned etching bias problem by filling the dummy single-diffusion isolation structures.

[0047] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor element comprising: A fin-like structure extending along a first direction on a base, the fin-like structure comprising a first portion and a second portion; Shallow grooves isolate and surround the fin-like structure; A first monodiffusion isolation structure extends between the first portion and the second portion along a second direction different from the first direction; and At least one second monodiffusion isolation structure extends along the second direction within the shallow trench isolation and is disposed beside the fin structure, wherein in the first direction, the second portion is located between the first monodiffusion isolation structure and the at least one second monodiffusion isolation structure and is spaced apart from the at least one second monodiffusion isolation structure.

2. The semiconductor device of claim 1, wherein the lower surface of the first monodiffusion isolation structure includes a wavy surface.

3. The semiconductor device of claim 1, wherein the lower surface of the at least one second monodiffusion isolation structure comprises a flat surface.

4. The semiconductor device of claim 1, wherein the at least one second monodiffusion isolation structure comprises a plurality of second monodiffusion isolation structures.

5. The semiconductor device of claim 1, wherein the length of the at least one second monodiffusion isolation structure is the same as or different from the length of the first monodiffusion isolation structure.

6. The semiconductor device of claim 1, wherein the shallow trench isolation comprises silicon dioxide.

7. The semiconductor device of claim 1, wherein the material contained in the first monodiffusion isolation structure and / or the material contained in the at least one second monodiffusion isolation structure is different from the material contained in the shallow trench isolation.

8. The semiconductor device of claim 1, wherein the first monodiffusion isolation structure and the at least one second monodiffusion isolation structure comprise the same material.

9. The semiconductor device of claim 1, wherein the first single-diffusion isolation structure and the at least one second single-diffusion isolation structure comprise silicon nitride.

10. The semiconductor device of claim 1, wherein the upper surface of the first monodiffusion isolation structure is flush with the upper surface of the at least one second monodiffusion isolation structure.

11. The semiconductor device of claim 10, wherein the upper surface of the first monodiffusion isolation structure is flush with the upper surface of the shallow trench isolation.

12. The semiconductor device of claim 10, further comprising a buffer layer located on the shallow trench isolation, wherein the upper surface of the first monodiffusion isolation structure is flush with the upper surface of the buffer layer.

13. The semiconductor element of claim 1, wherein the first direction is perpendicular to the second direction.

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