Semiconductor device and electronic apparatus

Abstract

The application provides a semiconductor device and an electronic device; the semiconductor device comprises a thin film transistor, the thin film transistor comprises a substrate, a buffer layer and an active layer, the buffer layer is arranged on one side of the substrate, and the active layer is arranged on the side of the buffer layer away from the substrate, wherein the semiconductor device further comprises a metal layer, the metal layer is arranged on the side of the active layer facing the buffer layer, the metal layer comprises at least one metal block, and the metal block is in direct contact with at least part of the active layer. According to the application, the metal layer is arranged on the side of the active layer facing the buffer layer, the metal layer comprises at least one metal block, the metal block is in direct contact with at least part of the active layer, and when the active layer is converted from amorphous silicon into polycrystalline silicon, the size of the crystal grains in the polycrystalline silicon is large due to the catalysis of the metal block, the grain boundary in the polycrystalline silicon is reduced, and the mobility of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a semiconductor device and an electronic apparatus. Background Art

[0002] With the advancement of display technology, existing display devices are placing increasingly stringent demands on narrow bezels, high aperture ratios, high brightness, and high resolution. Consequently, it is necessary to maintain good on-state current while reducing the size of thin-film transistors. Existing semiconductor devices use polycrystalline silicon as the active layer to improve carrier mobility and thus increase on-state current. However, due to process limitations in the polycrystalline silicon preparation process, the polycrystalline silicon formed after laser annealing has a small grain size, resulting in low carrier mobility and, consequently, low on-state current in the semiconductor device, which cannot meet these requirements.

[0003] Therefore, existing semiconductor devices have a technical problem of low mobility of the semiconductor device due to the small grain size of polysilicon formed due to process limitations. Summary of the Invention

[0004] Embodiments of the present application provide a semiconductor device and an electronic apparatus to alleviate the technical problem of low mobility of the semiconductor device caused by the small grain size of polysilicon formed due to process limitations in existing semiconductor devices.

[0005] The present invention provides a semiconductor device.

[0006] A thin film transistor, comprising:

[0007] substrate;

[0008] a buffer layer, disposed on one side of the substrate;

[0009] an active layer, disposed on a side of the buffer layer away from the substrate;

[0010] The semiconductor device further includes a metal layer, which is arranged on a side of the active layer facing the buffer layer. The metal layer includes at least one metal block, and the metal block is in direct contact with at least a portion of the active layer.

[0011] In some embodiments, a groove is provided in a region of the buffer layer in contact with the active layer, and the metal block is disposed in the groove.

[0012] In some embodiments, the melting point of the material of the metal layer is less than 1410 degrees Celsius.

[0013] In some embodiments, the material of the metal layer includes at least one of aluminum, nickel, gallium, and indium.

[0014] In some embodiments, the semiconductor device includes a plurality of thin film transistors, and an active layer of at least one of the thin film transistors has no grain boundaries.

[0015] In some embodiments, the active layer of the thin film transistor includes first crystal grains, the first crystal grains are arranged corresponding to the metal blocks, and the number of the first crystal grains is equal to the number of the metal blocks.

[0016] In some embodiments, the first grains are round or quasi-round in shape, and have a diameter of 1 micrometer to 5 micrometers.

[0017] In some embodiments, the thin film transistor includes a plurality of first crystal grains, the metal layer includes metal blocks arranged in an array, and a grain boundary of the first crystal grains is located between two adjacent metal blocks.

[0018] In some embodiments, the active layer includes a channel portion and a first doped portion and a second doped portion located on both sides of the channel portion, and the shape of the first doped portion and the second doped portion along the line connecting the channel portion is the same as the shape of the metal blocks corresponding to the first doped portion and the second doped portion of the thin film transistor along the line connecting the channel portion.

[0019] In some embodiments, a line connecting the first doping portion and the second doping portion along the channel portion is in the shape of a straight line, and the metal blocks are arranged along the straight line array.

[0020] In some embodiments, the first doping portion and the second doping portion are located on the same horizontal line, a line connecting the first doping portion and the second doping portion along the channel portion is in the shape of a fold line, and the metal blocks are arranged along the fold line array.

[0021] In some embodiments, the channel portion includes a first portion arranged in a perpendicular direction of the first doped portion, a second portion arranged in a perpendicular direction of the second doped portion, and a third portion vertically connected to the first portion and the second portion. The first doped portion and the second doped portion are arranged along the first portion, the third portion, and the second portion along the line connecting the channel portions, and the metal block is arranged in an array along the first portion, the third portion, and the second portion.

[0022] In some embodiments, the channel portion includes a fourth portion and a fifth portion connecting the first doped portion and the second doped portion, the fourth portion and the fifth portion are vertically arranged, and the metal blocks are arranged in an array along the direction of the fourth portion and the fifth portion.

[0023] In some embodiments, a diameter of the first grain is equal to a distance between center points of adjacent metal blocks.

[0024] At the same time, an embodiment of the present application provides an electronic device, which includes the semiconductor device as described in any of the above embodiments.

[0025] Beneficial Effects: The present application provides a semiconductor device and an electronic device; the semiconductor device includes a thin film transistor, which includes a substrate, a buffer layer, and an active layer, wherein the buffer layer is disposed on one side of the substrate, and the active layer is disposed on a side of the buffer layer away from the substrate. The semiconductor device further includes a metal layer, which is disposed on a side of the active layer facing the buffer layer, and the metal layer includes at least one metal block, and the metal block is in direct contact with at least a portion of the active layer. The present application provides a metal layer on a side of the active layer facing the buffer layer, wherein the metal layer includes at least one metal block, and the metal block is in direct contact with at least a portion of the active layer. Therefore, when the active layer is converted from amorphous silicon to polycrystalline silicon, the catalytic effect of the metal block increases the size of the polycrystalline silicon grains, reduces the grain boundaries in the polycrystalline silicon, and improves the mobility of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0027] Figure 1 This is a first schematic diagram of a semiconductor device provided in an embodiment of the present application.

[0028] Figure 2 This is a second schematic diagram of a semiconductor device provided in an embodiment of the present application.

[0029] Figure 3 This is a first schematic diagram of the active layer provided in an embodiment of the present application.

[0030] Figure 4 This is a second schematic diagram of the active layer provided in an embodiment of the present application.

[0031] Figure 5 This is a third schematic diagram of the active layer provided in an embodiment of the present application.

[0032] Figure 6 This is a first structural diagram of a semiconductor device corresponding to each step of the semiconductor device manufacturing method provided in an embodiment of the present application.

[0033] Figure 7 A second structural diagram of the semiconductor device corresponding to each step of the semiconductor device manufacturing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0035] The embodiments of the present application provide a semiconductor device and an electronic device to alleviate the technical problem of low mobility of semiconductor devices caused by small grain size of polysilicon formed due to process limitations of existing semiconductor devices, so as to alleviate the above technical problem.

[0036] like Figure 1 As shown, an embodiment of the present application provides a semiconductor device. The semiconductor device 1 includes a thin film transistor 10. The thin film transistor 10 includes:

[0037] substrate 11;

[0038] a buffer layer 13, disposed on one side of the substrate 11;

[0039] an active layer 15 , disposed on a side of the buffer layer 13 away from the substrate 11 ;

[0040] The semiconductor device 1 further includes a metal layer 14 , which is disposed on a side of the active layer 15 facing the buffer layer 13 . The metal layer 14 includes at least one metal block, and the metal block is in direct contact with at least a portion of the active layer 15 .

[0041] An embodiment of the present application provides a semiconductor device, which is configured by arranging a metal layer on the side of the active layer facing the buffer layer, wherein the metal layer includes at least one metal block, so that the metal block is in direct contact with at least a portion of the active layer. When the active layer is converted from amorphous silicon to polycrystalline silicon, the catalytic effect of the metal block increases the size of the grains in the polycrystalline silicon, reduces the grain boundaries in the polycrystalline silicon, and improves the mobility of the semiconductor device.

[0042] It should be noted that, in the drawings of the present application, since grain boundaries can be seen microscopically, the positions and schematic shapes of the grain boundaries are shown with solid lines in the drawings of the present application.

[0043] In one embodiment, the metal block is disposed between the buffer layer and the active layer. By disposing the metal block between the buffer layer and the active layer, the metal block can catalyze the reaction of amorphous silicon during the formation of polycrystalline silicon. The metal block acts as a crystal nucleus, increasing the width of the formed grains, thereby reducing the number of grain boundaries and improving the mobility of the semiconductor device.

[0044] To address the problem that placing a metal block between the buffer layer and the active layer reduces the thickness of the active layer, thereby affecting the electrical properties of the active layer, in one embodiment, the buffer layer is provided with a groove in the area in contact with the active layer, and the metal block is disposed within the groove. By providing a groove in the buffer layer and positioning the metal block within the groove, the surface of the active layer in contact with the buffer layer and the metal block remains flat, improving the electrical properties of the active layer. The metal block also acts as a catalyst, increasing the width of the crystal grains in the active layer, reducing the number of grain boundaries, and improving the mobility of the semiconductor device.

[0045] Specifically, the material of the buffer layer includes silicon nitride, silicon oxide, or a stack of silicon nitride and silicon oxide.

[0046] Specifically, the thickness of the buffer layer ranges from 0.3 micrometers to 1 micrometer.

[0047] Specifically, the groove depth ranges from 0.05 microns to 0.5 microns, the groove width ranges from 0.5 microns to 2 microns, the spacing between adjacent edges of adjacent grooves ranges from 0.5 microns to 3 microns, and the spacing between the midpoints of adjacent grooves ranges from 1 micron to 5 microns. By setting the groove depth range from 0.05 to 0.5 microns, the thickness of the buffer layer formed in the grooves is reduced due to excessive groove depth, thereby improving the buffer layer's ability to block water and oxygen. The groove width ranges from 0.5 microns to 2 microns, allowing metal blocks to be placed within the grooves to catalyze the active layer and reduce grain boundaries. Setting the spacing between adjacent edges of adjacent grooves to 0.5 microns to 3 microns and the spacing between the midpoints of adjacent grooves to 1 micron to 5 microns allows the metal blocks to have a certain period, resulting in larger grains and fewer grain boundaries.

[0048] In one embodiment, the melting point of the material of the metal layer is less than 1410 degrees Celsius. By using a material with a melting point less than 1410 degrees Celsius as the material of the metal layer, the melting point of the metal layer is lower than the melting point of silicon, and the metal layer easily forms a solid solution with silicon. Therefore, during the process of converting amorphous silicon into polycrystalline silicon, the metal layer catalyzes the reaction process, increases the size of the polycrystalline silicon grains, and reduces grain boundaries.

[0049] In one embodiment, the metal layer comprises one of aluminum, nickel, gallium, and indium. By using aluminum, nickel, gallium, or indium as the material for the metal layer, the metal layer easily forms a solid solution with silicon. Thus, during the conversion of amorphous silicon to polycrystalline silicon, the metal layer catalyzes the reaction, thereby increasing the size of the polycrystalline silicon grains and reducing grain boundaries.

[0050] To address the problem of low mobility in semiconductor devices caused by a high number of polycrystalline silicon grain boundaries, in one embodiment, the semiconductor device includes multiple thin-film transistors, at least one of which has an active layer without grain boundaries. By eliminating grain boundaries in the active layer of the thin-film transistor, particles are not blocked by grain boundaries during migration, thereby improving the mobility of the semiconductor device.

[0051] Specifically, such as Figure 2 As shown, the metal layer 14 includes a metal block, and the active layer 15 includes single-crystal silicon, with a diameter of less than 5 microns. When the width of the active layer is less than 5 microns, a metal block can be placed below the active layer to catalyze the conversion of amorphous silicon into single-crystal silicon. This results in only one crystal grain, eliminating grain boundaries within the active layer and improving the mobility of the semiconductor device.

[0052] In one embodiment, if Figure 1 、 Figure 3 As shown, the active layer 15 of the thin film transistor 10 includes first crystal grains 151. The first crystal grains 151 are arranged corresponding to the metal blocks 141, and the number of the first crystal grains 151 is equal to the number of the metal blocks 141. By arranging the first crystal grains corresponding to the metal blocks and the number of the first crystal grains being equal to the number of the metal blocks, the first crystal grains are formed under the catalysis of the metal blocks, and the first crystal grains have a larger diameter, which reduces the number of grain boundaries and improves the mobility of the semiconductor device.

[0053] Specifically, when amorphous silicon is converted into polycrystalline silicon through a laser annealing process, first grains are formed by the catalysis of metal blocks. Even if there are still grains with a diameter smaller than the first grains between the first grains due to process limitations, since the diameter of the first grains is larger, the number of grain boundaries in the active layer can still be reduced, thereby improving the mobility of the semiconductor device.

[0054] In one embodiment, the first grains are circular or quasi-circular, and have a diameter of 1 to 5 microns. By setting the diameter of the first grains to 1 to 5 microns, the first grains are larger, the number of grain boundaries is reduced, and the mobility of the semiconductor device is improved.

[0055] Specifically, such as Figure 1 、 Figure 3As shown, the metal layer 14 includes metal blocks 141 arranged in an array, and the active layer 15 includes a plurality of first crystal grains 151. The number of the metal blocks 141 is equal to the number of the first crystal grains 151, and the grain boundaries 152 of the first crystal grains are located between two adjacent metal blocks 141. By making the number of metal blocks equal to the number of first crystal grains, each first crystal grain is formed through the catalysis of the metal blocks, and the width of each first crystal grain is larger, thereby reducing the number of grain boundaries and improving the mobility of the semiconductor device. The first crystal grains will grow in all directions along the position of the metal blocks, so that the grain boundaries of the first crystal grains are located between two adjacent metal blocks. By adjusting the spacing between the metal blocks, the width of the first crystal grains can be adjusted, thereby reducing the number of grain boundaries and improving the mobility of the semiconductor device.

[0056] Specifically, the thickness of the metal layer ranges from 0.05 microns to 0.5 microns. By setting the thickness of the metal layer to 0.05 microns to 0.5 microns, it is avoided that the thickness of the metal layer is too large, resulting in a small thickness of the buffer layer, and water and oxygen invading from the position where the buffer layer is thin.

[0057] Specifically, the spacing between the metal blocks is 1 micron to 5 microns. By making the array period of the metal blocks 1 micron to 5 microns, the width of the grains is 1 micron to 5 microns, increasing the width of the grains, reducing the number of grain boundaries, and improving the mobility of the semiconductor device.

[0058] Specifically, the width of the metal block ranges from 0.5 microns to 2 microns. When setting the metal block, if the width of the metal block is too small, the width of the grain will be smaller, resulting in a larger number of grain boundaries and a lower mobility of the semiconductor device. If the width of the metal block is too large, the aperture ratio of the display panel will be lower, affecting the transmittance of the display panel. When the width of the metal block is large, there may be multiple nucleation sites on the metal block, resulting in a metal block forming multiple grains, making the width of the grain smaller and the number of grain boundaries more. Therefore, the width of the metal block is set to 0.5 microns to 2 microns, and the period of adjacent metal arrays is controlled to 1 micron to 5 microns, and grains with a grain width of 1 micron to 5 microns are prepared, so that the width of the formed grains is larger, the number of grain boundaries is smaller, and the mobility of the semiconductor device is improved.

[0059] In one embodiment, if Figure 3As shown, the active layer 15 includes a channel portion 251 and a first doped portion 252 and a second doped portion 253 located on either side of the channel portion 251. The shape of the first doped portion 252 and the second doped portion 253 along the line connecting the channel portion 251 is identical to the shape of the metal block 141 corresponding to the first doped portion 252 and the second doped portion 253 of the thin film transistor along the line connecting the channel portion. By making the shape of the first doped portion and the second doped portion along the line connecting the channel portion identical to the shape of the metal block corresponding to the first doped portion and the second doped portion of the thin film transistor along the line connecting the channel portion, for active layers with different configurations, the width of the grains in the active layer located in the channel portion, the first doped portion, and the second doped portion can be increased by changing the configuration of the metal array, thereby reducing the number of grain boundaries and improving the mobility of the semiconductor device.

[0060] Specifically, compared to using amorphous silicon as a catalyst to increase the grain size, since the metal blocks can be arranged in an array in the present application and the spacing and width of the metal blocks can be set according to the required shape of the active layer, the width of the grains of the active layer can be larger and the number of grain boundaries can be smaller. When the width of the active layer is small, single crystal silicon can also be formed to improve the mobility of the semiconductor device.

[0061] In one embodiment, if Figure 3 As shown, the line connecting the first doped portion 252 and the second doped portion 253 along the channel portion 251 is in the shape of a straight line, and the metal blocks 141 are arranged along the straight line array. By arranging the metal blocks along the straight line array, the grains in the area where the metal blocks are located can grow along the direction of the metal blocks, resulting in a larger grain width and a smaller number of grain boundaries, thereby improving the mobility of the semiconductor device.

[0062] Specifically, such as Figure 3 As shown in (a) in the figure, when forming the active layer, the amorphous silicon layer is processed to obtain the polysilicon layer 25. Specifically, the amorphous silicon layer can be processed by laser annealing. Since the metal block 141 is provided in the region of the active layer 15, the grains of the active layer 15 grow faster under the catalysis of the metal block 141, and the width of the grains is larger. However, since there is no metal block in the region outside the active layer 15, the width of the grains in the ineffective portion 26 is smaller and the number of grain boundaries is larger. Then, the polysilicon layer is etched, as shown in FIG. Figure 3As shown in (b), the ineffective part 26 is removed and the pattern of the active layer is formed to obtain the active layer 15. At this time, the shape of the line connecting the first doping part and the second doping part along the channel part is the same as the shape of the metal block corresponding to the first doping part and the second doping part along the channel part. The channel part, the first doping part and the second doping part are arranged along the setting direction of the metal block to obtain an active layer with an "in-line channel", and the width of the grains of the active layer is large, the number of grain boundaries is small, and the mobility of the semiconductor device is high.

[0063] In one embodiment, if Figure 4 As shown, the first doping portion 252 and the second doping portion 253 are located on the same horizontal line. The line connecting the first doping portion 252 and the second doping portion 253 along the channel portion 251 is in the shape of a zigzag line, and the metal blocks 141 are arranged along the zigzag line array. By arranging the metal blocks along the zigzag line array, the channel portion, the first doping portion, and the second doping portion can be formed into the shape of the metal blocks. Due to the catalytic effect of the metal blocks, the width of the grains in the channel portion, the first doping portion, and the second doping portion is larger and the number of grain boundaries is reduced, thereby improving the mobility of the semiconductor device.

[0064] In one embodiment, if Figure 4 As shown, the channel portion 251 includes a first portion arranged in a direction perpendicular to the first doped portion 252, a second portion arranged in a direction perpendicular to the second doped portion 253, and a third portion perpendicularly connected to the first and second portions. The first doped portion 252 and the second doped portion 253 are arranged along the first portion, the third portion, and the second portion along the line connecting the channel portion 251, and the metal block 141 is arranged in an array along the first portion, the third portion, and the second portion. By making the metal block include a portion arranged in a horizontal direction, a portion perpendicular to the horizontally arranged portion, and a connecting portion, the formed channel portion, the first doped portion, and the second doped portion can be formed into the shape formed by the metal block. Due to the catalytic effect of the metal block, the width of the grains of the channel portion, the first doped portion, and the second doped portion is larger and the number of grain boundaries is smaller, thereby improving the mobility of the semiconductor device.

[0065] Specifically, such as Figure 4 As shown in (a) in the figure, when forming the active layer, the amorphous silicon layer is processed to obtain the polysilicon layer 25. Specifically, the amorphous silicon layer can be processed by laser annealing. Since the metal block 141 is provided in the region of the active layer 15, the grains of the active layer 15 grow faster under the catalysis of the metal block 141, and the width of the grains is larger. However, since there is no metal block in the region outside the active layer 15, the width of the grains in the ineffective portion 26 is smaller and the number of grain boundaries is larger. Then, the polysilicon layer is etched, as shown in FIG. Figure 4 As shown in (b), the ineffective portion 26 is removed and a pattern of the active layer is formed to obtain an active layer 15. At this time, the channel portion, the first doping portion and the second doping portion of the active layer are arranged along the setting direction of the metal block to obtain an active layer with an "X-shaped channel". The width of the grains of the active layer is large, the number of grain boundaries is small, and the mobility of the semiconductor device is high.

[0066] In one embodiment, if Figure 5 As shown, the channel portion 251 includes a fourth portion and a fifth portion connecting the first doped portion 252 and the second doped portion 253. The fourth and fifth portions are arranged perpendicularly, and the metal blocks 141 are arranged in an array along the fourth and fifth portions. By having the metal blocks include mutually perpendicular portions, the active layer can be formed along the metal blocks during formation. Due to the catalytic effect of the metal blocks, the grains of the channel portion, the first doped portion, and the second doped portion have larger widths and fewer grain boundaries, thereby improving the mobility of the semiconductor device.

[0067] Specifically, such as Figure 5 As shown in (a) in the figure, when forming the active layer, the amorphous silicon layer is processed to obtain the polysilicon layer 25. Specifically, the amorphous silicon layer can be processed by laser annealing. Since the metal block 141 is provided in the region of the active layer 15, the grains of the active layer 15 grow faster under the catalysis of the metal block 141, and the width of the grains is larger. However, since there is no metal block in the region outside the active layer 15, the width of the grains in the ineffective portion 26 is smaller and the number of grain boundaries is larger. Then, the polysilicon layer is etched, as shown in FIG. Figure 5 As shown in (b), the ineffective portion 26 is removed and a pattern of the active layer is formed to obtain an active layer 15. At this time, the channel portion, the first doping portion and the second doping portion of the active layer are arranged along the setting direction of the metal block to obtain an active layer with an "L-shaped channel". The width of the grains of the active layer is large, the number of grain boundaries is small, and the mobility of the semiconductor device is high.

[0068] It should be noted that in Figure 3 、 Figure 4 and Figure 5 In the process, no metal block is set under the polysilicon outside the active layer. The width of the polysilicon grains outside the active layer is smaller and the number of grain boundaries is larger, but the embodiments of the present application are not limited to this. For example, a metal block can also be set under the polysilicon outside the active layer.

[0069] In one embodiment, if Figure 1As shown, the diameter L1 of the first crystal grain is equal to the spacing L2 between the center points of adjacent metal blocks. By making the spacing between the center points of the metal blocks equal to the diameter of the first crystal grain, the width of the crystal grains in the active layer can be adjusted by the spacing and width of the metal blocks, thereby reducing the number of grain boundaries in the active layer and improving the mobility of the semiconductor device.

[0070] Specifically, the metal blocks are arranged at equal intervals. When the cross section of the first crystal grain is a trapezoid, the diameter of the first crystal grain refers to the width at the center line of the trapezoid.

[0071] Specifically, the above embodiment is described in detail using the example of metal blocks being arranged at equal spacing, but the embodiments of the present application are not limited thereto. For example, when the grain widths required for the channel portion and the doping portion are different, the spacing of the metal blocks can be made unequal, and the sizes of the metal blocks can be made unequal, so that the grain widths of the channel portion and the doping portion can be made different.

[0072] Specifically, compared to the current semiconductor device method of increasing grain width by placing amorphous silicon within a buffer layer and then depositing amorphous silicon, which results in an increase in amorphous silicon thickness and, during laser annealing, increases nucleation sites within the buffer layer, which easily leads to an increase in the number of grains, but with little significant effect on increasing grain size, the present embodiment uses metal blocks as catalysts. Because the metal blocks are made of different materials than amorphous silicon, they do not combine with amorphous silicon, causing an increase in amorphous silicon thickness and performance changes. Furthermore, the metal blocks, unlike amorphous silicon, do not increase nucleation sites, increasing grain width, reducing the number of grain boundaries, and improving the mobility of the semiconductor device. Furthermore, compared to using amorphous silicon to increase grain width, the metal blocks used in the present invention can be arranged in an array, with the spacing and width of the metal blocks set according to the shape of the active layer, reducing the number of grain boundaries within the active layer. When the width of the active layer is small, single crystal silicon can also be obtained, thereby improving the mobility of the semiconductor device.

[0073] In one embodiment, if Figure 1 As shown, the semiconductor device 1 further includes a light shielding layer 12 , and the light shielding layer 12 is provided corresponding to the active layer 15 .

[0074] In one embodiment, if Figure 1As shown, the semiconductor device 1 also includes a gate insulating layer 16, a gate layer 17, an interlayer insulating layer 18, a source and drain electrode layer 19, a planarizing layer 20, a first electrode layer 21, a passivation layer 22 and a second electrode layer 23. The gate insulating layer 16 is arranged on the side of the active layer 15 away from the buffer layer 13, the gate layer 17 is arranged on the side of the gate insulating layer 16 away from the active layer 15, the interlayer insulating layer 18 is arranged on the side of the gate layer 17 away from the gate insulating layer 16, the source and drain electrode layer 19 is arranged on the side of the interlayer insulating layer 18 away from the gate layer 17, the planarizing layer 20 is arranged on the side of the source and drain electrode layer 19 away from the interlayer insulating layer 18, the first electrode layer 21 is arranged on the side of the planarizing layer 20 away from the source and drain electrode layer 19, the passivation layer 22 is arranged on the side of the first electrode layer 21 away from the planarizing layer 20, and the second electrode layer 23 is arranged on the side of the passivation layer 22 away from the first electrode layer 21.

[0075] At the same time, an embodiment of the present application provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device comprising:

[0076] A substrate is provided, and a light shielding layer is formed on the substrate, a buffer layer is deposited on the light shielding layer, and a groove is formed by an exposure, development and etching process; the structure of the semiconductor device corresponding to this step is as follows Figure 6 As shown in (a);

[0077] Then a metal layer is deposited on the buffer layer; the structure of the semiconductor device corresponding to this step is as follows Figure 6 As shown in (b);

[0078] Specifically, such as Figure 6 As shown in (b) in FIG. 1 , when the metal film 24 is deposited on the buffer layer, since the buffer layer is provided with grooves, the metal 24 will form metal blocks at the positions where the grooves are formed.

[0079] Then a photoresist is formed on the metal layer; the structure of the semiconductor device corresponding to this step is as follows Figure 6 As shown in (c);

[0080] Specifically, such as Figure 6 As shown in (c) in FIG. 1 , by providing a photoresist 35 , the semiconductor device can be leveled, which facilitates subsequent manufacturing processes.

[0081] Then, the photoresist and the metal film on the buffer layer are etched on the entire surface by dry etching, and the etching process is controlled so that the etching is stopped after the metal outside the groove is etched, and the metal inside the groove is retained; the structure of the semiconductor device corresponding to this step is as follows Figure 6 As shown in (d);

[0082] Then an amorphous silicon layer is deposited on the buffer layer; the structure of the semiconductor device corresponding to this step is as follows Figure 7 As shown in (a);

[0083] Specifically, such as Figure 7 As shown in (a) in FIG. 4 , by forming an amorphous silicon layer 41 on the buffer layer, polycrystalline silicon can be formed through the amorphous silicon layer.

[0084] Then, the amorphous silicon layer is laser annealed to transform the amorphous silicon layer into a polycrystalline silicon layer. The structure of the semiconductor device corresponding to this step is as follows: Figure 7 As shown in (b);

[0085] Specifically, such as Figure 7 As shown in (b), when the amorphous silicon layer is transformed into the polysilicon layer 25, the width of the polysilicon grains is different for the area where the metal blocks exist and the area where the metal blocks do not exist, and the number of the polysilicon grain boundaries is different. The width of the polysilicon grains in the area where the metal blocks exist is larger and the number of the grain boundaries is smaller, so that when the active layer is formed, the width of the grains of the active layer is larger and the number of the grain boundaries is smaller, thereby improving the mobility of the semiconductor device.

[0086] Specifically, this step is described by taking the transformation of an amorphous silicon layer into a polycrystalline silicon layer as an example, but the embodiments of the present application are not limited thereto. For example, an amorphous silicon layer can be transformed into a single crystal silicon layer.

[0087] Then the polysilicon layer is exposed, developed and etched to form an active layer; the structure of the semiconductor device corresponding to this step is as follows Figure 7 As shown in (c);

[0088] Then, a gate insulating layer, a gate layer, an interlayer insulating layer, a source and drain electrode layer, a planarization layer, a first electrode layer, a passivation layer and a second electrode layer are formed on the active layer to obtain a semiconductor device.

[0089] At the same time, an embodiment of the present application provides an electronic device, which includes the semiconductor device as described in any of the above embodiments.

[0090] Specifically, the electronic device may be a liquid crystal display panel or an organic light emitting diode display panel.

[0091] According to the above embodiments, it can be seen that:

[0092] Embodiments of the present application provide a semiconductor device and an electronic device; the semiconductor device includes a thin film transistor, which includes a substrate, a buffer layer, and an active layer, wherein the buffer layer is disposed on one side of the substrate, and the active layer is disposed on a side of the buffer layer away from the substrate. The semiconductor device also includes a metal layer, which is disposed on a side of the active layer facing the buffer layer. The metal layer includes at least one metal block, and the metal block is in direct contact with at least a portion of the active layer. The present application provides a metal layer on a side of the active layer facing the buffer layer, wherein the metal layer includes at least one metal block, and the metal block is in direct contact with at least a portion of the active layer. Therefore, when the active layer is converted from amorphous silicon to polycrystalline silicon, the catalytic effect of the metal block increases the size of the polycrystalline silicon grains, reduces the grain boundaries in the polycrystalline silicon, and improves the mobility of the semiconductor device.

[0093] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0094] The above is a detailed introduction to a semiconductor device and an electronic device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: A thin film transistor is included, wherein the thin film transistor includes: substrate; a buffer layer, disposed on one side of the substrate; an active layer, disposed on a side of the buffer layer away from the substrate; In which, the semiconductor device also includes a metal layer, which is arranged on the side of the active layer facing the buffer layer, and the metal layer includes at least one metal block, and the metal block is in direct contact with at least part of the active layer; the buffer layer is provided with a groove in the area in contact with the active layer, and the metal block is arranged in the groove.

2. The semiconductor device according to claim 1, wherein The melting point of the material of the metal layer is less than 1410 degrees Celsius.

3. The semiconductor device according to claim 2, wherein The material of the metal layer includes at least one of aluminum, nickel, gallium, and indium.

4. The semiconductor device according to claim 1, wherein The semiconductor device includes a plurality of thin film transistors, and an active layer of at least one of the thin film transistors has no grain boundaries.

5. The semiconductor device according to claim 1, wherein The active layer of the thin film transistor includes first crystal grains, the first crystal grains are arranged corresponding to the metal blocks, and the number of the first crystal grains is equal to the number of the metal blocks.

6. The semiconductor device according to claim 5, wherein The first crystal grains are round or quasi-round in shape, and have a diameter of 1 micron to 5 microns.

7. The semiconductor device according to claim 5, wherein The thin film transistor includes a plurality of first crystal grains, the metal layer includes metal blocks arranged in an array, and a grain boundary of the first crystal grains is located between two adjacent metal blocks.

8. The semiconductor device according to claim 7, wherein The active layer includes a channel portion and a first doped portion and a second doped portion located on both sides of the channel portion. The shape of the first doped portion and the second doped portion along the line connecting the channel portion is the same as the shape of the metal blocks corresponding to the first doped portion and the second doped portion of the thin film transistor along the line connecting the channel portion.

9. The semiconductor device according to claim 8, wherein The shape of a line connecting the first doping portion and the second doping portion along the channel portion is a straight line, and the metal blocks are arranged along the straight line array.

10. The semiconductor device according to claim 8, wherein The first doping portion and the second doping portion are located on the same horizontal line. The shape of the line connecting the first doping portion and the second doping portion along the channel portion is a fold line. The metal blocks are arranged along the fold line array.

11. The semiconductor device according to claim 10, wherein The channel portion includes a first portion arranged in a perpendicular direction of the first doped portion, a second portion arranged in a perpendicular direction of the second doped portion, and a third portion vertically connected to the first portion and the second portion. The first doped portion and the second doped portion are arranged along the first portion, the third portion, and the second portion along a line connecting the channel portions, and the metal block is arranged in an array along the first portion, the third portion, and the second portion.

12. The semiconductor device according to claim 8, wherein The channel portion includes a fourth portion and a fifth portion connecting the first doping portion and the second doping portion, the fourth portion and the fifth portion are vertically arranged, and the metal blocks are arranged in an array along the direction of the fourth portion and the fifth portion.

13. The semiconductor device according to claim 7, wherein The diameter of the first crystal grain is equal to the distance between the center points of adjacent metal blocks.

14. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 13.

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