Current limiting release circuit for dc-dc converter and dc-dc converter

Abstract

Embodiments of the present disclosure provide a current limit release circuit for a DC-DC converter and the DC-DC converter. The current limit release circuit includes a ramp signal generation circuit, a reset circuit, and an output circuit. The ramp signal generation circuit is configured to generate a ramp signal according to an output voltage of the DC-DC converter, a bias voltage from a bias voltage terminal, a first voltage from a first voltage terminal, and a second voltage from a second voltage terminal, and provide the ramp signal to the output circuit via a first node. The reset circuit is configured to reset a voltage of the first node to the second voltage under control of a drive signal of the DC-DC converter. The output circuit is configured to generate a current limit release signal according to the voltage of the first node and a reference voltage from a reference voltage terminal.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to a current limiting release circuit for a DC-DC converter, and a DC-DC converter. Background Technology

[0002] With the rapid development of the integrated circuit industry and the expanding analog integrated circuit market, DC-DC (direct-to-direct-current) converters have also received widespread attention and rapid development. As a high-efficiency switching power supply technology, DC-DC converters have advantages such as fast dynamic response, simple control, and direct control of output current. In a DC-DC converter, the power transistor and freewheeling transistor alternately conduct to control the charging and discharging of the inductor, thereby achieving a stable output. A current detection circuit can be incorporated into the DC-DC converter. When the inductor current flowing through it is too high, the charging of the inductor can be stopped by controlling the power transistor and freewheeling transistor, thus achieving overcurrent protection. Summary of the Invention

[0003] The embodiments described herein provide a current limiting release circuit for a DC-DC converter, and a DC-DC converter.

[0004] According to a first aspect of this disclosure, a current limiting release circuit for a DC-DC converter is provided. The current limiting release circuit includes: a ramp signal generation circuit, a reset circuit, and an output circuit. The ramp signal generation circuit is configured to generate a ramp signal based on the output voltage of the DC-DC converter, a bias voltage from a bias voltage terminal, a first voltage from a first voltage terminal, and a second voltage from a second voltage terminal, and provide the ramp signal to the output circuit via a first node. The reset circuit is configured to reset the voltage of the first node to the second voltage under the control of a drive signal of the DC-DC converter. The output circuit is configured to generate a current limiting release signal based on the voltage of the first node and a reference voltage from a reference voltage terminal.

[0005] In some embodiments of this disclosure, the ramp signal generation circuit includes: a voltage-controlled current source circuit, a bias current generation circuit, and an energy storage circuit. The voltage-controlled current source circuit is configured to generate a first current based on the output voltage of the DC-DC converter and provide the first current to the energy storage circuit via a first node. The bias current generation circuit is configured to generate a bias current based on a bias voltage and provide the bias current to the energy storage circuit via the first node. The energy storage circuit is configured to store charge from the first current and the bias current to generate the ramp signal.

[0006] In some embodiments of this disclosure, the voltage-controlled current source circuit includes a first transistor, a second transistor, a third transistor, and a first resistor. The control electrode of the first transistor is provided with the output voltage of the DC-DC converter. The first electrode of the first transistor is coupled to a first terminal of the first resistor. The second electrode of the first transistor is coupled to the control electrode and a second electrode of the second transistor. The control electrode of the second transistor is coupled to the control electrode of the third transistor. The first electrode of the second transistor is coupled to a first voltage terminal. The first electrode of the third transistor is coupled to the first voltage terminal. The second electrode of the third transistor is coupled to a first node. The second terminal of the first resistor is coupled to a second voltage terminal.

[0007] In some embodiments of this disclosure, the bias current generation circuit includes a fourth transistor. The control electrode of the fourth transistor is coupled to a bias voltage terminal. The first electrode of the fourth transistor is coupled to a first voltage terminal. The second electrode of the fourth transistor is coupled to a first node.

[0008] In some embodiments of this disclosure, the energy storage circuit includes a first capacitor. A first terminal of the first capacitor is coupled to a first node. A second terminal of the first capacitor is coupled to a second voltage terminal.

[0009] In some embodiments of this disclosure, the reset circuit includes a fifth transistor. The control terminal of the fifth transistor is provided with a drive signal for the DC-DC converter. The first terminal of the fifth transistor is coupled to a second voltage terminal. The second terminal of the fifth transistor is coupled to a first node.

[0010] In some embodiments of this disclosure, the output circuit includes a voltage comparator. A first input terminal of the voltage comparator is coupled to a first node. A second input terminal of the voltage comparator is coupled to a reference voltage terminal. The output terminal of the voltage comparator is coupled to logic circuitry in a DC-DC converter.

[0011] According to a second aspect of this disclosure, a current limiting release circuit for a DC-DC converter is provided. The current limiting release circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first resistor, a first capacitor, and a voltage comparator. The control electrode of the first transistor is provided with the output voltage of the DC-DC converter. The first electrode of the first transistor is coupled to a first terminal of the first resistor. The second electrode of the first transistor is coupled to the control electrode and the second electrode of the second transistor. The control electrode of the second transistor is coupled to the control electrode of the third transistor. The first electrode of the second transistor is coupled to a first voltage terminal. The first electrode of the third transistor is coupled to the first voltage terminal. The second electrode of the third transistor is coupled to a first terminal of the first capacitor. The second terminal of the first resistor is coupled to a second voltage terminal. The control electrode of the fourth transistor is coupled to a bias voltage terminal. The first electrode of the fourth transistor is coupled to the first voltage terminal. The second electrode of the fourth transistor is coupled to a first terminal of the first capacitor. The second terminal of the first capacitor is coupled to the second voltage terminal. The control electrode of the fifth transistor is provided with a drive signal for the DC-DC converter. The first electrode of the fifth transistor is coupled to the second voltage terminal. The second electrode of the fifth transistor is coupled to a first terminal of the first capacitor and a first input terminal of the voltage comparator. The second input of the voltage comparator is coupled to the reference voltage. The output of the voltage comparator is coupled to the logic circuitry in the DC-DC converter.

[0012] In some embodiments of this disclosure, the reference voltage from the reference voltage terminal, the capacitance of the first capacitor, and the equivalent transconductance of the first transistor, the second transistor, the third transistor, and the first resistor satisfy the following equation:

[0013] Vref×C1 / gm=(I HS -I LS )×L

[0014] Where Vref represents the reference voltage from the reference voltage terminal, C1 represents the capacitance value of the first capacitor, gm represents the equivalent transconductance of the first transistor, the second transistor, the third transistor, and the first resistor, and I HS I represents the current limiting value of the inductor in a DC-DC converter. LS This represents the current limiting release value of the inductor in the DC-DC converter, where L represents the inductance value of the inductor in the DC-DC converter.

[0015] In some embodiments of this disclosure, the bias voltage from the bias voltage terminal is set such that the drain-source current I of the fourth transistor is... M4 Satisfy the following formula:

[0016] I M4 =Vref×C1 / Toff_max,

[0017] Where Toff_max represents the maximum off-time of the power transistor in the DC-DC converter.

[0018] According to a third aspect of this disclosure, a DC-DC converter is provided. The DC-DC converter includes: a current limiting release circuit as described in the first or second aspect of this disclosure, and logic circuitry. A current limiting release signal output by the current limiting release circuit is provided to the logic circuitry. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0020] Figure 1 This is a schematic block diagram of a DC-DC converter;

[0021] Figure 2 This is a schematic block diagram of a DC-DC converter according to an embodiment of the present disclosure;

[0022] Figure 3 This is a schematic block diagram of a current limiting release circuit according to an embodiment of the present disclosure; and

[0023] Figure 4 This is an exemplary circuit diagram of a current limiting release circuit according to an embodiment of the present disclosure.

[0024] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0026] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0027] In all embodiments of this disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current directions between the source and drain (emitter and collector) of N-type and P-type transistors are opposite, the controlled middle terminal of the transistor is referred to as the control terminal, and the remaining two terminals of the transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0028] Figure 1 A DC-DC converter is shown. This DC-DC converter includes: logic circuitry, driver circuitry, power transistor HS, freewheeling transistor LS, inductor Lx, capacitor Co (the equivalent series resistance of capacitor Co is shown as Resr), and resistor R. L The circuit consists of resistors R1 and R2, a main loop control module, a power transistor current-limiting circuit, and a freewheeling transistor current-limiting circuit. The drive circuit generates power transistor and freewheeling transistor control signals based on the drive signal Drive to control the alternating conduction of the power transistor HS and the freewheeling transistor LS. When the power transistor HS is on and the freewheeling transistor LS is off, the inductor Lx charges, and the inductor current flowing through Lx gradually increases. The power transistor current-limiting circuit is coupled to node SW to detect the inductor current of Lx. When the inductor current rises to the inductor's current-limiting value (also known as the "power transistor overcurrent value") I... HS When the power transistor's current limiting circuit is off and the freewheeling transistor LS is on, the inductor Lx discharges, and the inductor current flowing through Lx gradually decreases. The freewheeling transistor's current limiting circuit is coupled to node SW to detect the inductor current of Lx. When the inductor current decreases to the inductor's current limiting release value (also known as the "freewheeling transistor overcurrent value") I... LSAt this time, the freewheeling diode current limiting circuit provides a current limiting release signal Locp to the logic circuit. The main loop control module generates a PWM signal based on the feedback voltage FB of the output voltage Vout. The logic circuit generates a drive signal Drive based on the PWM signal, the current limiting indication signal Hocp, and the current limiting release signal Locp. Under normal circumstances (without inductor current overcurrent), the drive signal Drive is in phase with the PWM signal. When the PWM signal is high, if the logic circuit receives the current limiting indication signal Hocp, the drive signal Drive is pulled low until the logic circuit receives the current limiting release signal Locp, at which point the drive signal Drive is allowed to flip high again with the PWM signal, thus turning on the power transistor HS.

[0029] In short, when the inductor current rises to I HS When the inductor current drops to I, the power transistor HS is turned off and the freewheeling transistor LS is turned on. LS The power transistor HS is only allowed to be turned on when the time is right.

[0030] exist Figure 1 In the example, because the freewheeling diode current limiting circuit needs to detect the inductor current of inductor Lx, a certain blanking time is required when the freewheeling diode LS is turned on to accurately detect the inductor current. However, due to the limitation of the blanking time, it is difficult for the DC-DC converter to be upgraded to higher frequencies. In addition, the freewheeling diode current limiting circuit requires a current comparator, which occupies a large area. Moreover, the DC-DC converter has high requirements for the gain and response speed of this current comparator, so the freewheeling diode current limiting circuit also has a negative impact on the power consumption of the DC-DC converter, which is undesirable.

[0031] Embodiments of this disclosure present a DC-DC converter. Figure 2 A schematic block diagram of a DC-DC converter according to an embodiment of the present disclosure is shown. Instead of the conventional approach of real-time detection of the freewheeling transistor current, embodiments of the present disclosure use an adaptive power transistor turn-off time (which may be referred to in this context as the Toff time) to determine when the inductor current decreases to the inductor's current-limiting release value (i.e., the valley of the inductor current). LS .exist Figure 2 The current limiting release circuit 200 is used to replace the DC-DC converter. Figure 1 The current limiting circuit for the freewheeling transistor is included. The current limiting release circuit 200, without detecting the inductor current, can indicate an adaptive Toff time to the logic circuit, wherein the adaptive Toff time maintains a strong correlation with the output voltage Vout. The logic circuit can generate a drive signal based on this adaptive Toff time to control when the power transistor is allowed to turn on.

[0032] As mentioned above, the overcurrent value I of the power transistor is known. HS Given the output voltage Vout and the inductance value L of the inductor, the required overcurrent value I of the freewheeling diode is... LS In this case, the Toff time needs to meet the following requirements:

[0033] I HS -I LS =Toff×Vout / L.

[0034] The target I can be calculated using the slope of the inductor current. LS The corresponding Toff time is:

[0035] Toff = (I HS -I LS )×L / Vout.

[0036] Based on the above idea, a timing circuit can be designed when the inductor current is I. HS The timing starts at a certain time, and when the timing reaches Toff, a current limiting release signal is output to indicate that the inductor current has decreased to the desired I. LS The timing circuit is simpler than the current detection circuit and does not require a blanking time. This allows for a more concise and effective control of the inductor current's peak value I. LS The current limiting release circuit 200 according to embodiments of this disclosure can realize the function of the timing circuit described above. For example... Figure 2 As shown, the current limiting release circuit 200 can provide a current limiting release signal Toff_min to the logic circuit. The logic circuit can generate a drive signal Drive based on the current limiting release signal Toff_min to control the shortest cutoff time of the power transistor.

[0037] Figure 3 A schematic block diagram of a current limiting release circuit 200 according to an embodiment of the present disclosure is shown. The current limiting release circuit 200 may include a ramp signal generation circuit 310, a reset circuit 320, and an output circuit 330. The ramp signal generation circuit 310 may be coupled to the reset circuit 320, the output circuit 330, the output terminal Vout of the DC-DC converter, a first voltage terminal V1, a second voltage terminal V2, and a bias voltage terminal Vb. The ramp signal generation circuit 310 may be configured to generate a ramp signal based on the output voltage Vout of the DC-DC converter, a bias voltage Vb from the bias voltage terminal Vb, a first voltage V1 from the first voltage terminal V1, and a second voltage V2 from the second voltage terminal V2, and provide the generated ramp signal to the output circuit 330 via a first node N1.

[0038] The reset circuit 320 can be coupled to the ramp signal generation circuit 310, the output circuit 330, the second voltage terminal V2, and the output terminal of the logic circuit in the DC-DC converter (from which the drive signal Drive is output). The reset circuit 320 can be configured to reset the voltage of the first node N1 to the second voltage V2 under the control of the drive signal Drive of the DC-DC converter.

[0039] Output circuit 330 can be coupled to ramp signal generation circuit 310, reset circuit 320, and reference voltage terminal Vref. Output circuit 330 can be configured to generate a current limiting release signal Toff_min based on the voltage of the first node N1 and the reference voltage Vref from the reference voltage terminal Vref. As described above, the current limiting release signal Toff_min can be provided to the logic circuit in the DC-DC converter. The logic circuit can generate a drive signal Drive based on the current limiting release signal Toff_min to control the shortest off-time of the power transistor.

[0040] In some embodiments of this disclosure, when the drive signal Drive of the DC-DC converter is high (power transistor enabled), the reset circuit 320 can reset the voltage of the first node N1 to the second voltage V2. The phase when the drive signal Drive is high can be referred to as the reset phase. When the drive signal Drive of the DC-DC converter is low (power transistor disabled), the reset circuit 320 can stop operating (thus not affecting the voltage of the first node N1), and the ramp signal generation circuit 310 can start generating a ramp signal. When the ramp signal rises to the reference voltage Vref, the output circuit 330 can output a current limiting release signal Toff_min. By controlling the slope of the ramp signal and the reference voltage Vref, the reset phase can be terminated (inductor current is I). HS The time between the output current limiting release signal Toff_min and the current limiting release signal is equal to the time between the inductor current I and the current limiting release signal Toff_min. HS Reduce to I LS The time.

[0041] exist Figure 3 In the example, a high voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded.

[0042] Figure 4 An exemplary circuit diagram of a current limiting release circuit 200 according to an embodiment of the present disclosure is shown. Figure 4As shown, the ramp signal generation circuit 310 may include: a voltage-controlled current source circuit 411, a bias current generation circuit 412, and an energy storage circuit 413. The voltage-controlled current source circuit 411 may be coupled to the bias current generation circuit 412, the energy storage circuit 413, the output terminal Vout of the DC-DC converter, a first voltage terminal V1, a second voltage terminal V2, and a bias voltage terminal Vb. The voltage-controlled current source circuit 411 may be configured to generate a first current I1 based on the output voltage Vout of the DC-DC converter, and provide the first current I1 to the energy storage circuit 413 via a first node N1. The current value of the first current I1 is I1 = gm × Vout. Here, gm represents the equivalent transconductance of the voltage-controlled current source circuit 411, and Vout represents the voltage value of the output voltage Vout of the DC-DC converter.

[0043] In some embodiments of this disclosure, the voltage-controlled current source circuit 411 may include: a first transistor M1, a second transistor M2, a third transistor M3, and a first resistor Rs. The control electrode of the first transistor M1 is provided with the output voltage Vout of the DC-DC converter. The first electrode of the first transistor M1 is coupled to the first terminal of the first resistor Rs. The second electrode of the first transistor M1 is coupled to the control electrode and the second electrode of the second transistor M2. The control electrode of the second transistor M2 is coupled to the control electrode of the third transistor M3. The first electrode of the second transistor M2 is coupled to a first voltage terminal V1. The first electrode of the third transistor M3 is coupled to the first voltage terminal V1. The second electrode of the third transistor M3 is coupled to a first node N1. The second terminal of the first resistor Rs is coupled to a second voltage terminal V2. In this embodiment, the magnitude of the output voltage Vout of the DC-DC converter can affect the magnitude of the current flowing through the first transistor M1. The second transistor M2 and the third transistor M3 form a current mirror. Therefore, the first current I1 is equal to the current flowing through the first transistor M1. The equivalent transconductance gm of the voltage-controlled current source circuit 411 is 1 / (1+Rs). Where Rs represents the resistance value of the first resistor Rs. By setting the value of Rs, gm≈1 / Rs can be achieved.

[0044] Those skilled in the art should understand that Figure 4 The internal structure of the voltage-controlled current source circuit 411 is exemplary, and the voltage-controlled current source circuit 411 can also be implemented by other circuits. The embodiments of this disclosure do not limit the specific implementation of the voltage-controlled current source circuit 411.

[0045] The bias current generation circuit 412 can be coupled to the voltage-controlled current source circuit 411, the energy storage circuit 413, and the bias voltage terminal Vb. The bias current generation circuit 412 can be configured to generate a bias current I2 according to the bias voltage Vb and supply the bias current I2 to the energy storage circuit 413 via the first node N1. In some embodiments of the present disclosure, the current value I2 of the bias current I2 is less than 1 / 10 of the current value I1 of the first current I1, that is, I2 < I1 / 10. In one example, I2 < I1 / 100.

[0046] In some embodiments of the present disclosure, the bias current generation circuit 412 may include: a fourth transistor M4. Wherein, the control electrode of the fourth transistor M4 is coupled to the bias voltage terminal Vb. The first electrode of the fourth transistor M4 is coupled to the first voltage terminal V1. The second electrode of the fourth transistor M4 is coupled to the first node N1. By setting the magnitude of the bias voltage Vb from the bias voltage terminal Vb, the magnitude of the current I flowing through the fourth transistor M4 can be controlled. M4 In Figure 4 the example, I M4 = I2. [[ID=eleven]]

[0047] The energy storage circuit 413 can be coupled to the voltage-controlled current source circuit 411, the bias current generation circuit 412, and the second voltage terminal V2. The energy storage circuit 413 can be configured to store the charges from the first current I1 and the bias current I2 to generate a ramp signal. In some embodiments of the present disclosure, the energy storage circuit 413 may include: a first capacitor C1. Wherein, the first terminal of the first capacitor C1 is coupled to the first node N1. The second terminal of the first capacitor C1 is coupled to the second voltage terminal V2. The first current I1 and the bias current I2 can charge the first capacitor C1, thereby raising the voltage of the first terminal of the first capacitor C1 to generate a ramp signal.

[0048] When the magnitude of the output voltage Vout of the DC-DC converter is such that the first current I1 = 0, the bias current I2 can still continuously supply charges to the energy storage circuit 413, so that a ramp signal can still be generated.

[0049] In some embodiments of the present disclosure, the reset circuit 320 may include: a fifth transistor M5. Wherein, the control electrode of the fifth transistor M5 is provided with the drive signal Drive of the DC-DC converter. The first electrode of the fifth transistor M5 is coupled to the second voltage terminal V2. The second electrode of the fifth transistor M5 is coupled to the first node N1. In Figure 4 the example, when the drive signal Drive is at a high level, the fifth transistor M5 is turned on, thereby resetting the voltage of the first node N1 to the second voltage V2. When the drive signal Drive is at a low level, the fifth transistor M5 is turned off, so that the second voltage V2 from the second voltage terminal V2 does not affect the voltage of the first node N1.

[0050] In some embodiments of this disclosure, the output circuit 330 may include a voltage comparator COMP. The first input terminal of the voltage comparator COMP is coupled to a first node N1. The second input terminal of the voltage comparator COMP is coupled to a reference voltage terminal Vref. The output terminal of the voltage comparator COMP is coupled to logic circuitry in a DC-DC converter.

[0051] exist Figure 4 In this example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first transistor M1 and the fifth transistor M5 are N-type transistors, while the second transistor M2, the third transistor M3, and the fourth transistor M4 are P-type transistors. The first input terminal of the voltage comparator COMP is the non-inverting input terminal. The second input terminal of the voltage comparator COMP is the inverting input terminal.

[0052] exist Figure 4 In the example, the power transistor's turn-off time Toff = Vref × C1 / (I1 + I2). Since I2 is at least less than I1 / 10, I2 can be ignored in the above formula. Thus,

[0053] Toff=Vref×C1 / I1=Vref×C1 / (gm×Vout) (1)

[0054] exist Figure 1 In the example, Toff = (I HS -I LS )×L / Vout (2)

[0055] Therefore, according to equations (1) and (2), in order to make Figure 4 The timing of the current limiting release circuit in the example Figure 1 In the example, the inductor current is from I HS Become I LS The time is the same, which can make

[0056] Vref×C1 / gm=(I HS -I LS )×L (3)

[0057] Where Vref represents the reference voltage from the reference voltage terminal, C1 represents the capacitance value of the first capacitor, gm represents the equivalent transconductance of the first transistor, the second transistor, the third transistor, and the first resistor, and I HS I represents the current limiting value of the inductor in a DC-DC converter. LS This represents the current limiting release value of the inductor in the DC-DC converter, where L represents the inductance value of the inductor in the DC-DC converter.

[0058] According to I HS ILS The values ​​of Vref, C1, and gm are set using the values ​​of L.

[0059] Furthermore, as described above, when the magnitude of the output voltage Vout of the DC-DC converter makes the first current I1 = 0 (i.e., Vout... <V TH_M1 At that time, V TH_M1 (This represents the threshold voltage of the first transistor M1), and the bias current I2 can still continuously provide charge to the first capacitor C1. The current value of the bias current I2 is I2 = I... M4 =Vref×C1 / Toff_max. Where Toff_max represents the maximum off time of the power transistor. Given Vref and C1 determined according to equation (3), the bias current I2 can be adjusted according to Toff_max.

[0060] In summary, the current limiting release circuit according to embodiments of this disclosure can indicate an adaptive Toff time to the logic circuit without detecting the inductor current. The adaptive Toff time can maintain a strong correlation with the output voltage Vout. The logic circuit can generate a drive signal based on this adaptive Toff time to control when the power transistor is allowed to turn on. Thus, the DC-DC converter using this current limiting release circuit has a smaller area and lower power consumption.

[0061] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0062] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0063] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0064] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A current limiting release circuit for a DC-DC converter, comprising: The ramp signal generation circuit, reset circuit, and output circuit are included. The ramp signal generation circuit is configured to generate a ramp signal based on the output voltage of the DC-DC converter, the bias voltage from the bias voltage terminal, the first voltage from the first voltage terminal, and the second voltage from the second voltage terminal, and to provide the ramp signal to the output circuit via the first node. The reset circuit is configured to reset the voltage of the first node to the second voltage under the control of the drive signal of the DC-DC converter; The output circuit is configured to generate a current limiting release signal based on the voltage of the first node and the reference voltage from the reference voltage terminal. The ramp signal generation circuit includes: a voltage-controlled current source circuit, a bias current generation circuit, and an energy storage circuit. The voltage-controlled current source circuit is configured to generate a first current based on the output voltage of the DC-DC converter and provide the first current to the energy storage circuit via the first node. The bias current generation circuit is configured to generate a bias current based on the bias voltage and provide the bias current to the energy storage circuit via the first node; The energy storage circuit is configured to store charge from the first current and the bias current to generate the ramp signal.

2. The current limiting release circuit according to claim 1, wherein, The voltage-controlled current source circuit includes: a first transistor, a second transistor, a third transistor, and a first resistor. The control electrode of the first transistor is provided with the output voltage of the DC-DC converter, the first electrode of the first transistor is coupled to the first terminal of the first resistor, and the second electrode of the first transistor is coupled to the control electrode and the second electrode of the second transistor. The control electrode of the second transistor is coupled to the control electrode of the third transistor, and the first electrode of the second transistor is coupled to the first voltage terminal; The first terminal of the third transistor is coupled to the first voltage terminal, and the second terminal of the third transistor is coupled to the first node; The second end of the first resistor is coupled to the second voltage terminal.

3. The current limiting release circuit according to claim 1, wherein, The bias current generation circuit includes: a fourth transistor. The control electrode of the fourth transistor is coupled to the bias voltage terminal, the first electrode of the fourth transistor is coupled to the first voltage terminal, and the second electrode of the fourth transistor is coupled to the first node.

4. The current limiting release circuit according to claim 1, wherein, The energy storage circuit includes: a first capacitor, Wherein, the first end of the first capacitor is coupled to the first node, and the second end of the first capacitor is coupled to the second voltage terminal.

5. The current limiting release circuit according to claim 1, wherein, The reset circuit includes: a fifth transistor, The control electrode of the fifth transistor is provided with the drive signal of the DC-DC converter, the first electrode of the fifth transistor is coupled to the second voltage terminal, and the second electrode of the fifth transistor is coupled to the first node.

6. A current limiting release circuit for a DC-DC converter, comprising: The transistor comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first resistor, a first capacitor, and a voltage comparator. The control electrode of the first transistor is provided with the output voltage of the DC-DC converter, the first electrode of the first transistor is coupled to the first terminal of the first resistor, and the second electrode of the first transistor is coupled to the control electrode and the second electrode of the second transistor. The control electrode of the second transistor is coupled to the control electrode of the third transistor, and the first electrode of the second transistor is coupled to the first voltage terminal; The first terminal of the third transistor is coupled to the first voltage terminal, and the second terminal of the third transistor is coupled to the first terminal of the first capacitor; The second end of the first resistor is coupled to the second voltage terminal; The control electrode of the fourth transistor is coupled to the bias voltage terminal, the first electrode of the fourth transistor is coupled to the first voltage terminal, and the second electrode of the fourth transistor is coupled to the first terminal of the first capacitor. The second terminal of the first capacitor is coupled to the second voltage terminal; The control electrode of the fifth transistor is provided with the drive signal of the DC-DC converter, the first electrode of the fifth transistor is coupled to the second voltage terminal, and the second electrode of the fifth transistor is coupled to the first terminal of the first capacitor and the first input terminal of the voltage comparator; The second input terminal of the voltage comparator is coupled to the reference voltage terminal, and the output terminal of the voltage comparator is coupled to the logic circuit in the DC-DC converter.

7. The current limiting release circuit according to claim 6, wherein, The reference voltage from the reference voltage terminal, the capacitance of the first capacitor, and the equivalent transconductance of the first transistor, the second transistor, the third transistor, and the first resistor satisfy the following equation: Vref×C1 / gm =(I HS - I LS )×L Where Vref represents the reference voltage from the reference voltage terminal, C1 represents the capacitance value of the first capacitor, gm represents the equivalent transconductance of the first transistor, the second transistor, the third transistor, and the first resistor, and I HS I represents the current limiting value of the inductor in the DC-DC converter. LS The value represents the current limiting release value of the inductor in the DC-DC converter, and L represents the inductance value of the inductor in the DC-DC converter.

8. The current limiting release circuit according to claim 7, wherein, The bias voltage from the bias voltage terminal is set such that the drain-source current I of the fourth transistor is... M4 Satisfy the following formula: I M4 =Vref×C1 / Toff_max, Where Toff_max represents the maximum off-time of the power transistor in the DC-DC converter.

9. A DC-DC converter, comprising: According to any one of claims 1 to 8, the current limiting release circuit and the logic circuit are provided to the logic circuit.

Images