Pixel driver redundancy scheme

Abstract

This disclosure describes display panel redundancy schemes and redundant building blocks. In one embodiment, a pixel driver chip is connected to both primary and redundant strings of LEDs within a local passive matrix, and driver terminal switches within the pixel driver chip are used to select either the primary or redundant strings of LEDs.

Description

Background Art Technical Field

[0001] Embodiments described herein relate to display systems, and more particularly, to redundancy schemes to increase display yield. Background Art

[0003] Display panels are used in a variety of different electronic devices. Common types of display panels include active matrix display panels, in which each pixel element, such as a light emitting diode (LED), can be driven individually to display a frame of data, and passive matrix display panels, in which rows and columns of pixel elements can be driven in a frame of data. The frame rate can be related to display artifacts and can be set at a specific level based on the display application.

[0004] Conventional organic light emitting diode (OLED) or liquid crystal display (LCD) technology features a thin film transistor (TFT) substrate. Recently, it has been proposed to replace the TFT substrate with an array of pixel driver chips (also called micro driver chips or microcontroller chips) bonded to the substrate, and to integrate a micro LED (μLED) array with an array of pixel driver chips, where each pixel driver chip is used to switch and drive a corresponding plurality of micro LEDs. Such micro LED displays can be arranged for active matrix addressing or passive matrix addressing.

[0005] In one implementation described in U.S. Patent Publication No. 2019 / 0347985, a local passive matrix (LPM) display includes an arrangement of pixel driver chips and LEDs, wherein each pixel driver chip is coupled to an LPM group of LEDs arranged in display rows and columns. In operation, a global data signal is transmitted to the pixel driver chip, and each display row of LEDs in the LPM group is driven one display row at a time by the pixel driver chip. In particular, the pixel driver chip may include different driver portions or slices to provide redundancy for defective or inactive pixel driver chips. In an exemplary implementation, the LPM group of LEDs includes an arrangement of primary LEDs coupled to a primary pixel driver chip and an overlapping arrangement of redundant LEDs coupled to adjacent redundant pixel driver chips. In the event of a defective primary pixel driver chip or primary LED, the connecting slice of the primary pixel driver chip is deactivated, and the redundant pixel driver chip is activated to drive the redundant LEDs in the LPM group. Summary of the invention

[0006] The embodiments describe various redundant building blocks to implement specific pixel driver redundancy configurations within a display panel. For example, various redundant building blocks include driver terminal switches to select a primary string of LEDs or a redundant string of LEDs, selective building block redundancy features, and redundant pixel driver circuits. Various combinations can be utilized to increase manufacturing yield percentages, increase LED matrix size, and reduce the amount of silicon or the number of pixel driver chips required to operate a display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a schematic top view illustration of a display system according to one embodiment.

[0008] Figure 1B is a close-up schematic cross-sectional side view illustration of a portion of a display panel according to one embodiment.

[0009] Figure 2A is a schematic diagram of an LED matrix including redundant LED pairs driven by adjacent pairs of pixel driver chips according to one embodiment.

[0010] Figure 2B is a schematic diagram of an LED matrix including redundant LED pairs driven by a single pixel driver chip according to one embodiment.

[0011] Figure 3A Schematic top view illustration of an upper / lower redundancy scheme.

[0012] Figure 3B is a schematic top view illustration of a redundancy scheme with spare pixel driver chips according to one embodiment.

[0013] Figure 3C is a schematic top view illustration of a redundancy scheme with a single pixel driver chip according to one embodiment.

[0014] Figure 4A is a schematic diagram of input / output terminals of a pixel driver chip according to one embodiment.

[0015] Figure 4B FIG. 1 is a schematic diagram of selective redundancy within functional blocks of a pixel driver chip according to one embodiment.

[0016] Figure 5 is a circuit diagram of a pixel driver chip with driver terminal switches and optional redundant pixel driver circuits according to one embodiment.

[0017] Figure 6 is a schematic diagram of a pixel driver chip including a combination of redundant building blocks according to one embodiment.

[0018] Fig. 7A is a schematic top view illustration of a redundancy scheme including a pixel driver chiplet having driver terminal switches arranged in an up / down redundancy scheme according to one embodiment.

[0019] Figure 7B is a schematic top view illustration of a redundancy scheme including a pixel driver chiplet having driver terminal switches arranged in a redundancy scheme with a spare pixel driver chiplet according to one embodiment.

[0020] FIG. 7C to FIG. 7C ' is a schematic top view illustration of a redundancy scheme including a pixel driver chiplet having driver terminal switches arranged in a redundancy scheme with a single pixel driver chiplet according to one embodiment.

[0021] Figure 7C ” is a schematic top view illustration of a redundancy scheme including a pixel driver chiplet having driver terminal switches and redundant pixel driver circuits arranged in a redundancy scheme with a single pixel driver chiplet according to one embodiment.

[0022] Figure 8 is an isometric view of a mobile phone according to one embodiment.

[0023] Fig. 9 is an isometric view of a tablet computing device according to one embodiment.

[0024] Fig.10 is an isometric view of a wearable device according to one embodiment.

[0025] Fig.11 is an isometric view of a laptop computer according to one embodiment.

[0026] Fig.12 is a system diagram of a portable electronic device according to one embodiment. DETAILED DESCRIPTION

[0027] The embodiments describe various pixel driver chip redundancy schemes that can increase display yield and thereby expand the size of the LED matrix and reduce display costs. In particular, it has been observed that pixel driver chip defects, typically characterized by defective parts per million (DPPM), affect the minimum manufacturing yield percentage of the display. For example, a pixel driver chip may have xy dimensions of approximately tens to hundreds of microns and include dozens of contact / terminal pads. Due to the size limitations of the contact / terminal pads, it may be difficult to test a single pixel driver chip at the wafer level using traditional probing techniques. This can result in defective pixel driver chips being transferred and integrated into a display panel.

[0028] An exemplary integration sequence according to the embodiment may include producing wafer-level pixel driver chips and transferring multiple pixel driver chips from one or more donor substrates to a display substrate. A redistribution layer (RDL) is then formed for electrical routing to / from the pixel driver chips and forming LED driver pads. Testing may optionally be performed using the RDL to determine the operability of the transferred pixel driver chips, after which the LED array is transferred to the display substrate and bonded to the driver pads. Various pixel driver chip redundancy schemes according to the embodiment may mitigate the risk of integrating fully or partially defective pixel driver chips into a display panel, and thereby increase manufacturing yield.

[0029] In an embodiment, the display panel includes an array of pixel driver chips connected to a corresponding LED matrix array. For example, each LED matrix can be a local passive matrix (LPM) of LEDs that is locally operated by adjacent pixel driver chips or pixel driver chips. As a repeating pattern, the LED matrix array may include a first LED matrix and a second LED matrix, wherein the pixel driver chip array includes a first pixel driver chip connected to the first LED matrix and the second LED matrix. Therefore, the pixel driver chip can operate at least a portion of the two LED matrices. The pixel driver chip can also be configured to operate the main / redundant string LED pairs within each matrix. In an embodiment, the first LED matrix includes a plurality of first main strings of LEDs and a plurality of first redundant strings of LEDs, and the second LED matrix includes a plurality of second main strings of LEDs and a plurality of redundant strings of LEDs. In an embodiment, the pixel driver chip includes a first group of first output drivers for driving a plurality of first main strings of LEDs in the first LED matrix and a second group of output drivers for driving a plurality of second redundant strings of LEDs in the second LED matrix. In such an embodiment, each first output driver can be connected to a corresponding first driver terminal switch (such as a tri-state switch) to select a first main driver terminal or a first redundant driver terminal. Each second output driver may be connected to a second driver terminal switch, such as a tri-state switch, to select the second primary driver terminal or the second redundant driver terminal.

[0030] In one aspect, various pixel driver redundancy schemes are described that can increase the allowable number of DPPMs of a pixel driver chip while maintaining an acceptable manufacturing yield percentage and increasing the LED matrix size (e.g., LPM size). According to some embodiments, both the main string LEDs and the redundant string LEDs within the LED matrix can be connected to terminals of two adjacent pixel driver chips. Each pixel driver chip may include a switching circuit to select a main string LED or a redundant string LED. Such a redundant configuration can accommodate an increase in the number of DPPMs of the pixel driver chip. In some embodiments, the pixel driver chip may include additional redundant circuits coupled between a first pixel driver circuit and a sending pixel driver circuit to provide shared pixel driver circuit redundancy.

[0031] On the other hand, various pixel driver redundancy schemes are described that can reduce display costs by reducing the number of total silicon or pixel driver chips while maintaining an acceptable manufacturing yield percentage and increasing the LED matrix size (e.g., LPM size). Such redundancy configurations can utilize additional redundancy configurations with switching circuits and / or shared pixel driver circuit redundancy within the pixel driver chip. According to some embodiments, both the main string LEDs and the redundant string LEDs within the LED matrix are connected to the driver terminals of a single pixel driver chip. While maintaining the DPPM tolerance, such an arrangement can facilitate a reduced number of pixel driver chips.

[0032] LPM displays according to embodiments can be implemented in both large area displays as well as high resolution displays with high pixel density. In addition, the LED and pixel driver chip sizes can be scaled from macroscopic to microscopic sizes. In one embodiment, for a display with high resolution and pixel density, the pixel driver chip may have a length of less than 400 μm, or even less than 200 μm, with the LED maximum dimension being less than 100 μm, or even less than 20 μm, such as less than 10 μm, or even less than 5 μm.

[0033] In various embodiments, description is made with reference to the accompanying drawings. However, certain embodiments may be practiced without one or more of these specific details or in combination with other known methods and structures. In the following description, many specific details such as specific configurations, sizes and processes are shown to provide a thorough understanding of the embodiments. In other cases, well-known semiconductor processes and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the embodiments. "One embodiment" mentioned throughout the specification refers to the specific features, structures, constructions or characteristics described in conjunction with the embodiments being included in at least one embodiment. Therefore, the phrase "in one embodiment" that appears in multiple places throughout the specification does not necessarily refer to the same embodiment. In addition, specific features, structures, constructions or characteristics may be combined in one or more embodiments in any appropriate manner.

[0034] As used herein, the terms "on," "over," "to," "between," and "on" may refer to the relative position of one layer with respect to other layers. A layer that is "on," "over," or "on" another layer or bonded "to," or "in contact with," another layer may be directly in contact with the other layer or may have one or more intervening layers. A layer that is "between" multiple layers may be directly in contact with the multiple layers or may have one or more intervening layers.

[0035] Reference now Figure 1A , provides a cross-sectional side view illustration of a display system 100 according to one embodiment. Figure 1A As shown, the display system includes rows of pixel driver chips 110. Each pixel driver chip 110 may include two parts or slices 0, 1 for operation of the LED matrix 115 above and below the pixel driver chip 110. Slices 0, 1 may be divided into a master / redundant configuration or a master / slave configuration. Each LED matrix 115 may include a plurality of LEDs 104 and a plurality of pixels 106. In some configurations, the rows of pixel driver chips 110 are arranged into rows where every other row is a row of primary pixel driver chips (e.g., rows 1, 3, etc.) or a row of redundant pixel driver chips (e.g., rows 2, 4, etc.). It should be understood that the number and size of pixel driver chips 110 within the display area are not necessarily drawn to scale and are exaggerated for schematic illustration.

[0036] Typically, the display system 100 may include a display panel 103 that includes a display area having pixels 106 with LEDs 104, an optional column driver, an optional row driver, and an external control circuit 105 attached to the display panel 103 to supply various control signals, video signals, and power supply voltages to the display panel 103.

[0037] Figure 1BA close-up schematic cross-sectional side view illustration of a portion of a display panel according to an embodiment. The manufacturing method may include transferring an array of pixel driver chips 110 to a display substrate 200. For example, the display substrate 200 may be a rigid or flexible substrate, such as glass, polyimide, etc. An adhesive layer 202 may be optionally formed on the display substrate 200 to receive the pixel driver chips 110. The transfer may be completed using a pick-and-place tool. In one embodiment, the back side (non-functionalized) side is placed on the adhesive layer 202, with the front side (active side, including the contact pad 112) facing up. The contact (terminal) pad 112 may be formed before or after the transfer. As shown, a passivation layer 204 may be formed around the pixel driver chip 110, for example to fix the pixel driver chip 110 to the display substrate 200 and provide step coverage for additional wiring. Suitable materials for the passivation layer 204 include polymers, spin-coated glass, oxides, etc. In one embodiment, the passivation layer is a thermosetting material such as acrylic, epoxy, benzocyclobutene (BCB), or the like.

[0038] A redistribution layer (RDL) 210 may then be formed over the array of pixel driver chips 110. The RDL may, for example, fan out from the contact (terminal) pads 112, and may additionally include routing to / from the control circuit 105. The RDL 210 may include one or more redistribution lines 208 and a dielectric layer 206. For example, the redistribution lines 208 may be metal lines (e.g., Cu, Al, etc.), and the dielectric layer 206 may be formed of a suitable insulating material, including oxides (e.g., SiOx), nitrides, polymers, etc. According to an embodiment, the RDL 210 includes a plurality of global signal lines and power lines (e.g., data signal 350, row synchronization signal 334, frame synchronization signal 336, and vertical synchronization token (VST) 340, Vdd, etc., see Figure 4A ) in one or more. Still refer to Figure 1B , RDL 210 additionally includes driver pads 211 for the LEDs. According to some embodiments, each string of LEDs can be connected to a corresponding interconnect (eg, string or line).

[0039] At this stage in the manufacturing process, the partially produced display panel 103 can be tested to determine the operability of the pixel driver chip 110. For example, this can be done by probing the driver pads 211 or other test circuits formed in the RDL 210. For example, the RDL 210 may include a test circuit with a test pad at the edge of the display panel 103, which can be probed to test the function of the pixel driver chip 110. This test can be performed before or after the transfer LED 104. In one embodiment, the test circuit can be removed from the edge of the display panel 103 after the test. In some embodiments, the pixel driver chip 110 can be fully or partially activated or deactivated based on the test results. For example, the entire pixel driver chip or only a specific piece can be deactivated. In addition, a specific driver terminal switch can be programmed to select a main driver terminal or a redundant driver terminal. Therefore, redundancy and selectivity can be at a finer granularity compared to the piece level. However, it should be understood that the pixel driver chip does not have to be programmed at this stage.

[0040] The display panel is now suitable for subsequent processing of both micro-LED and OLED. In the OLED manufacturing process, this may include the deposition of the organic emission layer and the pixel definition layer. Figure 1B In the illustrated micro-LED manufacturing process, additional dielectric layers and wiring layers may be optionally formed before the micro-LED 104 is transferred and bonded to the stacked structure. In one embodiment, the micro-LED 104 is optionally bonded inside the bank structure opening 230 in the bank layer 220. The bank structure opening 230 may optionally be reflective and may optionally be filled after bonding the micro-LED 104. The bank layer 220 may be further patterned to create an opening 240 to expose a wiring layer, such as a (e.g., negative) voltage supply line 114 or a cathode. A top transparent or semi-transparent conductive layer 260 may then be deposited to provide an electrical connection from the top side of the micro-LED 104 to the voltage supply line or cathode. Suitable materials include transparent conductive oxides (TCOs), conductive polymers, thin transparent metal layers, and the like. Further processing may then be performed on the encapsulation, polarizers, and the like.

[0041] Reference now Figure 2A , provides a schematic diagram of an LED matrix including redundant LED pairs that can be driven by adjacent pairs of pixel driver chips 110. In particular, Figure 2A1 is an illustration of a top pixel driver chip 110 with a lower slice 1 and a lower pixel driver chip 110 with an upper slice 0, both connected to an LED matrix 115. For example, slices 0, 1 can be divided into a primary / redundant configuration or a master / slave configuration. It should be understood that the use of the term "slice" is simplified and in no way implies a geometric partitioning of the circuitry within the pixel driver chip 110, but rather a simple reference to the top and bottom connections in the illustration.

[0042] In the illustrated embodiment, the columns of LEDs 104 correspond to different emission colors of the LEDs, such as red (R), green (G), blue (B) in an RGB pixel arrangement. Each column of LEDs 104 may also be a string 107 of LEDs. Alternative pixel arrangements may also be used. The illustrated number of rows and columns of LEDs within the LED matrix is ​​exemplary, and embodiments are not limited thereto. For example, an additional LED column would be included to share pixels with a red (R) LED 104 in a fourth column.

[0043] In the illustrated embodiment, two portions, namely slice 1 of the lower pixel driver chip 110 and slice 0 of the upper pixel driver chip 110, include driver terminals 120 (e.g., Figure 1B In contrast, an adjacent pixel driver chiplet 110 includes a row terminal 122 coupled to a redundant LED row using a row interconnector 262 (e.g., Figure 1B The row interconnect 262 may be a combination of a top transparent or semi-transparent conductive layer 260 and a (negative) voltage supply line 114 (eg, cathode) that connects a string 107 of LEDs 104 to the row terminal 122.

[0044] The row terminals 122 may be coupled to corresponding row line switches and level shifters within the pixel driver chip 110, and the driver terminals 120 may be coupled to the output drivers 140 and driver terminal switches 130 of the pixel driver chip 110. The row interconnects 262 may connect electrodes (e.g., cathodes) of a row of LEDs 104 to corresponding row line switches and level shifters, and the interconnects 212 may connect electrodes (e.g., anodes) of a column of LEDs 104 to corresponding output drivers 140, or vice versa.

[0045] Specifically, the redundant driver terminal 120R may be coupled to a redundant interconnect 212R corresponding to a string 107 or a column of redundant LEDs 104, and the primary driver terminal 120P may be coupled to a primary interconnect 212P corresponding to a string 107 or a column of primary LEDs 104. In addition, the row terminals 122 of the slice 1 of the upper pixel driver chip 110 and the slice 0 of the lower pixel driver chip 110 may each be coupled to a row interconnect 262, and the corresponding rows of primary LEDs 104 and redundant LEDs are also coupled to the columns of primary interconnect lines 212P and redundant interconnect lines 212R. In this way, the slice 1 of the upper pixel driver chip 110 and the slice 0 of the lower pixel driver chip 110 share the same timing associated with the same matrix 115.

[0046] exist Figure 2A In the particular embodiment shown, the LED matrix 115 is connected to two adjacent pixel driver chips 110. In such embodiments, a plurality of row interconnects 262 are connected between a first plurality of row terminals 122 (e.g., chip 1) of a first pixel driver chip and a corresponding second plurality of row terminals 122 (e.g., chip 0) of a second pixel driver chip, wherein each row interconnect 262 of the plurality of row interconnects is coupled to both a plurality of first redundant strings of LEDs (connected to redundant interconnect lines 212R) and a plurality of first primary strings of LEDs (connected to primary interconnect lines 212P) in the LED matrix. As shown, the row terminals 122 need not be redundant.

[0047] In some embodiments including spare pixel driver chips, for each pixel driver chip, the master portion or slice 0 of each pixel driver chip is active by default, and the slave portion or slice 1 of each pixel driver chip is inactive by default. Therefore, the slave portion or redundant portion becomes inactive only when the master portion or main portion from the adjacent pixel driver chip is defective or passive. In some embodiments, the portion or slice 0, 1 of the main pixel driver chip is active by default, and the corresponding portion or slice 0, 1 of the redundant pixel driver chip is inactive by default. Therefore, part or all of the redundant pixel driver chip becomes active only when the adjacent main pixel driver chip portion is defective or inactive. Alternatively, specific driver terminals and strings of LEDs can be activated in any suitable configuration with a finer granularity than the slice level. Therefore, the entire slice does not need to be completely active or inactive.

[0048] Figure 2BSchematic diagram of an LED matrix including redundant LED pairs driven by a single pixel driver chip according to an embodiment. As shown, a plurality of row interconnects 262 are connected to a first plurality of row terminals 122 (e.g., chip 1) of only a single pixel driver chip, wherein each row interconnect 262 of the plurality of row interconnects is coupled to both a plurality of first redundant strings of LEDs (connected to redundant interconnect lines 212R) and a plurality of first main strings of LEDs (connected to main interconnect lines 212P) in the LED matrix. As shown, the row terminals 122 do not have to be redundant.

[0049] Reference now FIG. 3A to FIG. 3C , showing that it can be similar to Figure 1A Various redundant configurations of the arrangements of the pixel driver chip 110 and the LED matrix 115. Figure 3A 1 is a schematic top view illustration of an upper / lower redundancy scheme. As shown, each pixel driver chiplet 110 includes a first portion (chip 0) of a pixel driver circuit 150-0 and a second portion (chip 1) of a pixel driver circuit 150-1, the first portion and the second portion of the pixel driver circuit optionally including independent logic (e.g., to receive and store control bits and pixel bits). Figure 3A In the illustrated implementation, each portion of the pixel driver circuit 150-0, 150-1 includes a plurality of output drivers 140, each of which is connected to a corresponding string 107 (primary string 107P, redundant string 107R) of LEDs via an interconnect 212 (primary interconnect 212P, redundant interconnect 212R). In this configuration, the corresponding LED matrix 115 can be driven by the first portion (chip 0) of the pixel driver circuit 150-0 of the upper pixel driver chip 110 or by the second portion (chip 1) of the pixel driver circuit 150-1 of the lower pixel driver chip 110.

[0050] Figure 3B FIG. 1 is a schematic top view illustration of a redundancy scheme with a spare pixel driver chip according to one embodiment. In particular, Figure 3B Indicates that Figure 2A The same redundant configuration as described in Figure 3A The comparison includes additional redundant configurations, such as interconnect 212 connected to two adjacent pixel driver chiplets 110, and each pixel driver chiplet 110 includes a driver switch 130 to select the connected primary interconnect 212P (and corresponding primary string 107P LEDs) or redundant interconnect 212R (and corresponding redundant string 107R LEDs).

[0051] In an embodiment, the display panel 103 includes an array of pixel driver chips 110 connected to a corresponding array of LED matrices 115, the LED matrix array includes a first LED matrix 115A and a second LED matrix 115B, and the array of pixel driver chips 110 includes a first pixel driver chip (a middle pixel driver chip in the figure) connected to the first LED matrix 115A and the second LED matrix 115B. In the illustrated embodiment, the first LED matrix includes a plurality of first main strings 107P LEDs and a plurality of first redundant strings 107R LEDs, and the second LED matrix includes a plurality of second main strings 107P LEDs and a plurality of second redundant strings 170R LEDs.

[0052] The first pixel driver chip 110 includes a first portion (chip 0) of a pixel driver circuit 150-0 and a second portion (chip 1) of a pixel driver circuit 150-1, each portion optionally including independent logic (e.g., to receive control bits and pixel bits). The first portion of the pixel driver circuit 150-0 includes a first group of first output drivers 140-0 to drive a plurality of first redundant strings 107R LEDs in a first LED matrix 115A. The second portion of the pixel driver circuit 150-1 includes a second group of second output drivers 140-1 to drive a plurality of second main strings 107P LEDs in a second LED matrix 115B. As shown, each first output driver 140-0 is connected to a corresponding first driver terminal switch 130 to select a first main driver terminal 120P or a first redundant driver terminal 120R of the first pixel driver chip 110, and each second output driver 140-1 is connected to a corresponding second driver terminal switch 130 to select a second main driver terminal 120P or a second redundant driver terminal 120R of the first pixel driver chip 110. For example, the driver terminal switches can be tri-state switches. Still reference Figure 3B In a redundant configuration, each first redundant string 107R LED is connected to a corresponding first redundant driver terminal 120R, and each second main string 107P LED is connected to a corresponding second main driver terminal 120P.

[0053] As shown, the second pixel driver chip 110 (top pixel driver chip) can be connected to the first LED matrix 115A and the third LED matrix 115C, and the third LED matrix 115C similarly includes a plurality of third main strings 107P LEDs and a plurality of third redundant strings 107R LEDs. Similarly, the second pixel driver chip 110 (top pixel driver chip) can include a third group of third output drivers 140-0 for driving a plurality of third redundant strings 107R LEDs in the third LED matrix 115C, and a fourth group of fourth output drivers 140-1 for driving a plurality of first main strings 107P LEDs in the first LED matrix 115A. Each third output driver 140-0 is connected to a corresponding third driver terminal switch 130 to select the third main driver terminal 120P or the third redundant driver terminal 120R of the second pixel driver chip 110, and each fourth output driver 140-1 is connected to a corresponding fourth driver terminal switch 130 to select the fourth main driver terminal 120P or the fourth redundant driver terminal 120R of the second pixel driver chip.

[0054] As shown in the figure, Figure 3B The additional redundancy scheme of the LED matrix connects the main string 107P LED and the redundant string 107R LED in the LED matrix to the main driver terminals and redundant driver terminals 120 (120P, 120R) for two adjacent pixel driver chips 110. Each pixel driver chip may further include a driver terminal switch 130 to select the main string LED or the redundant string LED. Such a redundant configuration can accommodate an increase in the number of DPPMs of the pixel driver chip by providing additional redundancy in each pixel driver chip. Therefore, the manufacturing yield can be improved and / or the LPM size can be increased. It should be understood that Figure 3B The embodiments shown in may additionally be combined with other redundancy configurations described herein, such as selective redundancy within functional blocks and shared pixel driver circuit redundancy.

[0055] Reference now Figure 3C , provides a schematic top view illustration of a redundancy scheme with a single pixel driver chip according to one embodiment. Figure 3C Indicates that Figure 2B As shown, each LED matrix 115 is driven by a single pixel driver chip 110, and the LED matrix 115 is not coupled to the output driver of another pixel driver chip 110 in the pixel driver chip array. Figure 3C The pixel driver chip may be similar to that previously described with respect to Figure 3BIn this case, the number of pixel driver chips 110 can be reduced, thereby driving down display cost by driving down silicon cost. However, the lack of pixel driver chip redundancy can reduce DPPM tolerance, and display panel yield can be reduced. This can be balanced by reducing the LPM size and therefore reducing the LED matrix 115 size while maintaining DPPM tolerance, such as due to the redundant strings 107P, 107R LEDs and driver terminal switches 130.

[0056] exist FIG. 3A to FIG. 3C In the particular configuration shown, the first portion (slice 0) of pixel driver circuit 150-0 and the second portion (slice 1) of pixel driver circuit 150-1 are shown as separate slices (slices 0, 1). FIG. 3A to FIG. 3B In the exemplary implementation shown, such slice redundancy can facilitate pixel driver chip redundancy, where adjacent pixel driver chiplets 110 can back up each other for corresponding LED matrices 115. In this way, slices 0 / 1 of adjacent pixel driver chiplets 110 can share the same timing associated with the same matrix 115. In addition, slices 0 / 1 within the same pixel driver chiplet 110 can include independent logic to independently receive and store control bits and pixel bits. Figure 3C In the particular embodiment shown, adjacent pixel driver chips 110 do not back up each other for corresponding LED matrices 115. In such an embodiment, portions of pixel driver circuits 150-0, 150-1 for separate chips may optionally include independent logic to independently receive and store control bits and pixel bits. However, two or more portions separated into pixel driver circuits 150-0, 150-1 ... 150-n may be used to test functional groups (including groups of driver terminals, etc.), and independent logic may not be required to independently receive and store control bits and pixel bits. Therefore, it may not be necessary to test each single pixel driver pad, etc. In addition, such groupings may be used to implement additional functional block redundancy.

[0057] Referring now to FIG. 4 , a high level schematic diagram of the input / output terminals for the pixel driver chip 110 is provided according to one embodiment from a data load perspective. Data scanning is based on raster scanning using vertical data 350 signals (e.g., originating from a column driver) and horizontal data clock signals 330, 342 (e.g., originating from a row driver or hybrid pixel driver / row driver chip). Also shown in FIG. 4 is the input / output terminals for the pixel driver chip 110 as previously described. FIG. 2A to FIG. 2B The two parts (e.g., chips 0 and 1) of the pixel driver chip 110 are used to output row terminals 122 to the LED row interconnector 262 and driver terminals 120 (main driver terminals 120P, redundant driver terminals 120R) for the LED column interconnector 212 (main interconnector 212P, redundant interconnector 212R).

[0058] Each slice 1 / 0 may receive a separate input for a data clock 330, 342, a configuration clock 332, 344, a transmit clock 338, 346, respectively. In addition, each slice may include multiple transmit clock inputs 338, 346 for individual LED colors (e.g., R, G, B). The pixel driver chip 110 may additionally include inputs for global signals such as a row sync signal 334, a frame sync signal 336, and a vertical sync token (VST) 340.

[0059] According to some embodiments, the first portion (e.g., slice 1) and the second portion (e.g., slice 0) of each pixel driver chiplet 110 may optionally independently receive (e.g., capture) control bits and pixel bits for storage in corresponding data registers 335, 345 (see Figure 4B ). In operation, the configuration clock signals 332, 344 are transmitted to the slices of the pixel driver chip 110 to declare whether to update the control (configuration) bits or pixel bits from the data signal 350. When the configuration clock signals 332, 344 go high and overlap with the data clock 330, 342 of the corresponding slice 1 / 0, the control (configuration) bits or pixel bits of the pixel driver chip 110 slice are updated.

[0060] Depending on the embodiment, the pixel driver chiplet 110 may alternatively or additionally include a selective redundancy feature. Figure 4B 1 is a schematic diagram of various functional blocks found within the pixel driver chip 110. As shown, selective redundancy 400 may be included within various functional blocks, such as providing additional current sources / switches within a current source block, or providing memory / switches within a memory block, all of which may have corresponding redundant contact pads / terminals 402 (see Figure 6 ). Such redundant contact pads / terminals 402 may also be Figure 1B A portion of the contact pads 112. In addition, redundant contact pads / terminals 402 may be made for global signal I / Os, such as for the row sync signal 334, the frame sync signal 336, and the vertical sync token (VST) 340, as well as various power supplies.

[0061] Reference now Figure 5 , provides a partial circuit diagram of a pixel driver chip with a driver terminal switch 130 and optional redundant pixel driver circuits according to one embodiment. In general, Figure 5A high-level wiring for slice redundancy is shown, which includes a redundant circuit 150-R (e.g., a redundant slice) coupled between a first portion of a pixel driver circuit 150-0 (corresponding to slice 0) and a second portion of a pixel driver circuit 150-1 (corresponding to slice 1). As shown, the corresponding pixel driver circuit may have a digital block 152 and an analog block 154. In the illustrated specific embodiment, data (e.g., digital) may be input to a digital slice 152-0, for example, from a data register 335. Data (e.g., digital) may be input to a digital slice 152-1, for example, from a data register 345. Digital blocks 152-0, 152-1 may be input to optional analog blocks 154-0, 154-1, respectively, which are input to output drivers 140-0, 140-1, respectively. For example, an analog block may provide a current source. Various signals 156, 158 are input to various digital blocks 152 and analog blocks 154. For example, these signals may include a transmit clock, VST, etc. Similar to the previous description, the driver terminal switch 130 is connected to the output terminal of the output driver 140 so as to select the primary driver terminal 120P or the redundant driver terminal 120R.

[0062] In one embodiment, data (digital) inputs, such as from data registers 335, 345, are input into multiplexer 151 of redundant circuit 150-R. Multiplexer 151 has an output leading to redundant digital block 152-R, which outputs to the output of optional redundant analog block 154-R, which redundant digital block and optional redundant analog block can operate similarly to the digital block and analog block of slice 0 / 1. Redundant analog block 154-R can output a current source to redundant output driver 140-R. In the illustrated embodiment, a first redundant circuit selection switch 170-0R is located between redundant output driver 140-R and first driver terminal switch 130 (for slice 0). A second redundant selection circuit switch 170-1R is located between redundant output driver 140-R and first driver terminal switch 130 (for slice 1). Similarly, selection circuit switches 170 - 0 and 170 - 1 may be disposed between output drivers 140 - 0 , 140 - 1 and the corresponding driver terminal switches 130 of these output drivers.

[0063] As about Figure 4B As described, selective redundancy features may be included for specific functional blocks, such as additional memory (e.g., data registers 335, 345), current sources (e.g., analog block 154), global signals associated with pixel data, and control data latches. Figure 5 In the particular embodiment shown, the configuration blocks for the pixel driver chiplet 110 do not need to be redundant.

[0064] So far, building blocks for various redundant configurations have been described individually or in specific combinations. However, it should be understood that various building blocks can be combined to achieve specific redundancy. Figure 6 1 is a schematic diagram of a pixel driver chip 110 including a combination of redundant building blocks that can be used in various embodiments. In particular, Figure 6 A first portion of pixel driver circuit 150-0 (corresponding to slice 0), a second portion of pixel driver circuit 150-1 (corresponding to slice 1), and redundant circuit 150-R are shown. A plurality of driver terminal switches 130 are also shown between primary driver terminals 120P and redundant driver terminals 120R. Additionally, redundant contact pads / terminals 402 corresponding to a selective redundancy feature are shown. These various building blocks can be combined in various suitable arrangements to fabricate a pixel driver chip with a desired amount of redundancy for minimum DPPM and LPM sizes.

[0065] Fig. 7A FIG. 1 is a schematic top view illustration of a redundancy scheme including a pixel driver chip having driver terminal switches 140 arranged in an up / down redundancy scheme. As shown in the figure, Fig. 7A Driver terminal switches 130, redundancy circuits 150-R, or redundant building blocks with selective redundancy features of additional terminals 402 are not implemented.

[0066] Figure 7B FIG. 1 is a schematic top view illustration of a redundant scheme including a pixel driver chiplet having driver terminal switches arranged in a redundant scheme with a spare pixel driver chiplet according to one embodiment. As shown in the figure, Figure 7B A redundant building block of driver terminal switches 130 is implemented. In this way, each slice 0 / 1 of each pixel driver chiplet 110 can provide redundancy to the slice of an adjacent pixel driver chiplet 110. Exemplary modes of operation include a master / slave arrangement, where slices are assigned as primary or redundant by default and only require reprogramming in the event of a defect. Another mode of operation is to make each other pixel driver chiplet in the column active or inactive (i.e., backup). Alternatively, the driver terminal switches 130 can be selected in any suitable manner to make a combination of the primary driver terminals 120P and the redundant driver terminals 120R active.

[0067] FIG. 7C to FIG. 7C ' is a schematic top view illustration of a redundancy scheme including a pixel driver chiplet having driver terminal switches arranged in a redundancy scheme with a single pixel driver chiplet according to one embodiment. FIG. 7C to FIG. 7CBoth implement redundant building blocks of the driver terminal switches 130. In such a single pixel driver chip arrangement, each LED matrix 115 is connected to only a single pixel driver chip 110. Figure 7C The embodiment shown in ' additionally includes redundant contact pads / terminals 402 corresponding to the selectively redundant features.

[0068] Figure 7C ” is a schematic top view illustration of a redundancy scheme including a pixel driver chiplet having driver terminal switches and redundant pixel driver circuits arranged in a redundancy scheme with a single pixel driver chiplet according to one embodiment. Figure 7C The specific embodiment shown in " is similar to Figure 7C 'Specific implementation, in which redundant circuit 150-R is added. It should be understood that the implementation is not limited to 7A to 7C ” The specific combinations specifically shown in the “, and the various redundant building blocks described herein may be combined in any suitable manner. For example, the embodiments of Figures 7 ' to 7 ” may be performed without separate portions of the pixel driver circuits 150-0, 150-1, 150-R...150-n.

[0069] Figures 8 to 11 Various portable electronic systems are shown in which various embodiments may be implemented. Figure 8 An exemplary mobile phone 800 is shown including a display panel 103 including a display screen 101 enclosed in a housing 802 . Fig. 9 An exemplary tablet computing device 900 is shown that includes a display panel 103 including a display screen 101 enclosed in a housing 902 . Fig.10 An exemplary wearable device 1000 is shown that includes a display panel 103 including a display screen 101 enclosed in a housing 1002 . Fig.11 An exemplary laptop computer 1100 is shown that includes a display panel 103 including a display screen 101 enclosed in a housing 1102 .

[0070] Fig.12 A system diagram of an embodiment of a portable electronic device 1200 including a display panel 103 as described herein is shown. The portable electronic device 1200 includes a processor 1220 and a memory 1240 for managing the system and executing instructions. The memory includes non-volatile memory, such as flash memory, and may additionally include volatile memory, such as static or dynamic random access memory (RAM). The memory 1240 may additionally include a portion dedicated to read-only memory (ROM) to store firmware and configuration utilities.

[0071] The system also includes a power module 1280 (e.g., a flexible battery, wired or wireless charging circuitry, etc.), a peripheral interface 1208, and one or more external ports 1290 (e.g., Universal Serial Bus (USB), HDMI, DisplayPort, and / or other). In one embodiment, the portable electronic device 1200 includes a communication module 1212 configured to interface with the one or more external ports 1290. For example, the communication module 1212 may include one or more transceivers that operate in accordance with IEEE standards, 3GPP standards, or other communication standards, 4G, 5G, etc. and are configured to receive and transmit data via the one or more external ports 1290. The communication module 1212 may additionally include one or more WWAN transceivers configured to communicate with a wide area network including one or more cellular towers or base stations to communicatively connect the portable electronic device 1200 to additional devices or components. Additionally, the communication module 1212 may include one or more WLAN and / or WPAN transceivers configured to connect the portable electronic device 1200 to a local area network and / or a personal area network, such as a Bluetooth network.

[0072] The display system 1200 may also include a sensor controller 1270 to manage input from one or more sensors (such as, for example, a proximity sensor, an ambient light sensor, or an infrared transceiver). In one embodiment, the system includes an audio module 1231, which includes one or more speakers 1234 for audio output and one or more microphones 1232 for receiving audio. In an embodiment, the speaker 1234 and the microphone 1232 can be piezoelectric components. The portable electronic device 1200 also includes an input / output (I / O) controller 1222, a display screen 101, and additional I / O components 1218 (e.g., keys, buttons, lights, LEDs, cursor control devices, tactile devices, etc.). The display screen 101 and the additional components 1218 can be considered to form part of a user interface (e.g., a portion of the portable electronic device 1200 associated with presenting information to a user and / or receiving input from a user).

[0073] The various embodiments described herein can be combined in various suitable ways to achieve a particular redundancy. In one embodiment, the display panel 103 includes an array of pixel driver chips 110 connected to a corresponding array of LED matrices 115, the LED matrix arrays including a first LED matrix 115-A, and the pixel driver chip array includes a first pixel driver chip 110 connected to the first LED matrix 115-A (see, e.g., FIG. 3A to FIG. 3C The middle pixel driver chip in the ).

[0074] The first LED matrix 115-A may include a plurality of first main strings 107P LEDs and a plurality of redundant strings 107R LEDs. As shown, the first pixel driver chip includes a corresponding plurality of first main driver terminals 120P coupled to the plurality of first main strings 107P LEDs and a corresponding plurality of first redundant driver terminals 120R coupled to the plurality of first redundant strings 107R LEDs. The first pixel driver chip 110 may further include a first portion of a pixel driver circuit 150-0, the first portion including a first group of output drivers 140-0 and a first group of driver terminal switches 130, wherein each first output driver 140-0 is connected to a corresponding first driver terminal switch 130 to select a first main driver terminal 120P or a first redundant driver terminal switch 120R of the first pixel driver chip 110 (middle). The driver terminal switches according to the embodiment may be tri-state switches.

[0075] The LED matrix array according to the embodiment may further include a second LED matrix 115-B to which the first pixel driver chip 110 is connected. Similarly, the second LED matrix 115-B includes a plurality of second main strings 107P LEDs and a plurality of second redundant strings 107R LEDs. The first pixel driver chip 110 (middle) includes a corresponding plurality of second main driver terminals 120P coupled to the plurality of second main strings 107P LEDs and a corresponding plurality of second redundant driver terminals 120R coupled to the plurality of second redundant strings 107R LEDs. As shown, the first pixel driver chip 110 may also include a second portion of the pixel driver circuit 150-1, the second portion including a second group of output drivers 140-1 and a second group of driver terminal switches 130, wherein each second output driver 140-1 is connected to a corresponding second driver terminal switch 130 to select the second main driver terminal 120P or the second redundant driver terminal 120R of the first pixel driver chip 110 (middle).

[0076] The pixel driver chip array may include a second pixel driver chip 110 (eg, Figure 3B). Similarly, the third LED matrix 115-C may include a plurality of third main strings 107P LEDs and a plurality of third redundant strings 107R LEDs. The second pixel driver chip 110 may include a third group of third output drivers 140-0; and a corresponding plurality of third main driver terminals 120P and a corresponding plurality of third redundant driver terminals 120R, the corresponding plurality of third main driver terminals are coupled to a plurality of third main strings 107P LEDs in the third LED matrix 115-C, and the corresponding plurality of third redundant driver terminals are coupled to a plurality of third redundant strings 107R LEDs in the third LED matrix 115-C. As shown in the figure, the second pixel driver chip 110 may include a fourth group of output drivers 140-1; and a corresponding plurality of fourth main driver terminals 120P and a corresponding plurality of fourth redundant driver terminals 120R, the corresponding plurality of fourth main driver terminals are coupled to a first main string 107P LED in the first LED matrix 115-A, and the corresponding plurality of fourth redundant driver terminals are coupled to a plurality of first redundant strings 107R LEDs in the first LED matrix 115-A. Each third output driver 140-0 may be connected to a corresponding third driver terminal switch 130 to select a third primary driver terminal 120P or a third redundant driver terminal 120R of a second pixel driver chip (e.g., connected to the third LED matrix 115-C), and each fourth output driver 140-1 may be connected to a corresponding fourth driver terminal switch to select a fourth primary driver terminal 120P or a fourth redundant driver terminal 120R of a second pixel driver chip (e.g., connected to the first LED matrix 115-C). Figure 2A As shown, a plurality of row interconnects 262 may be connected between a first plurality of row terminals 122 (chip 0) of a first pixel driver chip and a corresponding second plurality of row terminals 122 (chip 1) of a second pixel driver chip. In addition, each row interconnect 262 may be coupled to a row of primary LEDs and redundant LEDs in both the plurality of first redundant strings 107RLEDs and the plurality of first primary strings 107PLEDs in the first LED matrix 115-A. Each of the first portion 150-0 and the second portion 150-1 of the pixel driver circuit may include independent logic to receive control bits and pixel bits independently of each other.

[0077] In one embodiment, the first LED matrix 115-A and the second LED matrix 115-B are not coupled to the output driver of another pixel driver chip in the array of pixel driver chips, see e.g. Figure 3C The plurality of row interconnectors 262 may be connected to the first pixel driver chip 110 (eg, Figure 3CThe first plurality of row terminals 122 of the middle chip in the first LED matrix 115-A are connected to a row of main LEDs and redundant LEDs in both the plurality of first redundant strings 107R LEDs and the plurality of first main strings 107P LEDs in the first LED matrix 115-A. Figure 2B As shown, the pixel driver chip 110 may be similarly coupled to a row of primary LEDs and redundant LEDs in both the plurality of first redundant strings 107R LEDs and the plurality of first primary strings 107P LEDs in the second LED matrix 115-B. In both cases, the row interconnect 262 may not be bonded to adjacent pixel driver chips 110, such as Figure 2A shown.

[0078] The pixel driver chip 110 according to an embodiment may include additional redundancy features. In one embodiment, the redundant circuit 150-R (e.g., see Figure 5 ) may be coupled between a first portion of the pixel driver circuit 150-0 and a second portion of the pixel driver circuit 150-1. A first redundant circuit selection switch 170-R may be connected between a redundant output driver 140-R and a first driver terminal switch 130 (in the second portion of the pixel driver circuit 150-0), and a second redundant circuit selection switch 170-1R may be connected between a redundant output driver 140-R and a second driver terminal switch 130 (in the second portion of the pixel driver circuit 150-1). In addition, a first digital input terminal 335 and a second digital input terminal 345 may be connected to a multiplexer 151 in the redundant circuit 150-R. It should be understood that additional redundant circuit configurations are contemplated and embodiments are not limited thereto. Redundancy may be included in various functional blocks within the pixel driver circuit. For example, a redundant current source may be included. In one embodiment, a first portion of the pixel driver circuit includes a first redundant current source contact pad (e.g., Figure 1B 122), and the second portion of the pixel driver circuit includes a second redundant current source contact pad (eg, Figure 1B A plurality of redundant contact pads may be included in a redundant functional block.

[0079] When utilizing various aspects of the embodiments, it will become apparent to those skilled in the art that combinations or variations of the above embodiments are possible for forming display panel redundancy schemes. Although the embodiments are described in language specific to structural features and / or methodological acts, it should be understood that the appended claims are not necessarily limited to the specific features or acts described. The specific features and acts disclosed should instead be understood as embodiments of the claims for illustrative purposes.

Claims

1. A display panel, comprising: a pixel driver chip array connected to a corresponding LED matrix array, the LED matrix array comprising a first LED matrix, and the pixel driver chip array comprising a first pixel driver chip connected to the first LED matrix; wherein the first LED matrix comprises a plurality of first main strings of LEDs and a plurality of first redundant strings of LEDs; wherein the first pixel driver chip comprises a corresponding plurality of first primary driver terminals coupled to the plurality of first primary strings of LEDs and a corresponding plurality of first redundant driver terminals coupled to the plurality of first redundant strings of LEDs; and The first pixel driver chip includes a first part of a pixel driver circuit, and the first part of the pixel driver circuit includes: a first set of first output drivers; and a first set of first driver terminal switches; Each first output driver is connected to a corresponding first driver terminal switch to select a first main driver terminal or a first redundant driver terminal of the first pixel driver chip, and the first driver terminal switch switches between the first main driver terminal and the first redundant driver terminal. 2 . The display panel of claim 1 , wherein each of the first driver terminal switches is a three-state switch.

3. The display panel according to claim 1, wherein the LED matrix array includes a second LED matrix, and the first pixel driver chip is connected to the second LED matrix; wherein the second LED matrix comprises a plurality of second main strings of LEDs and a plurality of second redundant strings of LEDs; The first pixel driver chip comprises a corresponding plurality of second main driver terminals coupled to the plurality of second main strings of LEDs and a corresponding plurality of second redundant driver terminals coupled to the plurality of second redundant strings of LEDs.

4. The display panel according to claim 3, wherein the first pixel driver chip comprises a second portion of a pixel driver circuit, the second portion of the pixel driver circuit comprising: a second set of second output drivers; and a second set of second driver terminal switches; Each second output driver is connected to a corresponding second driver terminal switch to select a second main driver terminal or a second redundant driver terminal of the first pixel driver chip.

5. The display panel according to claim 4, wherein the pixel driver chip array includes a second pixel driver chip connected to the first LED matrix and the third LED matrix; wherein the third LED matrix comprises a plurality of third main strings of LEDs and a plurality of third redundant strings of LEDs; The second pixel driver chip comprises: a third group of third output drivers; a corresponding plurality of third primary driver terminals coupled to the plurality of third primary strings of LEDs in the third LED matrix and a corresponding plurality of third redundant driver terminals coupled to the plurality of third redundant strings of LEDs in the third LED matrix; and a fourth group of fourth output drivers; a corresponding plurality of fourth primary driver terminals coupled to the plurality of first primary strings of LEDs in the first LED matrix and a corresponding plurality of fourth redundant driver terminals coupled to the plurality of first redundant strings of LEDs in the first LED matrix, Wherein each third output driver is connected to a corresponding third driver terminal switch to select a third main driver terminal or a third redundant driver terminal of the second pixel driver chip, and each fourth output driver is connected to a corresponding fourth driver terminal switch to select a fourth main driver terminal or a fourth redundant driver terminal of the second pixel driver chip.

6. The display panel according to claim 5, further comprising: A plurality of row interconnects are connected between a first plurality of row terminals of the first pixel driver chip and a corresponding second plurality of row terminals of the second pixel driver chip, wherein each of the plurality of row interconnects is coupled to both the plurality of first redundant string LEDs and the plurality of first main string LEDs in the first LED matrix.

7. The display panel of claim 4, wherein the first and second portions of the pixel driver circuit include independent logic to each independently receive the control bit and the pixel bit.

8. The display panel of claim 4, wherein the first LED matrix and the second LED matrix are not coupled to an output driver of another pixel driver chip in the pixel driver chip array.

9. The display panel according to claim 8, further comprising: A plurality of row interconnects connected to a first plurality of row terminals of the first pixel driver chip, wherein each of the plurality of row interconnects is coupled to both the plurality of first redundant string LEDs and the plurality of first main string LEDs in the first LED matrix.

10. The display panel according to claim 4, further comprising: A redundant circuit is coupled between the first portion of the pixel driver circuit and the second portion of the pixel driver circuit. The display panel of claim 10 , wherein the redundant circuit comprises a redundant output driver.

12. The display panel according to claim 11, further comprising: a first redundant circuit selection switch, the first redundant circuit selection switch being located between the redundant output driver and the first driver terminal switch; and A second redundant circuit selection switch is located between the redundant output driver and the second driver terminal switch. 13 . The display panel of claim 11 , wherein the first digital input terminal and the second digital input terminal are connected to a multiplexer in the redundant circuit.

14. The display panel according to claim 4, wherein: The first portion of the pixel driver circuit includes a first redundant current source contact pad for the first pixel driver chip; and The second portion of the pixel driver circuit includes a second redundant current source contact pad for the first pixel driver chip.

15. A pixel driver chip, comprising: a first plurality of primary driver terminals and a corresponding first plurality of redundant driver terminals; and A first part of a pixel driver circuit, the first part of the pixel driver circuit comprising: a first set of first output drivers; and a first set of first driver terminal switches; Each first output driver is connected to a corresponding first driver terminal switch to select a first main driver terminal or a first redundant driver terminal, and the first driver terminal switch switches between the first main driver terminal and the first redundant driver terminal.

16. The pixel driver chip according to claim 15, further comprising: a second plurality of primary driver terminals and a corresponding plurality of second redundant driver terminals; and A second part of the pixel driver circuit, the second part of the pixel driver circuit comprising: a second set of second output drivers; and a second set of second driver terminal switches; Each of the second output drivers is connected to a corresponding second driver terminal switch to select the second main driver terminal or the second redundant driver terminal.

17. The pixel driver chip according to claim 16, further comprising: A redundant circuit is coupled between the first portion of the pixel driver circuit and the second portion of the pixel driver circuit.

18. The pixel driver chip of claim 17, wherein the redundant circuitry comprises redundant output drivers.

19. The pixel driver chip according to claim 18, further comprising: a first redundant circuit selection switch, the first redundant circuit selection switch being located between the redundant output driver and the first driver terminal switch; and A second redundant circuit selection switch is located between the redundant output driver and the second driver terminal switch.

20. The pixel driver chip according to claim 18, wherein: The first portion of the pixel driver circuit includes a first data input terminal; and The second portion of the pixel driver circuit includes a second data input terminal; The first data input terminal and the second data input terminal are connected to a multiplexer in the redundant circuit.

21. The pixel driver chip according to claim 16, wherein: The first portion of the pixel driver circuit comprises a plurality of non-redundant first row terminals; and The second portion of the pixel driver circuit includes a plurality of non-redundant second row terminals.

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