Semiconductor device

Abstract

A semiconductor device includes at least three arms. Channels of the first and second arms extend to a channel of the third arm. A ballistic electron current is generated from the channels of the first and second arms to the channel of the third arm when a current from the first arm flows to the second arm due to an application of a first voltage. A fin structure is located in the third arm and includes a gate above the fin structure. The gate is controlled using a second voltage. The fin structure is formed to induce an energy field structure that is shifted by an amount of the second voltage to control an opening through which the ballistic electron current of the gate passes, thereby subjecting the ballistic electrons to diffraction and then interference, which in turn changes a depletion width.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor devices, and more particularly to the field of gate-controlled semiconductor devices. Background Technology

[0002] Superconducting electronic devices (SCEs) based on Josephson junctions (JJs) offer several options in the timescale beyond Moore's Law. Digital superconducting electronic devices based on single-flux quantum (SFQ) logic are an area of ​​research to further understand SFQ logic in multiple logic families at integration levels of up to approximately one million devices per chip. Since its inception in the 1960s, superconducting electronic devices have been considered an option for supercomputers, although the term "supercomputer" has been expanded to include data centers. Quantum information processing (QIP) is a rapidly developing field that includes areas such as quantum computing and quantum artificial intelligence. Since the discovery of Shor's algorithm for factoring numbers, quantum computers have been considered ultra-powerful computers in finite fields.

[0003] For example, a quantum computer is a computing system that uses the collective quantum mechanical phenomena of atoms in highly quantum degenerate regions to process data. Unlike digital computers, which encode data as binary digits (bits) in one of two definite states ("0" or "1"), quantum computing requires encoding data into qubits (qubits), where a single qubit can represent "1", "0", or any quantum superposition of these two qubit states. Typically, a quantum computer with N qubits can be in up to 2^32 states simultaneously. N In any superposition of four different states, that is, a pair of qubits can be in any superposition of four states, and three qubits can be in any superposition of eight states. Large-scale quantum computers can solve certain problems faster than digital computers. In the operation of a quantum computer, computation is initialized by setting the qubits to controlled initial states. By manipulating these qubits, quantum logic gates representing a predetermined sequence of problems to be solved are implemented; this is called a quantum algorithm. Quantum algorithms, such as Shor's algorithm and Simon's algorithm, run faster than any possible probabilistic conventional algorithm. Quantum algorithms are typically nondeterministic because they only provide the correct solution with a certain known probability. The computation is accomplished using a measurement that compresses the system of qubits into 2... N One of the pure states, in which each quantum bit is either "0" or "1".

[0004] Many different types of quantum computers have been developed. For example, the trapped-ion quantum computer is a type of quantum computer in which ions, or charged atomic particles, can be confined and suspended in free space using an electromagnetic field. Qubits are stored as the stable electronic states of individual ions, and quantum information can be processed and transmitted through the collective quantized motion of the ions in the trap (via Coulomb force interactions).

[0005] US 5,793,091A (PTL 1) developed a quantum computer architecture based on an array of elliptical ion traps. Each ion trap contains multiple ions, and each ion stores a physical qubit. Single-qubit operations are performed on the ions using appropriately timed laser pulses. Two-qubit quantum communication operations between ions in a single trap are mediated by a collective phonon mode of the trapped ions. Quantum communication between ions in different traps is achieved by placing the traps in cavities and using a photonic cavity mode to mediate between ions separated in a specified space. However, the architecture of US 5,793,091A does not address the conventional control electronics and software necessary to execute various quantum algorithms. Furthermore, the physical location of the ion traps must allow the cavity photonic mode to transfer quantum information from one trap to another; distributed ion traps are not supported, and the architecture does not address error correction. Additionally, the architecture of US 5,793,091A fails to provide all the components required for a complete quantum computer architecture: local quantum computing, distributed quantum computing, conventional control electronics, conventional control software, and error correction.

[0006] [List of References]

[0007] [Patent Literature]

[0008] [PTL1]

[0009] US 5,793,091A Summary of the Invention

[0010] Technical issues

[0011] Therefore, with the rise of quantum computing, it is necessary to overcome the problem that conventional electronic devices cannot function properly at temperatures below 4K due to the carrier freeze-out effect, and to improve the electronic control devices for quantum computers used in quantum computing.

[0012] Technical solution

[0013] This disclosure relates to semiconductor devices, and more particularly to the field of gate-controlled semiconductor devices.

[0014] Some embodiments of this disclosure include a semiconductor device comprising a structure having a first arm, a second arm, and a third arm, wherein channels of the first and second arms extend to a channel of the third arm. When a current from a first voltage flows from a first electrode of the first arm to a second electrode of the second arm, a ballistic electron flow is generated from the channels of the first and second arms to the channel of the third arm, flowing through the third arm channel. The semiconductor device may include a fin structure located in the third arm channel and positioned at a conduction change distance from the end of the third arm. The fin structure includes a gate formed transversely to the longitudinal axis of the fin structure. The gate is controlled using a second voltage on the fin structure. The fin structure may be configured to sense an energy field structure that is shifted by the amount of the second voltage to control the opening through which the ballistic electron flow through the gate will pass, thereby subjecting the ballistic electrons to diffraction and then interference, the opening altering the depletion width.

[0015] However, to better understand the challenges overcome by this disclosure, it is necessary to understand some of the conventional problems of conventional quantum computers today. The initial challenge overcome using conventional quantum computers was developing a quantum computer that eliminates the need for conventional electronics to obtain a working quantum computer. In particular, this disclosure overcomes multiple implementations using conventional electronics by creating a single device for quantum computing that essentially combines the features of conventional electronics with components for quantum computing; that is, conventional electronics are not required. At least one reason for eliminating the use of conventional electronic components with quantum computing components is that conventional electronic devices operate at a single temperature (i.e., room temperature), while quantum computing components operate at different temperatures (i.e., below zero degrees Celsius).

[0016] Conventional electronic devices used in quantum computing are used for qubit control and readout (i.e., shaping electrical pulses, amplification, etc.). For example, a qubit (or quantum bit) is the fundamental container of information in a quantum computer, replacing the conventional fundamental container of information in a conventional computer, the "bit". Conventional electronic components operate at room temperature, while most quantum computing qubits operate near absolute zero. This creates a requirement for electronic devices that can operate at milliKelvin (mK) temperatures to avoid unacceptable cooling loads. Conventional electronic devices cannot function properly below 4K due to carrier freezing effects. The inoperability of conventional electronic devices at lower temperature limits is due to temperature effects that lower the ionization energy of dopants in conventional electronic devices. Dopants are impurity elements added to semiconductor crystals to form electrical junctions or boundaries between "n" and "p" regions in the crystal. The n-type region contains an excess of electrons for conduction. The p-type region contains an excess of electron holes or acceptors. Dopants typically require some energy to ionize and generate charge carriers in the semiconductor. This energy is typically thermal, and if the temperature is too low, the dopant will not be sufficiently ionized and there will be insufficient charge carriers; that is, the lack of charge carriers means that there is little or no current flow. The result is a condition known as "freezing".

[0017] Semiconductor devices operate by means of the movement of charge carriers (electrons and holes). The key is to control this movement through the arrangement of n-type, p-type, and intrinsic regions (and insulators) with different electrical properties. A simple example is the pn junction, where, due to different doping on both sides of the junction, charge carriers can move through the junction in one direction rather than the other. This means that temperature is one of the most important parameters in semiconductors. When absolute scaling is mentioned in this disclosure, it refers to temperatures expressed in Kelvin, such as 300 K or 0 K, without a degree symbol because it is an absolute temperature. Temperature is very important, at least because the average energy of a solid and its components (atoms, electrons, etc.) is measured by its temperature. The higher the temperature, the more (thermal energy) is available to atoms and electrons. Temperature has a significant effect on the behavior of electrons regarding temperature and the operation of conventional “electronic” devices, meaning that temperature must have a significant effect on the behavior of electronic devices. For example, the average kinetic energy of electrons in a solid is linearly proportional to the temperature of the solid, such that at room temperature, the average velocity of a free electron is approximately 10⁻⁶. 7 cm / sec. At absolute zero, the average velocity of a free electron is approximately equal to that of its lowest energy state. Therefore, addressing how electronic devices can operate at low temperatures and require extremely high energy efficiency presents numerous challenges.

[0018] At least one implementation of this disclosure involves constructing a semiconductor device that eliminates the need for conventional electronic devices and essentially combines the practicality of conventional electronics into a single device capable of operating at sub-zero temperatures. However, this implementation contradicts conventional thinking because current quantum computing requires substantial conventional information processing via conventional electronic components (i.e., control processing units) to compute the quantum operations needed to correct errors based on measured synthesis results, requiring significant additional time for this processing, which slows down the operation of the quantum computer. For example, an initial experiment began with a modular quantum computer architecture having a hierarchical structure supporting a large number of qubits and interactions between qubits, and used to form the quantum computing circuitry. However, to make the test quantum computer run, the experimental architecture required a control processor unit (CPU) to handle efficient error correction mechanisms and intelligent coding schemes for fault-tolerant operation. This test device was not further tested because it failed to meet some of the goals of this disclosure regarding creating a single device capable of operating at a single temperature for quantum computing.

[0019] Further experiments revealed that another implementation of this disclosure utilizes polarization-based doping as an efficient way to circumvent the operational component problems of conventional quantum computing devices that require two operating temperatures. Instead, it features a single device operating at sub-zero temperatures (i.e., at a single operating temperature) because the charge carriers are not provided by the dopant. Polarization doping is used to generate free electrons. These free electrons are generated at the interface of two semiconductor materials with two different spontaneous polarizations. Since the proposed method uses polarization rather than doping to generate free carriers, the free carrier density is temperature-independent. For example, some embodiments of this disclosure include a single semiconductor device utilizing polarization-based doping to generate free electrons at sub-zero temperatures, where free electrons enter a channel having a gate or two gates connected in series. The gates open and close based on a certain amount of bias voltage. A voltage is applied to the gates to change the depletion width, which in turn changes the aperture through which the electrons pass. As they pass through this narrow channel of the gates, the electrons undergo diffraction and then interference due to the wave-like nature of the electrons. This interference pattern produces a conductivity variation pattern, which allows a sensor to detect the amount of conductivity. Based on the applied gate bias, the detected conductance can vary by several orders of magnitude, allowing the small semiconductor device of this disclosure to be used as an inverter by sensing the conductance level. An inverter is one of the fundamental building blocks of any kind of digital circuit. The purpose of this circuit is to invert a signal; if the input is 1, the output is 0, and vice versa, hence the name inverter. Inverters aid in signal processing and useful computations. For example, inverters are needed to construct full adders or half adders. In other words, since low conductance refers to state 0 and high conductance refers to state 1, the detected conductance level causes the semiconductor device to operate as an inverter.

[0020] Some embodiments of this disclosure include a semiconductor structure comprising an epitaxial layer of a III-N heterostructure (preferably InAlN / GaN). The indium concentration can be tuned to match the GaN lattice to provide the higher electron mobility necessary for the generation of ballistic electrons.

[0021] Some embodiments of the semiconductor structure disclosed herein also include a voltage applied between the electrodes of the first arm and the second arm of the cross-shaped structure to generate high-speed electrons / ballistic electrons. These ballistic electrons then reach the third arm, which also has a voltage applied to its electrodes. Two fin structures or fin-shaped structures are fabricated in the third arm, followed by oxide and gate metal deposition around the fins. A voltage can be applied to the third electrode to change the respective gate depletion width; that is, as a higher voltage is applied, the depletion depth increases and the gate is turned on (see...). Figure 3A and Figure 3BThis, in turn, changes the aperture through which electrons pass through the two fin structures.

[0022] The device does not require a fourth arm for operation; however, a fourth arm may be used to determine whether ballistic electrons can be detected. Ballistic electrons are detected by measuring the voltage between the fourth and third arms. In the case of ballistic electrons, the voltage measured between the third and fourth arms will be negative; otherwise, it will be zero.

[0023] When passing through the narrow gate channel, electrons undergo diffraction due to their wave-like properties, and then interference as an interference pattern. This interference pattern produces a conductivity variation pattern (as mentioned above) at a distance D from the two fin structures to the end of the third arm. Wherein, if the metal is placed at a distance D from the two fin structures, and depending on the vertical position of the metal, a sensor position close to the metal can detect low or high conductivity. By applying a gate bias voltage, the detected conductivity can vary by several orders of magnitude. Therefore, by sensing the conductivity level, the semiconductor device of some embodiments of the present invention can be used as an inverter.

[0024] Practical Applications

[0025] One of the benefits and advantages of quantum computing is that, compared to using a conventional computer, the amount of time a quantum computer takes to run several times still yields results for solving very difficult problems exponentially faster. The amount of time a conventional computer takes to work on the same very difficult problem in a single run is equal to or corresponds to the amount of time a quantum computer takes to run it many times. The need for quantum computing to solve many of the complex problems that require it today is characterized by this exponential growth in the difficulty of solving such complex problems. For example, embodiments of this disclosure can therefore provide faster computation times for optimization problems, machine learning, sampling of large datasets, prediction, etc., through non-limiting examples. Furthermore, embodiments of this disclosure can address the growing need to solve these complex problems through the quantum computing properties of this disclosure.

[0026] Specifically, what makes quantum computers unique is the introduction of two quantum mechanical principles that are crucial to their operation: superposition and entanglement.

[0027] Superposition is the counterintuitive ability of quantum objects (such as electrons) to exist simultaneously in multiple "states." In the case of an electron, one of these states could be the lowest energy level in an atom, while the other could be the first excited energy level. If an electron is prepared under a superposition of these two states, then the electron has a certain probability of being in the lower state and a certain probability of being in the higher state. Measurement will disrupt this superposition, and only in this way can we say that it is in the lower or higher state.

[0028] Some embodiments of this disclosure provide a platform that allows such a configuration of quantum computing hardware to be built on a control electronics unit (CPU). At least one aspect of this arrangement is chip integration of the CPU and the quantum computing, which results in even faster overall quantum computing processing, i.e., compared to conventional systems that require two separate temperature zones—one for conventional electronics at room temperature and the other for quantum computing at zero temperature. For example, understanding superposition allows for understanding the fundamental components of information in quantum computing, namely, qubits. In conventional computing, a bit is a transistor that can be turned off or on, corresponding to states 0 and 1. In qubits such as electrons, 0 and 1 simply correspond to lower and higher energy levels as discussed above. The difference between qubits and conventional bits, which must always be in a 0 or 1 state, is that they can be in a superposition state with varying probabilities, which can be manipulated by quantum operations during computation.

[0029] Entanglement is a phenomenon in which quantum entities are created and / or manipulated such that neither of the two quantum entities can be described without involving the other quantum entities. They lose their individual identifiers. This concept is extremely difficult to conceptualize when considering how entanglement can persist over long distances. A measurement of one member of an entangled pair will immediately determine a measurement of its partner, making it seem as if information can travel faster than the speed of light. As mentioned above, some implementations provide platforms for integrating quantum computers, allowing all such quantum computing hardware to be built on a control electronics (CPU) unit. This on-chip integration of the CPU and quantum computing makes the entire quantum computing process even faster.

[0030] One approach to quantum computing is to solve a problem in parallel by trying every possible answer. In practice, a quantum computer uses the entanglement between qubits and the probabilities associated with superposition to perform a series of operations (quantum algorithms) that increase some probabilities (i.e., the probability of the correct answer) while decreasing others (i.e., the probability of the incorrect answer), even to zero. When a measurement is taken at the end of the computation, the probability of the correct answer should be maximized. The way quantum computers utilize probability and entanglement makes them so different from traditional computers. As mentioned above, some implementations provide platforms for integrating quantum computers.

[0031] One reason for the need for quantum computing is the prospect of developing a sufficiently sophisticated quantum computer to execute a large number of Shor's algorithms; that is, executing a large number of Shor's algorithms is a major motivation for advancing the field of quantum computing. For example, if a quantum computer with a sufficient number of qubits can operate without obeying quantum noise and other quantum decoherence phenomena, then Shor's algorithms can be used to break public-key cryptographic schemes (such as the widely used public-key encryption algorithm (RSA)). RSA encryption is based on the simple concept of prime factorization, the algorithm used to encrypt and decrypt messages. As mentioned above, quantum computers are most likely to be helpful for specific problems, including optimization-related problems, which play a crucial role in everything from defense to financial transactions. As mentioned above, some implementations provide platforms for integrating quantum computers.

[0032] There are also several additional applications of qubit systems that do not involve computation or simulation. These applications may include: (1) quantum sensing and metrology, which utilizes the extreme sensitivity of qubits to their environment to achieve sensing beyond the limitations of conventional shot noise; and (2) quantum networks and communications, which can lead to revolutionary ways of information sharing. As mentioned above, some implementations provide platforms for integrating quantum computers.

[0033] According to embodiments of this disclosure, a semiconductor device configured to operate as an inverter is provided. The semiconductor device includes an epitaxial layer forming a channel and includes a III-N heterostructure such as InAlN / GaN. The amount of In concentration in the InAlN / GaN is tuned to match the GaN lattice, thereby generating electron mobility to produce ballistic electrons. A fin structure located in the channel is positioned at a conductance variation distance from the end of the channel. The fin structure includes a gate formed transversely to the longitudinal axis of the channel. The gate is controlled using a voltage on the fin structure. The fin structure is configured to sense an energy field structure that shifts by the amount of voltage to control the opening through which the ballistic electron flow through the gate is passed, thereby interfering with the ballistic electrons and altering the depletion width. The semiconductor device is turned on by applying a voltage and turned off by not applying a voltage.

[0034] Another embodiment of this disclosure provides a semiconductor device configured to operate as an inverter. The semiconductor device includes an epitaxial layer forming a channel and includes a III-N heterostructure such as InAlN / GaN, wherein the amount of In concentration in the InAlN / GaN is tuned to match the GaN lattice, thereby generating electron mobility to produce ballistic electrons. At least two fin structures located in the channel are positioned at a conductance variation distance from the end of the channel. Each fin structure includes a gate formed transversely to the longitudinal axis of the channel. The gate is controlled using a voltage on the fin structure. The fin structure is configured to sense an energy field structure that is shifted by the amount of voltage to control the opening through which the ballistic electron flow through the gate is passed, thereby interfering with the ballistic electrons and altering the depletion width. The semiconductor device is turned on by applying a voltage and turned off by not applying a voltage.

[0035] Another embodiment of this disclosure provides a semiconductor device configured to operate as an inverter. The semiconductor device includes an epitaxial layer forming a channel and includes a III-N heterostructure such as InAlN / GaN. The amount of In concentration in the InAlN / GaN is tuned to match the GaN lattice, thereby generating electron mobility to produce ballistic electrons. At least two fin structures located in the channel are positioned at conductance variation distances from the ends of the channel. Each fin structure includes a gate formed transversely to the longitudinal axis of the channel. The gate is controlled using a voltage on the fin structure. The fin structure is configured to sense an energy field structure that is shifted by the amount of voltage to control the opening through which the ballistic electron flow through the gate passes, causing the ballistic electrons to undergo diffraction and then interference patterns caused by the wave characteristics of the ballistic electrons, which in turn alter the depletion width. This interference pattern generates a conductance variation pattern at conductance variation distances from the at least two fin structures. At least one metal is positioned at a distance of at least two fin structures from the end of the channel, such that the at least one metal is positioned vertically from the central axis to detect conductivity. The semiconductor device is turned on by applying a voltage and turned off by not applying a voltage.

[0036] Another embodiment of this disclosure provides a semiconductor device including a structure having a first arm, a second arm, and a third arm. Channels of the first and second arms extend into a channel of the third arm. When a current from a first voltage flows from a first electrode of the first arm to a second electrode of the second arm, a ballistic electron flow is generated from the channels of the first and second arms to the channel of the third arm, flowing through the third arm channel. The semiconductor device includes a fin structure located in the third arm channel and positioned at a conduction change distance from the end of the third arm. The fin structure includes a gate formed transversely to the longitudinal axis of the fin structure. The gate is controlled using a second voltage on the fin structure. The fin structure is configured to sense an energy field structure that is shifted by the amount of the second voltage to control the opening through which the ballistic electron flow through the gate will pass, causing the ballistic electrons to undergo diffraction and then interference, which in turn alters the depletion width. The semiconductor device is turned on by applying a certain amount of the first and second voltages and turned off by not applying a certain amount of the first and second voltages.

[0037] Another embodiment of this disclosure provides a semiconductor device including a structure having a first arm, a second arm, and a third arm. Channels of the first and second arms extend into a channel of the third arm. When a current from a first voltage flows from a first electrode of the first arm to a second electrode of the second arm, a ballistic electron flow is generated from the channels of the first and second arms to the channel of the third arm, flowing through the third arm channel. A plurality of fin structures located in the third arm channel are positioned at a conduction variation distance from the end of the third arm and are arranged in series. Each fin structure includes a gate formed transversely to the longitudinal axis of the fin structure. The gate is controlled using a second voltage on the fin structure. The fin structure is configured to sense an energy field structure that is shifted by the amount of the second voltage to control the opening through which the ballistic electron flow through the gate passes, thereby subjecting the ballistic electrons to diffraction and then interference, the opening altering the depletion width.

[0038] According to another embodiment of this disclosure, a semiconductor device is provided, comprising a structure having a first arm, a second arm, and a third arm. Channels of the first and second arms extend into a channel of the third arm. When a current from a first voltage flows from a first electrode of the first arm to a second electrode of the second arm, a ballistic electron flow is generated from the channels of the first and second arms to the channel of the third arm, flowing through the third arm channel. The semiconductor device includes a fin structure with a gate formed transversely to the longitudinal axis of the fin structure, wherein the gate is controlled using a second voltage on the fin structure. The fin structure is configured to sense an energy field structure that is shifted by the amount of the second voltage to control the opening through which the ballistic electron flow from the gate will pass, thereby subjecting the ballistic electrons to diffraction and then interference, the opening altering the depletion width. The fin structure is located in the third arm channel and positioned at a conductance variation distance from the end of the gate to the end of the third arm. The semiconductor device is turned on by applying a certain amount of the first and second voltages and turned off by not applying a certain amount of the first and second voltages. Attached Figure Description

[0039] The currently disclosed embodiments will be further explained with reference to the accompanying drawings. The drawings are not necessarily to scale; rather, the focus is generally on illustrating the principles of the currently disclosed embodiments.

[0040] Figure 1A This is a schematic diagram illustrating an experimental conventional quantum computer system built using various aspects of a conventional quantum computer architecture. This conventional quantum computer architecture is used to better understand the problems and technical constraints of current conventional quantum computing systems, which require two separate operating temperature zones.

[0041] Figure 1B This is a schematic diagram illustrating a quantum computing component that requires a single device to operate at a single temperature, according to some embodiments of the present disclosure.

[0042] Figure 2A This is a schematic cross-sectional view illustrating a top view of an embodiment of the present disclosure, according to some embodiments of the present disclosure.

[0043] Figure 2B These are examples illustrating some embodiments according to this disclosure. Figure 2A A schematic diagram of a cross-section of a longitudinal view from end 1 to end 2, showing the two fin structures.

[0044] Figure 2C These are examples illustrating some embodiments according to this disclosure. Figure 2A A schematic diagram of a cross-section of a longitudinal view from end 1 to end 2, showing a single fin structure.

[0045] Figure 2D These are examples illustrating some embodiments according to this disclosure. Figure 2A A schematic diagram of a cross-section in a longitudinal view from end 1 to end 2, which shows some of the material composition of the structure.

[0046] Figure 3A These are examples illustrating some embodiments according to this disclosure. Figure 2A A schematic diagram of a cross-section of a longitudinal view from end 1 to end 2, showing a single fin structure with the gate closed.

[0047] Figure 3B These are examples illustrating some embodiments according to this disclosure. Figure 2A A schematic diagram of a cross-section of a longitudinal view from end 1 to end 2, showing a single fin structure with the gate open.

[0048] Figure 4A This is an example of a graph illustrating, according to some embodiments of the invention, the application of a voltage to a gate to change the depletion width, which in turn changes the aperture through which electrons are passing.

[0049] Figure 4B This is a graph illustrating how the slit width (nm) or the aperture width of the gate varies with the gate voltage, according to some embodiments of this disclosure.

[0050] Figure 5A This is a graph illustrating analog electronic Fraunhofer diffraction for gate voltage according to some embodiments of the present disclosure, showing the conductivity level sensed by the semiconductor device, i.e., by applying a gate bias voltage, the detected conductivity can vary by several orders of magnitude, and by operating as an inverter, it corresponds to the semiconductor used as an inverter.

[0051] Figure 5B This is an example of a simulated electron Fraunhofer diffraction graph for gate voltage according to some embodiments of the present disclosure, which shows the conductivity level sensed by the semiconductor device, i.e., by applying a gate bias voltage, the detected conductivity can vary by several orders of magnitude, and by operating as an inverter, it corresponds to the semiconductor used as an inverter.

[0052] Figure 5C This is an example of a simulated electron Fraunhofer diffraction graph for gate voltage according to some embodiments of the present disclosure, which shows the conductivity level sensed by the semiconductor device, i.e., by applying a gate bias voltage, the detected conductivity can vary by several orders of magnitude, and by operating as an inverter, it corresponds to the semiconductor used as an inverter.

[0053] Figure 5DThis is an example of a simulated electron Fraunhofer diffraction graph for gate voltage according to some embodiments of the present disclosure, which shows the conductivity level sensed by the semiconductor device, i.e., by applying a gate bias voltage, the detected conductivity can vary by several orders of magnitude, and by operating as an inverter, it corresponds to the semiconductor used as an inverter.

[0054] Figure 6 This is a graph illustrating the conductance following the gate voltage variation according to some embodiments of the present disclosure, showing an on / off ratio > 10. 5 .

[0055] Figure 7A This illustrates the input waveform of an inverter designed according to some embodiments of the present disclosure. Figure 7A The curve graph.

[0056] Figure 7B This illustrates the output waveform of an inverter designed according to some embodiments of the present disclosure. Figure 7B The curve graph.

[0057] Figure 8 This is a block diagram illustrating some method operation steps for semiconductors according to some embodiments of the present disclosure.

[0058] While the above figures illustrate the currently disclosed embodiments, other embodiments are contemplated as mentioned in the discussion. This disclosure presents exemplary embodiments by way of example rather than limitation. Those skilled in the art can devise many other modifications and embodiments falling within the scope and spirit of the principles of the currently disclosed embodiments. Detailed Implementation

[0059] Figure 1A This is a schematic diagram illustrating an experimental conventional quantum computer system built using various aspects of a conventional quantum computer architecture. This conventional quantum computer architecture is used to better understand the problems and technical constraints of current conventional quantum computing systems, which require two separate operating temperature zones.

[0060] As mentioned above, conventional quantum computing components require conventional electronic devices to operate at a temperature (i.e., room temperature), while quantum computing components operate at temperatures below zero degrees Celsius. For example, current conventional quantum computing architectures do not address the constraints of conventional control electronics and software necessary to execute various quantum algorithms, requiring such conventional hardware and software to operate at room temperature. Specifically, conventional electronic devices used with conventional quantum computing are used for qubit control and readout (i.e., shaping electrical pulses, amplification, etc.). Here, conventional electronic components operate at room temperature, whereas, in contrast, the qubits of quantum computing operate near absolute zero. This creates a requirement for electronic devices that can operate at milliKelvin (mK) operating temperatures to avoid unacceptable cooling loads. Conventional electronic devices cannot function properly below 4K due to carrier freezing effects. Conventional electronic devices are inoperable at lower temperature limits due to temperature effects that lower the ionization energy of dopants in conventional electronic devices. However, this experimental quantum computer system 100 is constructed to aid in the development of some embodiments of this disclosure to better understand complex conventional quantum computing architectures and how to design and create individual devices that operate at a single operating temperature.

[0061] The experimental quantum computer system 100 is configured to include basic logic units (ELUs) 40 interconnected by a scalable photonic interconnect network 15, which links ELUs 14 over long distances via optical fibers in a flexible configuration.

[0062] The experimental quantum computer system 100 employs a conventional quantum computer architecture carrying qubits, wherein each ELU 14 includes a modular register of captured atomic-ion qubits, and wherein entangled quantum logic gates are mediated by local Coulomb interactions between qubits. The atomic qubits within each ELU 14 are coupled to a photonic quantum channel 38, and entanglement can occur between different ELU 14s via a reconfigurable optical cross-connection switch 41 and a position-sensitive imager 56. The cross-connection switch includes an input fiber 44 and an output fiber 50 with an output port 48, which is connected to the position-sensitive imager 22. A beam splitter (not shown) is located between the switch 41 and the position-sensitive imager 22. Detectors 55, 57 (i.e., the four rows of the position-sensitive imager 22 and four detectors per row) each include two fibers 58, 59 that interfere with the beam splitter (not shown), and the two detectors 55, 57 are connected to the corresponding output port 48 of the switch 41. Switch 41 provides an optical path between any input fiber 44 and any output fiber 48.

[0063] A conventional central processing unit (CPU) 24 receives input data 2 to be processed and computed, and controls the operation of the experimental quantum computer system 100 to perform predetermined operations according to a quantum algorithm 18. This quantum algorithm is used to implement a reconfigurable circuit scheme (i.e., using conventional electronic equipment) for quantum computation of the input data 2, with the aim of generating computation results depicted as output 6 (i.e., using conventional electronic equipment). A conventional fault tolerance (or fault tolerance) mechanism 16 is operatively coupled to the ELU 14, and to the switch 41 and CPU 12, as well as to the scheduling scheme (not shown) supported by the quantum algorithm 18. Additionally, a gate 40 may be located in the EMU, and another gate 42 may be located between the two EMUs. The basic unit of the quantum computer 100 is a collection of ELUs 14, which are qubit memories with local interactions.

[0064] Conventional laser unit 22 includes laser 24, mode-locked laser 26, and resonant laser 28, such that laser unit 22 is operatively coupled to conventional quantum control scheme 4 to generate desired laser pulses applied to qubits at different operational stages of the system. Each laser in laser unit 22 is driven to generate laser pulses with specific characteristics required at different stages of computer operation. The state of each qubit is measured in conventional measurement unit 20 by applying pulse 30 to resonant laser 28 in laser unit 22, which causes state-dependent fluorescence, which is imaged onto a multichannel photomultiplier tube for individual qubit state detection. When a constant state-dependent force is applied to the ionic qubits, multiple dissimilar modes remain entangled with these qubits overall after the interaction, thereby degrading quantum gate fidelity.

[0065] In the overall computational processing supported by the conventional quantum computer architecture of the experimental quantum computer system 100, system 100 needs to solve computational problems according to instructions issued by conventional CPU 12 consistent with algorithm 18. Note the conventional electronic equipment, namely, CPU 12, input 2, quantum control 4, output 6, time-division multiplexing 8, error tolerance 16, laser system 22, measurement system 20, and conventional charge-coupled device (CCD) imager 21. However, all the conventional electronic equipment of the experimental quantum computer system 100 requires an operating temperature of room temperature (i.e., the first temperature zone), while the quantum computing components operate at temperatures below zero degrees Celsius (i.e., the second temperature zone).

[0066] Figure 1BThis is a schematic diagram illustrating components of a quantum computing device that needs to operate at a single temperature, according to some embodiments of the present disclosure. The top layer 92, niobium nitride (NbN), can be used to fabricate quantum Q-bits. The bottom layer 94 is a combination of group III nitride semiconductor layers, which can be used to fabricate control circuitry as presented in this disclosure and to control the Q-bits. This can be a three-dimensional (3D) platform for fabricating small quantum computers. Furthermore, NbN exhibits superconducting behavior even at temperatures exceeding 10 K when growing group III nitride semiconductor layers. Therefore, the proposed platform allows quantum computers to operate at higher temperatures. This is important because maintaining a quantum computer near zero K is very expensive. Therefore, from this perspective, the proposed embodiments of the present disclosure significantly reduce costs and provide significant benefits for fabricating quantum computers.

[0067] Figure 2A This is a schematic cross-sectional view illustrating a top view of an embodiment of the present disclosure according to some embodiments thereof. The device includes a cross structure having four arms: 210 (first arm), 212 (second arm), 213 (fourth arm), and 214 (third arm). A voltage 1 is applied between the first arm 210 and the second arm 212 through electrodes E1 and E2, thereby generating an electron flow from the first arm 210 to the second arm 212. Only ballistic electrons with sufficiently high velocities can reach the third arm 214. The ballistic electrons (high-speed electrons) pass through the third arm 214 and through a fin (not shown, see [reference]) controlled by electrode E3. Figure 2B ) to reach the sensor (conductivity sensor, such as metal) 230 or 232. When ballistic electrons pass through the fin (see Figure 2B (This depends on whether the gate is on or off (see...)) Figure 2B The applied voltage E3 (see) Figure 2B The amount of ballistic electrons generates pattern 240. The size and distribution of pattern 240 depend on the distance d2 between the end of gate 220 and the end 222 of third arm 214, such that the distribution also depends on d2.

[0068] The fourth arm 213 is not required for the operation of the OR gate device; however, it can be useful in determining whether ballistic electrons can be detected. Ballistic electrons are detected by measuring the voltage applied between the fourth electrode E4 of the fourth arm 213 and the third electrode E3 of the third arm 214. In the case of ballistic electrons, the voltage measured between the third electrode E3 of the third arm 214 and the fourth electrode E4 of the fourth arm 213 will be negative or zero.

[0069] Figure 2B These are examples illustrating some embodiments according to this disclosure. Figure 2AA schematic diagram of a cross-section of a longitudinal view from end 1 to end 2, showing two fin structures positioned in series. Figure 2B Fins 254a and 254b, and the distance d1 between fins 254a and 254b, are shown. Fins 254a and 254b are encapsulated by oxide 252. This oxide 252 can be a material composed of Al2O3 / HfO2 / SiO2 or any other high-k gate dielectric. Fins 254a and 254b are also shown with depletion widths or regions H1, H2, H3, and H4. The depletion regions are caused by the work function difference between the semiconductors in fin regions H1, H2, H3, and H4 and the metal 250 of E3. Regarding the third arm 214, the third arm 214 includes a passivation layer or insulator 215 such as air or any oxide, the width of which 216 is also the width of the third arm 214.

[0070] Figure 2C These are examples illustrating some embodiments according to this disclosure. Figure 2A A schematic cross-sectional view of the longitudinal view from end 1 to end 2, showing a single fin structure. Fin F has a width B. The total width D of the fin includes oxide 252 surrounding fin F and gate A, and metal 250 of the third electrode. Semiconductor layer I of the third arm 214 includes a material such as III-N. Depletion widths H1 and H2 are caused by the work function difference between the metal 250 of the third electrode and semiconductor layer I. The total depletion width has a height C.

[0071] Figure 2D These are examples illustrating some embodiments according to this disclosure. Figure 2A A schematic cross-sectional view of the structure from end 1 to end 2, showing some of the material composition of the structure. Fin F may comprise two III-N layers: III-N1 and III-N2, in the third arm 214. To generate free electrons at the interface 260 between the III-nitrides III-N1 and III-N2, the band gap 262 of III-N1 is larger than the band gap 264 of III-N2. The reason why the band gap 262 of III-N1 needs to be larger than that of III-N2 is to ensure that the polarization difference between the two semiconductors III-N1 and III-N2 is positive, and to compensate for the positive fixed charge that accumulates negative mobile electrons at the interface between III-N1 262 and III-N2 264. These accumulated negative mobile electrons are also known as 2-DEG (two-dimensional electron gas).

[0072] Figure 3A These are examples illustrating some embodiments according to this disclosure. Figure 2AA schematic cross-sectional view of the fin from end 1 to end 2, showing a single fin structure with the gate closed. The gate metal 350 can be a low work function, for example, 4 eV. The oxide 352 can be approximately 5 nm to 10 nm thick and can be selected such that, at zero gate bias (gate closed), the depletion widths N1 and N2 cover the entire fin width (see [reference]). Figure 2C The B), thus causing the gate for electrons to close. One aspect of the depletion width of the gate closure is to prevent electrons from passing through the fin F.

[0073] Figure 3B These are examples illustrating some embodiments according to this disclosure. Figure 2A A schematic cross-section of the longitudinal view from end 1 to end 2 shows a single fin structure with the gate open. When a 5V gate voltage is applied at the metal 350 of the electrode, the depletion widths N1 and N2 decrease, causing the gate to open and allowing electrons to pass through.

[0074] Figure 4A This is an example of a graph illustrating, according to some embodiments of the invention, the application of a voltage to a gate to change the depletion width, which in turn changes the aperture through which electrons are passing. Figure 4A An example is shown where an increase in gate voltage produces an electrostatic effect that reduces the depletion width.

[0075] Figure 4B This is a graph illustrating how the slit width (nm) or the aperture width of the gate varies with the gate voltage, according to some embodiments of this disclosure. Figure 4B An increase in gate voltage is illustrated, which produces an electrostatic effect that reduces the depletion width. As the depletion width increases, it causes the aperture for electrons to pass through to open.

[0076] Figure 5A , Figure 5B , Figure 5C as well as Figure 5D The diagram illustrates simulated electron Fraunhofer diffraction curves for different gate voltages according to some embodiments of the present disclosure. It shows that the conductivity level is sensed by a semiconductor device, i.e., the detected conductivity can vary by several orders of magnitude by applying a gate bias voltage, which in turn corresponds to the semiconductor used as an inverter when operated as an inverter.

[0077] Figure 6 This is a graph illustrating the conductance following the gate voltage variation according to some embodiments of the present disclosure, showing an on / off ratio > 10. 5 Conductivity is determined by Figure 2A Sensors 230 and / or 232 detect, allowing the sensor to be located in Figure 2AThe specific location along the dashed line 222. The conductance can be changed by applying a bias voltage at the gate, and the difference between the changes can be several orders of magnitude.

[0078] Figure 7A and Figure 7B This illustrates the input waveform of an inverter designed according to some embodiments of the present disclosure. Figure 7A ) and the output waveform of the designed inverter ( Figure 7B The curve graph. Figure 7A Showing the direction Figure 7A The input voltage pulse is applied to the E3 electrode. Depending on the amount of bias applied, this causes the aperture of the fin to open and close (or shut down) to allow free electrons to pass through. (See sensor [reference]). Figure 2A In the fins (230, 232), whether free electrons are detected at the output can provide 5V or 0V. When the bias voltage applied at E3 is 0V, the aperture width on the fin is 0nm, so that no electrons pass through, and the sensor converts this state of no electrons / low conductivity to a 5V state, and vice versa.

[0079] Figure 8 This is a block diagram illustrating some method operation steps for semiconductors according to some embodiments of the present disclosure.

[0080] Step 805 illustrates the fabrication of the device starting with the growth of an epitaxial structure. The process begins with a Si / sapphire / SiC / GaN wafer. The wafer size can be 2 / 4 / 6 / 12 inches.

[0081] Step 810 shows that if the wafer is not a GaN wafer, a buffer layer is grown to address the lattice mismatch between the wafer material and the III-N semiconductor.

[0082] Step 815 then illustrates the GaN semiconductor grown on the buffer layer. The thickness of this layer can range from 450 nm to several micrometers. Ideally, a thicker GaN layer is desirable because it helps reduce the defect density in the III-N layer, which in turn contributes to optimal device performance.

[0083] Then, step 820 shows the III-N layer grown on top of the GaN layer. However, the band gap of the III-N layer needs to be higher than that of the GaN layer. Typically, the thickness of this layer can be from 5 nm to 30 nm. The buffer layer, GaN layer, and III-N layer can be grown by any growth method including but not limited to MBE / MOCVD / RPCVD / PLD / sputtering.

[0084] Step 825 illustrates that after material growth, device fabrication begins with the formation of the arm. The arm is formed via a dry anisotropic etching mechanism. During the etching process, a photoresist / electron beam resist soft mask or a metal hard mask can be used.

[0085] Step 830 illustrates the etching process typically performed using an ICP-RIE method employing Cl2 / BCl3 / Ar gases. A Ni hard mask is formed via electron beam lithography, followed by metal deposition and lift-off processes. Dry anisotropic etching is then performed to create fins in the third arm.

[0086] Step 835 illustrates the formation of Ti / Al / Ni / Au-based ohmic contacts in arms 1 and 2 through photolithography and lift-off processes followed by annealing at high temperature. These ohmic contacts serve as E1 and E2 electrodes.

[0087] Step 840 illustrates the subsequent deposition of the oxide layer using an atomic layer mapping method. The oxide layer includes, but is not limited to, Al2O3, HfO2, and doped HfO2.

[0088] Step 845 illustrates the subsequent formation of the E3 electrode via electron beam lithography, metal deposition, and a lift-off process. In this step, a low work function metal is deposited to promote depletion in the fin region without requiring any bias voltage to be applied at the E3 electrode.

[0089] Step 850 shows the placement of a sensor for detecting electrons at the edge of the third arm.

[0090] feature

[0091] A semiconductor device includes a structure having a first arm, a second arm, and a third arm. Channels of the first and second arms extend to a channel of the third arm. When a current from a first voltage flows from a first electrode of the first arm to a second electrode of the second arm, a ballistic electron flow is generated from the channels of the first and second arms to the channel of the third arm, flowing through the third arm channel. The semiconductor device may include a fin structure located in the third arm channel at a conduction change distance from the end of the third arm. The fin structure includes a gate formed transversely to the longitudinal axis of the fin structure. The gate is controlled using a second voltage on the fin structure. The fin structure is configured to sense an energy field structure that shifts by the amount of the second voltage to control the opening through which the ballistic electron flow through the gate will pass, causing the ballistic electrons to undergo diffraction and then interference, thus altering the depletion width of the opening. The semiconductor device is turned on by applying a certain amount of the first and second voltages and turned off by not applying a certain amount of the first and second voltages. The following aspects are intended to create one or more implementations, either individually or in combination, based on one or more combinations of the aspects listed below.

[0092] According to various aspects of this disclosure, another fin structure located in the third arm channel is positioned in series with the fin structure at the same distance from the end of the third arm. The other fin structure includes a gate formed transversely to the longitudinal axis of the other fin structure. The gate is controlled using a second voltage on the other fin structure. This causes the other fin structure to be configured to sense an energy field structure that shifts according to the amount of the second voltage, controlling the opening through which the ballistic electron flow through the gate of the other fin structure passes, thereby interfering with the ballistic electrons and altering the depletion width of the opening.

[0093] According to various aspects of this disclosure, a voltage is applied between the first and second arms, such that the first and second arms are configured in a cross-shaped structure to generate a ballistic electron flow. One aspect may include ballistic electrons in the form of, for example, approximately 2 × 10⁻⁶. 7 cm·sec -1 High-speed flow.

[0094] According to various aspects of this disclosure, when a ballistic electron passes through a gate opening, it undergoes interference. This interference generates an interference pattern due to the wave characteristics of the electrons, such that when the fin structure is positioned within a conductance variation distance, the interference pattern produces a conductance variation pattern. One aspect involves at least one sensor being positioned at a distance from the at least one metal to operably detect the conductance, provided that at least one metal is located at the end of the third arm and the vertical position of the at least one metal relative to the central axis of the third arm channel is vertically aligned with the metal. Another aspect involves the detected conductance being correlated with an order of magnitude, such that this order of magnitude changes according to a corresponding second voltage shift based on the energy field structure, which is applied to the fin structure controlling the size of the gate opening. Yet another aspect may include the detected conductance level causing the semiconductor device to operate as an inverter.

[0095] According to various aspects of this disclosure, the ballistic electron flow is generated by an InAlN / GaN epitaxial layer, such that a predetermined indium concentration is tuned to match the GaN lattice, thereby providing electron mobility. Alternatively, a first voltage and a second voltage may be connected to the same ground terminal.

[0096] According to various aspects of this disclosure, the fin structure is a U-shaped structure having a transverse portion and two upright portions integrally formed with the transverse portion and extending from the transverse portion to form a fin structure with a U-shaped cross-section. An additional transverse portion is integrally formed with the two upright portions and extends from the free ends of the two upright portions away from the opening formed between the two upright portions. An oxide material layer wraps along the inner surface of the fin structure and extends along the additional transverse portion.

[0097] definition

[0098] Based on various aspects of this disclosure and on experimental basis, the following definitions have been established, and are certainly not complete definitions of each phrase or term. The definitions provided are given only as examples, based on learning from experiments, and other interpretations, definitions, and other aspects may be involved. However, such definitions have been provided for at least a basic preview of the presented phrases or terms.

[0099] Ballistic electrons or ballistic conduction In mesoscopic physics, ballistic conduction (ballistic transport) is the transport of charge carriers (usually electrons) through a medium with negligible resistivity due to scattering. Without scattering, electrons simply obey Newton's second law of motion at non-relativistic velocities. Typically, the resistivity of a material exists because electrons are scattered as they move within the medium by impurities, defects, thermal fluctuations of ions in crystalline solids, or generally by any freely moving atoms / molecules that make up a gas or liquid. For a given particle, the mean free path can be described as the average length an electron can travel freely, i.e., the average length it travels freely before a collision, which can alter the electron's momentum. The mean free path can be increased by reducing the number of impurities in the crystal or by lowering the crystal's temperature. Ballistic transport is observed when the mean free path of an electron is longer than the dimension of the medium it traverses. The electron only changes its motion upon colliding with a wall. In the case of a wire suspended in air / vacuum, the surface of the wire acts as a box that reflects electrons and prevents them from leaving into the empty space / open air. This is because extracting electrons from the medium (work function) requires energy.

[0100] For example, ballistic transport can be observed in metallic nanowires: this is simply because the size of the wires is nanometers (10). -9Ballistic conduction is the unimpeded flow of charged or energy-carrying particles over relatively long distances within a material. Normally, electron (or hole) transport is dominated by scattering events that moderate carrier momentum in an effort to bring the conducting material to equilibrium. Therefore, ballistic conduction in a material is determined by how ballistically conductive that material behaves. Ballistic conduction differs from superconductivity because the Meissner effect is absent in the material. A ballistic conductor will stop conducting if the driving force is turned off, while current will continue to flow in a superconductor after the driving power source is disconnected. Due to the extreme size quantization effects in these materials, ballistic conduction is typically observed in quasi-one-dimensional structures such as carbon nanotubes or silicon nanowires. Ballistic conduction is not limited to electrons (or holes) and can also be applied to phonons. Theoretically, ballistic conduction can be extended to other quasiparticles, but this has not yet been experimentally verified.

[0101] Ballistic transport can utilize the quantum mechanical properties of electron wave functions. Ballistic transport is coherent in wave mechanics. Phenomena such as double-slit interference, spatial resonance (and other optical or microwave-like effects) can be exploited in nanoscale electronic systems, including systems containing nanowires and nanotubes. When the current flowing through a rough interface is confined to a finite number of contact points, the widely encountered electrical contact resistance, or ECR, occurs. The size and distribution of these contact points are governed by the topology of the contact surfaces forming the electrical contact. In particular, for surfaces with high fractal dimensions, the contact points can be very small. In such cases, when the radius of the contact point is smaller than the mean free path Λ(λ) of the electron, the resistance is governed by a Sharvin mechanism, in which electrons propagate ballistically through these micro-contacts, and the resistance can be described by the following equation: This term (where ρ1 and ρ2 correspond to the resistivity of the two contact surfaces) is called Chauvin resistance. Electrical contacts that lead to ballistic electron conduction are called Chauvin contacts. Contact resistance can be conventionally addressed when the radius of the contact point is greater than the mean free path of the electrons.

[0102] Exhausted widthIn semiconductor physics, a depletion region (also known as a depletion layer, depletion region, junction region, space charge region, or space charge layer) is an insulating region within a conductive, doped semiconductor material where mobile charge carriers have either diffused away or been forced away by an electric field. The only elements left in the depletion region are ionized donor or acceptor impurities. The depletion region is so named because it is formed from a conductive region by removing all free charge carriers, leaving no current-carrying carriers. Understanding the depletion region is crucial for explaining modern semiconductor electronics: diodes, bipolar junction transistors, field-effect transistors, and variable capacitor diodes all rely on the depletion region phenomenon. The depletion region forms instantaneously across a pn junction. It is most easily described when the junction is in thermal equilibrium or in a steady state: in both cases, the characteristics of the system do not change over time; these are called dynamic equilibria. Electrons and holes diffuse into regions with lower concentrations, much like ink diffuses into water until it is uniformly distributed. By definition, N-type semiconductors have an excess of free electrons (in the conduction band) compared to P-type semiconductors, while P-type semiconductors have an excess of holes (in the valence band). Therefore, when N-doped and P-doped semiconductors are placed together to form a junction, free electrons in the N-side conduction band migrate (diffuse) to the P-side conduction band, and holes in the P-side valence band migrate to the N-side valence band. After the transfer, the diffused electrons contact the holes and are eliminated through recombination on the P-side. Similarly, the diffused holes recombine with the free electrons, thus being eliminated on the N-side. The end result is the disappearance of both diffused electrons and holes. In the N-side region near the junction interface, free electrons in the conduction band disappear due to (1) electrons diffusing to the P-side and (2) electrons recombinating with holes diffusing from the P-side. Holes in the P-side region near the interface also disappear for similar reasons. As a result, the majority of charge carriers (free electrons in the N-type semiconductor and holes in the P-type semiconductor) are depleted in the region around the junction interface, hence this region is called the depletion region or depletion zone. Due to the diffusion of most charge carriers mentioned above, the depletion region is charged; its N-side is positively charged and its P-side is negatively charged. This generates an electric field that provides a force opposite to the charge diffusion. The depletion region reaches equilibrium when the electric field is strong enough to stop the further diffusion of holes and electrons. Integrating the electric field of the depletion region determines the so-called built-in voltage (also known as the junction voltage, barrier voltage, or contact potential). Physically, charge transfer in a semiconductor device arises from (1) charge carrier drift caused by the electric field and (2) charge carrier diffusion caused by spatial variation in carrier concentration. On the P-side of the depletion region, where holes drift through an electric field with conductivity σ and diffuse with a diffusion constant D, the net current density is given by equation Given, where E is the electric field and e is the elementary charge (1.6 × 10⁻⁶). -19The electric field (Coulomb) is the density of holes (the number of holes per unit volume). The electric field causes holes to drift along the field direction, and for diffused holes, this drift occurs in the direction of decreasing concentration; therefore, for holes, a negative current results in a positive density gradient. (If the charge carriers are electrons, the hole density p is replaced with the electron density n with a negative sign; in some cases, both electrons and holes must be included.) When the two current components are in equilibrium, such as in the depletion region of a dynamically balanced pn junction, the current is zero due to the Einstein relation (which relates D to σ).

[0103] Regarding the depletion width under forward bias, forward bias (applying a positive voltage to the P side relative to the N side) narrows the depletion region and lowers the barrier to carrier injection. More specifically, majority carriers gain some energy from the bias field, enabling them to enter the region and neutralize opposite charges. The higher the bias, the more neutralization (or sifting of ions in the region) occurs. Carriers can recombine into ions, but thermal energy immediately converts the recombinated carriers back as the Fermi energy approaches. When the bias is strong enough to make the depletion region very thin, the diffusion component of the current (through the junction interface) increases significantly, and the drift component decreases. In this case, the net current flows from the P side to the N side. The high carrier density (which varies exponentially with the applied bias) makes the junction conductive and allows for large forward currents. The mathematical description of the current is provided by the Shockley diode equation. The low current conducted under reverse bias and the large current conducted under forward bias are examples of rectification. With reverse bias (applying a negative voltage to the P side relative to the N side), the potential drop (i.e., voltage) across the depletion region increases. Essentially, majority carriers are pushed away from the junction, leaving more charged ions. Therefore, the depletion region is widened and its field becomes stronger, which increases the drift component of the current (through the junction interface) and reduces the diffusion component. In this case, the net current flows from the N side to the P side. The carrier density (primarily minority carriers) is low, and only a very small reverse saturation current flows.

[0104] diffractionDiffraction refers to the various phenomena that occur when a wave encounters an obstacle or slit. It is defined as the bending of a wave at the corner of an obstacle or through an aperture into the geometrically shaded region of the obstacle / aperture. The diffracting object or aperture effectively becomes a secondary source of the propagating wave. The phase contribution from the wavefront is projected at an infinite number of points along length d, producing a continuously varying intensity θ on the registration plate. The diffraction phenomenon is described by the Huygens-Fresnel principle, which considers each point in the propagating wavefront as a set of individual spherical wavelets. The characteristic banding pattern is most pronounced when a wave from a coherent source (such as a laser) encounters a slit / aperture of a size comparable to its wavelength, as shown in the inset image. This is due to the addition or interference of different points on the wavefront (or equivalently, individual wavelets) traveling through paths of varying lengths to the registration surface. However, if there are multiple closely spaced openings, complex patterns of varying intensities can be produced. These effects also occur when light waves pass through a medium with varying refractive indices, or when sound waves pass through a medium with varying acoustic impedances; all waves undergo diffraction, including gravitational waves, water waves, and other electromagnetic waves (such as X-rays and radio waves). Furthermore, quantum mechanics has demonstrated that matter possesses wave-like properties and therefore undergoes diffraction (measurable at the subatomic to molecular level). Diffraction and interference are closely related, and even if not precisely, their meanings are almost identical.

[0105] put one's oar in Particles are sent one at a time through a controllable gate or double-slit device, causing a single particle to appear on the screen. An interference pattern appears when these particles are allowed to accumulate one after another. This demonstrates wave-particle duality, which shows that all matter exhibits both wave and particle properties: a particle at a single location is measured as a single pulse, while a wave describes the probability of absorbing a particle at a specific location on the screen. This phenomenon has been shown to occur with photons and electrons. Therefore, experiments using electrons add compelling evidence to the idea that electrons, protons, neutrons, and even larger entities commonly referred to as particles still possess their own wave properties, even wavelengths (related to their momentum). The detection probability is the square of the wave amplitude and can be calculated using conventional wave theory. Particles do not arrive at the screen in a predictable order, so knowing where and in what order all previous particles appeared on the screen does not indicate where future particles will be detected. If wave cancellation exists at a point, it does not mean the particle has disappeared; it will appear elsewhere. Since the origins of quantum mechanics, some theorists have been studying ways to incorporate additional determinants or “hidden variables” that, if known, would explain the position of each individual’s influence on the target.

[0106] Interference patternThe overall pattern produced when two or more waves interfere with each other typically shows regions of constructive and destructive interference.

[0107] wave properties of electrons Waves involve the transfer of energy but not matter. In short, a wave can be described as a disturbance that travels through a medium, transferring energy from one location (its source) to another without transferring matter. Waves exhibit interesting properties, such as interference and diffraction, and are characterized by their wavelength. In the case of electrons, the wavelength depends on their velocity and is given by the equation λ = h / (mv).

[0108] Free particles For example, consider a free particle. In quantum mechanics, free matter is described by a wave function. The particle properties of matter become apparent when we measure its position and velocity. The wave properties of matter become apparent when we measure its wave properties (e.g., interference). This wave-particle duality characteristic is incorporated into the coordinate and operator relations in the formulas of quantum mechanics. Since the matter is free (unaffected by any interactions), its quantum state can be represented as a wave of arbitrary shape, extending in space as a wave function. The particle's position and momentum are observable. The uncertainty principle states that position and momentum cannot be measured simultaneously with perfect precision. However, it is possible to measure the position of a moving free particle (single) to produce an eigenstate of a position x with a very large wave function (Dirac δ) at a specific position x and zero at other positions. If a position measurement is performed on such a wave function, the result x will be obtained with 100% probability (i.e., with complete determinism or complete precision). This is called the eigenstate of position, or, in mathematical terms, the generalized position eigenstate (eigenvalue distribution). If a particle is in an eigenstate of position, its momentum is completely unknown. On the other hand, if a particle is in an eigenstate of momentum, its position is completely unknown. In an eigenstate of momentum in the form of a plane wave, the wavelength can be shown to be equal to h / p, where h is Planck's constant and p is the momentum of the eigenstate.

[0109] Quantum BitA qubit, or quantum bit, is the fundamental container for information in quantum computing, replacing the bit in a conventional computer. A qubit can exist in both a ground state and an excited state simultaneously. The two logical states of each qubit must be mapped to the eigenstates of some suitable physical system. The most direct example is spin. Spin qubits, relying on the spin degree of freedom of electrons or nuclei, can store quantum information for extended periods. Note that many other examples of qubits exist: the two different polarizations of a photon, the two energy states of an electron orbiting a single atom, etc. Quantum computers are fundamentally different from traditional computers due to two distinct properties of qubits. The first property is configurable "quantum superposition," or linear combination. The second property is "quantum entanglement."

[0110] Conductivity variation mode Electrical conductivity depends on the number of electrons available at a specific point in a semiconductor. Higher electron concentration means higher conductivity, and vice versa.

[0111] The detected conductivity is related to orders of magnitude. The absence of electrons in a semiconductor can lead to a significant reduction in conductivity.

[0112] The detected conductivity level causes the semiconductor device to operate as an inverter. When the gate voltage is 0V (input logic state 0), electrons are allowed to pass through the fins, and a high conductance state is detected at the output terminal, which corresponds to output logic state 1. Similarly, when the input voltage is 5V (input logic state 1), the fin channel is depleted. No electrons are detected at the output terminal, which corresponds to low conductance. Therefore, when the input state is 1, the output logic state is 0. This completes the operation of the inverter.

[0113] Heterogeneous junction A heterojunction is an interface that appears between two layers or regions of dissimilar crystalline semiconductors. Unlike homojunctions, these semiconductor materials have unequal band gaps. This is often advantageous in designing electronic band gaps for many solid-state device applications, including semiconductor lasers, solar cells, and transistors, among others. Multiple heterojunctions combined together in a device are called a heterostructure, although the two terms are often used interchangeably. The requirement that each material be a semiconductor with unequal band gaps is somewhat relaxed (especially at small length scales), where electronic properties depend on spatial properties. A more modern definition of a heterojunction is an interface between any two solid-state materials, including crystalline and amorphous structures of metals, insulators, fast ion conductors, and semiconductors.

[0114] Effective mass mismatch (heterojunction) When a heterojunction is formed from two different semiconductors, quantum wells can be fabricated due to their different band structures. To calculate the static energy levels within the obtained quantum well, understanding the change or mismatch in effective mass across the heterojunction becomes important. A quantum well defined in a heterojunction can be considered as having a width of l. wThe finite well potential. The boundary conditions for the envelope function in the quantum well are called the Ben-Daniel-Duke boundary conditions, which require the envelope function in the fabricated quantum well to satisfy... The boundary conditions in the interface area are continuous.

[0115] Manufacturing (heterojunctions) Heterojunction fabrication typically requires molecular beam epitaxy (MBE) or chemical vapor deposition (CVD) techniques to precisely control the deposition thickness and create a clear lattice-matched abrupt interface. Generally, two steps are involved in heterojunction fabrication:

[0116] • Preparation of two-dimensional layered materials. The synthesis of 2D monolayers mainly includes top-down and bottom-up strategies.

[0117] • Top-down: Micromechanical exfoliation. While seemingly simple, this technique produces high-quality 2D crystalline flakes (flaks) and has been applied to many commonly used 2D materials, such as graphene, MoS2, and WSe2.

[0118] Bottom-up approach: Chemical vapor deposition (CVD). This method is primarily used to prepare larger films with more stable quality. One of the most popular applications is its use for growing MoS2, using S and MoO3 as precursors.

[0119] • Heterogeneous structural components. Van der Waals heterojunctions (vdWH) can be fabricated by riveting together monolayers. Both top-down and bottom-up methods can be applied.

[0120] • Top-down: Peel-off and re-deposition method. The first layer should be attached to the substrate. The second layer can be transferred to a transparent mold with a sacrificial polymer using wet or dry transfer techniques. Sheet stacking should be performed precisely under a micromanipulator, and then the polymer mold should be removed. This is the most widely used method.

[0121] • Bottom-up: Direct CVD growth of heterostructured layers on top of each other. Growth conditions need to be precisely controlled. For example, graphene, h-BN, and TMD vdWH can be prepared in this way.

[0122] Band alignment (heterojunction) The behavior of a semiconductor junction depends critically on the band alignment at the interface. Semiconductor interfaces can be organized into three types of heterojunctions: cross-gap (Type I), staggered-gap (Type II), or open-gap (Type III), as seen in the figure. Far from the junction, band bending can be calculated based on the conventional process of solving the Poisson equation. Various models exist to predict band alignment.

[0123] The simplest (and least accurate) model is Anderson's rule, which predicts band alignment based on the properties of the vacuum-semiconductor interface (especially vacuum electron affinity). Its main limitation is that it neglects chemical bonding.

[0124] A common anion rule was proposed, which hypothesized that materials with the same anion should have a very small valence band shift since the valence band is related to the anion state. However, this did not explain the data, but rather the tendency for two materials with different anions to have a valence band shift larger than the conduction band shift.

[0125] Tersoff proposed a bandgap state model based on the more familiar metal-semiconductor junction, where the conduction band shift is given by the difference in Schottky barrier height. This model includes a dipole layer at the interface between the two semiconductors, generated by an electron tunneling effect (similar to metal-induced bandgap states) from the conduction band of one material to the bandgap of the other. This model fits well into systems where the two materials (such as GaAs / AlGaAs) are tightly lattically matched.

[0126] The 60:40 rule applies to semiconductor GaAs and alloy semiconductor Al. x Ga 1-x The specific case of the knot between As is heuristic. With Al x Ga 1-x As x changes from 0 to 1, the ratio ΔE C / ΔE V It tends to maintain a value of 60 / 40. For comparison, the Adelson rule predicts ΔE for the GaAs / AlAs junction (x=1). C / ΔE V =0.73 / 0.27.

[0127] A typical method for measuring band shift is to calculate it by measuring the exciton energy in the emission spectrum.

[0128] Implementation

[0129] The following description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the following description of exemplary embodiments will provide those skilled in the art with a description that can be used to implement one or more exemplary embodiments. Various changes to the function and arrangement of the elements are contemplated without departing from the spirit and scope of the disclosed subject matter set forth in the appended claims.

[0130] Specific details are set forth in the following description to provide a thorough understanding of the embodiments. However, those skilled in the art will understand that these embodiments can be practiced without these specific details. For example, systems, processes, and other elements of the disclosed subject matter may be shown as components in block diagram form to avoid obscuring these embodiments with unnecessary detail. In other instances, well-known processes, structures, and techniques may be shown without unnecessary detail to avoid obscuring these embodiments. Furthermore, the same reference numerals and designations in the various figures denote the same elements.

[0131] Furthermore, each implementation can be described as a process, depicted as a flowchart, flow diagram, data flow diagram, structure diagram, or block diagram. Although a flowchart can describe operations as sequential processes, many operations can be executed in parallel or simultaneously. Additionally, the order of operations can be rearranged. A process may terminate upon completion of its operations, but may have additional steps not discussed or included in the diagram. Moreover, not all operations in any particularly described process may occur in all implementations. A process can correspond to a method, function, procedure, subroutine, subroutine, etc. When a process corresponds to a function, the termination of that function may correspond to the function returning to the calling function or the main function.

[0132] Furthermore, implementations of the disclosed subject matter can be carried out at least partially, manually, or automatically. They can be executed, or at least assisted by, machines, hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof, for manual or automatic implementation. When implemented in software, firmware, middleware, or microcode, program code or code segments for performing the necessary tasks can be stored in a machine-readable medium. The processor can then perform the necessary tasks.

[0133] Furthermore, the embodiments of this disclosure and the functional operations described in this specification can be implemented in digital electronic circuits, in tangibly embodied computer software or firmware, in computer hardware including the structures disclosed in this specification and their equivalents, or in one or more of these combinations. Additionally, some embodiments of this disclosure can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory program carrier for execution by a data processing device or for controlling the operation of a data processing device. Further, program instructions can be encoded on artificially generated propagation signals (e.g., machine-generated electrical signals, optical signals, or electromagnetic signals), which are generated to encode information for transmission to a suitable receiver device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or one or more combinations thereof.

[0134] According to embodiments of this disclosure, the term "data processing apparatus" can encompass all kinds of devices, apparatuses, and machines for processing data, including, for example, programmable processors, computers, or multiple processors or computers. The apparatus may include special-purpose logic circuitry, such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits). In addition to hardware, the apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, protocol stacks, database management systems, operating systems, or combinations thereof.

[0135] Computer programs (which may also be referred to or described as programs, software, software applications, modules, software modules, scripts, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and can be deployed in any form, including as standalone programs or as modules, components, subroutines, or other units suitable for use in a computing environment. A computer program may, but does not necessarily, correspond to a file in a file system. A program may be stored as a portion of a file containing other programs or data, for example, as one or more scripts stored in a markup language document, a single file dedicated to the program in question, or multiple collaborating files, such as files storing one or more modules, subroutines, or portions of code. Computer programs can be deployed to execute on a single computer or on multiple computers located at a site or distributed across multiple sites and interconnected by a communication network. For example, computers suitable for executing computer programs include central processing units (CPUs) that may be based on general-purpose or special-purpose microprocessors or both, or any other type. Typically, the CPU receives instructions and data from read-only memory or random access memory or both. The basic components of a computer are a central processing unit (CPU) for executing or carrying out instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices (e.g., disks, magneto-optical disks, or optical disks) for storing data, or operatively coupled to receive data from or transfer data to such mass storage devices, or both. However, a computer does not necessarily need to have such devices. Furthermore, a computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device (e.g., a Universal Serial Bus (USB) flash drive), and so on.

[0136] To provide interaction with the user, embodiments of the subject matter described herein can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user, and a keyboard and pointing device (e.g., a mouse or trackball) that the user can use to provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including sound, speech, or tactile input. Additionally, the computer can interact with the user by sending documents to and receiving documents from the device used by the user; for example, by sending a webpage to a web browser on the user's client device in response to a request received from a web browser.

[0137] Implementations of the themes described herein can be carried out in computing systems that include back-end components (e.g., a data server), middleware components (e.g., an application server), front-end components (e.g., a client computer with a graphical user interface or a web browser that a user can use to interact with an implementation of the themes described herein), or any combination of one or more such back-end, middleware, or front-end components. The components of the system can be interconnected via any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include local area networks (“LANs”) and wide area networks (“WANs”), such as the Internet.

[0138] This computing system may include clients and servers. Clients and servers are typically located far apart and interact via a communication network. The client-server relationship arises from computer programs running on the respective computers that have a client-server relationship with each other.

[0139] Although this disclosure has been described with reference to specific preferred embodiments, it is to be understood that various other changes and modifications may be made within the spirit and scope of this disclosure. Therefore, the appended claims cover all such changes and modifications that fall within the true spirit and scope of this disclosure.

Claims

1. A semiconductor device comprising a structure having a first arm, a second arm, and a third arm, such that a channel of the first arm and the second arm extends to a channel of the third arm, and when a current of a first voltage flows from a first electrode of the first arm to a second electrode of the second arm, a ballistic electron flow is generated from the channel of the first arm and the second arm to the channel of the third arm, the semiconductor device comprising: A fin structure, located in the channel of the third arm, is positioned at a distance from the end conductance change of the third arm. The fin structure includes a gate formed transversely to the longitudinal axis of the fin structure and is controlled by a second voltage on the fin structure. This causes the fin structure to be configured to sense an energy field structure that shifts by the amount of the second voltage to control the opening through which the ballistic electron stream passes through the gate, thereby interfering with the ballistic electrons. The opening then alters the depletion width. The sensor located at the edge of the third arm detects the conductivity by applying the second voltage.

2. The semiconductor device according to claim 1, further comprising: Another fin structure, located in the third arm channel, is positioned in series with the first fin at the same distance from the end of the third arm. The other fin structure includes a gate formed transversely to the longitudinal axis of the other fin structure and is controlled by a second voltage on the other fin structure, such that the other fin structure is configured to sense an energy field structure that shifts by the amount of the second voltage to control the opening through which the ballistic electron flow through the gate of the other fin structure passes, thereby interfering with the ballistic electrons and altering the depletion width of the opening.

3. The semiconductor device according to claim 1, wherein, The voltage is applied between the first arm and the second arm to generate the ballistic electron flow.

4. The semiconductor device according to claim 3, wherein, The ballistic electron is 2×10 7 cm·sec -1 High-speed flow.

5. The semiconductor device according to claim 1, wherein, As the ballistic electrons pass through the gate opening, they are subjected to interference, which generates an interference pattern due to the wave characteristics of the electrons, resulting in a conductivity variation pattern in the interference pattern.

6. The semiconductor device according to claim 5, wherein, At least one metal is positioned at the end of the third arm in a vertical position relative to the central axis of the third arm channel, such that the at least one metal is operatively configured as a sensor for detecting electrical conductivity.

7. The semiconductor device according to claim 6, wherein, The detected conductivity is correlated with an order of magnitude such that the order of magnitude changes according to a shift of the energy field structure by a corresponding amount of the second voltage applied to the fin structure that controls the size of the opening of the gate.

8. The semiconductor device according to claim 7, wherein, The detected conductivity causes the semiconductor device to operate as an inverter.

9. The semiconductor device according to claim 1, wherein, The ballistic electron flow is generated by an epitaxial layer that forms the third arm channel and includes InAlN / GaN, such that a predetermined amount of indium concentration is tuned to match the GaN lattice, resulting in higher electron mobility.

10. The semiconductor device according to claim 1, wherein, The first voltage and the second voltage are connected to the same ground terminal.

11. The semiconductor device according to claim 1, wherein, The fin structure is a U-shaped structure having a transverse portion and two upright portions integrally formed with the transverse portion and extending from the transverse portion to form the fin structure with a U-shaped cross-section, such that an additional transverse portion is integrally formed with the two upright portions and extends from the free ends of the two upright portions away from the opening formed between the two upright portions, wherein an oxide material layer is wrapped along the surface of the fin structure and extends along the additional transverse portion.

12. A semiconductor device, the semiconductor device comprising: The structure has a first arm, a second arm, and a third arm, such that the channels of the first arm and the second arm extend to the channel of the third arm, and when the current of the first voltage flows from the first electrode of the first arm to the second electrode of the second arm, a ballistic electron flow is generated from the channels of the first arm and the second arm to the channel of the third arm, flowing through the channel of the third arm. The fin structures, located in the channel of the third arm, are positioned at a distance from the end conductance change of the third arm and are arranged in series. Each fin structure includes: A gate is formed transversely to the longitudinal axis of the fin structure and is controlled by a second voltage on the fin structure, such that the fin structure is formed to sense an energy field structure that is shifted according to the second voltage to control the opening through which the ballistic electron stream of the gate passes, thereby subjecting the ballistic electrons to diffraction and then interference, and the opening then changing the depletion width.

13. The semiconductor device according to claim 12, wherein, As the ballistic electrons pass through the gate opening, they are subjected to interference, which generates an interference pattern due to the wave characteristics of the electrons, resulting in a conductivity variation pattern in the interference pattern.

14. The semiconductor device according to claim 13, wherein, At least one metal is positioned vertically at the end of the third arm relative to the central axis of the third arm channel, such that the at least one metal is operatively configured as a sensor for detecting electrical conductivity. The detected conductivity is correlated with an order of magnitude that changes according to a shift of the energy field structure by a corresponding amount of the second voltage applied to the fin structure that controls the size of the opening of the gate. The detected conductivity causes the semiconductor device to operate as an inverter.

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