Current sensing circuit

Abstract

Current sense circuits are disclosed. According to embodiments, a method of measuring a load current flowing through a current measurement resistor coupled between a source node and a load node includes measuring a first voltage across a replica resistor when a first end of the replica resistor is coupled to the source node and a second end of the replica resistor is coupled to a reference current source, measuring a second voltage across the replica resistor when the second end of the replica resistor is coupled to the source node and the first end of the replica resistor is coupled to the reference current source, measuring a third voltage across a current sense resistor, and calculating a corrected current measurement of the load current based on the measured first voltage, the measured second voltage, and the measured third voltage.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of Italian Patent Application No. 102021000010766, filed April 28, 2021, which is hereby incorporated by reference herein. TECHNICAL FIELD

[0003] Embodiments relate to current sensing circuitry. BACKGROUND

[0004] Accurate estimation of the absorbed power is a desirable feature in RX / TX (Receiver / Transmitter) wireless charger devices. Integrated circuits providing accurate current sensing features contribute to such estimation.

[0005] Various conventional solutions proposed for this effect include a (high-side) shunt resistor (for short “shunt”), followed by an analog front-end (amplifier, filter), an analog-to-digital converter (ADC), and a digital back-end processing.

[0006] Shunt accuracy and stability have a direct impact on the measurement precision.

[0007] Conventional solutions to these problems can be summarized in two different approaches.

[0008] The first approach involves the use of an external “discrete” shunt resistor, which can be accurate and stable.

[0009] Drawbacks possibly associated with this approach include cost, packaging complexity, and difficulty of separate calibration chip.

[0010] The other approach involves the use of an integrated shunt resistor and the application of temperature calibration.

[0011] A problem associated with such other approach is that temperature calibration involves accurate temperature sensing, and can not compensate for drifts that can occur after factory calibration. Accuracy over the expected lifetime of the circuit and related devices is correspondingly reduced. SUMMARY

[0012] One or more embodiments can relate to corresponding devices. Wireless charging devices can be an example of such devices.

[0013] One or more embodiments can relate to corresponding methods.

[0014] One or more embodiments contribute to achieving high overall accuracy over the entire lifetime of a high-side current sensor based on an integrated shunt resistor with run-time self-calibration capabilities.

[0015] One or more embodiments relate to features that can be added to a basic current sensor architecture, namely: an accurate current reference based on a switched-capacitor method, e.g. a scaled replica of the shunt resistor, which can comprise a set of resistive elements similar to those used for the shunt resistor, where the shunt resistor and replica form a cross-over structure, and a set of (high voltage, HV) switches configured to switch the input of the amplifier stage between an output pin coupled to the shunt resistor and an output pin coupled to the shunt replica, and a digital signal processing circuit block that can be used to apply a run-time calibration coefficient to the digital output from the measurement function.

[0016] In one or more embodiments, a replica shunt can be provided that is sufficiently matched to the shunt resistor (e.g. by being located in the same place, arranged in the same place, possibly with a cross-over structure), and the same analog front-end circuit (amplifier, advantageously followed by an analog-to-digital converter) can be used during the self-test phase and the current measurement phase. This facilitates the assumption that the offset and sensitivity drift of the self-test chain is the same as the offset and sensitivity drift of the measurement chain. As such, the output of the current sensor can be calibrated at run-time using information acquired during the self-test phase.

[0017] In one or more embodiments, the inaccuracy of the shunt and the analog front-end can be continuously tracked and compensated for.

[0018] Advantageously, in one or more embodiments, a stable self-test reference current (over the lifetime of the circuit) can be provided using a switched-capacitor reference generator, which is capable of producing a current that depends on the bandgap voltage, the clock frequency, and the capacitance. Notably, such an element can be (much) more stable than a shunt resistor, and is currently in production.

[0019] One or more embodiments can provide advantageous features, such as: an accurate current reference based on a switched-capacitor method; providing a scaled replica of the shunt resistor, which comprises a set of resistive elements equal to those used for the shunt resistor with a cross-over structure; a set of (high voltage, HV) switches can be used to periodically switch the input of the amplifier from the shunt output pin to the shunt replica output pin; a digital signal processing block can be used to apply a run-time calibration coefficient to the measurement digital output; and a temperature sensor and temperature compensation circuit (as is commonly used in conventional solutions) can be omitted. BRIEF DESCRIPTION OF DRAWINGS

[0020] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings in which:

[0021] Figure 1 is a block diagram of a conventional current shunt monitor;

[0022] Figure 2 is a block diagram of another conventional current sensor including an integrated shunt;

[0023] Figure 3 and Figure 4 is a circuit diagram of other conventional current sensors;

[0024] Figure 5 is a block diagram of a circuit according to an embodiment of the present specification; and

[0025] Figure 6 is a flowchart example of possible operations of a circuit according to an embodiment of the present specification. DETAILED DESCRIPTION

[0026] In the following description, different specific details are shown in order to provide a thorough understanding of examples of the embodiments. The embodiments can be obtained without one or more of the specific details, or by other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the embodiments.

[0027] Reference within the framework of the present specification to "an embodiment" or "one embodiment" is intended to indicate that a particular configuration, structure, or characteristic described in relation to this embodiment is included in at least one embodiment. Thus, the presence of such phrases in one or more points of the present specification does not necessarily refer to the same same embodiment.

[0028] Furthermore, a particular configuration, structure, or characteristic can be combined in any appropriate way in one or more embodiments.

[0029] The headings / references used herein are provided only for convenience and thus do not limit the scope of protection or the scope of the embodiments.

[0030] Also, throughout the present specification, for the sake of simplicity, the same name (for example, V RECT or V LOAD ) can be used to refer to both a certain circuit node / element signal and the signal that can be present at this node / element.

[0031] In the field of wireless charging, an accurate measurement of the current absorbed by both the transmitting circuit and the receiving circuit plays an important role.

[0032] Together with the voltage measurement, the current measurement provides an indication of the power transmitted and received by the system. Information related to the power transmitted and received is important in cases where specifications introduced in standard protocols used in the wireless charging environment rely on such information.

[0033] The ability to accurately measure current in systems such as high voltage systems, in particular at their high side, can benefit from the availability of high performance sensor elements such as shunt resistors.

[0034] The ability to "read" current with high accuracy (and to maintain this accuracy over the entire lifetime of a device) is generally recognized outside the field of wireless charging.

[0035] Therefore, embodiments as discussed herein are not limited to possible uses in the field of wireless charging: one or more embodiments can be applied generally to various current measurement circuits that include a resistive type of sensitive element (shunt) integrated in the same chip as the associated front-end readout circuitry, such circuits are expected to exhibit high accuracy over time, especially in solutions operating under high voltage conditions (high side sensing topology).

[0036] Different practical applications (wireless charging in consumer electronics can again be named as a non-limiting example of such applications) use shunt resistors (shunts for short) as sensitive elements for measuring current based on Ohm's law.

[0037] According to Ohm's law V = R * I, the current of intensity I flowing through a resistor generates a voltage drop V across the resistor, which is proportional to the resistance value R of the resistor. This voltage drop can be converted into digital, thereby providing a "reading" of the current intensity.

[0038] For various reasons, this approach can be advantageous, including low cost, integrability on semiconductor material (e.g. silicon) using standard processes, and direct measurement of current.

[0039] However, such an approach can exhibit certain drawbacks related to accuracy. Indeed, the current measurement value obtained via the shunt resistor depends (linearly) on the resistance value of the shunt resistor.

[0040] A resistor integrated on e.g. silicon using standard processes can exhibit inaccurate resistance values due to reasons such as process diffusion in silicon diffusion processes, thermal drift, and sensitivity to mechanical stress and aging. Moreover, if the circuit measuring (absorbing) the current is an H-bridge with a high voltage power supply, which can be the case for a transmitter or receiver for wireless charging, the shunt resistor can be arranged in series with the power supply path to the bridge. Therefore, the voltage drop across the resistor can exhibit a common mode in the vicinity of the bridge power supply, which can be as high as tens of volts.

[0041] Another limitation stemming from the use of a shunt resistor is related to the fact that the resistance value is expected to remain small in order to reduce the impact on the efficiency of the H-bridge. Therefore, the voltage value that can be read across the shunt resistor is correspondingly reduced, typically of the order of a few mV. This almost inevitably involves the use of a low-offset, low-noise amplifier stage to amplify this weak voltage signal. This in turn involves other factors that must be taken into account, namely the common-mode rejection ratio (CMRR) of the amplifier and the offset of the amplifier (and possibly of the analog-to-digital converter ADC associated therewith).

[0042] In summary, the main factors that negatively affect the accuracy include: with respect to the shunt resistor, process spread, thermal drift, drift due to mechanical stress and aging; and with respect to the amplifier, CMRR and offset.

[0043] Various approaches have been proposed to deal with these possible sources of inaccuracy. While effective, some of these approaches exhibit various drawbacks.

[0044] For example, the process spread problem related to the shunt resistor can be addressed via in-plant calibration of each individual device; this is inevitably a time-consuming process, thus negatively affecting the cost.

[0045] The amplifier offset and its drift over time can be counteracted using chopping or self- zeroing techniques, which help to obtain an amplifier exhibiting a low offset value. The problem related to the amplifier CMRR can be addressed by means of an architecture involving components that exhibit a good match at the cost of a certain increase in the area occupied on silicon. The thermal drift of the shunt resistor can be addressed by in-plant calibration at different temperatures.

[0046] However, all these measures are quite expensive to implement and are hardly suitable for wireless chargers, which are widely used in the consumer market where cost and simplicity are important factors.

[0047] An auto-compensation-based solution can be considered as a possible alternative.

[0048] The sensitivity of the shunt resistor to mechanical stress and various aging phenomena is a largely unsolved problem, which greatly limits the overall accuracy of the current measurement system. Post-soldering drift or thermal post-cycling represent other limiting factors for the accuracy of a current measurement system based on an integrated shunt resistor.

[0049] Figure 1 The circuit diagram of US 2017 / 0123394 is an example of an arrangement disclosed by H. Cheng in “High sensitivity current shunt monitor with extended input common-mode voltage range” at the International Conference on Integrated Circuits and Systems, 2017. Figure 1 The arrangement shown in US 2017 / 0123394 comprises a low voltage output regulator 10 that receives a supply voltage V supplyand a regulated voltage Vdd is provided to a current sense circuit 12 having two inputs coupled to an external shunt resistor R via resistors Rin1, Rin2 s The opposite end of the external shunt resistor is coupled between a first voltage Vin+ and a second voltage Vin- with the load 14 coupled between the input voltage Vin- and ground.

[0050] The current sense circuit 12 provides an output voltage V OUT1 to a linear regulator 16 which is sensitive to the voltage Vdd providing the output voltage V OUT .

[0051] The system as shown in Figure 1 uses an integrated amplifier with low offset and high CMRR coupled with an external discrete shunt resistor R s (i.e. a resistor not integrated in the chip) solves the various accuracy problems sufficiently.

[0052] This solution can provide good accuracy. For cost reasons this solution is hardly attractive for the following reasons: the inherent cost of a discrete resistor; the increased packaging and board complexity due to the involvement of at least four additional pads for connecting the external component; and the inherent difficulty of performing in- factory system calibration which almost inevitably involves system calibration after assembly of the entire application board.

[0053] Figure 2 The diagram of shunt corresponds to the solution disclosed in Shalmany, Draxelmayr and Makinwa, "A ±36A integrated CSS with 0.3% gain error and 400uA offset", IEEE Journal of Solid-State Circuits, April 2017. This arrangement involves again a shunt resistor 20 which is intended to be traversed by the current I to be measured and which generates a shunt voltage V Ref which is converted into digital in a (first) analog-to-digital converter 22.

[0054] A bandgap reference generator 24 generates a reference signal V Ref applied to the analog-to-digital converter 22 as well as to another analog-to-digital converter 26. The output signals from the two converters 22, 26 (i.e. μΙ and μΤ respectively) are applied to a digital back-end circuit 28 which generates a resulting output signal D OUT based on the signals from the converters 22 and 26.

[0055] The arrangement as shown in Figure 2 is suitable for integrating the shunt resistor 20 together with a low offset readout circuit.

[0056] The problem related to the thermal variation of the resistance value of the shunt resistor 20 is solved by thermal compensation implemented via an integrated digital algorithm. The algorithm compensates based on temperature information (such as that sensed via the bandgap generator 24 and the analog-to-digital converter 26) and the thermal coefficient of the shunt resistor 20.

[0057] It was found that this thermal compensation may be insufficient for two main reasons. First, the thermal compensation is based on a predetermined thermal coefficient, which is fixed and may be inaccurate. In any case, the thermal compensation does not track possible changes in the shunt resistance value and its thermal coefficient, such as those caused by soldering and aging. Second, it is not easy to implement a temperature sensor capable of detecting the precise temperature of a shunt resistor with high accuracy: in cases where there is a high current flowing locally within the shunt resistor, a significant thermal gradient may form between the location of the shunt resistor and the location of the temperature sensor, even if both are located on the same chip.

[0058] Figure 3 and Figure 4 The figure is an example of a solution as disclosed in "A + / -12-A High-Side Current Sensor with a 25V Input CM Range from -40°C to 85°C and a 0.35% Gain Error" in IEEE Solid State Circuits Letters, Vol. 1, No. 4, April 2018. Here, a shunt resistor 30 is again provided, which is configured to be coupled to the provided voltage V Bat The power source (battery) 32 is subjected to current I S Pass through.

[0059] The voltage across the "+" and "-" terminals of the shunt resistor 30 (with the negative terminal coupled to the ground-referenced load 34) is applied to the (high-voltage) analog-to-digital converter 36.

[0060] Reference voltage generator 38 generates a PTAT-type signal ΔV that is proportional to absolute temperature. BE Provided to converter 36 and additional analog-to-digital converter 40, which also receives reference bandgap voltage V from generator 38. BG .

[0061] As in Figure 2 In the case shown, Figure 3 The analog-to-digital converters 36 and 40 provide the corresponding output signals μI and μT to the digital back-end circuit 42, which provides the output signal D. out .

[0062] Figure 4This is a circuit diagram example of a possible implementation of an analog-to-digital converter 36 built around a fully differential amplifier stage 360 ​​with a feedback network, the feedback network including a capacitor C configured to be coupled via the input. S1 C S2 Receiver shunt resistor R S Voltage signal V at both ends s and voltage V PTAT Switched capacitors.

[0063] like Figure 4 As shown, converter 36 may further include a second integrator stage 362, which provides an output quantizer 364 whose output is fed back to the applied voltage V. PTAT The input, its arrangement can be basically compared to a Δ-Σ modulator.

[0064] Figure 3 and 4 The arrangement is again based on an integrated shunt resistor, which, together with an amplifier having dynamic offset cancellation achieved by chopper operation, Figure 4 It features 360° coupling and, due to its fully differential architecture with capacitive inputs, also exhibits a high CMRR value.

[0065] Figure 3 and 4 The arrangement shown also utilizes a hybrid analog / digital approach to provide compensation for thermal variations in the shunt resistor 30.

[0066] Furthermore, the problem with this type of thermal compensation is that it cannot track changes in the shunt resistor and its thermal coefficient that occur after device calibration (post-soldering drift and aging).

[0067] Figure 5 The arrangement shown (specified as 100 overall) includes input node V. RECT This input node is configured to be coupled to a (high) voltage to supply current to the electrical load EL, representing the current to be measured. For example, node V RECT This can correspond to the power supply pin of the inverter (in the example of a wireless power transmitter) or the output pin of the rectifier (in the case of a wireless power receiver).

[0068] Note again that references to possible uses in wirelessly powered transmitters / receivers are merely exemplary and do not limit the possible applications of the embodiments.

[0069] As mentioned earlier, in Figure 5 In the arrangement shown, the current to be measured is obtained by coupling at node V. RECT Shunt resistor R between the load EL and the load EL SHUNT In V RECT The current flowing between the pin and the electrical load EL.

[0070] It is also noted that the electric load EL can be an element different from the embodiments, which is an element intended to be coupled to Figure 5 the circuitry shown in the middle.

[0071] In the circuit 100 as shown in Figure 5 , a shunt resistor R SHUNT is provided, designated R REPLICA . In one or more embodiments, a replica resistor R REPLICA is implemented comprising the same (possibly scaled) resistive element as the resistive element of the main shunt resistor R SHUNT .

[0072] Advantageously, such resistive elements of the shunt resistor R SHUNT and of the replica resistor R REPLICA are located in the same location (being integrated at the same location or in close proximity to each other) and / or exhibit a layout that is mutually crossing.

[0073] This helps to achieve a situation in which both the main shunt resistor R SHUNT and the replica resistor R REPLICA are exposed to the same environmental conditions. This choice is advantageous as it helps to reproduce in the replica resistor R REPLICA the same characteristics of the shunt resistor R SHUNT in terms of phenomena such as thermal drift, post solder drift and aging.

[0074] That is, it can be assumed that the replica resistor R REPLICA and the shunt resistor R SHUNT exhibit substantially equal relative variations of their resistance values caused by these phenomena.

[0075] Figure 5 Reference number 102 in the middle denotes analog front end (AFE) circuitry comprising a (high voltage) amplifier (with gain G) 1021 having input nodes 102A, 102B and being followed by a cascaded low pass filter 1022.

[0076] The signal output from the analog front end circuit 102 (which is a function of the voltage applied between the input nodes 102A, 102B) is provided to an analog-to-digital converter 104 configured to convert the output signal from the analog front end circuit 102 into digital and to provide a (digital) output signal OUT ADC (e.g. n bits).

[0077] Briefly, Figure 5 the circuit 100 is shown, which comprises an input node VREF and the load node V configured to be coupled to the electrical load EL in order to provide load current to the electrical load EL. LOAD .

[0078] like Figure 5 As shown, the shunt resistor R SHUNT Arranged at input node V RECT and load node V LOAD In the middle, so that when the input signal is applied to the input node V RECT And load node V LOAD When coupled to the electrical load EL, with the shunt resistor R SHUNT The voltage drop across the terminals indicates the strength of the load current supplied to the electrical load EL.

[0079] Figure 5 The gain circuit system 102 shown has a first sensing node 102A and a second sensing node 102B and is configured to generate an output signal OUT. ADC The output signal is a function of the voltage drop between the first sensing node 102A and the second sensing node 102B.

[0080] Provide a replica shunt resistor R SHUNT Replica resistor R REPLICA Among them, the replica resistor R REPLICA and shunt resistor R SHUNT They are configured to exhibit substantially equal relative (e.g., percentage) changes in their resistance values ​​due to factors such as process diffusion, thermal drift, mechanical stress, and drift caused by aging. Replica resistor R REPLICA It has a first end and a second end.

[0081] like Figure 5 As shown, the digital output signal OUT ADC Provided to digital calibration circuit 106, which is configured to generate a compensation output signal OUT. COMP (e.g., k bits).

[0082] Figure 5 The reference current generator 108 shown is configured to generate a current with intensity I ST The reference current generator 108 can be implemented in any manner known to those skilled in the art. Advantageously, the reference current generator 108 includes a switched capacitor reference generator 108.

[0083] Similarly, unless the context of the discussion below indicates otherwise, the analog front-end circuitry 102 and the analog-to-digital converter 104 can be considered conventional in the art, so there is no need to provide a more detailed description herein.

[0084] This also applies to digital calibration block 106, which calculates calibration coefficients and applies them to the digital output signal OUT from converter 104. ADC .

[0085] In this regard, it should be understood that these embodiments primarily focus on the methods by which these calibration coefficients can be derived (e.g., using a replica resistor R). REPLICA The focus is on the provision of the relevant switching circuit system discussed below, rather than on how these coefficients can be applied to the signal OUT. ADC In fact, for applying these coefficients to the signal OUT... ADC To generate the compensation output signal OUT COMP In this way, one or more embodiments are largely "obvious".

[0086] Figure 5 One or more embodiments shown help to achieve high-accuracy sensing (measurement) from node V RECT The current flowing to the load EL, thereby enabling the integration of shunt resistors (such as R) SHUNT High-side current sensor.

[0087] Figure 5 The circuit system shown also takes into account (and compensates for) those losses in accuracy that may occur after possible in-factory calibration of the equipment throughout the entire life cycle of the circuit and related systems by implementing continuous field self-calibration.

[0088] to this end, Figure 6 The circuit system shown includes a set of (high-voltage) electronic switches (e.g., MOSFET transistors) denoted as R, ST, STp, and STn. These electronic switches are configured to "turn on" (i.e., turn on) and "turn off" (disconnect) in response to homogeneous control signals R, ST, STp, STn provided by a controller circuit (such as microcontroller 110).

[0089] Controller circuit 110 can be configured (in a manner known to those skilled in the art) to implement, as will be discussed below. Figure 5 The flowchart illustrates the sequence of operations.

[0090] Briefly, as in Figure 5 As shown, the switch designated R (when on) will shunt resistor R. SHUNT The opposite ends are coupled to nodes 102A and 102B, that is, coupled to the (differential) input of amplifier 1021 in analog front-end circuit 102. The switch designated as ST (when on) will replicate resistor R. REPLICAThe opposite ends are coupled to nodes 102A and 102B, that is, coupled to the (differential) input of amplifier 1021 in analog front-end circuit 102.

[0091] It is important to note that the main resistor R SHUNT and replica resistor R REPLICA This coupling with the input of the differential amplifier 1021 has the same polarity, that is, it has the same sign.

[0092] Moreover, such as Figure 6 As shown, of the two switches designated as STp, the first switch is located at input node V. RECT and replica resistor R REPLICA The second switch is located in the middle of the first end, and the second switch is located at the replica resistor R. REPLICA The second terminal is located between the reference current generator 108 and the reference current generator. Therefore, when the switch STp is turned on, it makes the current equal to I. ST The current flows from node V in the first direction (from the first end to the second end). RECT Flow through the replica resistor R REPLICA To reference generator 108. Of the two switches designated STn, the first switch is located at input node V. RECT and replica resistor R REPLICA The second switch is located in the middle of the second end of the replica resistor R. REPLICA The first terminal is located between the reference current generator 108 and the reference current generator. Therefore, when the switch STn is turned on, it makes the current equal to I. ST The current flows from node V in a second direction opposite to the first direction (from the second end to the first end). RECT Flow through the replica resistor R REPLICA To reference generator 108.

[0093] Figure 5 The flowchart is as follows Figure 5 Examples of possible operation of the circuit shown depict a first mode represented by block 1000 (STp stage) and block 1002 (STn stage), and a second mode represented by block 1004 (R stage).

[0094] During the STp phase of box 1000: switch R is not conducting, and switch ST is conducting, replicating resistor R. REPLICA The differential input of the differential amplifier 1021 is coupled across the two ends of the differential amplifier 1021 in the analog front-end circuit 102; and switch STp is turned on (switch STn is not turned on), replicating resistor R. REPLICA From the first end to the second end (i.e., in) Figure 5 The representation from left to right (with intensity I) ST The current flows through. In the STp stage of box 1000, the output OUT from converter 104...ADC Designated as OUT ADCSTp .

[0095] During the STn phase of box 1002: switch R is not conducting, and switch ST is conducting, replicating resistor R. REPLICA It is recoupled across the differential input of the differential amplifier 1021 in the analog front-end circuit 102; and switch STn is turned on (switch STp is not turned on), replicating resistor R. REPLICA From the second end to the first end (i.e., in) Figure 6 The representation from right to left (i.e., the opposite direction relative to the STp stage of block 1000) has intensity I. ST The current flows through. During the STn stage of block 1002, the output OUT from converter 104... ADC Designated as OUT ADCSTn .

[0096] That is, in Figure 6 During the first operating mode, represented by blocks 1000 and 1002, the replica resistor R is... REPLICA : Coupled between the first sensing node 102A and the second sensing node 102B of the gain circuit system 102, and coupled to the current generator 108, so as to be controlled by the reference current I ST It alternately passes through the first and second directions, with the second direction being opposite to the first direction. Therefore, the output signal OUT from the gain circuit... ADC : In response to reference current I ST Through the replica resistor R in the first direction REPLICA And presenting the first value OUT ADCSTp ; and in response to the reference current (I ST The second value OUT is obtained by passing through the replica resistor RREPLICA in the second direction. ADCSTn .

[0097] During phase R of box 1004, switch R is on and switch ST is off (switches STp and STn are similarly off to avoid replicating resistor R). REPLICA Unnecessary power absorption in the shunt resistor R SHUNT The differential inputs of the differential amplifier 1021, coupled to the analog front-end circuit system 102, are used to sense the connection at node V. RECT Resistor R between the load EL and the load EL SHUNT The voltage across the terminals. In the R stage of block 1004, the output OUT from converter 104. ADC Designated as OUT ADCR .

[0098] That is, during the second mode of operation, represented by block 1004, the shunt resistor R SHUNT coupled between the first and second sense nodes 102A, 102B of the gain circuitry 102 and from the output signal OUT ADC presents a third value OUT ADCR .

[0099] The following equations describe the operation of the circuit 100 along the lines of the flowchart. Figure 5

[0100] The following definitions are helpful in reading and understanding the equations reproduced below:

[0101] V OFFAFE : offset of the AFE 102 (e.g., amplifier 1021 and filter 1022);

[0102] V CMAFE : error due to finite CMRR in the AFE block;

[0103] V OFFADC : offset of the ADC 104;

[0104] R SHUNT0 : initial value of the shunt resistor R shunt (shic this can be measured during factory calibration);

[0105] R REPLICA0 : initial value of the replica resistor R REPLICA (shic this can be measured during factory calibration)

[0106] G0: initial value of the gain G of the AFE 102 (this can be measured during factory calibration process);

[0107] I ST0 : initial value of the reference current I st (this can be measured during factory calibration process); and

[0108] SENS ST0 : output from stage 'ST' at "zero time" (this can be measured during factory calibration and stored in memory, e.g., in the controller 110).

[0109] The output in stage R

[0110]

[0111] The output in stages 'STp' and 'STn' of blocks 1000 and 1002:

[0112] ​

[0113]

[0114] To calculate the compensation output OUT COMP The calculations performed in the digital calibration circuit block 106 may include:

[0115]

[0116]

[0117] SENS ST0 =I ST0 ·R REPLICA0 ·G0

[0118]

[0119]

[0120] That is, in the possible implementations discussed in this paper, the calibration circuit 106 is configured to generate a first value OUT. ADCSTp Second value OUT ADCSTn average And generate OUT as the third value ADCR With the first value OUT ADCSTp Second value OUT ADCSTn The aforementioned average value OFF ST The difference between (OUT) ADCR -OFF ST The compensated output signal OUT of the function. COMP .

[0121] Furthermore, in the possible implementations discussed herein, the calibration circuit 106 is configured to generate normalized values. This normalized value is the first value OUT. ADCSTp With the second value OUT ADCSTn The difference between The function, and relative to the normalized value SENS DRIFT For the compensated output signal OUT COMP Normalize.

[0122] like Figure 6 As shown, circuit 100 includes an analog-to-digital converter (ADC 104) between gain circuitry system 102 and calibration circuitry 106. This ADC 104 is configured to convert the output signal OUT from gain circuitry system 102 into a digital signal. ADC The value is converted to a digital value. Therefore, the calibration circuit 106 may include a digital circuit system configured to calculate the value OUT as a digital value.ADCSTp , OUT ADCSTn and OUT ADCR the function of the compensated output signal OUT COMP .

[0123] Considering the expression of the compensated output:

[0124]

[0125] The resistor R REPLICA is a scaled copy of the resistor R SHUNT . Moreover, it is exposed to the same thermal and mechanical stresses and to the same process-related variations (e.g. due to being located in the same place, possibly in a mutually crossing arrangement). Therefore, it can be reasonably assumed that the resistor R REPLICA will undergo a relative variation of its resistance value with respect to the initial value R REPLICA0 This replicates, in turn, the relative variation of the resistance value of R SHUNT with respect to the initial value R SHUNT of R SHUNT0 i.e.:

[0126]

[0127] i.e. by referring to the expression of the compensated output:

[0128]

[0129] Assuming that I ST is generated by the switched-capacitor reference generator 108 (in a manner known to those skilled in the art), IST can be expressed as:

[0130] I ST = V bg · C · f ck

[0131] where V bg is a bandgap voltage, C is a capacitance, and f ck is a clock frequency.

[0132] All these parameters can be considered substantially stable with respect to the value of R shunt , and it can be assumed that:

[0133]

[0134] As a conclusion, the digitally compensated output corresponds to the expected output, without error contribution

[0135] OUT COMP = I IN · R​​SHUNT0 ·G0.

[0136] Therefore, during the phases designated as STp and STn ( Figure 6 Boxes 1000 and 1002 in the diagram can be used to measure resistor R. REPLICA The offset and gain changes of the entire chain, including the analog front-end 102 and the analog-to-digital converter 104.

[0137] As discussed, the replica resistor R REPLICA It is a shunt resistor R SHUNT A scaled-down copy. Advantageously, resistor R REPLICA and shunt resistor R SHUNT This includes physically identical modules arranged in an intersecting pattern. As a result, it can be reasonably assumed that the replica resistor R... REPLICA Passing through shunt resistor R SHUNT The same changes that occur during this process (thermal drift, mechanical stress, and aging).

[0138] Furthermore, the analog front-end circuit 102 and the analog-to-digital converter 104 are connected through... Figure 6 All stages of boxes 1000, 1002, and 1004 are identical and subject to the same changes.

[0139] Therefore, the total change measured during stages STP and STn can be used to compensate for the shunt resistance R. SHUNT Offset and gain changes in the chain of analog front-end circuit 102 and analog-to-digital converter 104.

[0140] During the phase designated as R ( Figure 6 In box 1004, the measured value of the current through the load EL is available at the output of analog-to-digital converter 104, such as OUT. ADR This includes due to the shunt resistor R SHUNT Error contributions caused by analog front-end circuit 102 and analog-to-digital converter 104.

[0141] Digital calibration circuit 106 can utilize data acquired during the phases designated STp and STn in blocks 1000 and 1002 (primarily OFF). ST and SENS DRIFT To calculate entity OUT COMP .

[0142] As shown, this corresponds to the reading (measured value) of the input current, where due to R SHUNT All error sources caused by the analog front-end 102 and the analog-to-digital converter 104 were removed.

[0143] Figure 5The flowchart of the circuit is represented by the blocks 1000 and 1002 in Figure 6 The example of the possibility of automatic repetition of the circuit in

[0144] For example, in those applications in which a high level of accuracy is desired and / or a rapid development over time of the relevant (thermal or mechanical) stress phenomena is expected, the steps of the blocks 1000 and 1002 can be repeated before each step of measuring the current as represented by the block 1004.

[0145] This option is represented by the possible positive outcome (Y) of the check performed in the step 1006 (high precision desired and / or stress of significant rapid variation expected). In that case, the steps of the blocks 1000 and 1002 can be repeated after each current measurement step of the block 1004.

[0146] The negative outcome (N) of the check of the block 1006 can be considered indicative of a situation in which a lower level of accuracy is desired and / or the stress sources are expected to develop more slowly over time.

[0147] In that case, a further negative outcome (N) of the check as represented by the block 1008 can lead to the execution of a new measurement R phase without the need to repeat the steps STp and STn represented by the blocks 1000 and 1002.

[0148] On the contrary, the positive outcome (Y) of the check of the block 1008 can be an example of a threshold number of measurement steps R that have already been carried out without self-calibration (as can be indicated in the internal counter in the step 1004). Therefore, this positive outcome of the check of the block 1008 would cause the calibration of the blocks 1000 and 1002 to be repeated before the new measurement step of the block 1004.

[0149] Namely, the operation of the circuit 100 as discussed herein can comprise an alternation of a first mode (blocks 1000, 1002 in Figure 6 and a second mode (block 1004 in Figure 6 , in which, selectively (see block 1006 in Figure 5 : each occurrence of the second mode 1004 is followed by an occurrence of the first mode 1000, 1002 (outcome Y of the step 1006) or, after a plurality of occurrences of the second mode 1004 (as determined in the step 1008), the first mode 1000, 1002 is repeated (outcome N of the step 1006).

[0150] Note that the arrangement discussed here benefits from an accurate matching of the shunt resistor R SHUNT and the replica resistor R REPLICA .

[0151] the high resolution of the analog-to-digital converter 104 and the precise trimming of the gain of the cascade arrangement of the analog front-end circuit 102 and the analog-to-digital converter 104, and the reduced variation of the capacitance and bandgap source used to generate the reference current I ST may represent other advantageous factors that facilitate the adequate operation of the arrangement as shown in ​

[0152] The simulation results show that even taking into account possible non-idealities among the factors discussed above, one or more embodiments can reduce errors affecting the compensation output (OUT CONF as a function of temperature and other error sources) in a very narrow range around zero.

[0153] Therefore, one or more embodiments facilitate obtaining a current measurement in a high-side arrangement, for example, with an integrated shunt resistor (such as R SHUNT ) that has the ability to compensate for major error sources throughout the useful life of the associated device. This can be achieved through self-calibration that can be repeated periodically in the field during device operation.

[0154] An advantage is the ability to also compensate for those errors related to variations of electrical parameters of components in the circuit that can occur after the initial factory calibration.

[0155] In a device (as a non-limiting example, a wireless charging device) that includes a circuit 100 as discussed herein having an electrical load EL coupled with a load node V LOAD , the compensation output signal OUT COMP indicates the strength of the load current provided to the electrical load EL with high accuracy.

[0156] In an embodiment, the circuit includes gain circuitry configured to produce an output signal that is a function of a voltage drop across a shunt resistor traversed by a current applied to the electrical load. A replica resistor of the shunt resistor is provided that exhibits a relative variation of resistance value that is substantially equal to a relative variation of resistance value of the shunt resistor. A switching circuit is provided that is controllable in a first mode in which the replica resistor is coupled to an input of the gain circuitry and traversed by a reference current in an opposite direction, such that in a second mode the output signal from the gain circuitry assumes a first value OUT ADCSTp and a second value OUT ADCSTn , respectively, in which the shunt resistor is coupled to the input of the gain circuitry, the output signal from the gain circuitry assumes a third value OUT ADCR . A calibration circuit receives the output signal from the gain circuitry and produces a first OUT ADCSTp , a second OUT​ADCSTn and a third OUT ADCR a compensated output signal of a function of the values, which provides an accurate measurement of the current applied to the electrical load.

[0157] The details and embodiments can vary considerably without departing from the basic principles, without departing from the scope of protection.

Claims

1. A circuit comprising: A shunt resistor is coupled between an input node and a load node, the input node being configured to have an input signal applied thereto, and the load node being configured to be coupled to an electrical load, wherein, when the input signal is applied to the input node and the load node is coupled to the electrical load, the voltage drop across the shunt resistor indicates the load current supplied to the electrical load. A replica resistor is made, the shunt resistor is replicated, the replicated resistor having a first terminal and a second terminal; A gain circuit system is configured to generate an output signal that is a function of the voltage drop between the first sensing node and the second sensing node; A current generator is configured to generate a reference current; A set of electronic switches is configured to connect: In a first mode, the replicated resistor is coupled between the first and second sensing nodes of the gain circuit system and is coupled to the current generator to be alternately passed through by the reference current in a first direction and a second direction opposite to the first direction. The output signal from the gain circuit system exhibits a first value in response to the reference current passing through the replicated resistor in the first direction and a second value in response to the reference current passing through the replicated resistor in the second direction. In the second mode, the shunt resistor is coupled between the first sensing node and the second sensing node of the gain circuit system, and the output signal from the gain circuit system exhibits a third value; and A calibration circuit system is configured to receive the output signal from the gain circuit system and generate a compensation output signal as a function of the first value, the second value, and the third value; The calibration circuit system is configured as follows: Generate the average of the first value and the second value; and The compensation output signal is generated as a function of the difference between the third value and the average of the first value and the second value.

2. The circuit of claim 1, wherein the replica resistor and the shunt resistor exhibit equal relative changes in their resistance values.

3. The circuit according to claim 1, further comprising: A first switching circuit system is configured to couple the shunt resistor between the first sensing node and the second sensing node when it is turned on. A second switching circuit system is configured to couple the replica resistor between the first sensing node and the second sensing node when it is turned on. A third switching circuit system is configured to couple the first and second terminals of the replica resistor to the input node and the current generator, respectively, when the replica resistor is turned on, wherein the replica resistor is traversed by the reference current flowing through the replica resistor in the first direction; as well as A fourth switching circuit system is configured to couple the second and first terminals of the replica resistor to the input node and the current generator, respectively, when the replica resistor is turned on, wherein the replica resistor is traversed by the reference current flowing through the replica resistor in the second direction opposite to the first direction; as well as A switch control circuit system is configured to control the first switch circuit system, the second switch circuit system, the third switch circuit system, and the fourth switch circuit system: In the first mode, the second switching circuit system is turned on to couple the replica resistor between the first sensing node and the second sensing node of the gain circuit system, and the third and fourth switching circuit systems are alternately turned on, wherein the output signal from the gain circuit system exhibits the first value in response to the third switching circuit being turned on, and exhibits the second value in response to the fourth switching circuit being turned on. In the second mode, the first switching circuit system is turned on to couple the shunt resistor between the first sensing node and the second sensing node of the gain circuit system, and the output signal from the gain circuit system presents the third value.

4. The circuit according to claim 3, wherein: The first switching circuit system includes a first electronic switch pair, which is configured to couple the opposite ends of the shunt resistor to the first sensing node and the second sensing node of the gain circuit system when turned on. and The second switching circuit system includes a second pair of electronic switches configured to couple the first and second terminals of the replica resistor to the first and second sensing nodes of the gain circuit system when the resistor is turned on.

5. The circuit according to claim 4, wherein: The third switching circuit system includes a corresponding pair of electronic switches, which are configured to couple the first and second terminals of the replica resistor to the input node and the current generator, respectively, when the circuit is turned on. and The fourth switching circuit system includes another corresponding electronic switch pair configured to couple the second and first terminals of the replica resistor to the input node and the current generator, respectively, when turned on.

6. The circuit of claim 1, wherein the current generator includes a switched-capacitor reference generator configured to generate a reference current as a function of the product of the bandgap voltage, capacitance, and clock frequency.

7. The circuit of claim 1, further comprising an analog-to-digital converter (ADC) system coupled between the gain circuit system and the calibration circuit system, the ADC system configured to convert an output signal from the gain circuit system into a digital value, wherein the calibration circuit system includes a digital circuit system configured to calculate a compensation output signal as a function of the first value, the second value, and the third value, wherein the first value, the second value, and the third value are converted into a digital value.

8. The circuit according to claim 1, wherein: The gain circuit system includes a differential amplifier, wherein the first sensing node and the second sensing node provide differential inputs to the differential amplifier; or The gain circuit system includes a low-pass filter located at the output of the gain circuit system.

9. The circuit of claim 1, wherein the replica resistor and the shunt resistor are located in the same position, wherein the replica resistor and the shunt resistor have an intersecting structure.

10. The circuit of claim 1, wherein the calibration circuit system is configured as follows: Generate a normalized value, which is a function of the difference between the first value and the second value; and The compensated output signal is normalized relative to the normalized value.

11. An apparatus comprising: The circuit according to claim 1, and An electrical load, coupled to the load node in the circuit, wherein the compensation output signal indicates the load current supplied to the electrical load.

12. A method of operating the device according to claim 11, the method comprising: The first mode alternates with the second mode, wherein the first mode occurs every time the second mode occurs, or the first mode is repeated after the second mode has occurred multiple times.

13. A current sensing circuit, comprising: A current-sensing resistor is coupled between the source node and the load node; A replica resistor having the same temperature characteristics as the current sensing resistor; A voltage measurement circuit, coupled to the current sensing resistor and the replica resistor, is configured as follows: When the first terminal of the replica resistor is coupled to the source node and the second terminal of the replica resistor is coupled to the reference current source, a first voltage is measured across the replica resistor. When the second terminal of the replica resistor is coupled to the source node and the first terminal of the replica resistor is coupled to the reference current source, measure the second voltage across the replica resistor, and Measure the third voltage across the current sensing resistor; as well as A calibration circuit, coupled to the voltage measurement circuit, is configured to generate a calibrated current measurement value based on a measured first voltage, a measured second voltage, and a measured third voltage, the calibrated current measurement value indicating the current flowing through the current sensing resistor. The calibration circuit includes a digital calibration circuit, which is configured to: Calculate the average of the measured first voltage and the measured second voltage; and The corrected current measurement is calculated based on the difference between the measured third voltage and the calculated average value.

14. The current sensing circuit of claim 13, wherein the voltage measurement circuit comprises: A plurality of switches are coupled between the replica resistor and the voltage measurement circuit; The second plurality of switches are coupled between the current sensing resistor and the voltage measuring circuit; A first switch is coupled between the source node and the first terminal of the replica resistor; A second switch is coupled between the source node and the second terminal of the replica resistor; A third switch is coupled between the first terminal of the replica resistor and the reference current source; as well as A fourth switch is coupled between the second terminal of the replica resistor and the reference current source.

15. The current sensing circuit of claim 14, further comprising a controller, the controller being configured to: When the voltage measuring circuit measures the first voltage, the first plurality of switches, the first switch, and the fourth switch are closed. When the voltage measuring circuit measures the second voltage, the first plurality of switches, the second switch, and the third switch are closed. as well as When the voltage measuring circuit measures the third voltage, the second plurality of switches are closed.

16. The current sensing circuit according to claim 13, wherein: The voltage measurement circuit includes an analog-to-digital converter; and The digital calibration circuit is coupled to the output of the analog-to-digital converter.

17. A method for measuring load current flowing through a current sensing resistor coupled between a source node and a load node, the method comprising: When the first end of the replica resistor is coupled to the source node and the second end of the replica resistor is coupled to the reference current source, the first voltage across the replica resistor is measured. When the second end of the replica resistor is coupled to the source node and the first end of the replica resistor is coupled to the reference current source, measure the second voltage across the replica resistor; Measure the third voltage across the current sensing resistor; as well as Based on the measured first voltage, the measured second voltage, and the measured third voltage, calculate the corrected current measurement value of the load current; The calculation of the corrected current measurement value includes: Calculate the average of the measured first voltage and the measured second voltage; as well as The corrected current measurement is calculated based on the difference between the measured third voltage and the calculated average value.

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