Methods, devices and storage media for acquiring memory data

Abstract

This application discloses a method, apparatus, and storage medium for acquiring memory data, belonging to the field of virtualization technology. The hardware resources of a computer device are divided into an REE side and a TEE side. The processor shares the first page table of address mapping on the REE side with the TEE side. A VMI program runs in the target SP on the TEE side. Based on the target virtual address, the first page table, and the second page table, the VMI program running in the target SP acquires the memory data of the target VM on the REE side. The first page table refers to the page table that maps virtual addresses to intermediate addresses, and the second page table refers to the page table that maps intermediate addresses to physical addresses. Because the VMI program running in the target SP uses the shared pages on the REE side when acquiring the memory data of the target VM, and does not occupy the page table of the target VM, there are no monitoring blind spots, and the target VM is unaware of the existence of the target SP.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of virtualization, and particularly relate to a memory data acquisition method and device and storage medium. BACKGROUND

[0002] Hardware resources of a computer device can be divided into a Rich Execution Environment (REE) side and a Trusted Execution Environment (TEE) side. The REE side includes a plurality of virtual machines (VMs), and the VMs are used to process user-related data. However, the security of the REE side is lower than that of the TEE side, and the VMs are vulnerable to malicious attacks, which results in low security of user data. Therefore, it is necessary to acquire memory data of the VMs to monitor the VMs, so as to avoid malicious attacks on the VMs.

[0003] Virtual machine introspection (VMI) technology is a security monitoring solution that is concerned by the industry, that is, memory data of a VM is acquired by using the VMI technology to monitor the VM, which can avoid malicious attacks on the VM. A related technology proposes a method for acquiring memory data by using the VMI technology. The method introduces an Immersive Execution Environment (ImEE) system, and one or more page table entries of an Extended Page Table (EPT) of a target VM are modified. The modified page table entries point to a VMI program. The ImEE system can use a virtual address of the target VM to directly determine a corresponding physical address from the EPT by running the VMI program. In this way, memory data of the target VM can be quickly and efficiently read, and the ImEE system can effectively detect whether the target VM is maliciously attacked because the virtual address can provide some semantic information.

[0004] However, the VMI program occupies a part of the page table entries of the EPT, and the data corresponding to the modified page table entries is the code and data of the VMI program, rather than the code and data of the target VM, that is, the code and data of the target VM corresponding to the page table entries are not monitored, which results in a monitoring blind spot. SUMMARY

[0005] Embodiments of the present application provide a memory data acquisition method and device and storage medium, which can avoid the monitoring blind spot to some extent. The present application is introduced in the following aspects. It should be understood that the implementation manners and beneficial effects of the following aspects can be mutually referred.

[0006] In a first aspect, a memory data acquisition method is provided, in which hardware resources of a computer device are divided into a REE side and a TEE side, the REE side includes one or more VMs, and the TEE side includes one or more SPs, the TEE side is deployed with a VMI program, and the method includes: a processor sharing a first page table for address mapping of the REE side to the TEE side, the first page table being a page table for mapping a virtual address to an intermediate address; the processor running the VMI program in a target SP, the target SP being an SP of the one or more SPs for acquiring memory data of a target VM, the target VM being any one of the one or more VMs; and the processor acquiring, according to a target virtual address, the first page table, and a second page table, memory data of the target VM through the VMI program running in the target SP, the second page table being a page table shared by the TEE side and the REE side and used for mapping the intermediate address to a physical address, and the target virtual address being a virtual address corresponding to the memory data to be acquired.

[0007] The first page table is a page table for mapping a virtual address to an intermediate address, and the second page table is a page table shared by the TEE side and the REE side and used for mapping the intermediate address to a physical address. Therefore, after the first page table and the second page table are shared by the REE side and the TEE side, the target SP of the TEE side can determine a physical address corresponding to a virtual address of the target VM according to the first page table and the second page table, and can quickly and efficiently acquire memory data of the target VM. Moreover, the VMI program running in the target SP does not occupy a page table of the target VM, that is, a page table entry in the first page table or the second page table is not modified to point to the VMI program running in the target SP, so that there is no monitoring blind spot, and the VMI program running in the target SP can also be well hidden in the REE side, and the target VM cannot perceive the existence of the target SP.

[0008] In order to better monitor the target VM, the target SP on the REE side not only needs to obtain data of the target VM in the user space, but also needs to obtain data of the target VM in the kernel space. In order to obtain the data of the target VM in the user space and the data of the target VM in the kernel space, the REE side and the TEE side both further include a first base address register and a second base address register, the first base address register being a base address register corresponding to the user space, and the second base address register being a base address register corresponding to the kernel space. That is, the first base address register points to a page table in the user space for mapping a virtual address to an intermediate address, and the second base address register points to a page table in the kernel space for mapping a virtual address to an intermediate address. In this way, in a case where the memory data to be obtained is data in the user space, the processor shares the page table pointed to by the first base address register on the REE side as a first page table to the first base address register on the TEE side. In a case where the memory data to be obtained is data in the kernel space, the processor shares the page table pointed to by the second base address register on the REE side as a first page table to the second base address register on the TEE side.

[0009] Since the processor can work on the REE side and can work on the TEE side, and the processor can switch between the REE side and the TEE side. When the processor works on the REE side, the hardware resources on the TEE side are prohibited from being accessed. However, when the processor works on the TEE side, the processor can access the hardware resources on the TEE side and can access the hardware resources on the REE side. Moreover, the target SP on the TEE side is used to obtain the memory data of the target VM on the REE side in the embodiments of the present application, so the processor works on the TEE side in the embodiments of the present application. In this way, the processor can access the first base address register and the second base address register on the REE side, so as to determine the page table pointed to by the first base address register and the page table pointed to by the second base address register, and further share the page table pointed to by the first base address register as a first page table to the TEE side in a case where the memory data to be obtained is data in the user space, and share the page table pointed to by the second base address register as a first page table to the TEE side in a case where the memory data to be obtained is data in the kernel space. In other embodiments, the processor can directly share the page table of the first base address register and / or the second base address register to the TEE side without the judgment of the two aforementioned "cases".

[0010] The base register is used to store a memory entry address, thereby pointing to data (which is page table data in this embodiment) corresponding to the memory entry address. Therefore, the process of sharing the page table pointed to by the first base register on the REE side as the first page table to the first base register on the TEE side includes modifying the address stored in the first base register on the TEE side to the page table entry address stored in the first base register on the REE side, so as to share the page table pointed to by the first base register on the REE side as the first page table to the first base register on the TEE side.

[0011] Similarly, the process of sharing the page table pointed to by the second base register on the REE side as the first page table to the second base register on the TEE side includes modifying the address stored in the second base register on the TEE side to the page table entry address stored in the second base register on the REE side, so as to share the page table pointed to by the second base register on the REE side as the first page table to the second base register on the TEE side.

[0012] In some embodiments of the present application, the VMI program is deployed in both the user space and the kernel space on the TEE side. In this way, in the case where the memory data to be acquired is data in the user space, after the processor shares the page table pointed to by the first base register on the REE side as the first page table to the first base register on the TEE side, the second base register on the TEE side needs to be pointed to the VMI program deployed in the kernel space on the TEE side, and the VMI program pointed to by the second base register needs to be run in the target SP with the kernel mode permission. In the case where the memory data to be acquired is data in the kernel space, after the processor shares the page table pointed to by the second base register on the REE side as the first page table to the second base register on the TEE side, the first base register on the TEE side needs to be pointed to the VMI program deployed in the user space on the TEE side, and the VMI program pointed to by the first base register needs to be run in the target SP with the kernel mode permission.

[0013] Since the TEE side includes the user mode and the kernel mode, the processor can work in the user mode and can also work in the kernel mode. When the data of the target VM in the user space is acquired, after the page table pointed to by the first base register of the REE side is shared as the first page table to the first base register of the TEE side, the second base register of the TEE side is pointed to the VMI program deployed in the kernel space of the TEE side, so that the processor runs the VMI program deployed in the kernel space of the TEE side in the target SP, and isolation of the target SP and the target VM is realized. Similarly, when the data of the target VM in the kernel space is acquired, after the page table pointed to by the second base register of the REE side is shared as the first page table to the second base register of the TEE side, the first base register of the TEE side is pointed to the VMI program deployed in the user space of the TEE side, so that the processor runs the VMI program deployed in the user space of the TEE side in the target SP, and isolation of the target SP and the target VM is realized.

[0014] The memory data to be acquired can be the data of the target VM in the user space or the data of the target VM in the kernel space. In order to realize the isolation of the target SP and the target VM, when the memory data to be acquired is the data of the target VM in the user space, the second base register of the TEE side is pointed to the VMI program deployed in the kernel space of the TEE side. Since the code and the data of the VMI program are located in the kernel space, the memory data to be acquired is located in the user space, and the permission level of the kernel mode is higher than that of the user mode, the processor in the kernel mode can access the hardware resources in the user space, therefore, the processor runs the VMI program located in the kernel space in the target SP with the kernel state permission, so that the memory data in the user space can be successfully read. That is, the VMI program pointed to by the second base register is run in the target SP with the kernel state permission, so that the memory data in the user space can be successfully read.

[0015] However, when the memory data to be acquired is the data of the target VM in the kernel space, the first base register on the TEE side points to the VMI program deployed in the user space on the TEE side. Since the code and data of the VMI program are located in the user space, the memory data to be acquired is located in the kernel space, and the permission level of the kernel mode is higher than that of the user mode, if the VMI program located in the user space is run in the target SP with the user state permission, so as to acquire the memory data in the kernel space, an error will occur in the permission check. Therefore, in the embodiment of the present application, when the processor runs the VMI program in the target SP, the VMI program located in the user space needs to be run in the target SP with the kernel state permission, so as to successfully read the memory data in the kernel space. That is, the VMI program pointed to by the first base register is run in the target SP with the kernel state permission, and the memory data in the kernel space can be successfully read, thereby solving the problem that the VMI program in the user space cannot read the data in the kernel space.

[0016] It should be noted that the VMI program needs to access the memory data required by itself during running. However, the VMI program is located on the TEE side, and the memory data required by the VMI program is stored in the secure memory, while the memory data of the target VM is stored in the non-secure memory. Therefore, in the embodiment of the present application, the TEE side further includes a fourth base register (such as the vsttbr_el2 described above), and the fourth base register points to a third page table. The third page table is a page table for intermediate address to physical address mapping for normal running of the VMI program. In this way, the processor can run the VMI program in the target SP according to the third page table pointed to by the fourth base register, so as to ensure that the VMI program can access the memory data required by itself in the secure memory during running. At the same time, the running of the VMI program can be better isolated from the target VM.

[0017] In order to realize the second layer memory address mapping, the REE side and the REE side further include a third base register, and the third base register on the REE side and the third base register on the TEE side both point to a second page table. In this way, the implementation process of the processor acquiring the memory data of the target VM through the VMI program running in the target SP according to the target virtual address, the first page table and the second page table includes: in the process of running the VMI program in the target SP, the processor determines the intermediate address corresponding to the target virtual address according to the first page table through the MMU, and determines the physical address corresponding to the intermediate address according to the second page table pointed to by the third base register on the TEE side. The processor acquires the memory data corresponding to the physical address through the VMI program running in the target SP.

[0018] In the case that the page table item where the intermediate address is located is stored in the secure memory, the NS bit in the page table item where the intermediate address is located is acquired by the MMU. If the NS bit is the first value, the physical address corresponding to the intermediate address is determined by the MMU according to the second page table pointed to by the third base register on the TEE side. In the case that the page table item where the intermediate address is located is stored in the non-secure memory, the physical address corresponding to the intermediate address is determined by the MMU according to the second page table pointed to by the third base register on the TEE side.

[0019] In the case that the page table item where the intermediate address is located is stored in the secure memory, the physical address mapped out by the second layer memory address mapping may fall into the secure memory or the non-secure memory. At this time, the NS bit in the page table item where the intermediate address is located needs to be acquired. If the NS bit is the first value, it is considered that the processor currently needs to acquire data of the non-secure memory, such as data of the target VM, so that the physical address mapped out by the second layer memory address mapping falls into the non-secure memory. Therefore, the MMU determines the physical address corresponding to the intermediate address according to the second page table pointed to by the third base register on the TEE side. If the NS bit is the second value, it is considered that the processor currently needs to acquire data of the secure memory, such as memory data of the VMI program during normal operation. Therefore, the physical address mapped out by the second layer memory address mapping falls into the secure memory. Therefore, the MMU determines the physical address corresponding to the intermediate address according to the third page table pointed to by the fourth base register on the TEE side.

[0020] However, in the case that the page table item where the intermediate address is located is stored in the non-secure memory, it is considered that the memory data currently acquired by the processor is necessarily data of the non-secure memory. Therefore, the MMU directly determines the physical address corresponding to the intermediate address according to the second page table pointed to by the third base register on the TEE side, without the need to determine through the NS bit in the page table item where the intermediate address is located.

[0021] In a second aspect, a memory data acquisition apparatus is provided, which has a function of implementing behaviors of the memory data acquisition method in the first aspect. The memory data acquisition apparatus includes at least one module for implementing the memory data acquisition method provided in the first aspect.

[0022] In a third aspect, a computer device is provided, which includes a processor and a memory. The memory is configured to store a program for implementing the memory data acquisition method provided in the first aspect, and store data involved in implementing the memory data acquisition method provided in the first aspect. The processor is configured to execute the program stored in the memory. The computer device can further include a communication bus configured to establish a connection between the processor and the memory.

[0023] In a fourth aspect, a computer readable storage medium is provided, which stores instructions. When the instructions are executed on a computer device, the computer device is caused to perform the steps of the memory data acquisition method provided in the first aspect.

[0024] In a fifth aspect, a computer program product is provided, which includes instructions. When the instructions are executed on a computer device, the computer device is caused to perform the steps of the memory data acquisition method provided in the first aspect.

[0025] The technical effects obtained by the second aspect, the third aspect, the fourth aspect and the fifth aspect are similar to the technical effects obtained by the corresponding technical means in the first aspect, and thus are not described herein.

[0026] In the embodiments of the present application, since the first page table refers to a page table for mapping a virtual address to an intermediate address, and the second page table refers to a page table shared by the TEE side and the REE side and used for mapping the intermediate address to a physical address, after the first page table and the second page table are shared by the REE side and the TEE side, the target SP on the TEE side can determine the physical address corresponding to the virtual address of the target VM according to the first page table and the second page table, and thus can quickly and efficiently acquire the memory data of the target VM. Moreover, the VMI program running in the target SP does not occupy the page table of the target VM, that is, the page table entry in the first page table or the second page table is not modified to point to the VMI program running in the target SP, so that there is no monitoring blind spot, and at the same time, the VMI program running in the target SP can be well hidden on the REE side, and the target VM cannot perceive the existence of the target SP. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 FIG. 1 is a schematic diagram of a hardware architecture of an ARM processor provided in an embodiment of the present application;

[0028] Figure 2 FIG. 2 is a schematic diagram of an architecture after virtualization of a TEE side and an REE side provided in an embodiment of the present application;

[0029] Figure 3 FIG. 3 is a schematic diagram of an architecture of a server scenario provided in an embodiment of the present application;

[0030] Figure 4 is a schematic diagram of an architecture of an intelligent terminal scene provided by an embodiment of the present application.

[0031] Figure 5 is a schematic diagram of a structure of a computer device provided by an embodiment of the present application.

[0032] Figure 6 is a flowchart of a memory data acquisition method provided by an embodiment of the present application.

[0033] Figure 7 is a schematic diagram of a memory acquisition apparatus provided by an embodiment of the present application. DETAILED DESCRIPTION

[0034] To make the objectives, technical solutions and advantages of embodiments of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0035] To facilitate understanding, before the memory data acquisition method provided by an embodiment of the present application is explained in detail, the implementation background of the embodiment of the present application is introduced.

[0036] With the continuous improvement of the performance of advanced RISC machines (ARM) processors, computer devices running ARM processors have brought great convenience to people's life. At the same time, more and more user data are carried on the computer devices, and users also pay more and more attention to the security of the computer devices.

[0037] The TrustZone technology is the mainstream technology for solving the security of computer devices. Through the TrustZone technology, the hardware resources of the computer device can be divided into the REE side and the TEE side, and the physical memory of the computer device is divided into non-secure memory and secure memory. The code and data of the REE side are stored in the non-secure memory, the code and data of the TEE side are stored in the secure memory, and the security of the REE side is lower than that of the TEE side. The user operating system works in the REE side, the TrustZone works in the TEE side as a hardware security feature, and the processor can work in the REE side and the TEE side, and can switch between the REE side and the TEE side.

[0038] When the processor works in the REE side, the hardware resources (such as registers, memories, caches, peripherals, etc.) in the TEE side are prohibited to be accessed, and once the processor attempts to access the hardware resources, the system will directly crash. For example, by means of the TrustZone technology, a TrustZone address space controller (TZASC) register and a TrustZone memory adapter (TZMA) register can be configured to set a sensitive memory as a secure memory, and the processor working in the REE side cannot access the secure memory but can access a non-secure memory. When the processor works in the TEE side, the processor can access both the hardware resources in the TEE side and the hardware resources in the REE side. For example, the processor working in the TEE side can access both the secure memory and the non-secure memory.

[0039] Due to the higher authority than the operating system in the REE side, the TrustZone can serve as a trusted root to provide security protection for the operating system in the REE side. The non-secure memory does not mean that the data stored therein is malicious, but the security of the environment in which the non-secure memory is located is lower than that of the secure memory. That is, the security of the non-secure memory is lower than that of the secure memory.

[0040] Figure 1 The hardware architecture of the ARM processor is described. The left side is the architecture of the REE side, and by means of hardware virtualization, the REE side can create multiple VMs, and each VM runs a user operating system (OS) (such as Android, Windows, Linux, etc.). Figure 1Moreover, in order to support hardware virtualization, the REE side includes not only user mode and kernel mode, but also HYP mode, which correspond to different hardware resources of the REE side, and the permission levels of the three modes are in ascending order, i.e., the permission level of user mode is the lowest, and the permission level of HYP mode is the highest. The VM runs in user mode and kernel mode of the REE side, i.e., the user operating system runs in user mode and kernel mode of the REE side, and the hypervisor (Hypervisor) for virtualization management runs in HYP mode, wherein the hypervisor is also called virtual machine monitor (VMM). Since HYP mode is the mode with the highest permission level of the REE side, when the processor works in HYP mode, it can access all hardware resources of user mode, kernel mode and HYP mode. However, when the processor runs in user mode or kernel mode, it cannot access the hardware resources of HYP mode. Therefore, the hypervisor has higher permission than the operating system. In addition, the processor can also switch between kernel mode and HYP mode, i.e., executing a hypervisor call (HVC) instruction in kernel mode of the REE side can enter HYP mode, and executing an ERET instruction in HYP mode will return to kernel mode.

[0041] As the REE side on the left, the TEE side on the right also includes user mode and kernel mode, but the TEE side does not support hardware virtualization at the beginning, so the TEE side does not include HYP mode, and the TEE side only runs one operating system. However, the TEE side also includes a special mode, namely the monitor mode, so the TEE side also includes three modes, namely the user mode, the kernel mode and the monitor mode, which correspond to different hardware resources of the TEE side, and the user mode has the lowest permission level and the monitor mode has the highest permission level. At the same time, the monitor mode is also a mode with the highest permission level of the entire processor, and when the processor works in the monitor mode, it can not only access all hardware resources of the TEE side, but also access all hardware resources of the REE side. Through the TrustZone technology, the Hypervisor-related control register can be configured in the monitor mode to initialize and activate the Hypervisor. The monitor mode is also a portal for the REE side to enter the TEE side, and the secure monitor call (SMC) instruction executed in the kernel mode or the HYP mode of the REE side can switch from the REE side to the monitor mode of the TEE side. The return (ERET) instruction executed in the monitor mode of the TEE side can make the processor determine whether to return to the kernel mode of the REE side or continue to stay in the TEE side by checking the non-secure (NS) bit of the secure control register (SCR) in the monitor mode. When the NS bit is 1, the processor returns to the kernel mode of the REE side, and when the NS bit is 0, the processor returns to the kernel mode of the TEE side.

[0042] In order to support memory virtualization, ARM introduces a second layer of memory address mapping memory virtualization technology. With this technology, the common one layer of memory address mapping from virtual address to physical address is changed into two layers of memory address mapping from virtual address to intermediate address, and then from intermediate address to physical address. The process of the second layer of memory address mapping is completely controlled by the Hypervisor, which is transparent to the operating system. In the view of the operating system, the intermediate address is the physical address corresponding to the virtual address. Therefore, by setting the properties of the control bits of the second layer address mapping page table entry, the Hypervisor can control the access of the operating system to the memory. The page table entry includes three control bits of read, write and execution. Among them, the read and write control bits are related to the data protection of the memory, and the execution control bit is related to the execution of the memory code. By configuring the read, write and execution control bits, the Hypervisor can monitor the access to the physical memory at the page granularity and protect the relevant sensitive information.

[0043] However, with the development of TrustZone technology, various manufacturers have adopted their own TEE operating system, that is, the TEE side uses an operating system, which is the operating system of each manufacturer, and the fragmentation of the TEE operating system is more and more serious. Moreover, the single TEE operating system on the TEE side to support multiple VMs on the REE side will also bring stability and robustness problems. Therefore, the embodiment of the present application introduces a new processor working mode SEL2 to support the hardware virtualization technology on the TEE side. In this way, the TEE side can construct a virtualization environment similar to the REE side, that is, the TEE side creates multiple SPs, and each SP can run a TEE operating system. The multiple TEE operating system architecture can solve the two problems of TEE operating system fragmentation and support for multiple VMs on the REE side. That is, as shown in Figure 2 the REE side includes multiple VMs, each of which runs a user operating system, and a virtual machine monitor is used to manage the multiple VMs. The REE side can also install an application (application, APP) for user use. Similarly, the TEE side includes multiple SPs, each of which runs a TEE operating system, and an SP manager is used to manage the multiple SPs.

[0044] Moreover, in the support of memory virtualization, the design of the first layer memory address mapping of the TEE side and the REE side is the same, and the design of the second layer memory address mapping of the TEE side and the REE side is slightly different. That is, the base register for performing the second layer memory address mapping of the TEE side includes two, vttbr_el2 and vsttbr_el2, while the REE side only has one base register for performing the second layer memory address mapping, that is, vttbr_el2. Among them, the physical address mapped by the page table pointed to by vttbr_el2 will fall on the non-safe memory, and the physical address mapped by the page table pointed to by vsttbr_el2 will fall on the safe memory. That is, through vttbr_el2 and vsttbr_el2, the processor working in the TEE side can access both the safe memory and the non-safe memory.

[0045] Since the user operating system runs in the VM for processing user-related data, and the VM is vulnerable to malicious attacks, the security of the user data is low. Moreover, the VMI technology is a security monitoring solution that the industry is concerned about, so the embodiment of the present application can run the VMI program in the multiple SPs created on the TEE side, and through the VMI program and the design of the second layer memory address mapping, the memory data of the VM can be obtained, thereby monitoring the VM and avoiding malicious attacks on the VM. For detailed implementation, see the subsequent description, which is not expanded here.

[0046] The method provided by the embodiments of the present application can be applied to a server scenario and can also be applied to a smart terminal scenario. In the server scenario, as shown in Figure 3 , the REE side and the TEE side both support hardware virtualization features, the REE side creates a plurality of VMs, each of which runs a user operating system and a client application (CA), and a virtual machine monitor is used to manage the plurality of VMs. The REE side can also install an APP for use by a user. Similarly, the TEE side creates a plurality of SPs, each of which runs a TEE operating system and a trusted application (TA), and an APP, such as an APP for intrusion detection, can also be installed in the SP, and an SP manager is used to manage the plurality of SPs. In order to provide support for a TEE trusted execution environment, when a certain VM is started, a corresponding SP is started on the TEE side, and the TEE operating system is run in the SP to support secure services in the VM.

[0047] In the smart terminal scenario, as shown in Figure 4 , although the REE side and the TEE side do not have a strong requirement to start a plurality of VMs or SPs, when the memory virtualization features of the REE side and the TEE side are turned on, the operating system (such as an Android operating system) of the REE side that is closely related to a user and the TEE operating system of the TEE side are considered to be running in a VM and an SP, respectively. In this scenario, the TEE operating system can also monitor the operating system in the VM, thereby detecting whether the operating system in the VM is maliciously attacked and improving the security of the operating system in the VM.

[0048] CA refers to a client that can call an application on the TEE side, and the CA runs on the REE side. TA refers to a trusted application that runs on the TEE side. For example, in the process of running, the CA in the VM can call the TA in the SP to implement certain functions. The embodiments of the present application rarely involve this aspect, and therefore the embodiments of the present application do not make a detailed introduction to this.

[0049] Please refer to Figure 5 , Figure 5 is a structural schematic diagram of a computer device according to an embodiment of the present application. The computer device is a server or a smart terminal. The computer device comprises at least one processor 501, a communication bus 502, a memory 503, and at least one communication interface 504.

[0050] The processor 501 is a general central processing unit (CPU), a network processor (NP), a microprocessor, or one or more integrated circuits utilized to implement a

[0051] The communication bus 502 is used to transmit information between the above-mentioned components. The communication bus 502 is divided into an address bus, a data bus, a control bus, and the like. For the sake of representation, only one thick line is shown in the figure, but it does not mean that there is only one bus or only one type of bus.

[0052] The memory 503 is a read-only memory (ROM), a random access memory (RAM), an electrically erasable programmable read-only memory (EEPROM), an optical disk (including a compact disc read-only memory (CD-ROM), a compact disc, a laser disc, a digital versatile disc, a Blu-ray disc, and the like), a magnetic disk storage medium or other magnetic storage device, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and capable of being accessed by a computer, but is not limited thereto. The memory 503 can exist independently and be connected to the processor 501 through the communication bus 502. The memory 503 can also be integrated with the processor 501.

[0053] The communication interface 504 uses any device such as a transceiver to communicate with other devices or communication networks. The communication interface 504 includes a wired communication interface and can also include a wireless communication interface. The wired communication interface is, for example, an Ethernet interface. The Ethernet interface is an optical interface, an electrical interface, or a combination thereof. The wireless communication interface is a wireless local area networks (WLAN) interface, a cellular network communication interface, or a combination thereof.

[0054] In a particular implementation, as one example, the processor 501 includes one or more CPUs, such as CPU0 and CPU1 as shown in FIG. 5. Figure 5

[0055] In a particular implementation, as one example, the computer device can include multiple processors, such as the processor 501 and the processor 505 as shown in FIG. 5. Each of these processors is a single-core processor, or a multi-core processor. A processor here refers to one or more devices, circuits, and / or processing cores for processing data, such as computer program instructions. Figure 5

[0056] In a particular implementation, as one example, the computer device can further include an output device 506 and an input device 507. The output device 506 is in communication with the processor 501 to display information in various ways. For example, the output device 506 is a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, a projector, or the like. The input device 507 is in communication with the processor 501 to receive user input in various ways. For example, the input device 507 is a mouse, a keyboard, a touch screen device, a sensor device, or the like.

[0057] In some embodiments, the memory 503 is used to store program code 510 for implementing the solutions of the present application, and the processor 501 can execute the program code 510 stored in the memory 503. The program code 510 includes one or more software modules, and the computer device can implement the following Figure 6 The memory data acquisition method provided by the embodiments.

[0058] Next, the memory data acquisition method provided by the embodiments of the present application will be explained in detail.

[0059] Figure 6 FIG. 5 is a flowchart of a memory data acquisition method provided by an embodiment of the present application, which is applied to a computer device. The hardware resources of the computer device are divided into a REE side and a TEE side. The REE side includes one or more VMs, and the TEE side includes one or more SPs. The TEE side is deployed with a VMI program. The embodiment of the present application is to run the VMI program through the SP of the TEE side to acquire the memory data of the VM of the REE side, so as to monitor the VM and avoid malicious attacks on the VM.

[0060] Please refer to​​Figure 6 The method comprises the following steps.

[0061] Step 601: The processor shares a first page table for address mapping on the REE side to the TEE side, the first page table being a page table for mapping a virtual address to an intermediate address.

[0062] Based on the foregoing description, in order to support memory virtualization, a memory virtualization technology of a second layer of memory address mapping is introduced. That is, when accessing memory data, two layers of memory address mapping are required, the first layer of memory address mapping being mapping a virtual address to an intermediate address, and the second layer of memory address mapping being mapping the intermediate address to a physical address. Since the first page table in the embodiment of the present application is a page table for mapping a virtual address to an intermediate address on the REE side, that is, the first page table is a page table used to implement the first layer of memory address mapping on the REE side. Therefore, when the target SP on the TEE side needs to obtain memory data of the target VM, in order to avoid the TEE side occupying the page table of the target VM, the first page table needs to be shared to the TEE side. The target VM refers to any one of one or more VMs on the REE side, and the target SP refers to an SP on the TEE side for obtaining memory data of the target VM.

[0063] Since the REE side includes a user mode and a kernel mode, the VM on the REE side can run in the user mode and the kernel mode, and the TEE side also includes a user mode and a kernel mode, and the SP on the TEE side can also run in the user mode and the kernel mode, therefore, the running space of the REE side includes a user space and a kernel space, and the running space of the TEE side also includes a user space and a kernel space, the VM on the REE side runs in the user space or the kernel space on the REE side, and the SP on the TEE side runs in the user space or the kernel space on the TEE side. Moreover, for the VM on the REE side, the memory data of the VM includes data of the VM in the user space and data of the VM in the kernel space. That is, the memory data of the VM has a distinction between the user space and the kernel space.

[0064] In the embodiment of the present application, in order to better monitor the target VM, the target SP on the REE side not only needs to obtain data of the target VM in the user space, but also needs to obtain data of the target VM in the kernel space. In order to be able to obtain data of the target VM in the user space and data of the target VM in the kernel space, the REE side and the TEE side each further include a first base address register and a second base address register, the first base address register being a base address register corresponding to the user space, and the second base address register being a base address register corresponding to the kernel space. That is, the first base address register points to a page table for mapping a virtual address to an intermediate address in the user space, and the second base address register points to a page table for mapping a virtual address to an intermediate address in the kernel space.

[0065] In the case that the memory data to be acquired is user space data, the processor shares the page table pointed to by the first base register on the REE side as a first page table to the first base register on the TEE side. In the case that the memory data to be acquired is kernel space data, the processor shares the page table pointed to by the second base register on the REE side as a first page table to the second base register on the TEE side.

[0066] Based on the foregoing description, the processor can work on the REE side and can work on the TEE side, and the processor can switch between the REE side and the TEE side. When the processor works on the REE side, the hardware resources on the TEE side are prohibited from being accessed. However, when the processor works on the TEE side, the processor can access the hardware resources on the TEE side and can access the hardware resources on the REE side. Moreover, the embodiment of the present application acquires the memory data of the target VM on the REE side by the target SP on the TEE side, and therefore, in the embodiment of the present application, the processor works on the TEE side. In this way, the processor can access the first base register and the second base register on the REE side, so as to determine the page table pointed to by the first base register and the page table pointed to by the second base register, and further share the page table pointed to by the first base register as a first page table to the TEE side in the case that the memory data to be acquired is user space data, and share the page table pointed to by the second base register as a first page table to the TEE side in the case that the memory data to be acquired is kernel space data.

[0067] The base register is used to store a memory entry address, so as to point to data corresponding to the memory entry address. Therefore, the implementation process in which the processor shares the page table pointed to by the first base register on the REE side as a first page table to the first base register on the TEE side includes: modifying the address stored in the first base register on the TEE side to the page table entry address stored in the first base register on the REE side, so as to share the page table pointed to by the first base register on the REE side as a first page table to the first base register on the TEE side.

[0068] Similarly, the implementation process in which the processor shares the page table pointed to by the second base register on the REE side as a first page table to the second base register on the TEE side includes: modifying the address stored in the second base register on the TEE side to the page table entry address stored in the second base register on the REE side, so as to share the page table pointed to by the second base register on the REE side as a first page table to the second base register on the TEE side.

[0069] Step 602: The processor runs the VMI program in the target SP.

[0070] In the embodiments of the present application, the VMI program is deployed in the user space and the kernel space of the TEE side. In this way, in the case that the memory data to be acquired is user space data, after the processor shares the page table pointed to by the first base register of the REE side as the first page table to the first base register of the TEE side, the processor also needs to point the second base register of the TEE side to the VMI program deployed in the kernel space of the TEE side, and run the VMI program pointed to by the second base register in the target SP with the kernel state permission. In the case that the memory data to be acquired is kernel space data, after the processor shares the page table pointed to by the second base register of the REE side as the first page table to the second base register of the TEE side, the processor also needs to point the first base register of the TEE side to the VMI program deployed in the user space of the TEE side, and run the VMI program pointed to by the first base register in the target SP with the kernel state permission.

[0071] Based on the foregoing description, the TEE side includes a user mode and a kernel mode, and the processor can work in the user mode and the kernel mode. When acquiring the data of the target VM in the user space, after the processor shares the page table pointed to by the first base register of the REE side as the first page table to the first base register of the TEE side, the processor points the second base register of the TEE side to the VMI program deployed in the kernel space of the TEE side, so as to make the processor run the VMI program deployed in the kernel space of the TEE side in the target SP, thereby realizing the isolation of the target SP and the target VM. Similarly, when acquiring the data of the target VM in the kernel space, after the processor shares the page table pointed to by the second base register of the REE side as the first page table to the second base register of the TEE side, the processor points the first base register of the TEE side to the VMI program deployed in the user space of the TEE side, so as to make the processor run the VMI program deployed in the user space of the TEE side in the target SP, thereby realizing the isolation of the target SP and the target VM.

[0072] Since the base register is used to store the memory entry address, thereby pointing to the data corresponding to the memory entry address. Therefore, the implementation process of the processor pointing the second base register of the TEE side to the VMI program deployed in the kernel space of the TEE side includes: modifying the address stored in the second base register of the TEE side to the entry address of the VMI program deployed in the kernel space of the TEE side, so as to point the second base register of the TEE side to the VMI program deployed in the kernel space of the TEE side. Similarly, the implementation process of the processor pointing the first base register of the TEE side to the VMI program deployed in the user space of the TEE side includes: modifying the address stored in the first base register of the TEE side to the entry address of the VMI program deployed in the user space of the TEE side, so as to point the first base register of the TEE side to the VMI program deployed in the user space of the TEE side.

[0073] Based on the description in step 601, the memory data to be acquired can be the data of the target VM in the user space or the data of the target VM in the kernel space. In order to realize the isolation of the target SP and the target VM, when the memory data to be acquired is the data of the target VM in the user space, the second base register on the TEE side points to the VMI program deployed in the kernel space on the TEE side. Since the code and data of the VMI program are located in the kernel space, the memory data to be acquired is located in the user space, and the permission level of the kernel mode is higher than that of the user mode, the processor in the kernel mode can access the hardware resources in the user space, therefore, the processor runs the VMI program in the kernel space in the target SP with the kernel state permission, so as to successfully read the memory data in the user space. That is, the VMI program pointed to by the second base register is run in the target SP with the kernel state permission, so as to successfully read the memory data in the user space.

[0074] However, when the memory data to be acquired is the data of the target VM in the kernel space, the first base register on the TEE side points to the VMI program deployed in the user space on the TEE side. Since the code and data of the VMI program are located in the user space, the memory data to be acquired is located in the kernel space, and the permission level of the kernel mode is higher than that of the user mode, if the VMI program in the user space is run in the target SP with the user state permission, so as to acquire the memory data in the kernel space, an error will occur in the permission check, therefore, in the embodiment of the present application, when the processor runs the VMI program in the target SP, the VMI program in the user space needs to be run in the target SP with the kernel state permission, so as to successfully read the memory data in the kernel space. That is, the VMI program pointed to by the first base register is run in the target SP with the kernel state permission, so as to successfully read the memory data in the kernel space, thereby solving the problem that the VMI program in the user space cannot read the data in the kernel space.

[0075] It should be noted that the VMI program needs to access the memory data required by itself during the running process, but the VMI program is located on the TEE side, and the memory data required by the VMI program is stored in the secure memory, while the memory data of the target VM is stored in the non-secure memory, therefore, in the embodiment of the present application, the TEE side further includes a fourth base register (such as the vsttbr_el2 described above), and the fourth base register points to a third page table, and the third page table is a page table for the intermediate address to physical address mapping for the normal running of the VMI program. In this way, the processor can run the VMI program in the target SP according to the third page table pointed to by the fourth base register, so as to ensure that the VMI program can access the memory data required by itself in the secure memory during the running process. Meanwhile, the running of the VMI program can be better isolated from the target VM.

[0076] In step 603, the processor obtains the memory data of the target VM through the VMI program running in the target SP according to the target virtual address, the first page table and a second page table, the second page table is a page table shared by the TEE side and the REE side and used for mapping the intermediate address to the physical address, and the target virtual address is a virtual address corresponding to the memory data to be obtained.

[0077] Since two layers of memory address mapping are needed when accessing the memory data, the first page table is a page table used for performing the first layer of memory address mapping, and the second page table is a page table used for mapping the intermediate address to the physical address, that is, the second page table is a page table used for performing the second layer of memory address mapping. Therefore, after the first page table is shared to the TEE side, the second page table also needs to be shared to the TEE side.

[0078] Based on the above description, the target VM can run in the user space or the kernel space, and the data of the target VM has the user space and the kernel space. Therefore, when performing the first layer of memory address mapping, the first page table needs to be dynamically switched between the user space and the kernel space. However, the second layer of memory address mapping is divided into mapping of the secure memory and the non-secure memory. For example, the physical address mapped through the second page table falls in the non-secure memory, and the physical address mapped through a third page table falls in the secure memory. That is, the second layer of memory address mapping is divided into mapping of the secure memory and the non-secure memory, and there is no distinction between the user space and the kernel space, and the data of the target VM is stored in the non-secure memory. Therefore, in the embodiment of the present application, the TEE side and the REE side can always share the second page table without the need of sharing again in the process of obtaining the data of the target VM.

[0079] In order to implement the second layer of memory address mapping, the REE side and the REE side each further include a third base address register (such as the vttbr_el2 described above), and the third base address register of the REE side and the third base address register of the TEE side each points to the second page table. In this way, the implementation process of the processor obtaining the memory data of the target VM through the VMI program running in the target SP according to the target virtual address, the first page table and the second page table includes that, in the process of the processor running the VMI program in the target SP, the processor determines the intermediate address corresponding to the target virtual address according to the first page table through the MMU, and determines the physical address corresponding to the intermediate address according to the second page table pointed to by the third base address register of the TEE side. The processor obtains the memory data corresponding to the physical address through the VMI program running in the target SP.

[0080] Generally, the processor is addressed by a virtual address, but the memory data is stored in the memory based on a physical address, therefore, after the processor obtains the target virtual address, the target virtual address can be mapped by the MMU to determine the corresponding physical address, and then the processor obtains the corresponding memory data according to the physical address.

[0081] In the implementation process of determining the physical address corresponding to the intermediate address by the MMU according to the second page table pointed by the third base register on the TEE side, in the case that the page table item where the intermediate address is located is stored in the secure memory, the NS bit in the page table item where the intermediate address is located is obtained by the MMU. If the NS bit is the first value, the physical address corresponding to the intermediate address is determined by the MMU according to the second page table pointed by the third base register on the TEE side. In the case that the page table item where the intermediate address is located is stored in the non-secure memory, the physical address corresponding to the intermediate address is determined by the MMU according to the second page table pointed by the third base register on the TEE side.

[0082] Based on the above description, the memory data of the target VM will be stored in the non-secure memory, but the VMI program may also need to access the memory data required by itself during running, and these memory data are stored in the secure memory, so when the processor obtains the memory data, it may access the secure memory or the non-secure memory, or the physical address mapped by the second layer memory address may fall into the secure memory or the non-secure memory. However, the process of memory address mapping is automatically completed by the MMU, and does not require any software to participate, therefore, for the MMU, the MMU does not know whether the processor currently needs to access the secure memory or the non-secure memory, so after the MMU determines the intermediate address, it needs to judge whether to perform the second layer memory address mapping by the second page table or the third page table based on whether the page table item where the intermediate address is located is stored in the secure memory or the non-secure memory.

[0083] In the case that the page table item where the intermediate address is located is stored in the secure memory, the physical address mapped out by the second layer memory address mapping may fall into the secure memory or the non-secure memory, at this time, the NS bit in the page table item where the intermediate address is located needs to be acquired. If the NS bit is the first value, it is considered that the processor currently needs to acquire the data of the non-secure memory, such as the data of the target VM, so that the physical address mapped out by the second layer memory address mapping falls into the non-secure memory, therefore, the MMU determines the physical address corresponding to the intermediate address according to the second page table pointed by the third base register of the TEE side. If the NS bit is the second value, it is considered that the processor currently needs to acquire the data of the secure memory, such as the memory data of the VMI program running normally, so that the physical address mapped out by the second layer memory address mapping falls into the secure memory, therefore, the MMU determines the physical address corresponding to the intermediate address according to the third page table pointed by the fourth base register of the TEE side.

[0084] However, in the case that the page table item where the intermediate address is located is stored in the non-secure memory, it is considered that the memory data currently acquired by the processor is necessarily the data of the non-secure memory, therefore, the MMU directly determines the physical address corresponding to the intermediate address according to the second page table pointed by the third base register of the TEE side, without the need to determine through the NS bit in the page table item where the intermediate address is located.

[0085] It needs to be noted that the first value and the second value are set in advance and can be adjusted according to the needs. For example, the first value is 1 and the second value is 0. That is, in the case that the NS bit in the page table item where the intermediate address is located is 1, the MMU determines the physical address corresponding to the intermediate address according to the second page table pointed by the third base register of the TEE side. In the case that the NS bit in the page table item where the intermediate address is located is 0, the MMU determines the physical address corresponding to the intermediate address according to the third page table pointed by the fourth base register of the TEE side.

[0086] In order to ensure the accuracy of the memory address mapping performed by the MMU, after the MMU maps the physical address from the intermediate address through the second-level memory address mapping, the MMU can also determine whether the relationship between the mapped physical address and the corresponding memory attribute matches, so as to determine whether an error occurs in the memory address mapping process. That is, after the MMU determines the physical address corresponding to the intermediate address according to the second page table pointed to by the third base register on the TEE side, the MMU determines whether the physical address is located in the non-secure memory. If the physical address is located in the non-secure memory, it is determined that no error occurs in the memory address mapping process, otherwise, it is determined that an error occurs in the memory address mapping process. Similarly, after the MMU determines the physical address corresponding to the intermediate address according to the third page table pointed to by the fourth base register on the TEE side, the MMU determines whether the physical address is located in the secure memory. If the physical address is located in the secure memory, it is determined that no error occurs in the memory address mapping process, otherwise, it is determined that an error occurs in the memory address mapping process. The subsequent detection can further improve the accuracy of the memory address mapping.

[0087] It should be noted that the page table includes multiple levels of page table entries, and the page table entries are used to indicate the mapping relationship of the memory address, and the page table entries include control bits such as the NS bit. The specific implementation process of the memory address mapping through the page table is not described in detail in the embodiments of the present application.

[0088] In addition, the VMI program can also deploy related analysis tools, so that after the target SP obtains the memory data of the target VM, the memory data of the target VM can be analyzed, especially for the target VM vulnerable to malicious attacks, intrusion detection, kernel integrity protection, etc., so as to realize real-time analysis of the process granularity in the target VM, and better protect the target VM to avoid malicious attacks on the target VM.

[0089] In the embodiments of the present application, since the first page table refers to the page table for mapping the virtual address to the intermediate address, and the second page table refers to the page table shared by the TEE side and the REE side and used for mapping the intermediate address to the physical address, after the REE side and the TEE side share the first page table and the second page table, the target SP on the TEE side can determine the physical address corresponding to the virtual address of the target VM according to the first page table and the second page table, and then quickly and efficiently obtain the memory data of the target VM. Moreover, the VMI program running in the target SP will not occupy the page table of the target VM, that is, the page table entries in the first page table or the second page table will not be modified to point to the VMI program running in the target SP, so that there is no monitoring blind spot, and the VMI program running in the target SP can also be well hidden on the REE side, and the target VM cannot perceive the existence of the target SP.

[0090] Further, since the virtual address can generally provide some semantic information, after the VMI program in the target SP obtains the target virtual address, the semantic information carried by the target virtual address can be known, and the memory data of the target VM can also be directly read according to the physical address corresponding to the target virtual address, so that the semantic gap problem is solved, and whether the target VM is maliciously attacked can be more effectively detected. In addition, the normal running of the VMI program in the target SP is to map the memory address through the non-shared third page table, which is completely isolated from the target VM, and the target SP is located on the TEE side and the target VM is located on the REE side, so the security of the target SP is higher than that of the target VM. Therefore, the VMI program running in the target SP is not easily attacked on the REE side, and the concealment and security of the VMI program running in the target SP are improved.

[0091] Figure 7 is a structural schematic diagram of a memory data acquisition device provided by an embodiment of the present application. The memory data acquisition device can be realized by software, hardware or a combination of both to become part or all of a computer device. The hardware resources of the computer device are divided into an REE side and a TEE side, the REE side includes one or more VMs, the TEE side includes one or more SPs, and the VMI program is deployed on the TEE side. Referring to Figure 7 , the device includes a page table sharing module 701, a program running module 702 and a data acquisition module 703.

[0092] The page table sharing module 701 is configured to share a first page table for address mapping of the REE side to the TEE side. The first page table refers to a page table for mapping a virtual address to an intermediate address. For details, please refer to the step 601 in the embodiment shown in the above Figure 6 , which will not be repeated here.

[0093] The program running module 702 is configured to run a VMI program in a target SP. The target SP refers to an SP for acquiring memory data of a target VM in the one or more SPs. The target VM refers to any VM in the one or more VMs. For details, please refer to the step 602 in the embodiment shown in the above Figure 6 , which will not be repeated here.

[0094] The data acquisition module 703 is configured to acquire memory data of a target VM by a VMI program running in a target SP according to a target virtual address, a first page table and a second page table. The second page table refers to a page table shared by the TEE side and the REE side and used for mapping an intermediate address to a physical address. The target virtual address refers to a virtual address corresponding to the memory data to be acquired. For details, please refer to the step 603 in the embodiment shown in the above Figure 6 , which will not be repeated here.

[0095] Optionally, the REE side and the TEE side each further include a first base address register and a second base address register, the first base address register being a base address register corresponding to a user space, and the second base address register being a base address register corresponding to a kernel space.

[0096] The page table sharing module 701 is specifically configured to:

[0097] In a case where the memory data to be acquired is data of the user space, a page table pointed to by the first base address register of the REE side is shared as a first page table to the first base address register of the TEE side.

[0098] Optionally, a VMI program is deployed in the user space and the kernel space of the TEE side.

[0099] The program running module 702 is specifically configured to:

[0100] The second base address register of the TEE side points to the VMI program deployed in the kernel space of the TEE side.

[0101] The VMI program pointed to by the second base address register is run in the target SP with a kernel mode permission.

[0102] Optionally, the REE side and the TEE side each further include a first base address register and a second base address register, the first base address register being a base address register corresponding to a user space, and the second base address register being a base address register corresponding to a kernel space.

[0103] The page table sharing module 701 is specifically configured to:

[0104] In a case where the memory data to be acquired is data of the kernel space, a page table pointed to by the second base address register of the REE side is shared as a first page table to the second base address register of the TEE side.

[0105] Optionally, a VMI program is deployed in the user space and the kernel space of the TEE side.

[0106] The program running module 702 is specifically configured to:

[0107] The first base address register of the TEE side points to the VMI program deployed in the user space of the TEE side.

[0108] The VMI program pointed to by the first base address register is run in the target SP with a kernel mode permission.

[0109] Optionally, the REE side and the TEE side each further include a third base address register, and the third base address register of the REE side and the third base address register of the TEE side each point to a second page table.

[0110] The data acquisition module 703 includes:

[0111] an address mapping unit, configured to determine, by a memory management unit (MMU), an intermediate address corresponding to the target virtual address according to the first page table and determine a physical address corresponding to the intermediate address according to a second page table pointed by a third base register on the TEE side during running of the VMI program in the target SP;

[0112] a data obtaining unit, configured to obtain memory data corresponding to the physical address by the VMI program running in the target SP.

[0113] Optionally, the address mapping unit is specifically configured to:

[0114] in a case where the page table item where the intermediate address is located is stored in the secure memory, obtain a non-secure (NS) bit in the page table item where the intermediate address is located by the MMU.

[0115] if the NS bit is the first value, determine the physical address corresponding to the intermediate address according to the second page table pointed by the third base register on the TEE side by the MMU.

[0116] Optionally, the address mapping unit is specifically configured to:

[0117] in a case where the page table item where the intermediate address is located is stored in the non-secure memory, determine the physical address corresponding to the intermediate address according to the second page table pointed by the third base register on the TEE side by the MMU.

[0118] Optionally, the TEE side further includes a fourth base register, and the fourth base register points to a third page table, and the third page table is a page table for normal running of the VMI program to perform intermediate address to physical address mapping.

[0119] The program running module 702 is specifically configured to:

[0120] run the VMI program in the target SP according to the third page table pointed by the fourth base register.

[0121] In the embodiments of the present application, since the first page table refers to a page table for mapping a virtual address to an intermediate address, and the second page table refers to a page table shared by the TEE side and the REE side and used for mapping the intermediate address to a physical address, after the first page table and the second page table are shared by the REE side and the TEE side, the target SP on the TEE side can determine the physical address corresponding to the virtual address of the target VM according to the first page table and the second page table, and then can quickly and efficiently obtain the memory data of the target VM. Moreover, the VMI program running in the target SP does not occupy the page table of the target VM, that is, the page table entry in the first page table or the second page table is not modified to point to the VMI program running in the target SP, so that there is no monitoring blind spot, and at the same time, the VMI program running in the target SP can be well hidden on the REE side, and the target VM cannot perceive the existence of the target SP.

[0122] Furthermore, since the virtual address can generally provide some semantic information, after the VMI program in the target SP obtains the target virtual address, the semantic information carried by the target virtual address can be known, and the memory data of the target VM can be directly read according to the physical address corresponding to the target virtual address, thereby solving the semantic gap problem and enabling the target VM to be more effectively detected whether it is maliciously attacked. In addition, the normal running of the VMI program in the target SP is to map the memory address through the non-shared third page table, which is completely isolated from the target VM, and the target SP is located on the TEE side and the target VM is located on the REE side, so the security of the target SP is higher than that of the target VM. Therefore, the VMI program running in the target SP is not easily attacked by the REE side, and the concealment and security of the VMI program running in the target SP are improved.

[0123] It should be noted that the memory data obtaining apparatus provided in the above embodiments is only exemplified by the division of the above functional modules when obtaining memory data. In actual applications, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the apparatus is divided into different functional modules to complete all or part of the above described functions. In addition, the memory data obtaining apparatus and the memory data obtaining method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process is described in detail in the method embodiments, which will not be repeated here.

[0124] In the above embodiments, all or part can be realized by software, hardware, firmware or any combination thereof. When realized by software, all or part can be realized in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed by a computer, the computer instructions generate all or part of the processes or functions described in the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another, for example, the computer instructions can be transferred from one website, computer, server or data center to another via wire (for example: coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example: infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium accessible by a computer, or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media is a magnetic medium (for example: floppy disk, hard disk, magnetic tape), an optical medium (for example: digital versatile disc (DVD)) or a semiconductor medium (for example: solid state disk (SSD)) etc. It should be noted that the computer-readable storage medium mentioned in the embodiments of the present application can be a non-volatile storage medium, in other words, it can be a non-transitory storage medium.

[0125] It should be understood that "multiple" mentioned herein refers to two or more. In the description of the embodiments of the present application, unless otherwise specified, " / " represents the meaning of or, for example, A / B can represent A or B; "and / or" herein only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone. In addition, in order to clearly describe the technical solutions of the embodiments of the present application, "first", "second" and the like are used to distinguish the same items or similar items with basically the same function and role in the embodiments of the present application. Those skilled in the art can understand that "first", "second" and the like do not limit the quantity and execution order, and "first", "second" and the like do not necessarily mean different.

[0126] The above describes the embodiments provided by the present application, which does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for obtaining memory data, characterized by, Hardware resources of a computer device are divided into a rich execution environment (REE) side and a trusted execution environment (TEE) side, the REE side including one or more virtual machines (VMs), and the TEE side including one or more secure enclaves (SPs), the TEE side being deployed with a virtual machine introspection (VMI) program, and the method includes: a processor sharing a first page table for address mapping of the REE side to the TEE side, the first page table being a page table for mapping a virtual address to an intermediate address; the processor running the VMI program in a target SP, the target SP being an SP of the one or more SPs for obtaining memory data of a target VM, the target VM being any VM of the one or more VMs; the processor obtaining, according to a target virtual address, the first page table and a second page table, the memory data of the target VM by the VMI program running in the target SP, the second page table being a page table shared by the TEE side and the REE side and used for mapping the intermediate address to a physical address, and the target virtual address being a virtual address corresponding to the memory data to be obtained; wherein the REE side and the TEE side each further include a first base register and a second base register, the first base register being a base register corresponding to a user space, the second base register being a base register corresponding to a kernel space, and the VMI program being deployed in the user space and the kernel space of the TEE side; the processor sharing the first page table for address mapping of the REE side to the TEE side, including: when the memory data to be obtained is data of the user space, the processor sharing, as the first page table, a page table pointed to by the first base register of the REE side to the first base register of the TEE side; when the memory data to be obtained is data of the kernel space, the processor sharing, as the first page table, a page table pointed to by the second base register of the REE side to the second base register of the TEE side; the processor running the VMI program in the target SP, including: when the memory data to be obtained is data of the user space, the processor pointing, by the second base register of the TEE side, to the VMI program deployed in the kernel space of the TEE side; and the processor running, in the target SP, the VMI program pointed to by the second base register in a kernel mode; when the memory data to be obtained is data of the kernel space, the processor pointing, by the first base register of the TEE side, to the VMI program deployed in the user space of the TEE side; and the processor running, in the target SP, the VMI program pointed to by the first base register in the kernel mode.

2. The method of claim 1, wherein, the REE side and the TEE side each further include a third base register, and the third base register of the REE side and the third base register of the TEE side each point to the second page table. The processor obtains memory data of the target VM through the VMI program running in the target SP according to the target virtual address, the first page table and the second page table, and the method comprises the following steps of: In the process of running the VMI program in the target SP, the processor determines an intermediate address corresponding to the target virtual address according to the first page table through a memory management unit (MMU), and determines a physical address corresponding to the intermediate address according to the second page table pointed by the third base register on the TEE side; The processor obtains memory data corresponding to the physical address through the VMI program running in the target SP.

3. The method of claim 2, wherein, The processor determines a physical address corresponding to the intermediate address according to the second page table pointed by the third base register on the TEE side through the MMU, and the method comprises the following steps of: In the case that the page table item at the intermediate address is stored in a secure memory, the MMU obtains a non-secure (NS) bit in the page table item at the intermediate address; If the NS bit is a first value, the MMU determines a physical address corresponding to the intermediate address according to the second page table pointed by the third base register on the TEE side.

4. The method of claim 2, wherein, The processor determines a physical address corresponding to the intermediate address according to the second page table pointed by the third base register on the TEE side through the MMU, and the method comprises the following steps of: In the case that the page table item at the intermediate address is stored in a non-secure memory, the MMU determines a physical address corresponding to the intermediate address according to the second page table pointed by the third base register on the TEE side.

5. The method according to any one of claims 1 to 4, characterized in that, The TEE side further comprises a fourth base register, and the fourth base register points to a third page table, which is a page table for mapping an intermediate address to a physical address for normal running of the VMI program; The processor runs the VMI program in a target SP, and the method comprises the following steps of: The processor runs the VMI program in the target SP according to the third page table pointed by the fourth base register.

6. A memory data acquisition apparatus, characterized by comprising: Hardware resources of a computer device are divided into a rich execution environment (REE) side and a trusted execution environment (TEE) side, the REE side comprises one or more virtual machines (VMs), the TEE side comprises one or more secure partitions (SPs), the TEE side is deployed with a virtual machine introspection (VMI) program, and the apparatus comprises: A page table sharing module is configured to share a first page table for address mapping of the REE side to the TEE side, and the first page table is a page table for mapping a virtual address to an intermediate address; A program running module is configured to run the VMI program in a target SP, and the target SP is an SP in the one or more SPs for obtaining memory data of a target VM, and the target VM is any VM in the one or more VMs. The data acquisition module is configured to acquire, according to a target virtual address, the first page table and a second page table, memory data of the target VM by the VMI program running in the target SP, the second page table being a page table shared by the TEE side and the REE side and used for mapping an intermediate address into a physical address, and the target virtual address being a virtual address corresponding to the memory data to be acquired. The REE side and the TEE side each further include a first base register and a second base register, the first base register being a base register corresponding to a user space, the second base register being a base register corresponding to a kernel space, and the VMI program being deployed in the user space and the kernel space of the TEE side. The page table sharing module is specifically configured to: when the memory data to be acquired is data of the user space, share, as the first page table, a page table pointed to by the first base register of the REE side to the first base register of the TEE side; when the memory data to be acquired is data of the kernel space, share, as the first page table, a page table pointed to by the second base register of the REE side to the second base register of the TEE side. The program running module is specifically configured to: when the memory data to be acquired is data of the user space, point, by the second base register of the TEE side, to the VMI program deployed in the kernel space of the TEE side; and run, in the target SP, the VMI program pointed to by the second base register in a kernel mode; when the memory data to be acquired is data of the kernel space, point, by the first base register of the TEE side, to the VMI program deployed in the user space of the TEE side; and run, in the target SP, the VMI program pointed to by the first base register in the kernel mode.

7. The apparatus of claim 6, wherein, The REE side and the TEE side each further include a third base register, and the third base register of the REE side and the third base register of the TEE side each point to the second page table. The data acquisition module includes: An address mapping unit is configured to, in a process of running the VMI program in the target SP, determine, by a memory management unit (MMU), an intermediate address corresponding to the target virtual address according to the first page table, and determine a physical address corresponding to the intermediate address according to the second page table pointed to by the third base register of the TEE side. A data acquisition unit is configured to acquire, by the VMI program running in the target SP, memory data corresponding to the physical address.

8. The apparatus of claim 7, wherein, The address mapping unit is specifically configured to: in a case where a page table item in which the intermediate address is located is stored in a secure memory, acquire, by the MMU, a non-secure (NS) bit in the page table item in which the intermediate address is located. if the NS bit is a first value, determine, by the MMU, the physical address corresponding to the intermediate address according to the second page table pointed to by the third base register of the TEE side.

9. The apparatus of claim 7, wherein, The address mapping unit is specifically configured to: In the case that the page table item where the intermediate address is located is stored in non-secure memory, the MMU determines the physical address corresponding to the intermediate address according to the second page table pointed to by the third base register on the TEE side.

10. The apparatus of any one of claims 6-9, wherein, The TEE side further includes a fourth base register pointing to a third page table, which is a page table for normal running of the VMI program to perform intermediate address to physical address mapping. The program running module is specifically configured to: run the VMI program in the target SP according to the third page table pointed to by the fourth base register.

11. A computer readable storage medium, characterized in that, The storage medium has instructions stored therein, and when the instructions are run on the computer device, the computer device is caused to perform the steps of the method of any one of claims 1-5.

12. A computer program product, characterised in that, The computer program product includes instructions, and when the instructions are run on the computer device, the computer device is caused to perform the steps of the method of any one of claims 1-5.

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